Texas Instruments TL16C554FNR, TL16C554FN, TL16C554APN, TL16C554PN, TL16C554IPN Datasheet

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TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Integrated Asynchronous Communications Element

Consists of Four Improved TL16C550 ACEs Plus Steering Logic

In FIFO Mode, Each ACE Transmitter and Receiver Is Buffered With 16-Byte FIFO to Reduce the Number of Interrupts to CPU

In TL16C450 Mode, Hold and Shift Registers Eliminate Need for Precise Synchronization Between the CPU and Serial Data

Up to 16-MHz Clock Rate for up to 1-Mbaud Operation

Programmable Baud Rate Generators Which Allow Division of Any Input Reference Clock by 1 to (2

–1) and

Generate an Internal 16 × Clock

Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and Parity) to or From the Serial Data Stream

Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts

Fully Programmable Serial Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (DC to 1-Mbit Per

Second)

False Start Bit Detection

Complete Status Reporting Capabilities

Line Break Generation and Detection

Internal Diagnostic Capabilities: – Loopback Controls for Communications

Link Fault Isolation

– Break, Parity , Overrun, Framing Error

Simulation

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR, DTR

, RI, and DCD)

3-State Outputs Provide TTL Drive Capabilities for Bidirectional Data Bus and Control Bus

description

The TL16C554 and the TL16C554I are enhanced quadruple versions of the TL16C550B asynchronous communications element (ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the quadruple ACE can be read at any time during functional operation by the CPU. The information obtained includes the type and condition of the operation performed and any error conditions encountered.

The TL16C554 and the TL16C554I quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. T o minimize system overhead and maximize system ef ficiency , all logic is on the chip. Two terminal functions allow signaling of direct memory access (DMA) transfers. Each ACE includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (2

–1).

The TL16C554 and the TL16C554I are available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package and in an 80-pin (TQFP) PN package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TL16C554, TL16C554I ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

28 29

DSRD CTSD DTRD GND RTSD INTD CSD TXD IOR TXC CSC INTC RTSC V

DTRC CTSC DSRC

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

DSRA

CTSA

DTRA

RTSA

INTA

CSA

TXA

IOW

TXB

CSB

INTB

RTSB

GND

DTRB

CTSB

DSRB

31 32 33 34

FN PACKAGE

(TOP VIEW)

87 65493

RXA

GNDD7D6D5D4

XTAL2

RESET

RXRDY

TXRDY

RXB

A2A1A0

XTAL1

168672

35 36 37 38 39

66 65

DCDB

INTN

64 63 62 61

40 41 42 43

GND

RXC

RIC

DCDC

RXD

RID

DCDD

DCDA

RIA

RIB

NC – No internal connection

TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NC DSRB CTSB DTRB GND RTSB INTB CSB TXB IOW NC TXA CSA INTA RTSA V

DTRA CTSA DSRA NC

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

DSRC

CTSC

DTRC

RTSC

INTC

CSC

TXC

IOR

TXD

CSD

INTD

RTSD

GND

DTRD

CTSD

DSRD

5678

PN PACKAGE

(TOP VIEW)

XTAL1

59 58 57 56 5560 54

RIC

RXC

GND

TXRDY

RXRDY

RESET

RID

RXD

INTN

D0D1D2

52 51 5053

10 11 12 13

49 48

47 46 45 44

14 15 16 17

GND

RXA

XTAL2

RXB

DCDC

RIA

DCDA

18 19 20

RIB

DCDB

43 42 41

DCDD

NC – No internal connection

TL16C554, TL16C554I ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

†

TL16C550B

Circuitry

TL16C550B

Circuitry

TL16C550B

Circuitry

TL16C550B

Circuitry

Receive

Control

Logic

Transmit

Control

Logic

Modem

Control

Logic

Control

Logic

Data

Bus

Clock

Circuit

RXx

TXx

CTSx RTSx DSRx DTRx RIx DCDx

D7–D0

A2–A0

CSx

IOR, IOW

RESET

XTAL1 XTAL2

INTx

TXRDY

, RXRDY

Interrupt

Logic

†

For TL16C550 circuitry, refer to the TL16C550B data sheet.

Terminal Functions

TERMINAL

NAME

NO.PNNO.

I/O

DESCRIPTION

A0 A1 A2

34 33 32

48 47 46

I Register select terminals. A0, A1, and A2 are three inputs used during read and write operations to

select the ACE register to read or write.

CSA, CSB, CSC

, CSD

16, 20,

50, 54

28, 33,

68, 73

I Chip select. Each chip select (CSx) enables read and write operations to its respective channel.

CTSA, CTSB, CTSC

, CTSD

11, 25,

45, 59

23, 38,

63, 78

I Clear to send. CTSx is a modem status signal. Its condition can be checked by reading bit 4 (CTS)

of the modem status register. CTS

has no affect on the transmit or receive operation.

D7–D0 66–68

1–5

15–11,

9–7

I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status

information between the TL16C554 and the CPU. D0 is the least significant bit (LSB).

DCDA, DCDB, DCDC

, DCDD

9, 27,

43, 61

19,42,

59, 2

I Data carrier detect. A low on DCDx indicates the carrier has been detected by the modem. The

condition of this signal is checked by reading bit 7 of the modem status register.

DSRA, DSRB, DSRC

, DSRD

10, 26,

44, 60

22, 39,

62, 79

Data set ready. DSRx is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem status register. DSR

has no affect on the transmit or receive operation.

DTRA, DTRB, DTRC

, DTRD

12, 24,

46, 58

24, 37,

64, 77

O Data terminal ready. DTRx is an output that indicates to a modem or data set that the ACE is ready

to establish communications. It is placed in the active state by setting the DTR bit of the modem control register. DTRx

is placed in the inactive state (high) either as a result of the master reset during

loop mode operation or clearing bit 0 (DTR

) of the modem control register.

GND 6, 23,

40, 57

16, 36,

56, 76

Signal and power ground

INTN

65 6 I

Interrupt normal. INTN operates in conjunction with bit 3 of the modem status register and affects operation of the interrupts (INTA, INTB, INTC, and INTD) for the four universal asynchronous receiver/transceivers (UARTs) per the following table.

INTN OPERATION OF INTERRUPTS

Brought low or allowed to float

Interrupts are enabled according to the state of OUT2 (MCR bit 3). When the MCR bit 3 is cleared, the 3-state interrupt output of that UART is in the high-impedance state. When the MCR bit 3 is set, the interrupt output of the UART is enabled.

Brought high Interrupts are always enabled, overriding the OUT2 enables.

TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME

NO.PNNO.

I/O

DESCRIPTION

INTA, INTB, INTC, INTD

15, 21,

49, 55

27, 34,

67, 74

O External interrupt output. The INTx outputs go high (when enabled by the interrupt register) and

inform the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt to be issued are: a receiver error, receiver data available or timeout (FIFO mode only), transmitter holding register empty , and an enabled modem status interrupt. The interrupt is disabled when it is serviced or as the result of a master reset.

IOR 52 70 I Read strobe. A low level on IOR transfers the contents of the TL16C554 data bus to the external CPU

bus. IOW 18 31 I Write strobe. IOW allows the CPU to write into the selected address by the address register . RESET 37 53 I Master reset. When active, RESET clears most ACE registers and sets the state of various signals.

The transmitter output and the receiver input is disabled during reset time. RIA, RIB,

RIC

, RID

8, 28,

42, 62

18, 43,

58, 3

I Ring detect indicator. A low on RIx indicates the modem has received a ring signal from the telephone

line. The condition of this signal can be checked by reading bit 6 of the modem status register. RTSA, RTSB,

RTSC

, RTSD

14, 22,

48, 56

26, 35,

66, 75

O Request to send. When active, RTSx informs the modem or data set that the ACE is ready to receive

data. Writing a 1 in the modem control register sets this bit to a low state. After reset, this terminal

is set high. These terminals have no affect on the transmit or receive operation. RXA, RXB

RXC, RXD

7, 29,

41, 63

17, 44,

57, 4

I Serial input. RXx is a serial data input from a connected communications device. During loopback

mode, the RXx input is disabled from external connection and connected to the TXx output internally . RXRDY 38 54 O Receive ready. RXRDY goes low when the receive FIFO is full. It can be used as a single transfer

or multitransfer. TXA, TXB

TXC, TXD

17, 19,

51, 53

29, 32,

69, 72

O Transmit outputs. TXx is a composite serial data output that is connected to a communications

device. TXA, TXB, TXC, and TXD are set to the marking (high) state as a result of reset. TXRDY 39 55 O T ransmit ready. TXRDY goes low when the transmit FIFO is full. It can be used as a single transfer

or multitransfer function. VCC 13, 30,

47, 64

5, 25,

45, 65

Power supply

XTAL1 35 50 I Crystal input 1 or external clock input. A crystal can be connected to XTAL1 and XT AL2 to utilize the

internal oscillator circuit. An external clock can be connected to drive the internal clock circuits. XTAL2 36 51 O Crystal output 2 or buffered clock output (see XTAL1).

absolute maximum ratings over free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range at any input, V

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

–0.5 V to VCC + 3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation at (or below) 70°C 500 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

: TL16C554 –0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TL16C554I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage levels are with respect to GND.

TL16C554, TL16C554I ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

4.75 5 5.25 V

Clock high-level input voltage at XTAL1, V

IH(CLK)

2 V

Clock low-level input voltage at XTAL1, V

IL(CLK)

–0.5 0.8 V

High-level input voltage, V

2 V

Low-level input voltage, V

–0.5 0.8 V

Clock frequency, f

clock

16 MHz

TL16C554 0 70 °C

O erating free-air tem erature, T

TL16C554I –40 85 °C

electrical characteristics over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

‡

High-level output voltage IOH = –1 mA 2.4 V

‡

Low-level output voltage IOL = 1.6 mA 0.4 V

Ikg

Input leakage current

VCC = 5.25 V, GND = 0, VI = 0 to 5.25 V, All other terminals floating

±10 µA

High-impedance output current

VCC = 5.25 V, GND = 0, VO = 0 to 5.25 V, Chip selected in write mode or chip deselected

±20 µA

Supply current

VCC = 5.25 V , TA = 25°C, RX, DSR

, DCD, CTS, and RI at 2 V , All other inputs at 0.8 V , XTAL1 at 4 MHz, No load on outputs, Baud rate = 50 kilobits per second

50 mA

i(XTAL1)

Clock input capacitance 15 20 pF

o(XTAL2)

Clock output capacitance

VCC = 0, VSS = 0,

20 30 pF

Input capacitance

All other terminals grounded

= 1

MHz

= 25°C

6 10 pF

Output capacitance

25 C

10 20 pF

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

These parameters apply for all outputs except XTAL2.

clock timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 1)

MIN MAX UNIT

Pulse duration, clock high (external clock) 31 ns

Pulse duration, clock low (external clock) 31 ns

Pulse duration, RESET 1000 ns

TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

read cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 4)

MIN MAX UNIT

Pulse duration, IOR low 75 ns

su1

Setup time, CSx valid before IOR low (see Note 2) 10 ns

su2

Setup time, A2–A0 valid before IOR low (see Note 2) 15 ns

Hold time, A2–A0 valid after IOR high (see Note 2) 0 ns

Hold time, CSx valid after IOR high (see Note 2) 0 ns

Delay time, t

su2

+ tw4 + td2 (see Note 3) 140 ns

Delay time, IOR high to IOR or IOW low 50 ns

NOTES: 2. The internal address strobe is always active.

3. In the FIFO mode, td1 = 425 ns (min) between reads of the receiver FIFO and the status registers (interrupt identification register and line status register).

write cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 5)

MIN MAX UNIT

Pulse duration, IOW↓ 50 ns

su3

Setup time, CSx valid before IOW↓ (see Note 2) 10 ns

su4

Setup time, A2–A0 valid before IOW↓ (see Note 2) 15 ns

su5

Setup time, D7–D0 valid before IOW↑ 10 ns

Hold time, A2–A0 valid after IOW↑ (see Note 2) 5 ns

Hold time, CSx valid after IOW↑ (see Note 2) 5 ns

Hold time, D7–D0 valid after IOW↑ 25 ns

Delay time, t

su4

+ tw5 + t

120 ns

Delay time, IOW↑ to IOW or IOR↓ 55 ns

NOTE 2: The internal address strobe is always active.

read cycle switching characteristics over recommended ranges of operating free-air temperature and supply voltage, C

= 100 pF (see Note 4 and Figure 4)

PARAMETER MIN MAX UNIT

Enable time, IOR↓ to D7–D0 valid 30 ns

dis

Disable time, IOR↑ to D7–D0 released 0 20 ns

NOTE 4: VOL and VOH (and the external loading) determine the charge and discharge time.

TL16C554, TL16C554I ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

transmitter switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figures 6, 7, and 8)

PARAMETER TEST CONDITIONS MIN MAX UNIT

Delay time, INTx↓ to TXx↓ at start 8 24

RCLK cycles

Delay time, TXx↓ at start to INTx↑ See Note 5 8 8

RCLK cycles

Delay time, IOW high or low (WR THR) to INTx↑ See Note 5 16 32

RCLK cycles

Delay time, TXx↓ at start to TXRDY↓ CL = 100 pF 8

RCLK cycles

pd1

Propagation delay time, IOW (WR THR)↓ to INTx↓ CL = 100 pF 35 ns

pd2

Propagation delay time, IOR (RD IIR)↑ to INTx↓ CL = 100 pF 30 ns

pd3

Propagation delay time, IOW (WR THR)↑ to TXRDY↑ CL = 100 pF 50 ns

NOTE 5: If the transmitter interrupt delay is active, this delay is lengthened by one character time minus the last stop bit time.

receiver switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figures 9 through 13)

PARAMETER TEST CONDITIONS MIN MAX UNIT

Delay time, stop bit to INTx↑ or stop bit to RXRDY↓ or read RBR to set interrupt See Note 6 1

RCLK

cycle

pd4

Propagation delay time, Read RBR/LSR to INTx↓/LSR interrupt↓

CL = 100 pF,

See Note 7

40 ns

pd5

Propagation delay time, IOR RCLK↓ to RXRDY↑ See Note 7 30 ns

NOTES: 6. The receiver data available indicator, the overrun error indicator, the trigger level interrupts, and the active RXRDY indicator are

delayed three RCLK (internal receiver timing clock) cycles in the FIFO mode (FCR0 = 1). After the first byte has been received, status indicators (PE, FE, BI) are delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after IOR

goes active for a read from the RBR register. There are eight RCLK cycle delays for trigger change level interrupts.

7. RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches.

modem control switching characteristics over recommended ranges of operating free-air temperature and supply voltage, C

= 100 pF (see Figure 14)

PARAMETER MIN MAX UNIT

pd6

Propagation delay time, IOW (WR MCR)↑ to RTSx, DTRx↑

50 ns

pd7

Propagation delay time, modem input CTSx, DSRx, and DCDx ↓↑ to INTx↑ 30 ns

pd8

Propagation delay time, IOR (RD MSR)↑ to interrupt↓ 35 ns

pd9

Propagation delay time, RIx↑ to INTx↑ 30 ns

TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Clock

(XTAL1)

clock

= 16 MHz MAX

0.8 V

2 V

RESET

2 V2 V

0.8 V

(a) CLOCK INPUT VOLTAGE WAVEFORM

(b) RESET VOLTAGE WAVEFORM

Figure 1. Clock Input and RESET Voltage Waveforms

82 pF (see Note A)

680 Ω

2.54 V

Device Under Test

TL16C554

NOTE A: This includes scope and jig capacitance.

Figure 2. Output Load Circuit

9-Pin D Connector

Serial

Channel 1

Buffers

Serial

Channel 2

Buffers

Serial

Channel 3

Buffers

Serial

Channel 4

Buffers

9-Pin D Connector

Data Bus

Address Bus

Control Bus

Quadruple

ACE

TL16C554

Figure 3. Basic Test Configuration

TL16C554, TL16C554I ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JUL Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Active

Valid

A2, A1, A0

Valid

Valid Data

IOR

IOW

D7–D0

su1

su2

Active

dis

Active

CSx

50%

Figure 4. Read Cycle Timing Waveforms

Valid

A2, A1, A0

Valid

Valid Data

IOR

IOW

D7–D0

su3

su4

su5

Active

CSx

50%

Figure 5. Write Cycle Timing Waveforms

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