TEXAS INSTRUMENTS TL16C554A, TL16C554AI Technical data

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Integrated Asynchronous-Communications Element

Consists of Four Improved TL16C550C ACEs Plus Steering Logic

In FIFO Mode, Each ACE Transmitter and Receiver Is Buffered With 16-Byte FIFO to Reduce the Number of Interrupts to CPU

In TL16C450 Mode, Hold and Shift Registers Eliminate Need for Precise Synchronization Between the CPU and Serial Data

Up to 16-MHz Clock Rate for up to 1-Mbaud Operation

Programmable Baud-Rate Generators Which Allow Division of Any Input Reference Clock by 1 to (2 Generate an Internal 16 × Clock

Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and Parity) to or From the Serial-Data Stream

Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts

5-V and 3.3-V Operation

description

–1) and

TL16C554A, TL16C554AI

ASYNCHRONOUS-COMMUNICATIONS ELEMENT

SLLS509A – AUGUST 2001 – REVISED JUL Y 2003

Fully Programmable Serial Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (DC to 1-Mbit Per

Second)

False Start Bit Detection

Complete Status Reporting Capabilities

Line Break Generation and Detection

Internal Diagnostic Capabilities: – Loopback Controls for Communications

Link Fault Isolation

– Break, Parity, Overrun, Framing Error

Simulation

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR, DTR

, RI, and DCD)

3-State Outputs Provide TTL Drive Capabilities for Bidirectional Data Bus and Control Bus

Programmable Auto-RTS and Auto-CTS

CTS Controls Transmitter in Auto-CTS Mode,

RCV FIFO Contents and Threshold Control RTS

in Auto-RTS Mode,

The TL16C554A is an enhanced quadruple version of the TL16C550C asynchronous-communications element (ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the quadruple ACE can be read by the CPU at any time during operation. The information obtained includes the type and condition of the operation performed and any error conditions encountered.

The TL16C554A quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. In the FIFO mode of operation, there is a selectable autoflow control feature that can significantly reduce software overhead and increase system efficiency by automatically controlling serial-data flow using RTS system efficiency . T wo terminal functions allow signaling of direct-memory access (DMA) transfers. Each ACE includes a programmable baud-rate generator that can divide the timing reference clock input by a divisor between 1 and 2

The TL16C554A is available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package and in an 80-pin (TQFP) PN package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

output and CTS input signals. All logic is on the chip to minimize system overhead and maximize

–1.

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FN PACKAGE

(TOP VIEW)

RXA

DCDA

RIA

GNDD7D6D5D4

INTN

RXD

RID

DCDD

DSRA

CTSA

DTRA

RTSA

INTA

CSA

TXA

IOW

TXB

CSB

INTB

RTSB

GND

DTRB

CTSB

DSRB

NC – No internal connection

87 65493

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

DCDB

28 29

RIB

RXB

31 32 33 34

A2A1A0

168672

35 36 37 38 39

XTAL1

XTAL2

66 65

RESET

RXRDY

64 63 62 61

40 41 42 43

RXC

GND

TXRDY

RIC

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

DCDC

DSRD CTSD DTRD GND RTSD INTD CSD TXD IOR TXC CSC INTC RTSC V

DTRC CTSC DSRC

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PN PACKAGE

(TOP VIEW)

TL16C554A, TL16C554AI

SLLS509A – AUGUST 2001 – REVISED JULY 2003

DSRC

CTSC

DTRC

RTSC

INTC

CSC

TXC

IOR

TXD

CSD

INTD

RTSD

GND

DTRD

CTSD

DSRD

DCDC

59 58 57 56 5560 54

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

RIC

RXC

5678

GND

TXRDY

RXRDY

RESET

52 51 5053

10 11 12 13

XTAL2

XTAL1

49 48

47 46 45 44

14 15 16 17

RXB

RIB

43 42 41

18 19 20

DCDB

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

NC DSRB CTSB DTRB GND RTSB INTB CSB TXB IOW NC TXA CSA INTA RTSA V

DTRA CTSA DSRA NC

RID

DCDD

NC – No internal connection

RXD

D0D1D2

INTN

GND

RXA

RIA

DCDA

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functional block diagram (per channel)

D(7–0)

A0 A1 A2

CSA CSB CSC CSD

RESET

IOR

IOW

TXRDY

XTAL1 XTAL2

RXRDY

INTN

GND

5 – 66

34 33

16 20

50 54

37 52

18 39 35 36 38 65

13, 30, 47, 64

6, 23, 40, 57

Data

Bus

Buffer

Select

and

Control

Logic

Internal

Power Supply

Data

Bus

S e

l e c

Receiver

Buffer

Line

Control

Divisor

Latch (LS)

Divisor

Latch (MS)

Line

Status

Transmitter

Holding

Modem

Control

Modem

Status

Interrupt

Enable

Receiver

FIFO

Transmitter

FIFO

Interrupt

Control

Logic

Baud

Generator

Receiver

Shift

Receiver

Timing and

Control

Transmitter

Timing and

Control

S e

l e c

Transmitter

Shift

Modem

Control

Logic

Autoflow Control (AFE)

11 12 10

9 8

RXA

RTSA

TXA

CTSA DTRA DSRA DCDA RIA

INTA

Interrupt

Identification

FIFO

Control

NOTE A: Terminal numbers shown are for the FN package and channel A.

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Terminal Functions

TERMINAL

NAME

A0 A1 A2

CSA, CSB, CSC

, CSD

CTSA, CTSB, CTSC

, CTSD

D7–D0 66–68

DCDA, DCDB, DCDC

, DCDD

DSRA, DSRB, DSRC

, DSRD

DTRA, DTRB, DTRC

, DTRD

GND 6, 23,

INTN

INTA, INTB, INTC, INTD

IOR 52 70 I Read strobe. A low level on IOR transfers the contents of the selected register to the external CPU

IOW 18 31 I Write strobe. IOW allows the the CPU to write to the register selected by the address. RESET 37 53 I Master reset. When active, RESET clears most ACE registers and sets the state of various signals.

RIA, RIB, RIC

, RID

RTSA, RTSB, RTSC

, RTSD

NO.PNNO.

34 33 32

16, 20,

50, 54

11, 25,

45, 59

43, 61

10, 26,

44, 60

12, 24,

46, 58

40, 57

15, 21,

49, 55

42, 62

14, 22,

48, 56

28, 33,

68, 73

23, 38,

63, 78

15–11,

1–5 9, 27,

19,42,

59, 2

22, 39,

62, 79

24, 37,

64, 77

16, 36,

56, 76

65 6 I

27, 34,

67, 74

8, 28,

18, 43,

58, 3

26, 35,

66, 75

I/O DESCRIPTION

48 47 46

9–7

I Register select terminals. A0, A1, and A2 are three inputs used during read and write operations to

select the ACE register to read or write.

I Chip select. Each chip select (CSx) enables read and write operations to its respective channel.

I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS)

of the modem-status register. Bit 0 (∆CTS) of the modem-status register indicates that CTS changed state since the last read from the modem-status register. If the modem-status interrupt is enabled when CTS changes levels and the auto-CTS mode is not enabled, an interrupt is generated. CTS

is also used in the auto-CTS mode to control the transmitter.

I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status

information between the TL16C554A and the CPU. D0 is the least-significant bit (LSB).

I Data carrier detect. A low on DCDx indicates the carrier has been detected by the modem. The

condition of this signal is checked by reading bit 7 of the modem-status register. Data set ready. DSRx is a modem-status signal. Its condition can be checked by reading bit 5 (DSR)

of the modem-status register. DSR

O Data terminal ready. DTRx is an output that indicates to a modem or data set that the ACE is ready

to establish communications. It is placed in the active state by setting the DTR bit of the modemcontrol register. DTRx loop-mode operation, or when clearing bit 0 (DTR

Signal and power ground

Interrupt normal. INTN operates in conjunction with bit 3 of the modem-status register and affects operation of the interrupts (INTA, INTB, INTC, and INTD) for the four universal asynchronous receiver/transceivers (UARTs) per the following table.

INTN OPERATION OF INTERRUPTS

Brought low or allowed to float

Brought high Interrupts are always enabled, overriding the OUT2 enables.

O External interrupt output. The INTx outputs go high (when enabled by the interrupt register) and

inform the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt to be issued are: receiver error, receiver data available or timeout (FIFO mode only), transmitter holding register empty , and an enabled modem-status interrupt. The interrupt is disabled when it is serviced or as the result of a master reset.

bus.

The transmitter output and the receiver input are disabled during reset time.

I Ring detect indicator . A low on RIx indicates the modem has received a ring signal from the telephone

line. The condition of this signal can be checked by reading bit 6 of the modem-status register.

O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive

data. RTS inactive (high) level either as a result of a master reset, or during loop-mode operations, or by clearing bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS is set to the inactive level by the receiver threshold-control logic.

is set to the active level by setting the RTS modem-control register bit, and is set to the

is placed in the inactive state (high) either as a result of the master reset during

Interrupts are enabled according to the state of OUT2 (MCR bit 3). When the MCR bit 3 is cleared, the 3-state interrupt output of that UART is in the high-impedance state. When the MCR bit 3 is set, the interrupt output of the UART is enabled.

has no effect on the transmit or receive operation.

) of the modem-control register.

has

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Terminal Functions (Continued)

TERMINAL

NAME

RXA, RXB RXC, RXD

RXRDY 38 54 O Receive ready. RXRDY goes low when the receive FIFO is full. It can be used as a single transfer

TXA, TXB TXC, TXD

TXRDY 39 55 O T ransmit ready. TXRDY goes low when the transmit FIFO is full. It can be used as a single transfer

XTAL1 35 50 I Crystal input 1 or external clock input. A crystal can be connected to XTAL1 and XT AL2 to utilize the

XTAL2 36 51 O Crystal output 2 or buffered clock output (see XT AL1).

NO.PNNO.

7, 29,

41, 63

17, 19,

51, 53

13, 30,

47, 64

17, 44,

29, 32,

69, 72

5, 25,

45, 65

57, 4

I/O DESCRIPTION

I Serial input. RXx is a serial-data input from a connected communications device. During loopback

mode, the RXx input is disabled from external connection and connected to the TXx output internally .

or multitransfer.

O Transmit outputs. TXx is a composite serial-data output connected to a communications device.

TXA, TXB, TXC, and TXD are set to the marking (high) state as a result of reset.

or multitransfer function. Power supply

internal oscillator circuit. An external clock can be connected to drive the internal-clock circuits.

absolute maximum ratings over free-air temperature range (unless otherwise noted)

Supply voltage range, V Input voltage range at any input, V Output voltage range, V

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to VCC + 3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Continuous total-power dissipation at (or below) 70°C 500 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

: TL16C554A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TL16C554AI –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage levels are with respect to GND.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

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O erating free-air tem erature, T

CC SS

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recommended operating conditions, standard voltage (5 V-nominal)

MIN NOM MAX UNIT

Supply voltage, V Clock high-level input voltage at XTAL1, V Clock low-level input voltage at XTAL1, V High-level input voltage, V Low-level input voltage, V Clock frequency, f

clock

IH(CLK)

IL(CLK)

TL16C554A 0 70 °C TL16C554AI –40 85 °C

electrical characteristics over recommended ranges of operating free-air temperature and supply voltage, standard voltage (5-V nominal) (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

‡

Ikg

i(XTAL1)

o(XTAL2)

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

These parameters apply for all outputs except XTAL2.

High-level output voltage IOH = –1 mA 2.4 V Low-level output voltage IOL = 1.6 mA 0.4 V

Input leakage current High-impedance output

current

Supply current

Clock input capacitance 15 20 pF Clock output capacitance Input capacitance Output capacitance 10 20 pF

VCC = 5.25 V, GND = 0, VI = 0 to 5.25 V, All other terminals floating

VCC = 5.25 V, GND = 0, VO = 0 to 5.25 V, Chip selected in write mode or chip deselected

VCC = 5.25 V, TA = 25°C, RX, DSR All other inputs at 0.8 V , XTAL1 at 4 MHz, No load on outputs, Baud rate = 50 kilobits per second

VCC = 0, VSS = 0, all other terminals grounded, f = 1 MHz, TA = 25°C

, DCD, CTS, and RI at 2 V,

4.75 5 5.25 V 2 V

–0.5 0.8 V

2 V

–0.5 0.8 V

16 MHz

±10 µA

±20 µA

50 mA

20 30 pF

6 10 pF

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O erating free-air tem erature, T

CC SS

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recommended operating conditions, low voltage (3.3-V nominal)

MIN NOM MAX UNIT

Supply voltage, V Clock high-level input voltage at XTAL1, V Clock low-level input voltage at XTAL1, V High-level input voltage, V Low-level input voltage, V Clock frequency, f

clock

IH(CLK)

IL(CLK)

TL16C554A 0 70 °C TL16C554AI –40 85 °C

electrical characteristics over recommended ranges of operating free-air temperature and supply voltage, low voltage (3.3-V nominal) (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

‡

Ikg

i(XTAL1)

o(XTAL2)

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

These parameters apply for all outputs except XTAL2.

High-level output voltage IOH = –1 mA 2.4 V Low-level output voltage IOL = 1.6 mA 0.4 V

Input leakage current High-impedance output

current

Supply current

Clock input capacitance 15 20 pF Clock output capacitance Input capacitance Output capacitance 10 20 pF

VCC = 3.6 V, GND = 0, VI = 0 to 3.6 V, All other terminals floating

VCC = 3.6 V, GND = 0, VO = 0 to 3.6 V, Chip selected in write mode or chip deselected

VCC = 3.6 V, TA = 25°C, RX, DSR All other inputs at 0.8 V , XTAL1 at 4 MHz, No load on outputs, Baud rate = 50 kilobits per second

VCC = 0, VSS = 0, all other terminals grounded, f = 1 MHz, TA = 25°C

, DCD, CTS, and RI at 2 V,

3 3.3 3.6 V 2 V

–0.5 0.8 V

2 V

–0.5 0.8 V

16 MHz

±10 µA

±20 µA

40 mA

20 30 pF

6 10 pF

clock timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 1)

Pulse duration, clock high (external clock) 31 ns Pulse duration, clock low (external clock) 31 ns Pulse duration, RESET 1000 ns

MIN MAX UNIT

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read cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 4)

MIN MAX UNIT

su1

su2

NOTES: 2. The internal address strobe is always active.

write cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 5)

su3

su4

su5

NOTE 2: The internal address strobe is always active.

Pulse duration, IOR low 75 ns Setup time, CSx valid before IOR low (see Note 2) 10 ns Setup time, A2–A0 valid before IOR low (see Note 2) 15 ns Hold time, A2–A0 valid after IOR high (see Note 2) 0 ns Hold time, CSx valid after IOR high (see Note 2) 0 ns Delay time, t Delay time, IOR high to IOR or IOW low 50 ns

3. In the FIFO mode, td1 = 425 ns (min) between reads of the receiver FIFO and the status registers (interrupt-identification register and line-status register).

Pulse duration, IOW↓ 50 ns Setup time, CSx valid before IOW↓ (see Note 2) 10 ns Setup time, A2–A0 valid before IOW↓ (see Note 2) 15 ns Setup time, D7–D0 valid before IOW↑ 10 ns Hold time, A2–A0 valid after IOW↑ (see Note 2) 5 ns Hold time, CSx valid after IOW↑ (see Note 2) 5 ns Hold time, D7–D0 valid after IOW↑ 25 ns Delay time, t Delay time, IOW↑ to IOW or IOR↓ 55 ns

+ tw4 + td2 (see Note 3) 140 ns

su2

MIN MAX UNIT

su4

+ tw5 + t

120 ns

read cycle switching characteristics over recommended ranges of operating free-air temperature and supply voltage, CL = 100 pF (see Note 4 and Figure 4)

PARAMETER MIN MAX UNIT

Enable time, IOR↓ to D7–D0 valid 30 ns

Disable time, IOR↑ to D7–D0 released 0 20 ns

dis

NOTE 4: VOL and VOH (and the external loading) determine the charge and discharge time.

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transmitter switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figures 6, 7, and 8)

PARAMETER TEST CONDITIONS MIN MAX UNIT

Delay time, INTx↓ to TXx↓ at start See Note 7 8 24

Delay time, TXx↓ at start to INTx↑ See Note 5 8 8

Delay time, IOW high or low (WR THR) to INTx↑ See Note 5 16 32

Delay time, TXx↓ at start to TXRDY↓ CL = 100 pF 8

Propagation delay time, IOW (WR THR)↓ to INTx↓ CL = 100 pF 35 ns

pd1

Propagation delay time, IOR (RD IIR)↑ to INTx↓ CL = 100 pF 30 ns

pd2

Propagation delay time, IOW (WR THR)↑ to TXRDY↑ CL = 100 pF 50 ns

pd3

NOTE 5: If the transmitter interrupt delay is active, this delay is lengthened by one character time minus the last stop-bit time.

receiver switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figures 9 through 13)

PARAMETER TEST CONDITIONS MIN MAX UNIT

Delay time, stop bit to INTx↑ or stop bit to RXRDY↓ or read RBR to set interrupt See Note 6 1

Propagation delay time, Read RBR/LSR to INTx↓/LSR interrupt↓

pd4

Propagation delay time, IOR RCLK↓ to RXRDY↑ See Note 7 30 ns

pd5

NOTES: 6. The receiver data available indicator, the overrun error indicator, the trigger level interrupts, and the active RXRDY indicator are

delayed three RCLK (internal receiver timing clock) cycles in the FIFO mode (FCR0 = 1). After the first byte has been received, status indicators (PE, FE, BI) are delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after IOR

goes active for a read from the RBR register. There are eight RCLK cycle delays for trigger change level interrupts.

7. RCLK and baudout are internal signals derived from divisor latches LSB (DLL) and MSB (DLM) and input clock.

CL = 100 pF,

See Note 7

RCLK cycles

RCLK

cycle

40 ns

modem control switching characteristics over recommended ranges of operating free-air temperature and supply voltage, C

Propagation delay time, IOW (WR MCR)↑ to RTSx, DTRx↑

pd6

Propagation delay time, modem input CTSx, DSRx, and DCDx ↓↑ to INTx↑ 30 ns

pd7

Propagation delay time, IOR (RD MSR)↑ to interrupt↓ 35 ns

pd8

Propagation delay time, RIx↑ to INTx↑ 30 ns

pd9

Propagation delay time, CTS low to SOUT↓ (See Note 7) 24

pd10

Setup time CTS high to midpoint of Tx stop bit 2

su6

Propagation delay time, RCV threshold byte to RTS↑ 2

pd11

Propagation delay time, IOR (RD RBR) low (read of last byte in receive FIFO) to RTS↓ 2

pd12

Propagation delay time, first data bit of 16th character to RTS↑ 2

pd13

Propagation delay time, IOR (RD RBR) low to RTS↓ 2

pd14

7. RCLK and baudout are internal signals derived from divisor latches LSB (DLL) and MSB (DLM) and input clock.

= 100 pF (see Figures 14, 15, 16, and 17)

PARAMETER MIN MAX UNIT

50 ns

baudout

cycles

baudout

cycles

baudout

cycles

baudout

cycles

baudout

cycles

baudout

cycles

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PARAMETER MEASUREMENT INFORMATION

TL16C554A, TL16C554AI

0.8 V

2 V2 V

= 16 MHz MAX

clock

0.8 V

Clock

(XTAL1)

(a) CLOCK INPUT VOLTAGE WAVEFORM

RESET

(b) RESET VOLTAGE WAVEFORM

Figure 1. Clock Input and RESET Voltage Waveforms

2.54 V

Device Under Test

TL16C554

680 Ω

82 pF (see Note A)

2 V

0.8 V

Data Bus

Address Bus

Control Bus

NOTE A: This includes scope and jig capacitance.

Figure 2. Output Load Circuit

Serial

Channel 1

Buffers

Serial

TL16C554A

Quadruple

ACE

Channel 2

Buffers

Serial

Channel 3

Buffers

Serial

Channel 4

Buffers

Figure 3. Basic Test Configuration

9-Pin D Connector

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PARAMETER MEASUREMENT INFORMATION

A2, A1, A0

CSx

IOR

IOW

D7–D0

50%

Valid

su1

su2

50%

Active

Valid Data

Figure 4. Read Cycle Timing Waveforms

50%

dis

50%

Active

A2, A1, A0

CSx

IOW

IOR

D7–D0

50%

Valid

su3

su4

50%

su5

Active

Valid Data

Figure 5. Write Cycle Timing Waveforms

50%

Active

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