TEXAS INSTRUMENTS TL16C552A, TL16C552AM Technical data

查询TL16C552A供应商

IBM PC/A T Compatible

Two TL16C550 ACEs

Enhanced Bidirectional Printer Port

16-Byte FIFOs Reduce CPU Interrupts

Up to 16-MHz Clock Rate for up to 1-Mbaud Operation

Transmit, Receive, Line Status, and Data Set Interrupts on Each Channel Independently Controlled

Individual Modem Control Signals for Each Channel

RXRDY0

DCD1

GND

TL16C552A, TL16C552AM

DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

Programmable Serial Interface Characteristics for Each Channel: – 5-, 6-, 7-, or 8-Bit Characters – Even, Odd, or No Parity Bit Generation

and Detection

– 1-, 1-1/2-, or 2-Stop Bit Generation

3-State Outputs Provide TTL Drive for the Data and Control Bus on Each Channel

Hardware and Software Compatible With TL16C452

HV or FN PACKAGE

(TOP VIEW)

ERR

SIN1

RI1

DSR1

CLK

CS1

TRI

ACK

PEMD

BUSY

SLCT

RXRDY1

SOUT1

DTR1

RTS1

CTS1

DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7

TXRDY0

RTS0

DTR0

SOUT0

87 65493

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

28 29

GND

CTS0

DCD0

31 32 33 34

RI0

DSR0

A2A1A0

CS0

168672

35 36 37 38 39

IOW

66 65

IOR

CS2

64 63 62 61

40 41 42 43

SIN0

RESET

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

ENIRQ

TXRDY1

INT1 INT2 SLIN INIT AFD STB GND PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 INT0 BDO

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

IBM PC/AT is a trademark of International Business Machines Corporation.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

PN PACKAGE

(TOP VIEW)

NC NC

RXRDY1

SIN1

ERR

SLCT

BUSY

ACK

PEMD

TRI CS1 CLK

DSR1

RI1

GND

DCD1

RXRDY0

INT1

79 78 77 76 7580 74

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

22 23

INT2

SLIN

25 26 27 28

INIT

AFD

STB

GND

PD0

72 71 7073

30 31 32 33

PD1

PD2

69 68

PD3

PD4

67 66 65 64

34 35 36 37

PD5

PD6

PD7

INT0

BDO

63 62 61

38 39 40

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

NC ENIRQ TXRDY1 SIN0 V

RESET CS2 IOR IOW A0 A1 A2 CS0 DSR0 RI0 DCD0 CTS0 GND NC NC

DTR1

SOUT1

RTS1

DB0

CTS1

DB1

DB2

DB3

DB4

DB5

DB6

DB7

TXRDY0

RTS0

DTR0

SOUT0

description

The TL16C552A is an enhanced dual-channel version of the popular TL16C550B asynchronous communications element (ACE). The device serves two serial input/output interfaces simultaneously in microcomputer or microprocessor-based systems. Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the dual ACE can be read at any time during functional operation by the CPU. The information obtained includes the type and condition of the transfer operations being performed and the error conditions encountered.

In addition to its dual communications interface capabilities, the TL16C552A provides the user with a bidirectional parallel data port that fully supports the parallel Centronics-type printer interface. The parallel port and the two serial ports provide IBM PC/A T-compatible computers with a single device to serve the three system ports. A programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (2

The TL16C552A is available in a 68-pin plastic-leaded chip-carrier (FN) package, a 48-pin TQFP (PN) package, and the 80-pin TQFP (PN) package. The TL16C552AM is available in a 68-pin ceramic quad flat (HV) package.

– 1) is included.

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functional block diagram

TL16C552A, TL16C552AM

DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

A0–A2

IOW

IOR

RESET

CLK

35–33 36 37 39 4

CTS0 DSR0 DCD0

RI0

SIN0

CS0

DB0–DB7

CTS1 DSR1 DCD1

RI1

SIN1

CS1

ERR

SLCT

BUSY

ACK

PEMD

CS2

ENIRQ

28 31 29 30 41 32 14–21

13 5 8 6 62 3

Select

and

Control

Logic

63 65 66 67 68 1 38 43

RTS0

DTR0

ACE

53–46

Parallel

Port

12 11 10 60 61 42

57 56 55 58 59

SOUT0 INT0 RXRDY0 TXRDY0

RTS1 DTR1 SOUT1 INT1 RXRDY1 TXRDY1

BDO

PD0–PD7 INIT AFD STB SLIN INT2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C552A, TL16C552AM

NAME

DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

Terminal Functions

TERMINAL

DESCRIPTION

has an internal pullup resistor to VDD of

terminal has changed states

. When ENIRQ is tied high, the PS-2 mode of interrupt

bit in the line printer status register.

. INT2 is held until the status register is read, which then

has an internal pullup resistor to VDD of

I/O

generates a printer port interrupt during its positive transition. Line printer autofeed. AFD is an open-drain line that provides the printer with an active-low signal when

continuous form paper is to be autofed to the printer. AFD approximately 10 kΩ.

2 for the decode of the serial channels and Table 13 for the decode of the parallel printer port.

port is read. BDO controls the system bus driver (74LS245 or 54LS245).

to accept data.

Chip select. Each CSx input acts as an enable for the write and read signals for serial channels 1 (CS0) and 2 (CS1

register (CTS is bit 4 of the modem status register, written as MSR4) of each ACE. A change of state in either CTS (MSR0) of each modem status register.

control, and status information between the TL16C552A and the CPU. These lines are normally in the high-impedance state except during read operations. DB0 is the least significant bit (LSB) and is the first serial data bit to be received or transmitted.

(DCD) of the modem status registers. MSR3 (∆DCD) of the modem status register indicates whether DCD

Data set ready. The logical state of the DSRx terminals is reflected in MSR5 of its associated modem status register. ∆DSR (MSR1) indicates whether the associated DSRx since the previous reading of the MSR.

Data terminal ready. Each DTRx can be set low by setting MCR0, modem control register bit 0 of its associated ACE. DTRx When active (low), DTRx

In AT mode, INT2 is internally connected to ACK is enabled and INT2 is internally tied to the inverse of the PRINT INT2 is latched high on the rising edge of ACK clears the PRINT

during the error condition. Ground (0 V). All terminals must be tied to GND for proper operation.

allows the printer initialization routine to be started. INIT approximately 10 kΩ.

MCR) goes active (high) when one of the following interrupts has an active (high) condition and is enabled by the interrupt enable register of its associated channel: receiver error flag, received data available, transmitter holding register empty , and modem status. The interrupt is cleared on appropriate service. Upon reset, the interrupt output is in the high-impedance state.

). CS2 enables the signals to the printer port.

terminal since the previous reading of the associated MSR causes the setting of ∆CTS

has changed states since the previous reading of the MSR. DCD has no effect on the receiver.

is cleared (high) by clearing the DTR bit (MCR0) or whenever a reset occurs.

indicates that its ACE is ready to receive data.

status bit and INT2.

NO.

FN PN

ACK 68 10 I Line printer acknowledge. ACK goes low to indicate a successful data transfer has taken place. ACK

AFD 56 75 I/O

A0, A1, A2 35, 34,3351, 50,49I Address. The address lines A0–A2 select the internal registers during CPU bus operations. See T able

BDO 44 63 O Bus buffer. BDO is the active-high output and is asserted when either the serial channel or the parallel

BUSY 66 8 I Line printer busy. BUSY is an input line from the printer that goes high when the printer is not ready

CLK 4 14 I Clock. CLK is the external clock input to the baud rate divisor of each ACE. CS0, CS1,

CS2 CTS0,

CTS1

DB0 – DB7

DCD0, DCD1

DSR0, DSR1

DTR0, DTR1

ENIRQ 43 59 I Parallel port interrupt source mode selection. When ENIRQ is low, the A T mode of interrupts is enabled.

ERR 63 5 I Line printer error. ERR is an input line from the printer. The printer reports an error by holding ERR low

GND 7, 27,5417, 43,

INIT 57 76 I/O Line printer initialize. INIT is an open-drain line that provides the printer with an active-low signal that

INT0, INT1 45, 60 64, 79 O External serial channel interrupt. Each serial channel interrupt 3-state output (enabled by bit 3 of the

32, 3,3848, 13,54I

28, 13 44, 26 I Clear to send. The logical state of each CTSx terminal is reflected in the CTS bit of the modem status

14 – 21 27 – 34 I/O Data bits DB0–DB7. The data bus provides eight I/O lines with 3-state outputs for the transfer of data,

29, 8 45, 18 I Data carrier detect. DCD is a modem input. Its condition can be tested by the CPU by reading MSR7

31, 5 47, 15 I

25, 11 38, 24 O

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TL16C552A, TL16C552AM

NAME

DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

Terminal Functions (Continued)

TERMINAL

NO.

FN PN

INT2 59 78 O Printer port interrupt. INT2 is an active-high, 3-state output generated by the positive transition of

IOR 37 53 I Input/output read strobe. IOR is an active-low input that enables the selected channel to output data

IOW 36 52 I Input/output write strobe. IOW is an active-low input causing data from the data bus to be input to either

PD0–PD7 53–46 72–65 I/O Parallel data bits (0–7). PD0–PD7 provide a byte wide input or output port to the system. PE 67 9 I Line printer paper empty. PE is an input line from the printer that goes high when the printer runs out

PEMD 1 11 I Printer enhancement mode. When low, PEMD enables the write data register to the PD0–PD7 lines.

RESET 39 55 I Reset. When low, RESET forces the TL16C552A into an idle mode in which all serial data activities

RTS0, RTS1

RXRDY0, RXRDY1

RI0, RI1 30, 6 46, 16 I Ring indicator. The RI signal is a modem control input. Its condition is tested by reading MSR6 (RI) of

SIN0, SIN1

SLCT 65 7 I Line printer select. SLCT is an input line from the printer that goes high when the printer is selected. SLIN 58 77 I/O Line printer select. SLIN is an open-drain I/O that selects the printer when active (low). SLIN has an

24, 12 37, 25 O Request to send. The RTS outputs are set low by setting MCR1 of its UARTs modem control register .

9, 61 19, 3 O

41, 62 57, 4 I Serial data. SIN0 and SIN1 move information from the communication line or modem to the

I/O

ACK

. INT2 is enabled by bit 4 of the write control register. Upon reset, INT2 is in the high-impedance

state. Its mode is also controlled by ENIRQ

to the data bus (DB0–DB7). The data output depends on the register selected by the address inputs A0, A1, A2, and chip select. Chip select 0 (CS0 and chip select 2 (CS2

ACE or to the parallel port. The destination depends on the register selected by the address inputs A0, A1, A2, and chip selects CS0

of paper.

A high on PEMD allows direction control of the PD0–PD7 port by the DIR bit in the control register. PEMD is usually tied low for the printer operation.

are suspended. The modem control register and its associated outputs are cleared. The line status register is cleared except for the transmitter holding register empty (THRE) and TEMT bits, which are set. All functions of the device remain in an idle state until programmed to resume serial data activities. RESET

has a hysteresis level of typically 400 mV.

Both RTS transmit. In half-duplex operations, RTS

Receiver ready. Receiver direct memory access (DMA) signaling is also available through this output. One of two types of DMA signaling can be selected using FCR3 when in FIFO mode. Only DMA mode 0 is allowed when in TL16C450 mode. For signal transfer DMA (a transfer is made between CPU bus cycles), mode 0 is used. Multiple transfers that are made continuously until the receiver FIFO has been emptied are supported by mode 1.

Mode 0. RXRDY is active (low) in FIFO mode (FCR0 = 1, FCR3 = 0) or in TL16C450 mode (FCR0 =

0) and the receiver FIFO or receiver holding register contains at least one character. When there are no more characters in the FIFO or holding register, RXRDY

Mode 1. RXRDY goes active (low) in the FIFO mode (FCR0 = 1) when FCR3 = 1 and the time-out or trigger levels have been reached. RXRDY empty.

each ACE. The modem status register output TERI (MSR2) indicates whether RI high to low since the previous reading of the modem status register.

TL16C552A receiver circuits. Mark is a high state and space is a low state. Data on serial data inputs is disabled in loop mode.

internal pullup resistor to VDD of approximately 10 kΩ.

terminals are reset high by RESET. A low on RTS indicates that its ACE has data ready to

) selects the printer port.

, CS1, and CS2.

DESCRIPTION

) selects ACE #1, chip select 1 (CS1) selects ACE #2,

controls the direction of the line.

goes inactive (high).

goes inactive (high) when the FIFO or holding register is

has changed from

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C552A, TL16C552AM

NAME

DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

Terminal Functions (Continued)

TERMINAL

DESCRIPTION

is active (low). Once

goes inactive

I/O

A mark is a high state and a space is a low state. Each SOUT is held in the mark condition when the transmitter is disabled (RESET mode.

is active (low), it provides the printer with a signal to latch the data currently on the parallel port. STB has an internal pullup resistor to VDD of approximately 10 kΩ.

is asserted, all I/Os and outputs are in the high-impedance state, allowing board level testers to drive the outputs without overdriving internal buffers. TRI is level sensitive and is pulled down with an internal resistor that is approximately 5 kΩ.

operating in FIFO mode. Only DMA mode 0 is allowed when in TL16C450 mode. Single-transfer DMA (a transfer is made between CPU bus cycles) is supported by mode 0. Multiple transfers that are made continuously until the transmitter FIFO has been filled are supported by mode 1.

Mode 0. In FIFO mode (FCR0 = 1, FCR3 = 0) or in TL16C450 mode (FCR0 = 0) when there are no characters in the transmitter holding register or transmitter FIFO, TXRDYx TXRDYx of the transmitter FIFO.

Mode 1. TXRDY goes active (low) in FIFO mode (FCR0 = 1) when FCR3 = 1 and there are no characters in the transmitter FIFO. When the transmitter FIFO is completely full, TXRDY (high).

Power supply. The VDD requirement is 5 V ±5%.

is activated (low), it goes inactive after the first character is loaded into the holding register

is asserted low), the transmitter register is empty, or when in the loop

NO.

FN PN

SOUT0, SOUT1

STB 55 74 I/O Line printer strobe. STB provides communication between the TL16C552A and the printer. When STB

TRI 2 12 I 3-state output control input. TRI controls the 3-state control of all I/O and output terminals. When TRI

TXRDY0 TXRDY1

26, 10 39, 23 O Serial data outputs. SOUT0 and SOUT1 are the serial data outputs from the ACE transmitter circuitry .

22, 42 35, 58 O Transmitter ready . T wo types of DMA signaling are available. Either can be selected using FCR3 when

23, 40,646, 36,

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V Input voltage range, V Output voltage range, V

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage levels are with respect to GND.

PACKAGE

FN 1730 mW 19.2 mW/°C 865 mW – HV 1689 mW 13.5 mW/°C 1081 mW 337 mW

‡

Power ratings assume a maximum junction temperature (TJ) of 115°C for ’I’ and 150°C for ’M’ suffix devices.

Derating factor is the inverse of the junction-to-ambient thermal resistance, R

(see Note 1) –0.5 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

: I suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

M suffix –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

DISSIPATION RATING TABLE‡

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 125°C

POWER RATING

θJA

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

Operating free-air temperature, T

°C

PARAMETER

TEST CONDITIONS

UNIT

with chi deselected or

IOZHigh im edance out ut current

5.25 V with chi

±20

µA

No load

IDDSupply current

In uts at 0.8 V or 2 V

clock

MHz

Supply voltage, V Clock high-level input voltage, V Clock low-level input voltage, V High-level input voltage, V Low-level input voltage, V Clock frequency, f

clock

IH(CLK)

IL(CLK)

I suffix –40 85 M suffix –55 125

package thermal characteristics

Junction-to-ambient thermal impedance Board mounted, no air flow 52 74 °C/W

θJA

Junction-to-case thermal impedance 14 3 °C/W

θJC

Junction temperature 115 150 °C/W

TL16C552A, TL16C552AM

DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

MIN NOM MAX UNIT

4.75 5 5.25 V 2 V 0 0.8 V 2 V 0 0.8 V

FN Package HV Package

MIN TYP MAX MIN TYP MAX

16 MHz

electrical characteristics over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

I(CLK)

NOTES: 2. Excluding INIT, AFD, STB, and SLIN. They are open-drain terminals with an internal pullup resistor to VDD of approximately 10 KΩ.

High-level output voltage

Low-level output voltage

Input current Clock input current VI = 0 to 5.25 V ±10 µA

High-impedance output current

3. Excluding the TRI input terminal. It contains an internal pulldown resistor of approximately 5 kΩ.

IOH = –12 mA for PD0–PD7, IOH = –4 mA for all other outputs (see Note 2),

IOL = 12 mA for PD0–PD7, IOL = 12 mA for INIT IOL = 4 mA for all other outputs

VDD = 5.25 V (see Note 3), All other terminals are floating

= 5.25 V,

, AFD, STB, and SLIN,

= 0

p and write mode selected (see Note

= 8

s on outputs,

2.4 V

0.4 V

±10 µA

±20

clock timing requirements over recommended ranges of operating free-air temperature and supply voltage

MIN MAX UNIT

t t t

w1 w2 w3

Pulse duration, CLK ↑ (external clock) (see Figure 1) 31 ns Pulse duration, CLK ↓ (external clock) (see Figure 1) 31 ns Pulse duration, RESET 1000 ns

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TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

read cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Note 4 and Figure 4)

MIN MAX UNIT

su1

su2

NOTES: 4. These parameters are not production tested.

write cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Note 7 and Figure 5)

su4

su5

su6

NOTES: 7. These parameters are not production tested.

Pulse duration, IOR ↓ 80 ns Setup time, CSx valid before IOR ↓ (see Note 5) 15 ns Setup time, A2–A0 valid before IOR ↓ (see Note 5) 15 ns Hold time, A2–A0 valid after IOR ↑ (see Note 5) 20 ns Hold time, CSx valid after IOR ↑ (see Note 5) 20 ns Delay time, t Delay time, IOR ↑ to IOR or IOW ↓ 80 ns

5. The internal address strobe is always active.

6. In FIFO mode, td1 = 425 ns (min) between reads of the receiver FIFO and the status registers (interrupt identification register and line status register).

Pulse duration, IOW ↓ 80 ns Setup time, CSx valid before IOW ↓ (see Note 8) 15 ns Setup time, A2–A0 valid before IOW ↓ (see Note 8) 15 ns Setup time, DB0–DB7 valid before IOW ↑ 15 ns Hold time, A2–A0 valid after IOW ↑ (see Note 8) 20 ns Hold time, CSx valid after IOW ↑ (see Note 8) 20 ns Hold time, DB0–DB7 valid after IOW ↑ 15 ns Delay time, t Delay time, IOW ↑ to IOW or IOR ↓ 80 ns

8. The internal address strobe is always active.

+ tw4 + td2 (see Note 6) 175 ns

su2

MIN MAX UNIT

su5

+ tw5 + t

175 ns

read cycle switching characteristics over recommended ranges of operating free-air temperature and supply voltage, C

Propagation delay time from IOR ↓ to BDO ↑ or from IOR ↑ to BDO ↓ 60 ns

pd1

Enable time from IOR ↓ to DB0–DB7 valid (see Note 10) 60 ns

Disable time from IOR ↑ to DB0–DB7 released (see Note 10) 60 ns

dis

NOTES: 9. These parameters are not production tested.

10. VOL and VOH (and the external loading) determine the charge and discharge time.

= 100 pF (see Note 9 and Figure 4)

PARAMETER MIN MAX UNIT

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TL16C552A, TL16C552AM

DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

transmitter switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Note 11 and Figures 6, 7, and 8)

PARAMETER TEST CONDITIONS MIN MAX UNIT

Delay time, interrupt THRE ↓ to SOUT ↓ at start See Figure 6 8 24

Delay time, SOUT ↓ at start to interrupt THRE ↑ See Note 12 and Figure 6 8 9

Delay time, IOW (WR THR) ↑ to interrupt THRE ↑ See Note 12 and Figure 6 16 32

Delay time, SOUT ↓ at start to TXRDY ↓

Propagation delay time from IOW (WR THR) ↓ to interrupt THRE ↓

pd2

Propagation delay time from IOR (RD IIR) ↑ to interrupt THRE ↓

pd4

Propagation delay time from IOW (WR THR) ↑ to TXRDY ↑

pd5

NOTES: 11. These parameters are not production tested.

12. When the transmitter interrupt delay is active, this delay is lengthened by one character time minus the last stop bit time.

CL = 100 pF, See Figures 7 and 8

CL = 100 pF, See Figure 6

CL = 100 pF, See Figures 7 and 8

RCLK cycles

RCLK

cycles

140 ns

195 ns

receiver switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Note 13 and Figures 9 through 13)

PARAMETER TEST CONDITIONS MIN MAX UNIT

Delay time from stop to INT ↑ See Note 14 1

Propagation delay time from RCLK ↑ to sample CLK ↑ 100 ns

pd6

Propagation delay time from IOR (RD RBR/RD LSR) ↓ to reset interrupt ↓ CL = 100 pF 150 ns

pd7

Propagation delay time from IOR (RD RBR) ↓ to RXRDY ↑ 150 ns

pd8

NOTES: 13. These parameters are not production tested.

14. The receiver data available indicator, the overrun error indicator, the trigger level interrupts, and the active RXRDY delayed three RCLK cycles in FIFO mode (FCR0 = 1). After the first byte has been received, status indicators (PE, FE, BI) are delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after RDRBR goes active. There are eight RCLK cycle delays for trigger change level interrupts.

RCLK

cycle

indicator are

modem control switching characteristics over recommended ranges of operating free-air temperature and supply voltage, C

Propagation delay time from IOW (WR MCR) ↑ to RTS (DTR) ↓↑ 100 ns

pd9

Propagation delay time from modem input (CTS, DSR) ↓↑ to interrupt ↑ 170 ns

pd10

Propagation delay time from IOR (RD MSR) ↑ to interrupt ↓ 140 ns

pd11

Propagation delay time from RI ↑ to interrupt ↑ 170 ns

pd12

NOTE 15: These parameters are not production tested.

= 100 pF (see Note 15 and Figure 14)

PARAMETER MIN MAX UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

parallel port timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 16 and Figures 15, 16, and 17)

MIN MAX UNIT

su7

d10

d11

d12

d13

d14

d15

d16

NOTES: 16. These parameters are not production tested.

Setup time, data valid before STB ↓ 1 µs Hold time, data valid after STB ↑ 1 µs Pulse duration, STB ↓ 1 µs Delay time, BUSY ↑ to ACK ↓ Defined by printer Delay time, BUSY ↓ to ACK ↓ Defined by printer Pulse duration, BUSY ↑ Defined by printer Pulse duration, ACK ↓ Defined by printer Delay time, BUSY ↑ after STB ↑ Defined by printer Delay time, INT2 ↓ after ACK ↓ (see Note 17) 22 ns Delay time, INT2 ↑ after ACK ↑ (see Note 17) 20 ns Delay time, INT2 ↑ after ACK ↑ (see Note 17) 24 ns Delay time, INT2 ↓ after IOR ↑ (see Note 17) 25 ns

17. t

d13–td16

are all measured with a 15-pF load.

PARAMETER MEASUREMENT INFORMATION

CLK (XTAL1)

clock

2 V

0.8 V

= 16 MHz MAX

Figure 1. CLK Voltage Waveform

2.54 V

Device Under T est

TL16C552A

NOTE A: This includes scope and jig capacitance.

Figure 2. Output Load Circuit

2 V

0.8 V

680 Ω

82 pF (see Note A)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C552A, TL16C552AM

DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

PARAMETER MEASUREMENT INFORMATION

TL16C552A

WITH FIFO

A2, A1, A0

, CS1, CS2

CS0

Data Bus

Address Bus

Control Bus

Serial

Channel 1

Buffers

Dual

ACE and

Printer

Port

Option

Jumpers

Serial

Channel 2

Buffers

Parallel

Port

R/C

Network

Figure 3. Basic Test Configuration

50% 50%

su1

su2

Valid

9-Pin D Connector

25-Pin D Connector

IOR

IOW

BDO

DB0–DB7

Active

50% 50%

pd1

50% 50%

Valid Data

Figure 4. Read Cycle Timing Waveforms

dis

pd1

50%

Active

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

PARAMETER MEASUREMENT INFORMATION

A2, A1, A0

CS0, CS1, CS2

DB0–DB7

Serial Out

(SOUT)

Interrupt

(THRE)

IOW

(WR THR)

pd2

IOW

IOR

50% 50%

su4

su5

Valid

Active

50% 50%

su6

Valid Data

50%

Active

Figure 5. Write Cycle Timing Waveforms

50%

50%50%

Start

50% 50% 50%

50%

Data Bits 5–8

50%

Stop (1–2)

Parity

pd2

Start

50%

pd4

IOR

(RD IIR)

IOW

(WR THR)

SOUT

TXRDY

Figure 6. Transmitter Timing Waveforms

Byte #1

50%

ParityData Stop

pd5

50%

Figure 7. Transmitter Ready Mode 0 Timing Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

50%

Start

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TEXAS INSTRUMENTS TL16C552A, TL16C552AM Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual