TEXAS INSTRUMENTS TL16C552 Technical data

查询TL16C552供应商

D

IBM PC/A T Compatible

D

Two TL16C550 ACEs

D

Enhanced Bidirectional Printer Port

D

16-Byte FIFOs Reduce CPU Interrupts

D

Independent Control of Transmit, Receive,
Line Status, and Data Set Interrupts on
Each Channel

D

Individual Modem Control Signals for Each
Channel

description

RXRDY0

DCD1

GND

DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS102B – DECEMBER 1990 – REVISED MARCH 1996

D

Programmable Serial Interface
Characteristics for Each Channel:

– 5-, 6-, 7-, or 8-bit Characters
– Even-, Odd-, or No-Parity Bit Generation

and Detection

– 1-, 1 1/2-, or 2-Stop Bit Generation

D

3-State TTL Drive for the Data and Control
Bus on Each Channel

D

Hardware and Software Compatible With
TL16C452

FN PACKAGE

(TOP VIEW)

DD

ERR

SIN1

RI1

DSR1

CLK

CS1

TRI

ACK

PEMD

PE

BUSY

SLCT

V

RXRDY1

TL16C552

description

SOUT1

DTR1

RTS1

CTS1

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

TXRDY0

V

DD

RTS0

DTR0

SOUT0

87 65493

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

27

28 29

GND

CTS0

31 32 33 34

30

RI0

DCD0

CS0

DSR0

A2A1A0

168672

35 36 37 38 39

IOW

66 65

IOR

CS2

64 63 62 61

40 41 42 43

DD

V

SIN0

RESET

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

ENIRQ

TXRDY1

INT1
INT2
SLIN
INIT
AFD
STB
GND
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
INT0
BDO

The TL16C552 is an enhanced dual channel version of the popular TL16C550 asynchronous communications
element (ACE). The device serves two serial input/output interfaces simultaneously in microcomputer or
microprocessor-based systems. Each channel performs serial-to-parallel conversion on data characters

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

IBM PC/AT is a trademark of International Business Machines Corporation.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1996, Texas Instruments Incorporated

1

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO

SLLS102B – DECEMBER 1990 – REVISED MARCH 1996

description (continued)

received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted
by the CPU. The complete status of each channel of the dual ACE can be read at any time during functional
operation by the CPU. The information obtained includes the type and condition of the transfer operations being
performed and the error conditions.

In addition to its dual communications interface capabilities, the TL16C552 provides the user with a fully
bidirectional parallel data port that fully supports the parallel Centronics-type printer. The parallel port and the
two serial ports provide IBM PC/A T -compatible computers with a single device to serve the three system ports.

A programmable baud rate generator is included that can divide the timing reference clock input by a divisor

16

between 1 and (2

– 1).

The TL16C552 is housed in a 68-pin plastic leaded chip carrier.

functional block diagram

CTS0
DSR0
DCD0

RI0

SIN0

CS0

DB–DB7

CTS1

DSR1
DCD1

RI1

SIN1

CS1

28
31
29
30
41
32

14–21 8

13
5
8
6
62
3

ACE

#1

8

ACE

#2

24
25
26
45

9

22

12
11
10
60
61
42

RTS0
DTR0
SOUT0
INT0
RXRDY0
TXRDY0

RTS1
DTR1
SOUT1
INT1
RXRDY1
TXRDY1

IOW

IOR

CLK

35–33
36
37
39
4

ENIRQ

ERR

SLCT
BUSY

PE

ACK

PEMD

CS2

Select

and

Control

Logic

63
65
66
67
68
1
38
43

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8

Parallel

Port

44

BDO

8

53–46

57
56
55
58
59

PD0–PD7
INIT
AFD
STB
SLIN
INT2

A0–A2

RESET

2

TL16C552

I/O

DESCRIPTION

DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS102B – DECEMBER 1990 – REVISED MARCH 1996

Terminal Functions

TERMINAL

NAME NO.

ACK

AFD

A0, A1, A2 35, 34, 33 I Address lines A0–A2. A0, A1, and A2 select the internal registers during CPU bus operations. See

BDO 44 O Bus buffer output. BDO is an active-high output that is asserted when either serial channel or the

BUSY 66 I Line printer busy. BUSY is an input line from the printer that goes high when the printer is not ready

CLK 4 I Clock input. CLK is an external clock input to the baud rate divisor of each ACE.
CS0, CS1, CS2

CTS0, CTS1

DB0 – DB7 14 – 21 I/O Data bits DB0 – DB7. The data bus provides eight 3-state I/O lines for the transfer of data, control,

DCD0, DCD1

DSR0, DSR1

DTR0, DTR1

ENIRQ

ERR

GND 7, 27, 54 Ground (0 V). All terminals must be tied to ground for proper operation.
INIT

IOR

IOW

68 I

56 I/O

32, 3, 38 I

28, 13 I

29, 8 I

31, 5 I

25, 11 O Data terminal ready lines. DTR0 and DTR1 can be asserted low by setting modem control register

43 I

63 I

57 I/O

37 I

36 I

Line printer acknowledge. ACK goes low to indicate a successful data transfer has taken place.
It generates a printer port interrupt during its positive transition.

Line printer autofeed. AFD is an open-drain line that provides the printer with an active-low signal
when continuous form paper is to be autofed to the printer. This terminal has an internal pullup
resistor to VDD of approximately 10 kΩ.

T able 2 for the decode of the serial channels and T able 13 for the decode of the parallel printer port.

parallel port is read. This output can control the system bus driver (74LS245).

to accept data.

Chip selects. CS0, CS1, and CS2 act as an enable for the write and read signals for the serial
channels 1 (CS0

Clear to send inputs. The logical state of CTS0 or CTS1 is reflected in the CTS bit of the modem
status register (CTS is bit 4 of the modem status register, written MSR4) of each ACE. A change
of state in either CTS
causes the setting of delta clear to send (∆CTS) bit (MSR0) of each modem status register.

and status information between the TL16C552 and the CPU. These lines are normally in a
high-impedance state except during read operations. D0 is the least significant bit (LSB) and is the
first serial data bit to be received or transmitted.

Data carrier detect. DCD is a modem input. Its condition can be tested by the CPU by reading the
MSR7 (DCD) bit of the modem status registers. The MSR3 (delta data carrier detect or ∆DCD) bit
of the modem status register indicates whether the DCD
previous reading of the modem status register. DCD

Data set ready inputs. The logical state of DSR0 and DSR1 is reflected in MSR5 of its associated
modem status register. The MSR1 (delta data set ready or ∆DSR) bit indicates whether the
associated DSR terminal has changed states since the previous reading of the modem status
register.

bit 0 (MCR0) of its associated ACE. This signal is asserted high by clearing the DTR bit (MCR0)
or whenever a reset occurs. When active (low), the DTR terminal indicates that its ACE is ready
to receive data.

Parallel port interrupt source mode selection. When ENIRQ is low, the PC/AT mode of interrupts
is enabled. In this mode, the INT2 output is internally connected to the ACK
input is tied high, the INT2 output is internally tied to the PRINT signal in the line printer status
register. INT2 is latched high on rising edge of ACK

Line printer error. ERR is an input line from the printer . The printer reports an error by holding this
line low during the error condition.

Line printer initialize. INIT is an open-drain line that provides the printer with an active-low signal,
which allows the printer initialization routine to be started. This terminal has an internal pullup
resistor to VDD of approximately 10 kΩ.

Input/output read strobe. IOR is an active-low input that enables the selected channel to output
data to the data bus (DB0 – DB7). The data output depends upon the register selected by the
address inputs A0, A1, A2, and chip select. Chip select 0 (CS0
selects ACE #2, and chip select 2 (CS2

Input/output write strobe. IOW is an active-low input causing data from the data bus to be input to
either ACE or to the parallel port. The destination depends upon the register selected by the address
inputs A0, A1, A2, and chip selects CS0

) and 2 (CS1). CS2 enables the signals to the printer port.

terminal, since the previous reading of the associated modem status register,

input has changed states since the

has no affect on the receiver.

input. When the ENIRQ

.

) selects ACE #1, chip select 1 (CS1)

) selects the printer port.

, CS1, and CS2.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TL16C552

I/O

DESCRIPTION

DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO

SLLS102B – DECEMBER 1990 – REVISED MARCH 1996

Terminal Functions (continued)

TERMINAL

NAME NO.

INT0, INT1 45, 60 O Serial channel interrupts. INT0 and INT1 are 3-state serial channel interrupt outputs (enabled by bit

3 of the MCR) that go active (high) when one of the following interrupts has an active (high) condition
and is enabled by the interrupt enable register of its associated channel: receiver error flag, received
data available, transmitter holding register empty, and modem status. The interrupt is cleared upon
appropriate service. When reset, the interrupt output is in the high-impedance state.

INT2 59 O

PD0–PD7 53–46 I/O Parallel data bits (0–7). These eight lines (PD0–PD7) provide a byte wide input or output port to the

PE 67 I Printer paper empty. PE is an input line from the printer that goes high when the printer runs out of

PEMD 1 I Printer enhancement mode. When low , PEMD enables the write data register to the PD0–PD7 lines.

RESET

RTS0, RTS1

RXRDY0,
RXRDY1

RI0, RI1

SIN0, SIN1 41, 62 I Serial data inputs. SIN0 and SIN1 are serial data inputs that move information from the communication

SLCT 65 I Printer selected. SLCT is an input line from the printer that goes high when the printer has been

SLIN

SOUT0, SOUT1 26, 10 O Serial data outputs. SOUT0 and SOUT1 are the serial data outputs from the ACE transmitter circuitry.

39 I

24, 12 O

9, 61 O

30, 6 I

58 I/O

Printer port interrupt. INT2 is an active-high, 3-state output generated by the positive transition of ACK.
It is enabled by bit 4 of the write control register. Upon a reset, the interrupt output is in the
high-impedance state. Its mode is also controlled by ENIRQ

system.

paper.

A high on this signal allows direction control of the PD0–PD7 port by the DIR bit in the control register .
PEMD is usually tied low for the printer operation.

Reset. When low, RESET forces the TL16C552 into an idle mode in which all serial data activities are
suspended. The modem control register along with its associated outputs are cleared. The line status
register is cleared except for the THRE and TEMT bits, which are set. All functions of the device remain
in an idle state until programmed to resume serial data activities. This input has a hysteresis level of
typically 400 mV .

Request to send outputs. RTSx is asserted low by setting MCR1, bit 1 of its UARTs modem control
register. Both R TSx
data ready to transmit. In half-duplex operations, RTSx

Receiver ready. RXRDY0 and RXRDY1 are receiver direct memory access (DMA) signaling
terminals. One of two types of DMA signaling can be selected using FIFO control register bit 3 (FCR3)
when operating in the FIFO mode. Only DMA mode 0 is allowed when operating in the TL16C450
mode. For signal transfer DMA (a transfer is made between CPU bus cycles), mode 0 is used. Multiple
transfers that are made continuously until the receiver FIFO has been emptied are supported by
mode 1.

Mode 0. RXRDYx is active (low) when in the FIFO mode (FCR0=1, FCR3=0) or when in the TL16C450
mode (FCR0=0) and the receiver FIFO or receiver holding register contain at least one character.
When there are no more characters in the receiver FIFO or receiver holding register, the RXRDYx
terminal goes inactive (high).

Mode 1. RXRDYx goes active (low) in the FIFO mode (FCR0=1) when FCR3=1 and the time-out or
trigger levels have been reached. It goes inactive (high) when the FIFO or receiver holding register is
empty.

Ring indicator inputs. RI0 and RI1 are modem control inputs. Their condition is tested by reading
MSR6 (RI) of each ACE. The modem status register outputs trailing edge of ring indicator (TERI or
MSR2) that indicates whether either input has changed states from high to low since the previous
reading of the modem status register.

line or modem to the TL16C552 receiver circuits. Mark (set) is a high state and a space (cleared) is
low state. Data on the serial data inputs is disabled when operating in the loop mode.

selected.
Line printer select. SLIN is an open-drain input that selects the printer when it is active (low). This

terminal has an internal pullup resistor to VDD of approximately 10 kΩ.

A mark is a high state and a space is a low state. Each SOUT is held in the mark condition when the
transmitter is disabled, when RESET
the loop mode.

terminals are set by RESET . A low on the RTSx terminal indicates that its ACE has

is true (low), when the transmitter register is empty, or when in

.

controls the direction of the line.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C552

I/O

DESCRIPTION

DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS102B – DECEMBER 1990 – REVISED MARCH 1996

Terminal Functions (continued)

TERMINAL

NAME NO.

STB

TRI 2 I 3-state control. TRI controls the 3-state control of all I/O and output terminals. When TRI is asserted,

TXRDY0,
TXRDY1

V

DD

55 I/O

22, 42 O

23, 40, 64 Power supply . VDD is the power supply requirement is 5 V ±5%.

Printer strobe. STB is an open-drain line that provides communication between the TL16C552 and the
printer. When it is active (low), it provides the printer with a signal to latch the data currently on the
parallel port. This terminal has an internal pullup resistor to VDD of approximately 10 kΩ.

all I/O and outputs become high impedance, allowing board level testers to drive the outputs without
overdriving the internal buffers. This terminal is level sensitive, is a CMOS input, and is pulled down
with an internal resistor that is approximately 5 kΩ.

Transmitter ready . TXRDY0 and TXRDY1 are transmitter ready signals. T wo types of DMA signaling
are available. Either can be selected using FCR3 when operating in the FIFO mode. Only DMA mode
0 is allowed when operating in the TL16C450 mode. Single-transfer DMA (a transfer is made between
CPU bus cycles) is supported by mode 0. Multiple transfers that are made continuously until the
transmitter FIFO has been filled are supported by mode 1.

Mode 0. When in the FIFO mode (FCR0=1, FCR3=0) or in the TL16C450 mode (FCR0=0) and there
are no characters in the transmitter holding register or transmitter FIFO, TXRDY

is activated (low), it goes inactive after the first character is loaded into the holding register of

TXRDY
transmitter FIFO.

Mode 1. TXRDYx goes active (low) if in the FIFO mode (FCR0=1) when FCR3=1 and there are no
characters in the transmitter FIFO. When the transmitter FIFO is completely full, TXRDYx
(high).

are active (low). Once

goes inactive

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Output voltage range, V

Continuous total power dissipation 500 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T
Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage levels are with respect to ground (VSS).

(see Note 1) –0.5 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

–0.5 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

–10°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

A

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V
Clock high-level input voltage, V
Clock low-level input voltage, V
High-level input voltage, V
Low-level input voltage, V
Clock frequency, f
Operating free-air temperature range, T

DD

IH(CLK)

IL(CLK)

IH

IL

clock

A

4.75 5 5.25 V
2 V

–0.5 0.8 V

2 V

–0.5 0.8 V

0 70 °C

DD

DD

8 MHz

V

V

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TL16C552

V

DD

V

O

with chi deselected, or

µ

IOZHigh im edance out ut current

V

ith chi

d

±20

µA

DD

,,

IDDSupply current

50

mA

DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO

SLLS102B – DECEMBER 1990 – REVISED MARCH 1996

electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage

PARAMETER TEST CONDITIONS MIN MAX UNIT

IOH = –0.4 mA for DB0–DB7,

V

OH

V

OL

I

I

I

I(CLK)

I

NOTE 2: These four terminals contain an internal pullup resistor to VDD of approximately 10 kΩ.

High-level output voltage

Low-level output voltage

Input current VDD = 5.25 V, All other terminals are floating ±10 µA
Clock input current VI = 0 to 5.25 V ±10 µA

High-impedance output current

pp

IOH = –2 mA for PD0–PD7,
IOH = –0.4 mA for INIT
IOH = –0.4 mA for all other outputs

IOL = 4 mA for DB0–DB7,
IOL = 12 mA for PD0–PD7,
IOL = 10 mA for INIT
IOL = 2 mA for all other outputs

= 5.25 V,

= 5.25 V w

O

V

= 5.25 V , No loads on outputs,
SIN0, SIN1, DSR0, DSR1, DCD0, DCD1, CTS0, CTS1,
RI0 and RI1 at 2 V, Other inputs at 0.8 V,
Baud rate generator f

, AFD, STB, and SLIN (see Note 2),

, AFD, STB, and SLIN (see Note 2),

= 0

p and write mode selecte

= 8 MHz, Baud rate = 56 kbit/s

clock

p

2.4 V

0.4 V

±20

A

clock timing requirements over recommended ranges of operating free-air temperature and supply
voltage

MIN MAX UNIT

t
t
t

w1
w2
w3

Pulse duration, CLK high (external clock, 8 MHz max) (see Figure 1) 55 ns
Pulse duration, CLK low (external clock, 8 MHz max) (see Figure 1) 55 ns
Pulse duration, master (RESET) low (see Figure 16) 1000 ns

read cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 4)

MIN MAX UNIT

t

w4

t

su1

t

su2

t

h1

t

h2

t

d1

t

d2

NOTES: 3. The internal address strobe is always active.

Pulse duration, IOR low 80 ns
Setup time, chip select valid before IOR low (see Note 3) 15 ns
Setup time, A2–A0 valid before IOR low (see Note 3) 15 ns
Hold time, A2–A0 valid after IOR high (see Note 3) 20 ns
Hold time, chip select valid after IOR high (see Note 3) 20 ns
Delay time, t
Delay time, IOR high to IOR or IOW low 80 ns

4. In the FIFO mode, td1 = 425 ns (min) between reads of the receiver FIFO and the status registers (IIR and LSR).

+ tw4 + td2 (see Note 4) 175 ns

su2

6

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TL16C552

DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS102B – DECEMBER 1990 – REVISED MARCH 1996

write cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 5)

MIN MAX UNIT

t

Pulse duration, IOW low 80 ns

w5

t

Setup time, chip select valid before IOW low (see Note 3) 15 ns

su4

t

Setup time, A2–A0 valid before IOW low (see Note 3) 15 ns

su5

t

Setup time, D0–D7 valid before IOW high 15 ns

su6

t

Hold time, A2–A0 valid after IOW high (see Note 3) 20 ns

h3

t

Hold time, chip select valid after IOW high (see Note 3) 20 ns

h4

t

Hold time, D0–D7 valid after IOW high 15 ns

h5

t

Delay time, t

d3

t

Delay time, IOW high to IOW or IOR low 80 ns

d4

NOTE 3: The internal address strobe is always active.

read cycle switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figure 4)

Propagation delay time from IOR high to BDO high or from IOR low to

t

pd1

BDO low

t

Enable time from IOR low to D0–D7 valid CL = 100 pF, See Note 5 60 ns

en

t

Disable time from IOR high to D0–D7 released CL = 100 pF, See Note 5 0 60 ns

dis

NOTE 5: VOL and VOH (and the external loading) determine the charge and discharge time.

su5

+ tw5 + t

d4

PARAMETER TEST CONDITIONS MIN MAX UNIT

CL = 100 pF, See Note 5 60 ns

175 ns

transmitter switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 6, 7, and 8)

PARAMETER TEST CONDITIONS MIN MAX UNIT

t

Delay time, interrupt THRE low to SOUT low at start 8 24

d5

t

Delay time, SOUT low at start to interrupt THRE high See Note 6 8 8

d6

t

Delay time, IOW (WR THR) high to interrupt THRE high See Note 6 16 32

d7

t

Delay time, SOUT low at start to TXRDY low CL = 100 pF 8

d8

t

Propagation delay time from IOW (WR THR) low to interrupt THRE low CL = 100 pF 140 ns

pd2

t

Propagation delay time from IOR (RD IIR) high to interrupt THRE low CL = 100 pF 140 ns

pd3

t

Propagation delay time from IOW (WR THR) high to TXRDY high CL = 100 pF 195 ns

pd4

NOTE 6: When the transmitter interrupt delay is active, this delay si lengthened by one character time minus the last stop bit time.

RCLK
cycles

RCLK
cycles

RCLK
cycles

RCLK
cycles

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7

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO

SLLS102B – DECEMBER 1990 – REVISED MARCH 1996

receiver switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 9, 10, 11, 12 and 13)

PARAMETER TEST CONDITIONS MIN MAX UNIT

t

Delay time from stop to INT high See Note 7 1

d9

t

Propagation delay time from RCLK high to sample CLK high 100 ns

pd5

t

Propagation delay time from IOR (RD RBR/RD LSR) high to reset interrupt low CL = 100 pF 150 ns

pd6

t

Propagation delay time from IOR (RD RBR) low to RXRDY high 150 ns

pd7

NOTE 7: The receiver data available indication, the overrun error indication, the trigger level interrupts and the active RXRDY indication is delayed

three RCLK cycles in the FIFO mode (FCR0 = 1). After the first byte has been received, status indicators (PE, FE, BI) is delayed three
RCLK cycles. These indicators are updated immediately for any further bytes received after RD RBR goes active. There are eight RCLK
cycle delays for trigger change level interrupts.

modem control switching characteristics over recommended ranges of operating free-air
temperature and supply voltage (see Figure 14)

PARAMETER TEST CONDITIONS MIN MAX UNIT

t

Propagation delay time from IOW (WR MCR) high to RTS (DTR) low/high CL = 100 pF 100 ns

pd8

t

Propagation delay time from modem input (CTS, DSR) low/high to interrupt high CL = 100 pF 170 ns

pd9

t

Propagation delay time from IOR (RD MSR) high to interrupt low CL = 100 pF 140 ns

pd10

t

Propagation delay time from RI high to interrupt high CL = 100 pF 170 ns

pd11

RCLK

cycle

parallel port timing requirements over recommended ranges of supply voltage and operating
free-air temperature (see Figure 15)

MIN MAX UNIT

t

su7

t

h6

t

w6

t

d10

t

d11

t

w6

t

w7

t

d12

Setup time, data valid before STB low 1 µs
Hold time, data valid after STB high 1 µs
Pulse duration, STB low 1 500 µs
Delay time, BUSY high to ACK low Defined by printer
Delay time, BUSY low to ACK low Defined by printer
Pulse duration, ACK low Defined by printer
Pulse duration, BUSY high Defined by printer
Delay time, BUSY high after STB high Defined by printer

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT

SLLS102B – DECEMBER 1990 – REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

t

w1

CLK (XTAL1)

t

w2

f

= 8 MHz MAX

clock

Figure 1. Clock Input (CLK) Voltage Waveform

2.54 V

Device Under T est

TL16C552

680 Ω

82 pF

2 V

0.8 V

†

TL16C552

WITH FIFO

Data Bus

Address Bus

Control Bus

Option

Jumpers

†

Includes scope and jig capacitance

Figure 2. Output Load Circuit

TL16C552

Serial

Channel 1

Buffers

Dual

Ace and

Printer

Port

Serial

Channel 2

Buffers

Parallel

Port

R/C

Network

Figure 3. Basic Test Configuration

9-Pin D Connector

9-Pin D Connector

25-Pin D Connector

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO

SLLS102B – DECEMBER 1990 – REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

A2, A1, A0

, CS1, CS2

CS0

IOR

IOW

BDO

Data

D0–D7

50%

Valid

Valid

t

h1

t

h2

t

d1

t

su2

t

su1

50% 50% 50%

t

pd1

t

en

Active

t

w4

Valid Data

Figure 4. Read Cycle Timing Waveforms

t

t

d2

50%50%

dis

50%50%

t

pd1

50%

50%

Active

OR

Active

A2, A1, A0

, CS1, CS2

CS0

IOW

IOR

Data

D0–D7

50%

50% 50%

Valid

Valid

t

su5

t

su4

t

su6

Active

t

w5

Valid Data

50% 50% 50%

Figure 5. Write Cycle Timing Waveforms

50%

t

h3

t

h4

t

d3

Active

t

d4

t

50%

h5

OR

Active

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265