Texas Instruments TL16C550CPTR, TL16C550CPT, TL16C550CPFB, TL16C550CN, TL16C550CIPT Datasheet

...

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Programmable Auto-RTS and Auto-CTS

In Auto-CTS Mode, CTS Controls Transmitter

In Auto-RTS Mode, RCV FIFO Contents and Threshold Control RTS

Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Power Drop

Capable of Running With All Existing TL16C450 Software

After Reset, All Registers Are Identical to the TL16C450 Register Set

Up to 16-MHz Clock Rate for Up to 1-Mbaud Operation

In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data

Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (2

–1) and Generates an Internal 16×

Clock

Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream

5-V and 3.3-V Operation

Independent Receiver Clock Input

Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled

Fully Programmable Serial Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation

and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (dc to 1 Mbit/s)

False-Start Bit Detection

Complete Status Reporting Capabilities

3-State Output TTL Drive Capabilities for Bidirectional Data Bus and Control Bus

Line Break Generation and Detection

Internal Diagnostic Capabilities: – Loopback Controls for Communications

Link Fault Isolation – Break, Parity, Overrun, and Framing

Error Simulation

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR, DTR

, RI, and DCD)

description

The TL16C550C and the TL16C550CI are functional upgrades of the TL16C550B asynchronous communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the TL16C550C and the TL16C550CI, like the TL16C550B, can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow using RTS

output and CTS input signals.

The TL16C550C and TL16C550CI perform serial-to-parallel conversions on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE status at any time. The ACE includes complete modem control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.

Both the TL16C550C and the TL16C550CI ACE include a programmable baud rate generator capable of dividing a reference clock by divisors from 1 to 65535 and producing a 16 × reference clock for the internal transmitter logic. Provisions are included to use this 16× clock for the receiver logic. The ACE accommodates a 1-Mbaud serial rate (16-MHz input clock) so that a bit time is 1 µs and a typical character time is 10 µs (start bit, 8 data bits, stop bit).

Two of the TL16C450 terminal functions on the TL16C550C and the TL16C550CI have been changed to TXRDY

and RXRDY, which provide signaling to a DMA controller.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D0 D1 D2 D3 D4 D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

XIN

XOUT

WR1 WR2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

RI DCD DSR CTS MR OUT1 DTR RTS OUT2 INTRPT RXRDY A0 A1 A2 ADS TXRDY DDIS RD2 RD1

N PACKAGE

(TOP VIEW)

MR OUT1 DTR RTS OUT2 NC INTRPT RXRDY A0 A1 A2

39 38 37 36 35 34 33 32 31 30 29

1819

7 8 9 10 11 12 13 14 15 16 17

D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

20 21 22 23

DCD

DSR

CTS

54 321644

D4D3D2D1D0NCV

RD2

DDIS

TXRDY

ADS

XIN

XOUT

WR1

WR2

RD1

42 41 4043

24 25 26 27 28

NC–No internal connection

FN PACKAGE

(TOP VIEW)

14 15

NC MR OUT1 DTR RTS OUT2 INTRPT RXRDY A0 A1 A2 NC

36 35 34 33 32 31 30 29 28 27 26 25

1 2 3 4 5 6 7 8 9 10 11 12

D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

17 18 19 20

PT/PFB PACKAGE

(TOP VIEW)

DCD

DSR

CTS

47 46 45 44 4348 42

NCD4D3D2D1

DDIS

TXRDY

ADS

XOUT

WR1

WR2

RD1

RD2

40 39 3841

22 23 24

XIN

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

autoflow control (see Figure 1)

Autoflow control is comprised of auto-CTS

and auto-RTS. With auto-CTS, the CTS input must be active before

the transmitter FIFO can emit data. With auto-RTS

, RTS becomes active when the receiver needs more data

and notifies the sending serial device. When RTS

is connected to CTS, data transmission does not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a TLC16C550C with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds the receiver FIFO read latency.

RCV FIFO

Serial to

Parallel

Flow

Control

XMT FIFO

Parallel

to Serial

Flow

Control

Parallel

to Serial

Flow

Control

Serial to

Parallel

Flow

Control

XMT FIFO

RCV FIFO

ACE1 ACE2

D7–D0

SIN SOUT

RTS

CTS

SOUT SIN

CTS

RTS

D7–D0

Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example

auto-RTS (see Figure 1)

Auto-RTS

data flow control originates in the receiver timing and control block (see functional block diagram) and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of 1, 4, or 8 (see Figure 3), RTS

is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because it may not recognize the deassertion of RTS

until after it has begun sending the additional byte. RTS

is automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register. When the trigger level is 14 (see Figure 4), RTS

is deasserted after the first data bit of the 16th character is

present on the SIN line. RTS

is reasserted when the RCV FIFO has at least one available byte space.

auto-CTS

(see Figure 1)

The transmitter circuitry checks CTS

before sending the next data byte. When CTS is active, it sends the next

byte. To stop the transmitter from sending the following byte, CTS

must be released before the middle of the

last stop bit that is currently being sent (see Figure 2). The auto-CTS

function reduces interrupts to the host

system. When flow control is enabled, CTS

level changes do not trigger host interrupts because the device

automatically controls its own transmitter. Without auto-CTS

, the transmitter sends any data present in the

transmit FIFO and a receiver overrun error may result.

enabling autoflow control and auto-CTS

Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to a 1. Autoflow incorporates both auto-RTS

and auto-CTS. When only auto-CTS is desired, bit 1 in the modem

control register should be cleared (this assumes that a control signal is driving CTS

TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

auto-CTS and auto-RTS functional timing

Start Bits 0–7 Start Bits 0–7 Start Bits 0–7

Stop Stop Stop

SOUT

CTS

NOTES: A. When CTS is low, the transmitter keeps sending serial data out.

B. If CTS

goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but it does

not send the next byte.

C. When CTS

goes from high to low, the transmitter begins sending data again.

Figure 2. CTS Functional Timing Waveforms

The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figures 3 and 4.

Start Byte N Start Byte N+1 Start Byte

Stop Stop Stop

SIN

RTS

(RD RBR)

N N+1

NOTES: A. N = RCV FIFO trigger level (1, 4, or 8 bytes)

B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS

section.

Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1,4, or 8 Bytes

Byte 14 Byte 15

SIN

RTS

(RD RBR)

Start Byte 18 StopStart Byte 16 Stop

RTS Released After the

First Data Bit of Byte 16

NOTES: A. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the

sixteenth byte.

B. RTS

is asserted again when there is at least one byte of space available and no incoming byte is in processing or there is more than

one byte of space available.

C. When the receive FIFO is full, the first receive buffer register read reasserts RTS

Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Receiver

Buffer

Divisor

Latch (LS)

Divisor

Latch (MS)

Baud

Generator

Receiver

FIFO

Line

Status

Transmitter

Holding

Modem Control

Modem

Status

Line

Control

Transmitter

FIFO

Interrupt

Enable

Interrupt

Identification

FIFO

Control

Select

and

Control

Logic

Interrupt

Control

Logic

S e

l e c

Data

Bus

Buffer

BAUDOUT

SIN

RCLK

SOUT

CTS DTR DSR DCD RI OUT1 OUT2 INTRPT

36 33 37 38 39 34 31

D(7–0)

8–1

Internal Data Bus

27 26

13 14

25 35 21

22 18 19 23 24 16 17 29

A1 A2

CS0 CS1 CS2

ADS

MR RD1 RD2

WR1 WR2

DDIS

TXRDY

XIN

XOUT

RXRDY

S e

l e c

Receiver

Shift

Receiver

Timing and

Control

Transmitter

Timing and

Control

Transmitter

Shift

Modem

Control

Logic

40 20

Power Supply

RTS

Autoflow Control (AFE)

NOTE A: Terminal numbers shown are for the N package.

TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME

NO.NNO.FNNO.

I/O

DESCRIPTION

A0 A1 A2

28 27 26

31 30 29

28 27 26

I Register select. A0–A2 are used during read and write operations to select the ACE register to read

from or write to. Refer to Table 1 for register addresses and refer to ADS

description.

ADS 25 28 24 I Address strobe. When ADS is active (low), A0, A1, and A2 and CS0, CS1, and CS2 drive the internal

select logic directly; when ADS

is high, the register select and chip select signals are held at the logic

levels they were in when the low-to-high transition of ADS

occurred.

BAUDOUT 15 17 12 O Baud out. BAUDOUT is a 16 × clock signal for the transmitter section of the ACE. The clock rate is

established by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT

may also be used for the receiver section by tying this output to RCLK.

CS0 CS1 CS2

12 13 14

14 15 16

I Chip select. When CS0 and CS1 are high and CS2 is low, these three inputs select the ACE. When any

of these inputs are inactive, the ACE remains inactive (refer to ADS

description).

CTS 36 40 38 I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of

the modem status register. Bit 0 (∆CTS) of the modem status register indicates that CTS

has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS

changes levels and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used

in the auto-CTS

mode to control the transmitter.

D0 D1 D2 D3 D4 D5 D6 D7

1 2 3 4 5 6 7 8

2 3 4 5 6 7 8 9

43 44 45 46 47

2 3 4

I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status

information between the ACE and the CPU.

DCD 38 42 40 I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD)

of the modem status register. Bit 3 (∆ DCD) of the modem status register indicates that DCD

has changed states since the last read from the modem status register. If the modem status interrupt is enabled when DCD

changes levels, an interrupt is generated.

DDIS 23 26 22 O Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDIS can disable

an external transceiver.

DSR 37 41 39 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of

the modem status register. Bit 1 (∆ DSR) of the modem status register indicates DSR

has changed levels since the last read from the modem status register. If the modem status interrupt is enabled when DSR

changes levels, an interrupt is generated.

DTR 33 37 33 O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to

establish communication. DTR

is placed in the active level by setting the DTR bit of the modem control

is placed in the inactive level either as a result of a master reset, during loop mode

operation, or clearing the DTR bit.

INTRPT 30 33 30 O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced.

Four conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INTRPT is reset (deactivated) either when the interrupt is serviced or as a result of a master reset.

MR 35 39 35 I Master reset. When active (high), MR clears most ACE registers and sets the levels of various output

signals (refer to Table 2).

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME

NO.NNO.FNNO.

I/O

DESCRIPTION

OUT1 OUT2

343138353431O Outputs 1 and 2. These are user-designated output terminals that are set to the active (low) level by

setting respective modem control register (MCR) bits (OUT1 and OUT2). OUT1

and OUT2 are set to inactive the (high) level as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR.

RCLK 9 10 5 I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE. RD1

RD2

212224251920I Read inputs. When either RD1 or RD2 is active (low or high respectively) while the ACE is selected,

the CPU is allowed to read status information or data from a selected ACE register. Only one of these inputs is required for the transfer of data during a read operation; the other input should be tied to its inactive level (i.e., RD2 tied low or RD1

tied high).

RI 39 43 41 I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the

modem status register. Bit 2 (TERI) of the modem status register indicates that RI

has transitioned from a low to a high level since the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated.

RTS 32 36 32 O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive

data. RTS

is set to the active level by setting the RTS modem control register bit and is set to the inactive (high) level either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR. In the auto-RTS

mode, RTS is set to the inactive level by the receiver threshold control logic.

RXRDY 29 32 29 O Receiver ready. Receiver direct memory access (DMA) signalling is available with RXRDY. When

operating in the FIFO mode, one of two types of DMA signalling can be selected using the FIFO control register bit 3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is at least one character in the receiver FIFO or receiver holding register, RXRDY

is active (low). When RXRDY has been active

but there are no characters in the FIFO or holding register, RXRDY

goes inactive (high). In DMA mode 1

(FCR0 = 1, FCR3 = 1), when the trigger level or the time-out has been reached, RXRDY

goes active (low); when it has been active but there are no more characters in the FIFO or holding register, it goes inactive (high).

SIN 10 11 7 I Serial data input. SIN is serial data input from a connected communications device SOUT 11 13 8 O Serial data output. SOUT is composite serial data output to a connected communication device. SOUT

is set to the marking (high) level as a result of master reset.

TXRDY 24 27 23 O Transmitter ready. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO

mode, one of two types of DMA signalling can be selected using FCR3. When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit FIFO has been filled.

40 44 42 5-V supply voltage

20 22 18 Supply common

WR1 WR2

181920211617I Write inputs. When either WR1 or WR2 is active (low or high respectively) and while the ACE is

selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer data during a write operation; the other input should be tied to its inactive level (i.e., WR2 tied low or WR1

tied high).

XIN XOUT

161718191415I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range at any input, V

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

, TL16C550C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TL16C550CI –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 10 seconds, T

: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N or PT package 260°C. . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions

low voltage (3.3 V nominal)

MIN NOM MAX UNIT

Supply voltage, V

3 3.3 3.6 V

Input voltage, V

0 V

High-level input voltage, VIH (see Note 2) 0.7 V

Low-level input voltage, VIL (see Note 2) 0.3 V

Output voltage, VO (see Note 3) 0 V

V High-level output current, IOH (all outputs) 1.8 mA Low-level output current, IOL (all outputs) 3.2 mA Input capacitance 1 pF Operating free-air temperature, T

0 25 70 °C Junction temperature range, TJ (see Note 4) 0 25 115 °C Oscillator/clock speed 14 MHz NOTES: 2. Meets TTL levels, V

IHmin

= 2 V and V

ILmax

= 0.8 V on nonhysteresis inputs

3. Applies for external output buffers

4. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is responsible for verifying junction temperature.

standard voltage (5 V nominal)

MIN NOM MAX UNIT

Supply voltage, V

4.75 5 5.25 V

Input voltage, V

0 V

High-level input voltage, V

0.7 V

Low-level input voltage, V

0.2 V

Output voltage, VO (see Note 5) 0 V

V High-level output current, IOH (all outputs) 4 mA Low-level output current, IOL (all outputs) 4 mA Input capacitance 1 pF Operating free-air temperature, T

0 25 70 °C Junction temperature range, TJ (see Note 6) 0 25 115 °C Oscillator/clock speed 16 MHz

5. Applies for external output buffers

6. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is responsible for verifying junction temperature.

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

low voltage (3.3 V nominal)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

‡

High-level output voltage IOH = –1 mA 2.4 V

‡

Low-level output voltage IOL = 1.6 mA 0.5 V

= 3.6 V, V

= 0,

IlInput current

VI = 0 to 3.6 V,

All other terminals floating

10µA

= 3.6 V

= 0

High-impedance-state output current

3.6 V, V

VO = 0 to 3.6 V,

±20 µA

Chip selected in write mode or chip deselect

= 3.6 V,

25 C

Supply current

SIN, DSR, DCD, CTS, and RI at 2 V

8mA

ICCSu ly current

All oth

er inputs at 0.8 V,

XTAL1 at 4 MH

No load on outputs, Baud rate = 50 kbit/s

i(CLK)

Clock input capacitance 15 20 pF

o(CLK)

Clock output capacitance

VCC = 0, VSS = 0,

20 30 pF

Input capacitance

= 1

MHz

25°C

All other terminals

rounded

6 10 pF

Output capacitance

All other terminals grounded

10 20 pF

†

All typical values are at VCC = 3.3 V and TA = 25°C.

‡

These parameters apply for all outputs except XOUT.

standard voltage (5 V nominal)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

‡

High-level output voltage IOH = –1 mA 2.4 V

‡

Low-level output voltage IOL = 1.6 mA 0.4 V

= 5.25 V , V

= 0,

IlInput current

VI = 0 to 5.25 V,

All other terminals floating

10µA

= 5.25 V

= 0

High-impedance-state output current

5.25 V, V

VO = 0 to 5.25 V,

±20 µA

Chip selected in write mode or chip deselect

= 5.25 V,

25 C

Supply current

SIN, DSR, DCD, CTS, and RI at 2 V

10 mA

ICCSu ly current

All oth

er inputs at 0.8 V,

XTAL1 at 4 MH

No load on outputs, Baud rate = 50 kbit/s

i(CLK)

Clock input capacitance 15 20 pF

o(CLK)

Clock output capacitance

VCC = 0, VSS = 0,

20 30 pF

Input capacitance

= 1

MHz

25°C

All other terminals

rounded

6 10 pF

Output capacitance

All other terminals grounded

10 20 pF

†

All typical values are at VCC = 5 V and TA = 25°C.

‡

These parameters apply for all outputs except XOUT.

TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

system timing requirements over recommended ranges of supply voltage and operating free-air temperature

ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

Cycle time, read (tw7 + td8 + td9) RC 87 ns

Cycle time, write (tw6 + td5 + td6) WC 87 ns

Pulse duration, clock high t

f = 16 MHz Max

Pulse duration, clock low t

f 16 MHz Max,

VCC = 5 V

Pulse duration, ADS low t

ADS

6, 7 9 ns

Pulse duration, WR t

6 40 ns

Pulse duration, RD t

7 40 ns

Pulse duration, MR t

1 µs

su1

Setup time, address valid before ADS↑ t

su2

Setup time, CS valid before ADS↑ t

6, 78ns

su3

Setup time, data valid before WR1↓ or WR2↑ t

6 15 ns

su4

Setup time, CTS↑ before midpoint of stop bit 17 10 ns

Hold time, address low after ADS↑ t

Hold time, CS valid after ADS↑ t

6, 70ns

Hold time, CS valid after WR1↑ or WR2↓ t

WCS

Hold time, address valid after WR1↑ or WR2↓ t

610ns

Hold time, data valid after WR1↑ or WR2↓ t

6 5 ns

Hold time, chip select valid after RD1↑ or RD2↓ t

RCS

7 10 ns

Hold time, address valid after RD1↑ or RD2↓ t

7 20 ns

†

Delay time, CS valid before WR1↓ or WR2↑ t

CSW

†

Delay time, address valid before WR1↓ or WR2↑ t

67ns

†

Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ t

6 40 ns

†

Delay time, CS valid to RD1↓ or RD2↑ t

CSR

†

Delay time, address valid to RD1↓ or RD2↑ t

77ns

Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ tRC 7 40 ns

d10

Delay time, RD1↓ or RD2↑ to data valid t

RVD

7 CL = 75 pF 45 ns

d11

Delay time, RD1↑ or RD2↓ to floating data t

7 CL = 75 pF 20 ns

†

Only applies when ADS is low

system switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 7)

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

dis(R)

Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ t

RDD

7 CL = 75 pF 20 ns

NOTE 7: Charge and discharge times are determined by VOL, VOH, and external loading.

baud generator switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C

= 75 pF

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

Pulse duration, BAUDOUT low t

f = 16 MHz, CLK ÷ 2

Pulse duration, BAUDOUT high t

f 16 MHz, CLK

VCC = 5 V

Delay time, XIN↑ to BAUDOUT↑ t

BLD

5 45 ns

Delay time, XIN↑↓ to BAUDOUT↓ t

BHD

5 45 ns

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

receiver switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 8)

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

d12

Delay time, RCLK to sample t

SCD

8 10 ns

d13

Delay time, stop to set INTRPT or read RBR to LSI interrupt or stop to RXRDY

↓

SINT

8, 9, 10,

11, 12

RCLK

cycle

d14

Delay time, read RBR/LSR to reset INTRPT t

RINT

8, 9, 10,

11, 12

CL = 75 pF 70 ns

NOTE 8: In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receive FIFO and the status registers (interrupt identification

transmitter switching characteristics over recommended ranges of supply voltage and operating free-air temperature

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

d15

Delay time, initial write to transmit start t

IRS

13 8 24

baudout

cycles

d16

Delay time, start to INTRPT t

STI

13 8 10

baudout

cycles

d17

Delay time, WR (WR THR) to reset INTRPT t

13 CL = 75 pF 50 ns

d18

Delay time, initial write to INTRPT (THRE†) t

13 16 34

baudout

cycles

d19

Delay time, read IIR† to reset INTRPT

(THRE†)

13 CL = 75 pF 35 ns

d20

Delay time, write to TXRDY inactive t

WXI

14,15 CL = 75 pF 35 ns

d21

Delay time, start to TXRDY active

SXA

14,15 CL = 75 pF 9

baudout

cycles

†

THRE = transmitter holding register empty; IIR = interrupt identification register.

modem control switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C

= 75 pF

PARAMETER ALT. SYMBOL FIGURE MIN MAX UNIT

d22

Delay time, WR MCR to output t

MDO

16 50 ns

d23

Delay time, modem interrupt to set INTRPT t

SIM

16 35 ns

d24

Delay time, RD MSR to reset INTRPT t

RIM

16 40 ns

d25

Delay time, CTS low to SOUT↓ 17 24

baudout

cycles

d26

Delay time, RCV threshold byte to RTS↑ 18 2

baudout

cycles

d27

Delay time, read of last byte in receive FIFO to RTS↓ 18 2

baudout

cycles

d28

Delay time, first data bit of 16th character to RTS↑ 19 2

baudout

cycles

d29

Delay time, RBRRD low to RTS↓ 19 2

baudout

cycles

TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

BAUDOUT

(1/1)

XIN

BAUDOUT

(1/2)

BAUDOUT

(1/3)

BAUDOUT

(1/N)

(N > 3)

2 XIN Cycles

(N–2) XIN Cycles

Figure 5. Baud Generator Timing Waveforms

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