TEXAS INSTRUMENTS TL16C550C, TL16C550CI Technical data

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Programmable Auto-RTS and Auto-CTS

In Auto-CTS Mode, CTS Controls Transmitter

In Auto-RTS Mode, RCV FIFO Contents and Threshold Control RTS

Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Power Drop

Capable of Running With All Existing TL16C450 Software

After Reset, All Registers Are Identical to the TL16C450 Register Set

Up to 16-MHz Clock Rate for Up to 1-Mbaud Operation

In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data

Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1

to (2 Clock

Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream

description

–1) and Generates an Internal 16×

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

5-V and 3.3-V Operation

Independent Receiver Clock Input

Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled

Fully Programmable Serial Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation

and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (dc to 1 Mbit/s)

False-Start Bit Detection

Complete Status Reporting Capabilities

3-State Output TTL Drive Capabilities for Bidirectional Data Bus and Control Bus

Line Break Generation and Detection

Internal Diagnostic Capabilities: – Loopback Controls for Communications

Link Fault Isolation – Break, Parity, Overrun, and Framing

Error Simulation

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR, DTR

, RI, and DCD)

The TL16C550C and the TL16C550CI are functional upgrades of the TL16C550B asynchronous communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the TL16C550C and the TL16C550CI, like the TL16C550B, can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow using RTS

The TL16C550C and TL16C550CI perform serial-to-parallel conversions on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE status at any time. The ACE includes complete modem control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.

Both the TL16C550C and the TL16C550CI ACE include a programmable baud rate generator capable of dividing a reference clock by divisors from 1 to 65535 and producing a 16 × reference clock for the internal transmitter logic. Provisions are included to use this 16× clock for the receiver logic. The ACE accommodates a 1-Mbaud serial rate (16-MHz input clock) so that a bit time is 1 µs and a typical character time is 10 µs (start bit, 8 data bits, stop bit).

Two of the TL16C450 terminal functions on the TL16C550C and the TL16C550CI have been changed to TXRDY

and RXRDY, which provide signaling to a DMA controller.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

output and CTS input signals.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

D0 D1 D2 D3 D4 D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

XIN

XOUT

WR1 WR2

N PACKAGE

(TOP VIEW)

RI DCD DSR CTS MR OUT1 DTR RTS OUT2 INTRPT RXRDY A0 A1 A2 ADS TXRDY DDIS RD2 RD1

D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

FN PACKAGE

(TOP VIEW)

D4D3D2D1D0NCV

54 321644

7 8 9 10 11 12 13 14 15 16 17

1819

XIN

XOUT

20 21 22 23

WR1

WR2

24 25 26 27 28

RD2

RD1

DCD

42 41 4043

DDIS

DSR

CTS

OUT1

DTR

RTS

OUT2

INTRPT

RXRDY

ADS

TXRDY

SOUT

BAUDOUT

NC–No internal connection

D5 D6 D7

RCLK

SIN

CS0 CS1 CS2

NCD4D3D2D1

47 46 45 44 4348 42

1 2 3 4 5 6 7 8 9 10 11 12

14 15

PT/PFB PACKAGE

(TOP VIEW)

17 18 19 20

WR1

WR2

XIN

XOUT

RD1

40 39 3841

RD2

DCD

DSR

22 23 24

DDIS

CTS

36 35 34 33 32 31 30 29 28 27 26 25

ADS

TXRDY

NC MR OUT1 DTR RTS OUT2 INTRPT RXRDY A0 A1 A2 NC

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detailed description

autoflow control (see Figure 1)

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

Autoflow control is comprised of auto-CTS the transmitter FIFO can emit data. With auto-RTS and notifies the sending serial device. When RTS

and auto-RTS. With auto-CTS, the CTS input must be active before

, RTS becomes active when the receiver needs more data

is connected to CTS, data transmission does not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a TLC16C550C with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds the receiver FIFO read latency.

ACE1 ACE2

SIN SOUT

RTS

SOUT SIN

CTS

RTS

Parallel

to Serial

XMT

FIFO

Flow

Control

Serial to

Parallel

RCV

FIFO

Flow

Control

D7–D0

RCV

FIFO

XMT

FIFO

Serial to

Parallel

Flow

Control

Parallel

to Serial

Flow

Control

Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example

auto-RTS (see Figure 1)

D7–D0

Auto-RTS

data flow control originates in the receiver timing and control block (see functional block diagram) and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of 1, 4, or 8 (see Figure 3), RTS

is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because it may not recognize the deassertion of RTS

until after it has begun sending the additional byte. RTS

is automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register. When the trigger level is 14 (see Figure 4), RTS

present on the SIN line. RTS

auto-CTS

(see Figure 1)

The transmitter circuitry checks CTS

is reasserted when the RCV FIFO has at least one available byte space.

before sending the next data byte. When CTS is active, it sends the next byte. To stop the transmitter from sending the following byte, CTS last stop bit that is currently being sent (see Figure 2). The auto-CTS system. When flow control is enabled, CTS automatically controls its own transmitter. Without auto-CTS

is deasserted after the first data bit of the 16th character is

must be released before the middle of the

function reduces interrupts to the host

level changes do not trigger host interrupts because the device

, the transmitter sends any data present in the

transmit FIFO and a receiver overrun error may result.

enabling autoflow control and auto-CTS

Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to a 1. Autoflow incorporates both auto-RTS control register should be cleared (this assumes that a control signal is driving CTS

and auto-CTS. When only auto-CTS is desired, bit 1 in the modem

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TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

auto-CTS and auto-RTS functional timing

SOUT

CTS

NOTES: A. When CTS is low, the transmitter keeps sending serial data out.

B. If CTS

C. When CTS

Start Bits 0–7 Start Bits 0–7 Start Bits 0–7

goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but it does

not send the next byte.

goes from high to low, the transmitter begins sending data again.

Stop Stop Stop

Figure 2. CTS Functional Timing Waveforms

The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figures 3 and 4.

SIN

RTS

(RD RBR)

NOTES: A. N = RCV FIFO trigger level (1, 4, or 8 bytes)

B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS

Start Byte N Start Byte N+1 Start Byte

Stop Stop Stop

N N+1

Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1,4, or 8 Bytes

section.

SIN

RTS

(RD RBR)

NOTES: A. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the

sixteenth byte.

B. RTS

is asserted again when there is at least one byte of space available and no incoming byte is in processing or there is more than

one byte of space available.

C. When the receive FIFO is full, the first receive buffer register read reasserts RTS

Byte 14 Byte 15

RTS Released After the

First Data Bit of Byte 16

Start Byte 18 StopStart Byte 16 Stop

Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes

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functional block diagram

Data

Bus

Buffer

Select

and

Logic

Power Supply

D(7–0)

A0 A1 A2

CS0 CS1 CS2

ADS

MR RD1 RD2

WR1 WR2

DDIS

TXRDY

XIN

XOUT

RXRDY

8–1

28 27

12 13

14 25

35 21

22 18

19 23 24 16 17 29

40 20

Internal Data Bus

Control

S e

l e c

Receiver

Buffer

Line

Control

Divisor

Latch (LS)

Divisor

Latch (MS)

Line

Status

Transmitter

Holding

Modem

Control

Modem

Status

Interrupt

Enable

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

Receiver

FIFO

Transmitter

FIFO

Interrupt

Control

Logic

Baud

Generator

Receiver

Shift

Receiver

Timing and

Control

Transmitter

Timing and

Control

S e

l e c

Transmitter

Shift

Modem

Control

Logic

BAUDOUT

Autoflow Control (AFE)

36 33 37 38 39 34 31

SIN

RCLK

RTS

SOUT

CTS DTR DSR DCD RI OUT1 OUT2 INTRPT

Interrupt

Identification

FIFO

Control

NOTE A: Terminal numbers shown are for the N package.

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TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

Terminal Functions

TERMINAL

NAME

A0 A1 A2

ADS 25 28 24 I Address strobe. When ADS is active (low), A0, A1, and A2 and CS0, CS1, and CS2 drive the internal

BAUDOUT 15 17 12 O Baud out. BAUDOUT is a 16× clock signal for the transmitter section of the ACE. The clock rate is

CS0 CS1 CS2

CTS 36 40 38 I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of

D0 D1 D2 D3 D4 D5 D6 D7

DCD 38 42 40 I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD)

DDIS 23 26 22 O Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDIS can disable

DSR 37 41 39 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of

DTR 33 37 33 O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to

INTRPT 30 33 30 O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced.

MR 35 39 35 I Master reset. When active (high), MR clears most ACE registers and sets the levels of various output

NO.NNO.FNNO.

I/O

I Register select. A0–A2 are used during read and write operations to select the ACE register to read 27 26

43 44 45 46 47

2 3 4

from or write to. Refer to Table 1 for register addresses and refer to ADS

select logic directly; when ADS levels they were in when the low-to-high transition of ADS

established by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT

I Chip select. When CS0 and CS1 are high and CS2 is low , these three inputs select the ACE. When any

of these inputs are inactive, the ACE remains inactive (refer to ADS

the modem status register. Bit 0 (∆CTS) of the modem status register indicates that CTS states since the last read from the modem status register. If the modem status interrupt is enabled when CTS

changes levels and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used

in the auto-CTS

I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status

information between the ACE and the CPU.

of the modem status register. Bit 3 (∆ DCD) of the modem status register indicates that DCD changed states since the last read from the modem status register. If the modem status interrupt is enabled when DCD

an external transceiver.

the modem status register. Bit 1 (∆ DSR) of the modem status register indicates DSR levels since the last read from the modem status register. If the modem status interrupt is enabled when DSR

changes levels, an interrupt is generated.

establish communication. DTR register. DTR operation, or clearing the DTR bit.

Four conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INTRPT is reset (deactivated) either when the interrupt is serviced or as a result of a master reset.

signals (refer to Table 2).

mode to control the transmitter.

changes levels, an interrupt is generated.

is placed in the inactive level either as a result of a master reset, during loop mode

is high, the register select and chip select signals are held at the logic

may also be used for the receiver section by tying this output to RCLK.

is placed in the active level by setting the DTR bit of the modem control

DESCRIPTION

description.

occurred.

description).

has changed

has

has changed

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

Terminal Functions (Continued)

TERMINAL

NAME

OUT1 OUT2

RCLK 9 10 5 I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE. RD1

RD2

RI 39 43 41 I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the

RTS 32 36 32 O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive

RXRDY 29 32 29 O Receiver ready. Receiver direct memory access (DMA) signalling is available with RXRDY. When

SIN 10 11 7 I Serial data input. SIN is serial data input from a connected communications device SOUT 11 13 8 O Serial data output. SOUT is composite serial data output to a connected communication device. SOUT

TXRDY 24 27 23 O Transmitter ready. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO

WR1 WR2

XIN XOUT

NO.NNO.FNNO.

343138353431O Outputs 1 and 2. These are user-designated output terminals that are set to the active (low) level by

212224251920I Read inputs. When either RD1 or RD2 is active (low or high respectively) while the ACE is selected,

40 44 42 5-V supply voltage 20 22 18 Supply common 181920211617I Write inputs. When either WR1 or WR2 is active (low or high respectively) and while the ACE is

161718191415I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

I/O

setting respective modem control register (MCR) bits (OUT1 and OUT2). OUT1 inactive the (high) level as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR.

the CPU is allowed to read status information or data from a selected ACE register. Only one of these inputs is required for the transfer of data during a read operation; the other input should be tied to its inactive level (i.e., RD2 tied low or RD1

modem status register. Bit 2 (TERI) of the modem status register indicates that RI a low to a high level since the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated.

data. RTS (high) level either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR. In the auto-RTS

operating in the FIFO mode, one of two types of DMA signalling can be selected using the FIFO control register bit 3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is at least one character in the receiver FIFO or receiver holding register, RXRDY but there are no characters in the FIFO or holding register, RXRDY (FCR0 = 1, FCR3 = 1), when the trigger level or the time-out has been reached, RXRDY (low); when it has been active but there are no more characters in the FIFO or holding register, it goes inactive (high).

is set to the marking (high) level as a result of master reset.

mode, one of two types of DMA signalling can be selected using FCR3. When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit FIFO has been filled.

selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer data during a write operation; the other input should be tied to its inactive level (i.e., WR2 tied low or WR1

is set to the active level by setting the RTS modem control register bit and is set to the inactive

mode, RTS is set to the inactive level by the receiver threshold control logic.

DESCRIPTION

and OUT2 are set to

tied high).

has transitioned from

is active (low). When RXRDY has been active

goes inactive (high). In DMA mode 1

goes active

tied high).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V Input voltage range at any input, V Output voltage range, V Operating free-air temperature range, T

Storage temperature range, T Case temperature for 10 seconds, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N or PT package 260°C. . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

, TL16C550C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TL16C550CI –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions

low voltage (3.3 V nominal)

MIN NOM MAX UNIT

Supply voltage, V Input voltage, V High-level input voltage, VIH (see Note 2) 0.7 V Low-level input voltage, VIL (see Note 2) 0.3 V Output voltage, VO (see Note 3) 0 V High-level output current, IOH (all outputs) 1.8 mA Low-level output current, IOL (all outputs) 3.2 mA Input capacitance 1 pF Operating free-air temperature, T Junction temperature range, TJ (see Note 4) 0 25 115 °C Oscillator/clock speed 14 MHz NOTES: 2. Meets TTL levels, V

= 2 V and V

3. Applies for external output buffers

4. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is responsible for verifying junction temperature.

IHmin

= 0.8 V on nonhysteresis inputs

ILmax

3 3.3 3.6 V 0 V

0 25 70 °C

V V V V

†

standard voltage (5 V nominal)

MIN NOM MAX UNIT

Supply voltage, V Input voltage, V High-level input voltage, V Low-level input voltage, V Output voltage, VO (see Note 5) 0 V High-level output current, IOH (all outputs) 4 mA Low-level output current, IOL (all outputs) 4 mA Input capacitance 1 pF Operating free-air temperature, T Junction temperature range, TJ (see Note 6) 0 25 115 °C Oscillator/clock speed 16 MHz

5. Applies for external output buffers

6. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is responsible for verifying junction temperature.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4.75 5 5.25 V 0 V

0.7 V

0 25 70 °C

0.2 V

V V V V

TL16C550C, TL16C550CI

IlInput current

10µA

3.6 V, V

25 C

SIN, DSR, DCD, CTS, and RI at 2 V

ICCSu ly current

All oth

XTAL1 at 4 MH

MHz

25°C

All other terminals grounded IlInput current

10µA

5.25 V, V

25 C

SIN, DSR, DCD, CTS, and RI at 2 V

ICCSu ly current

All oth

XTAL1 at 4 MH

MHz

25°C

All other terminals grounded

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

low voltage (3.3 V nominal)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

‡

i(CLK)

o(CLK)

†

All typical values are at VCC = 3.3 V and TA = 25°C.

‡

These parameters apply for all outputs except XOUT.

High-level output voltage IOH = –1 mA 2.4 V

‡

Low-level output voltage IOL = 1.6 mA 0.5 V

High-impedance-state output current

Supply current

Clock input capacitance 15 20 pF Clock output capacitance Input capacitance Output capacitance

= 3.6 V, V

VI = 0 to 3.6 V, V

= 3.6 V VO = 0 to 3.6 V, Chip selected in write mode or chip deselect

= 3.6 V,

er inputs at 0.8 V,

No load on outputs, Baud rate = 50 kbit/s

VCC = 0, VSS = 0,

= 1

All other terminals

rounded

= 0,

All other terminals floating V

= 0

20 30 pF

6 10 pF

10 20 pF

±20 µA

8mA

standard voltage (5 V nominal)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

‡

i(CLK)

o(CLK)

†

All typical values are at VCC = 5 V and TA = 25°C.

‡

These parameters apply for all outputs except XOUT.

High-level output voltage IOH = –1 mA 2.4 V

‡

Low-level output voltage IOL = 1.6 mA 0.4 V

High-impedance-state output current

Supply current

Clock input capacitance 15 20 pF Clock output capacitance Input capacitance Output capacitance

= 5.25 V, V VI = 0 to 5.25 V,

= 5.25 V VO = 0 to 5.25 V, Chip selected in write mode or chip deselect

= 5.25 V,

er inputs at 0.8 V,

No load on outputs, Baud rate = 50 kbit/s

VCC = 0, VSS = 0,

= 1

All other terminals

rounded

= 0,

All other terminals floating V

= 0

±20 µA

10 mA

20 30 pF

6 10 pF

10 20 pF

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550C, TL16C550CI

f 16 MHz Max,

6, 78ns

6, 70ns

610ns

67ns

77ns

f 16 MHz, CLK

ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

system timing requirements over recommended ranges of supply voltage and operating free-air temperature

ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

t t t t t t t t t t t t t t t t t t t t t t t t t t t

†

Cycle time, read (tw7 + td8 + td9) RC 87 ns

Cycle time, write (tw6 + td5 + td6) WC 87 ns

Pulse duration, clock high t

Pulse duration, clock low t

Pulse duration, ADS low t

Pulse duration, WR t

Pulse duration, RD t

Pulse duration, MR t

Setup time, address valid before ADS↑ t

su1

Setup time, CS valid before ADS↑ t

su2

Setup time, data valid before WR1↓ or WR2↑ t

su3

Setup time, CTS↑ before midpoint of stop bit 17 10 ns

su4

Hold time, address low after ADS↑ t

Hold time, CS valid after ADS↑ t

Hold time, CS valid after WR1↑ or WR2↓ t

Hold time, address valid after WR1↑ or WR2↓ t

Hold time, data valid after WR1↑ or WR2↓ t

Hold time, chip select valid after RD1↑ or RD2↓ t

Hold time, address valid after RD1↑ or RD2↓ t

†

Delay time, CS valid before WR1↓ or WR2↑ t

†

Delay time, address valid before WR1↓ or WR2↑ t

†

Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ t

†

Delay time, CS valid to RD1↓ or RD2↑ t

†

Delay time, address valid to RD1↓ or RD2↑ t

Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ tRC 7 40 ns

Delay time, RD1↓ or RD2↑ to data valid t

d10

Delay time, RD1↑ or RD2↓ to floating data t

d11 Only applies when ADS is low

ADS

AS CS DS

AH CH

WCS

RCS

CSW

AW WC

CSR

RVD

f = 16 MHz Max VCC = 5 V

6, 7 9 ns

6 40 ns 7 40 ns

6 15 ns

6 5 ns 7 10 ns 7 20 ns

6 40 ns

7 CL = 75 pF 45 ns 7 CL = 75 pF 20 ns

1 µs

system switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 7)

dis(R)

NOTE 7: Charge and discharge times are determined by VOL, VOH, and external loading.

baud generator switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ t

= 75 pF

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

Pulse duration, BAUDOUT low t Pulse duration, BAUDOUT high t Delay time, XIN↑ to BAUDOUT↑ t Delay time, XIN↑↓ to BAUDOUT↓ t

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RDD

LW HW

BLD

BHD

7 CL = 75 pF 20 ns

f = 16 MHz, CLK ÷ 2 VCC = 5 V

5 5 45 ns 5 45 ns

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

receiver switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 8)

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

d12

d13

d14

NOTE 8: In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receive FIFO and the status registers (interrupt identification

transmitter switching characteristics over recommended ranges of supply voltage and operating free-air temperature

d15

d16

d17

d18

d19

d20

d21

†

THRE = transmitter holding register empty; IIR = interrupt identification register.

Delay time, RCLK to sample t Delay time, stop to set INTRPT or read

RBR to LSI interrupt or stop to RXRDY Delay time, read RBR/LSR to reset INTRPT t

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

Delay time, initial write to transmit start t

Delay time, start to INTRPT t Delay time, WR (WR THR) to reset INTRPT t Delay time, initial write to INTRPT (THRE†) t Delay time, read IIR† to reset INTRPT

(THRE†) Delay time, write to TXRDY inactive t

Delay time, start to TXRDY active

↓

SCD

SINT

RINT

IRS

STI

WXI

SXA

8 10 ns

8, 9, 10,

11, 12

8, 9, 10,

11, 12

13 8 24

13 8 10 13 CL = 75 pF 50 ns 13 16 34

13 CL = 75 pF 35 ns 14,15 CL = 75 pF 35 ns 14,15 CL = 75 pF 9

CL = 75 pF 70 ns

baudout

cycles

baudout

cycles

baudout

cycles

baudout

cycles

RCLK

cycle

modem control switching characteristics over recommended ranges of supply voltage and

= 75 pF

operating free-air temperature, C

PARAMETER ALT. SYMBOL FIGURE MIN MAX UNIT

d22

d23

d24

d25

d26

d27

d28

d29

Delay time, WR MCR to output t Delay time, modem interrupt to set INTRPT t Delay time, RD MSR to reset INTRPT t

Delay time, CTS low to SOUT↓ 17 24

Delay time, RCV threshold byte to RTS↑ 18 2

Delay time, read of last byte in receive FIFO to RTS↓ 18 2

Delay time, first data bit of 16th character to RTS↑ 19 2

Delay time, RBRRD low to RTS↓ 19 2

MDO

SIM RIM

16 50 ns 16 35 ns 16 40 ns

baudout

cycles

baudout

cycles

baudout

cycles

baudout

cycles

baudout

cycles

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PARAMETER MEASUREMENT INFORMATION

XIN

BAUDOUT

(1/1)

BAUDOUT

(1/2)

BAUDOUT

(1/3)

BAUDOUT

(1/N)

(N > 3)

2 XIN Cycles

(N–2) XIN Cycles

Figure 5. Baud Generator Timing Waveforms

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PARAMETER MEASUREMENT INFORMATION

TL16C550C, TL16C550CI

ADS

A0–A2

CS0, CS1, CS2

WR1, WR2

D7–D0

†

Applicable only when ADS

50%

50%50%

su1

Valid Valid

su2

50% 50%

is low

Valid Valid

50% 50%

su3

Active

Valid Data

†

50%

50%50%

Figure 6. Write Cycle Timing Waveforms

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PARAMETER MEASUREMENT INFORMATION

ADS

A0–A2

CS0, CS1, CS2

RD1, RD2

DDIS

50%

50%50%

su1

Valid Valid

†

td8†

50% 50%

dis(R)

50% 50%

su2

50%

Active

50% 50%

50%

†

50%

†

dis(R)

D7–D0

†

Applicable only when ADS is low

Figure 7. Read Cycle Timing Waveforms

d10

Valid Data

d11

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RCLK

Sample Clock

TL16C450 Mode:

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

PARAMETER MEASUREMENT INFORMATION

8 CLKs

d12

TL16C550C, TL16C550CI

SIN

Sample Clock

INTRPT

(data ready)

INTRPT

(RCV error)

RD1

, RD2

(read RBR)

RD1

, RD2

(read LSR)

Parity StopStart Data Bits 5– 8

d13

50%

Figure 8. Receiver Timing Waveforms

Active

d14

50%

50%50%

Active

d14

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PARAMETER MEASUREMENT INFORMATION

SIN

Sample Clock

Trigger Level

INTRPT

(FCR6, 7 = 0, 0)

INTRPT

Line Status

Interrupt (LSI)

RD1

(RD LSR)

RD1

(RD RBR)

NOTE A: For a time-out interrupt, t

Figure 9. Receive FIFO First Byte (Sets DR Bit) Waveforms

SIN

= 9 RCLKs.

d13

Data Bits 5–8

(see Note A)

Stop

d13

50%

Stop

d14

Active

(FIFO at or above

50%

d14

50%50%

50%

Active

trigger level) (FIFO below

trigger level)

Sample Clock

Time-Out or

Trigger Level

Interrupt

Line Status

Interrupt (LSI)

RD1, RD2

(RD LSR)

, RD2

RD1 (RD RBR)

NOTE A: For a time-out interrupt, t

(see Note A)

Previous Byte

Read From FIFO

= 9 RCLKs.

d13

50%

d13

Top Byte of FIFO

d13

Active Active

50% 50%

d14

50%

50%50%

50%

(FIFO at or above trigger level)

(FIFO below trigger level)

Figure 10. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms

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PARAMETER MEASUREMENT INFORMATION

TL16C550C, TL16C550CI

(RD RBR)

SIN

(first byte)

Sample Clock

(see Note B)

RXRDY

NOTE A: This is the reading of the last byte in the FIFO.

d13

Stop

50%

d14

50%

Active

See Note A

50%

Figure 11. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)

(RD RBR)

SIN

(first byte that reaches

the trigger level)

Sample Clock

50%

Active

See Note A

= 9 RCLKs.

d13

(see Note B)

RXRDY

NOTES: A. This is the reading of the last byte in the FIFO.

B. For a time-out interrupt, t

Figure 12. Receiver Ready (RXRDY) Waveforms, FCR0 = 1 or FCR3 = 1 (Mode 1)

d14

50%50%

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TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

PARAMETER MEASUREMENT INFORMATION

SOUT

INTRPT

(THRE)

(WR THR)

RD IIR

Start

50%

d15

50% 50% 50% 50% 50%

d18

d17

50%

Data Bits

d17

Parity Stop

d16

Start

50%

Figure 13. Transmitter Timing Waveforms

(WR THR)

SOUT

Byte #1

Data

50%

Parity

Stop

Start

50%

d19

50%

d21

50%

TXRDY

d20

50%

Figure 14. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)

(WR THR)

SOUT

TXRDY

Data

Byte #16

d20

50%

Parity

Stop

FIFO Full

Start

50%

d21

50%

Figure 15. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)

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PARAMETER MEASUREMENT INFORMATION

TL16C550C, TL16C550CI

(WR MCR)

RTS, DTR,

OUT1

, OUT2

CTS, DSR, DCD

INTRPT

(modem)

RD2

(RD MSR)

50% 50%

d22

50% 50%

50%

d23

d24

50%

d22

50%

d23

Figure 16. Modem Control Timing Waveforms

CTS

SOUT

SIN

RTS

RBRRD

50% 50%

d25

50%

Midpoint of Stop Bit

Figure 17. CTS and SOUT Autoflow Control Timing (Start and Stop) Waveforms

Midpoint of Stop Bit

50%

d27

50%

d26

50%

Figure 18. Auto-RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms

su4

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PARAMETER MEASUREMENT INFORMATION

Midpoint of Data Bit 0

SIN

RTS

RBRRD

15th Character 16th Character

d28

50%

Figure 19. Auto-RTS Timing for RCV Threshold of 14 Waveforms

APPLICATION INFORMATION

SOUT

SIN RTS DTR DSR

DCD

CTS

XIN

XOUT

BAUDOUT

RCLK

232-D Drivers

and Receivers

C P U

B u s

D7–D0

MEMR

or I/OR

MEMW or I/ON

INTR

RESET

A0 A1 A2

D7–D0

RD1 WR1

INTRPT MR

A0 A1 A2

ADS WR2 RD2

CS2 CS1 CS0

TL16C550C

(ACE)

EIA

50%

3.072 MHz

d29

50%

Figure 20. Basic TL16C550C Configuration

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APPLICATION INFORMATION

TL16C550C, TL16C550CI

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

Microcomputer

System

Figure 21. Typical Interface for a High Capacity Data Bus

Data Bus Data Bus

8-Bit

Bus Transceiver

Receiver Disable

Driver Disable

WR1

TL16C550C

(ACE)

D7–D0

DDIS

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TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

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APPLICATION INFORMATION

A16–A23

CPU

RSI/ABT

AD0–AD15

PHI1 PHI2

ADS

Address Decoder

Buffer

A16–A23

AD0–AD7

12 13 14

TL16C550C

CS0 CS1 CS2

ADS

A0–A2

D0–D7

XIN

XOUT

BAUDOUT

RCLK

DTR RTS

OUT1 OUT2

DCD DSR

CTS

Alternate

17 15 9

33 32 34 31

38 37 36

Crystal Control

8 6 5

RSTO

PHI1 PHI2

NOTE A: Terminal numbers shown are for the N package.

ADS

TCU

AD0–AD15

Figure 22. Typical TL16C550C Connection to a CPU

GND (VSS)

RD1

WR1

RD2 WR2

SOUT

SIN

INTRPT

TXRDY

DDIS

RXRDY

20 40

5 V

(VCC)

10 30 24 23 2919

7 1

EIA-232-D Connector

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TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

PRINCIPLES OF OPERATION

Table 1. Register Selection

†

DLAB

0 L L L Receiver buffer (read), transmitter holding register (write) 0 L L H Interrupt enable register X L H L Interrupt identification register (read only) X L H L FIFO control register (write) X L H H Line control register X H L L Modem control register X H L H Line status register X H H L Modem status register X H H H Scratch register 1 L L L Divisor latch (LSB) 1 L L H Divisor latch (MSB)

†

The divisor latch access bit (DLAB) is the most significant bit of the line control register . The DLAB signal is controlled by writing to this bit location (see Table 4).

A2 A1 A0 REGISTER

Table 2. ACE Reset Functions

Interrupt Enable Register Master Reset All bits cleared (0–3 forced and 4–7 permanent) Interrupt Identification Register Master Reset FIFO Control Register Master Reset All bits cleared

Line Control Register Master Reset All bits cleared Modem Control Register Master Reset All bits cleared (6–7 permanent) Line Status Register Master Reset Bits 5 and 6 are set; all other bits are cleared Modem Status Register Master Reset Bits 0–3 are cleared; bits 4–7 are input signals SOUT Master Reset High INTRPT (receiver error flag) Read LSR/MR Low INTRPT (received data available) Read RBR/MR Low INTRPT (transmitter holding register empty) Read IR/Write THR/MR Low INTRPT (modem status changes) Read MSR/MR Low OUT2 Master Reset High RTS Master Reset High DTR Master Reset High OUT1 Master Reset High Scratch Register Master Reset No effect Divisor Latch (LSB and MSB) Registers Master Reset No effect Receiver Buffer Register Master Reset No effect Transmitter Holding Register Master Reset No effect RCVR FIFO MR/FCR1–FCR0/∆FCR0 All bits cleared XMIT FIFO MR/FCR2–FCR0/∆FCR0 All bits cleared

Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits 4 –5 are permanently cleared

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PRINCIPLES OF OPERATION

accessible registers

The system programmer, using the CPU, has access to and control over any of the ACE registers that are summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow Table 3.

Table 3. Summary of Accessible Registers

0DLAB=0 0DLAB = 0 1 DLAB = 0 2 2 3 4 5 6 7 0 DLAB = 1 1 DLAB = 1

Receiver

BIT

Buffer

NO.

(Read Only)

RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM

0 Data Bit 0†Data Bit 0

1 Data Bit 1 Data Bit 1

2 Data Bit 2 Data Bit 2

3 Data Bit 3 Data Bit 3

4 Data Bit 4 Data Bit 4 0 0 Reserved

5 Data Bit 5 Data Bit 5 0 0 Reserved

6 Data Bit 6 Data Bit 6 0

7 Data Bit 7 Data Bit 7 0

†

Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

NOTE 9: These bits are always 0 in the TL16C450 mode.

Transmitter

Holding Register

(Write

Only)

Interrupt

Enable

Received

Data

Available

Interrupt

(ERBI) Enable

Transmitter

Holding

Empty Interrupt (ETBEI)

Enable

Receiver

Line Status

Interrupt

(ELSI)

Enable Modem

Status Interrupt (EDSSI)

Interrupt

Ident.

(Read

Only)

0 if Interrupt Pending

Interrupt

Bit 1

Interrupt

Bit 2

Interrupt

Bit 3 (see

Note 9)

FIFOs

Enabled

(see

Note 9)

FIFOs

Enabled

(see

Note 9)

FIFO

Control

(Write

Only)

FIFO

Enable

Receiver

FIFO

Reset

Transmitter

FIFO

Reset

DMA

Mode

Select

Receiver

Trigger

(LSB)

Receiver

Trigger

(MSB)

Line

Control

Word

Length

Select

Bit 0

(WLS0)

Word

Length

Select

Bit 1

(WLS1)

Number

Stop Bits

(STB)

Parity

Enable

(PEN)

Even Parity Select (EPS)

Stick

Parity

Break

Control

Divisor

Latch

Access

Bit

(DLAB)

Modem Control

Data

Terminal

Ready (DTR)

Request

to Send

(RTS)

OUT1

OUT2

Loop

Autoflow

Control

Enable

(AFE)

Line

Status

Data

Ready

(DR)

Overrun

Error

(OE)

Parity

Error

(PE)

Framing

Error

(FE)

Break

Interrupt

(BI)

Transmitter

Holding

(THRE)

Transmitter

Empty

(TEMT) Error in

RCVR

FIFO

(see

Note 9)

Modem

Status

Delta Clear

to Send

∆CTS)

(

Delta Data

Set

Ready

∆DSR)

(

Trailing

Edge Ring

Indicator

(TERI)

Delta Data

Carrier

Detect

∆DCD)

(

Clear

Send

(CTS)

Data

Set Ready (DSR)

Ring

Indicator

(RI)

Data

Carrier

Detect (DCD)

Scratch

Bit 0 Bit 0 Bit 8

Bit 1 Bit 1 Bit 9

Bit 2 Bit 2 Bit 10

Bit 3 Bit 3 Bit 11

Bit 4 Bit 4 Bit 12

Bit 5 Bit 5 Bit 13

Bit 6 Bit 6 Bit 14

Bit 7 Bit 7 Bit 15

Divisor

Latch (LSB)

Latch

(MSB)

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PRINCIPLES OF OPERATION

FIFO control register (FCR)

The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.

Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bits are written to or they are not programmed. Changing this bit clears the FIFOs.

Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not cleared. The 1 that is written to this bit position is self clearing.

Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not cleared. The 1 that is written to this bit position is self clearing.

Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.

Bits 4 and 5: These two bits are reserved for future use.

Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 4).

Table 4. Receiver FIFO Trigger Level

BIT 7 BIT 6

0 0 01 0 1 04 1 0 08 1 1 14

RECEIVER FIFO

TRIGGER LEVEL (BYTES)

FIFO interrupt mode operation

When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt occurs as follows:

1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.

2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the interrupt, it is cleared when the FIFO drops below the trigger level.

3. The receiver line status interrupt (IIR = 06) has higher priority than the received data available (IIR = 04) interrupt.

4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO. It is cleared when the FIFO is empty.

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PRINCIPLES OF OPERATION

FIFO interrupt mode operation (continued)

When the receiver FIFO and receiver interrupts are enabled:

1. FIFO time-out interrupt occurs if the following conditions exist: a. At least one character is in the FIFO. b. The most recent serial character was received more than four continuous character times ago (if two

stop bits are programmed, the second one is included in this time delay).

c. The most recent microprocessor read of the FIFO has occurred more than four continuous character

times before. This causes a maximum character received command to interrupt an issued delay of 160 ms at a 300 baud rate with a 12-bit character.

2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional to the baud rate).

3. When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor reads one character from the receiver FIFO.

4. When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received or after the microprocessor reads the receiver FIFO.

When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as follows:

1. The transmitter holding register interrupt [IIR (3–0) = 2] occurs when the transmit FIFO is empty. It is cleared [IIR (3–0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit FIFO while servicing this interrupt) or the IIR is read.

2. The transmitter FIFO empty indicator (LSR5 (THRE) = 1) is delayed one character time minus the last stop bit time when there have not been at least two bytes in the transmitter FIFO at the same time since the last time that THRE = 1. The first transmitter interrupt after changing FCR0 is immediate if it is enabled.

Character time-out and receiver FIFO trigger level interrupts have the same priority as the current received-data-available interrupt; transmit FIFO empty has the same priority as the current THRE interrupt.

FIFO polled mode operation

With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 puts the ACE in the FIFO polled mode of operation. Since the receiver and transmitter are controlled separately, either one or both can be in the polled mode of operation.

In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously:

LSR0 is set as long as there is one byte in the receiver FIFO.

LSR1 – LSR 4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt mode; the IIR is not affected since IER2 = 0.

LSR5 indicates when the THR is empty.

LSR6 indicates that both the THR and TSR are empty.

LSR7 indicates whether there are any errors in the receiver FIFO.

There is no trigger level reached or time-out condition indicated in the FIFO polled mode. However, the receiver and transmitter FIFOs are still fully capable of holding characters.

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PRINCIPLES OF OPERATION

interrupt enable register (IER)

The IER enables each of the five types of interrupts (refer to Table 5) and enables INTRPT in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of this register are summarized in Table 3 and are described in the following bullets.

Bit 0: When set, this bit enables the received data available interrupt.

Bit 1: When set, this bit enables the THRE interrupt.

Bit 2: When set, this bit enables the receiver line status interrupt.

Bit 3: When set, this bit enables the modem status interrupt.

Bits 4 through 7: These bits are not used (always cleared).

interrupt identification register (IIR)

The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with most popular microprocessors.

The ACE provides four prioritized levels of interrupts:

Priority 1 – Receiver line status (highest priority)

Priority 2 – Receiver data ready or receiver character time-out

Priority 3 – Transmitter holding register empty

Priority 4 – Modem status (lowest priority)

When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and described in Table 5. Detail on each bit is as follows:

Bit 0: This bit is used either in a hardwire prioritized or polled interrupt system. When bit 0 is cleared, an interrupt is pending If bit 0 is set, no interrupt is pending.

Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 3

Bit 3: This bit is always cleared in TL16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a time-out interrupt is pending.

Bits 4 and 5: These two bits are not used (always cleared).

Bits 6 and 7: These bits are always cleared in TL16C450 mode. They are set when bit 0 of the FIFO control register is set.

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LEVEL

METHOD

ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

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PRINCIPLES OF OPERATION

interrupt identification register (IIR) (continued)

Table 5. Interrupt Control Functions

INTERRUPT

IDENTIFICATION REGISTER BIT 3 BIT 2 BIT 1 BIT 0

0 0 0 1 None None None None 0 1 1 0 1 Receiver line status

0 1 0 0 2 Received data available

1 1 0 0 2

0 0 1 0 3

0 0 0 0 4 Modem status

PRIORITY

INTERRUPT TYPE INTERRUPT SOURCE

Overrun error, parity error, framing error, or break interrupt

Receiver data available in the TL16C450 mode or trigger level reached in the FIFO mode

No characters have been

Character time-out indication

Transmitter holding register empty

removed from or input to the receiver FIFO during the last four character times, and there is at least one character in it during this time

Transmitter holding register empty

Clear to send, data set ready, ring indicator, or data carrier detect

INTERRUPT RESET

Read the line status register

Read the receiver buffer register

Read the interrupt identification register (if source of interrupt) or writing into the transmitter holding register

Read the modem status register

line control register (LCR)

The system programmer controls the format of the asynchronous data communication exchange through the LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates the need for separate storage of the line characteristics in system memory. The contents of this register are summarized in Table 3 and described in the following bulleted list.

Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. These bits are encoded as shown in Table 6.

Table 6. Serial Character Word Length

BIT 1 BIT 0 WORD LENGTH

0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits

Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit regardless of the number of stop bits selected. The number of stop bits generated in relation to word length and bit 2 are shown in Table 7.

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PRINCIPLES OF OPERATION

line control register (LCR) (continued)

Table 7. Number of Stop Bits Generated

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

BIT 2

Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between

WORD LENGTH SELECTED

BY BITS 1 AND 2

0 Any word length 1 1 5 bits 1 1/2 1 6 bits 2 1 7 bits 2 1 8 bits 2

NUMBER OF STOP

BITS GENERATED

the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is cleared, no parity is generated or checked.

Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set even parity (an even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is cleared, odd parity (an odd number of logic 1s) is selected.

Bit 5: This bit is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. If bit 5 is cleared, stick parity is disabled.

Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no affect on the transmitter logic; it only effects SOUT.

Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver buffer, the THR, or the IER.

line status register (LSR)

†

The LSR provides information to the CPU concerning the status of data transfers. The contents of this register are summarized in Table 3 and described in the following bulleted list.

Bit 0: This bit is the data ready (DR) indicator for the receiver. DR is set whenever a complete incoming character has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of the data in the RBR or the FIFO.

Bit 1‡: This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in the RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every time the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO beyond the trigger level, an overrun error occurs only after the FIFO is full and the next character has been completely received in the shift register. An overrun error is indicated to the CPU as soon as it happens. The character in the shift register is overwritten, but it is not transferred to the FIFO.

†

The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.

‡

Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.

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TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

PRINCIPLES OF OPERATION

line status register (LSR) (continued)

Bit 2‡: This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity of the received data character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.

Bit 3‡: This bit is the framing error (FE) indicator. When FE is set, it indicates that the received character did not have a valid (set) stop bit. FE is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the next start bit. The ACE samples this start bit twice and then accepts the input data.

Bit 4‡: This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the received data input was held low for longer than a full-word transmission time. A full-word transmission time is defined as the total time to transmit the start, data, parity , and stop bits. BI is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after SIN goes to the marking state for at least two RCLK samples and then receives the next valid start bit.

Bit 5: This bit is the THRE indicator. THRE is set when the THR is empty, indicating that the ACE is ready to accept a new character. If the THRE interrupt is enabled when THRE is set, an interrupt is generated. THRE is set when the contents of the THR are transferred to the TSR. THRE is cleared concurrent with the loading of the THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared when at least one byte is written to the transmit FIFO.

†

Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are both empty . When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode, TEMT is set when the transmitter FIFO and shift register are both empty.

Bit 7: In the TL16C550C mode, this bit is always cleared. In the TL16C450 mode, this bit is always cleared. In the FIFO mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO.

modem control register (MCR)

The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is emulating a modem. The contents of this register are summarized in T able 3 and are described in the following bulleted list.

Bit 0: This bit (DTR) controls the DTR output.

Bit 1: This bit (RTS) controls the RTS output.

Bit 2: This bit (OUT1) controls OUT1, a user-designated output signal.

Bit 3: This bit (OUT2) controls OUT2, a user-designated output signal.

When any of bits 0 through 3 are set, the associated output is forced low. When any of these bits are cleared, the associated output is forced high.

†

The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.

‡

Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.

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PRINCIPLES OF OPERATION

modem control register (MCR) (continued)

Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP is set, the following occurs:

– The transmitter SOUT is set high. – The receiver SIN is disconnected. – The output of the TSR is looped back into the receiver shift register input.

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

– The four modem control inputs (CTS – The four modem control outputs (DTR

modem control inputs.

– The four modem control outputs are forced to the inactive (high) levels.

Bit 5: This bit (AFE) is the autoflow control enable. When set, the autoflow control as described in the detailed description is enabled.

In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational, but the modem control interrupt’s sources are now the lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the IER.

The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 8.

MCR BIT 5

(AFE)

1 1 Auto-RTS and auto-CTS enabled (autoflow control enabled) 1 0 Auto-CTS only enabled 0 X Auto-RTS and auto-CTS disabled

modem status register (MSR)

, DSR, DCD, and RI) are disconnected.

, RTS, OUT1, and OUT2) are internally connected to the four

Table 8. ACE Flow Configuration

MCR BIT 1

(RTS)

ACE FLOW CONFIGURATION

The MSR is an 8-bit register that provides information about the current state of the control lines from the modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change information; when a control input from the modem changes state, the appropriate bit is set. All four bits are cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are described in the following bulleted list.

Bit 0: This bit is the change in clear-to-send (∆ CTS) indicator. ∆ CTS indicates that the CTS input has changed state since the last time it was read by the CPU. When ∆CTS is set (autoflow control is not enabled and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is enabled (∆CTS is cleared), no interrupt is generated.

Bit 1: This bit is the change in data set ready (∆DSR) indicator. ∆DSR indicates that the DSR input has changed state since the last time it was read by the CPU. When ∆DSR is set and the modem status interrupt is enabled, a modem status interrupt is generated.

Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that the RI input to the chip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled, a modem status interrupt is generated.

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SLLS177E – MARCH 1994 – REVISED APRIL1998

PRINCIPLES OF OPERATION

modem status register (MSR) (continued)

Bit 3: This bit is the change in data carrier detect (∆DCD) indicator . ∆DCD indicates that the DCD input to the chip has changed state since the last time it was read by the CPU. When ∆DCD is set and the modem status interrupt is enabled, a modem status interrupt is generated.

Bit 4: This bit is the complement of the clear-to-send (CTS) input. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1 (RTS).

Bit 5: This bit is the complement of the data set ready (DSR) input. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR).

Bit 6: This bit is the complement of the ring indicator (RI) input. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 2 (OUT1).

Bit 7: This bit is the complement of the data carrier detect (DCD) input. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2).

programmable baud generator

The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16 MHz and divides it by a divisor in the range between 1 and (2 sixteen times (16×) the baud rate. The formula for the divisor is:

divisor = XIN frequency input ÷ (desired baud rate × 16)

Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.

T ables 9 and 10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz respectively. For baud rates of 38.4 kbits/s and below, the error obtained is very small. The accuracy of the selected baud rate is dependent on the selected crystal frequency (refer to Figure 23 for examples of typical clock circuits).

–1). The output frequency of the baud generator is

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PRINCIPLES OF OPERATION

programmable baud generator (continued)

Table 9. Baud Rates Using a 1.8432-MHz Crystal

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

DESIRED

BAUD RATE

50 2304 75 1536

110 1047 0.026

134.5 857 0.058 150 768 300 384 600 192

1200 96 1800 64 2000 58 0.69 2400 48 3600 32 4800 24 7200 16

9600 12 19200 6 38400 3 56000 2 2.86

DIVISOR USED TO GENERATE

16 × CLOCK

PERCENT ERROR

DIFFERENCE BETWEEN

DESIRED AND ACTUAL

Table 10. Baud Rates Using a 3.072-MHz Crystal

DESIRED

BAUD RATE

50 3840 75 2560

110 1745 0.026

134.5 1428 0.034 150 1280 300 640 600 320

1200 160 1800 107 0.312 2000 96 2400 80 3600 53 0.628 4800 40 7200 27 1.23

9600 20 19200 10 38400 5

DIVISOR USED TO GENERATE

16 × CLOCK

PERCENT ERROR

DIFFERENCE BETWEEN

DESIRED AND ACTUAL

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SLLS177E – MARCH 1994 – REVISED APRIL1998

PRINCIPLES OF OPERATION

programmable baud generator (continued)

Oscillator Clock to Baud Generator Logic

External

Clock

Optional

Clock

Output

Driver

Optional

Driver

XIN

Crystal

XOUT

CRYSTAL

3.072 MHz 1 MΩ 1.5 kΩ 10–30 pF 40–60 pF

1.8432 MHz 1 MΩ 1.5 kΩ 10–30 pF 40–60 pF

Oscillator Clock to Baud Generator Logic

TYPICAL CRYSTAL OSCILLATOR NETWORK

RX2 C1 C2

RX2

XOUT

XIN

Figure 23. Typical Clock Circuits

receiver buffer register (RBR)

The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte FIFO. Timing is supplied by the 16× receiver clock (RCLK). Receiver section control is a function of the ACE line control register.

The ACE RSR receives serial data from SIN. The RSR then concatenates the data and moves it into the RBR FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt is enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR. In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.

scratch register

The scratch register is an 8-bit register that is intended for the programmer’s use as a scratchpad in the sense that it temporarily holds the programmer’s data without affecting any other ACE operation.

transmitter holding register (THR)

The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a 16-byte FIFO. Timing is supplied by BAUDOUT register.

The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR. The TSR serializes the data and outputs it at SOUT. In the TL16C450 mode, if the THR is empty and the transmitter holding register empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.

. Transmitter section control is a function of the ACE line control

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TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

MECHANICAL DATA

FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

E1E

NO. OF

PINS

D/E

0.032 (0,81)

0.026 (0,66)

0.050 (1,27)

0.008 (0,20) NOM

D1/E1

MINMAXMIN

MAX

D2/E2

MIN

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

0.020 (0,51) MIN

D2/E2

0.021 (0,53)

0.013 (0,33)

0.007 (0,18)

MAX

20 28 44 52 68 84

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018

0.385 (9,78)

0.485 (12,32)

0.685 (17,40)

0.785 (19,94)

0.985 (25,02)

1.185 (30,10)

0.395 (10,03)

0.495 (12,57)

0.695 (17,65)

0.795 (20,19)

0.995 (25,27)

1.195 (30,35)

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0.350 (8,89)

0.450 (11,43)

0.650 (16,51)

0.750 (19,05)

0.950 (24,13)

1.150 (29,21)

0.356 (9,04)

0.456 (11,58)

0.656 (16,66)

0.756 (19,20)

0.958 (24,33)

1.158 (29,41)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.441 (11,20)

0.541 (13,74)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

0.469 (11,91)

0.569 (14,45)

4040005/B 03/95

TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

MECHANICAL DATA

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

24 PIN SHOWN

0.560 (14,22)

0.520 (13,21)

0.060 (1,52) TYP

0.200 (5,08) MAX

0.020 (0,51) MIN

0.100 (2,54)

0.021 (0,53)

0.015 (0,38)

0.010 (0,25)

PINS **

DIM

A MAX

A MIN

1.270

(32,26) (36,83)

1.230

(31,24)

1.450

1.410

(35,81)

0.125 (3,18) MIN

322824

1.650

(41,91)

1.610

(40,89)

Seating Plane

0.010 (0,25) NOM

524840

2.090 2.450 2.650

2.040

(51,82)

(62,23)(53,09)

2.390

(60,71)

(67,31)

2.590

(65,79)

0.610 (15,49)

0.590 (14,99)

0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-011 D. Falls within JEDEC MS-015 (32 pin only)

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4040053/B 04/95

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

MECHANICAL DATA

PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK

1,05 0,95

0,50

0,27 0,17

5,50 TYP

7,20

6,80 9,20

8,80

0,08

0,05 MIN

Seating Plane

0,13 NOM

Gage Plane

0,25

0°–7°

0,75 0,45

1,20 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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0,08

4073176/B 10/96

TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

MECHANICAL DATA

PT (S-PQFP-G48) PLASTIC QUAD FLATPACK

0,50

1,45 1,35

0,27 0,17

5,50 TYP

7,20

6,80 9,20

8,80

0,08

0,05 MIN

0,13 NOM

Gage Plane

0,25

0°–7°

1,60 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. This may also be a thermally enhanced plastic package with leads conected to the die pads.

Seating Plane

0,10

0,75 0,45

4040052/C 11/96

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TEXAS INSTRUMENTS TL16C550C, TL16C550CI Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual