TEXAS INSTRUMENTS TL16C550C, TL16C550CI Technical data

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Programmable Auto-RTS and Auto-CTS

In Auto-CTS Mode, CTS Controls Transmitter

In Auto-RTS Mode, RCV FIFO Contents and Threshold Control RTS

Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Power Drop

Capable of Running With All Existing TL16C450 Software

After Reset, All Registers Are Identical to the TL16C450 Register Set

Up to 16-MHz Clock Rate for Up to 1-Mbaud Operation

In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data

Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1

to (2 Clock

Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream

description

–1) and Generates an Internal 16×

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

5-V and 3.3-V Operation

Independent Receiver Clock Input

Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled

Fully Programmable Serial Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation

and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (dc to 1 Mbit/s)

False-Start Bit Detection

Complete Status Reporting Capabilities

3-State Output TTL Drive Capabilities for Bidirectional Data Bus and Control Bus

Line Break Generation and Detection

Internal Diagnostic Capabilities: – Loopback Controls for Communications

Link Fault Isolation – Break, Parity, Overrun, and Framing

Error Simulation

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR, DTR

, RI, and DCD)

The TL16C550C and the TL16C550CI are functional upgrades of the TL16C550B asynchronous communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the TL16C550C and the TL16C550CI, like the TL16C550B, can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow using RTS

The TL16C550C and TL16C550CI perform serial-to-parallel conversions on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE status at any time. The ACE includes complete modem control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.

Both the TL16C550C and the TL16C550CI ACE include a programmable baud rate generator capable of dividing a reference clock by divisors from 1 to 65535 and producing a 16 × reference clock for the internal transmitter logic. Provisions are included to use this 16× clock for the receiver logic. The ACE accommodates a 1-Mbaud serial rate (16-MHz input clock) so that a bit time is 1 µs and a typical character time is 10 µs (start bit, 8 data bits, stop bit).

Two of the TL16C450 terminal functions on the TL16C550C and the TL16C550CI have been changed to TXRDY

and RXRDY, which provide signaling to a DMA controller.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

output and CTS input signals.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

D0 D1 D2 D3 D4 D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

XIN

XOUT

WR1 WR2

N PACKAGE

(TOP VIEW)

RI DCD DSR CTS MR OUT1 DTR RTS OUT2 INTRPT RXRDY A0 A1 A2 ADS TXRDY DDIS RD2 RD1

D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

FN PACKAGE

(TOP VIEW)

D4D3D2D1D0NCV

54 321644

7 8 9 10 11 12 13 14 15 16 17

1819

XIN

XOUT

20 21 22 23

WR1

WR2

24 25 26 27 28

RD2

RD1

DCD

42 41 4043

DDIS

DSR

CTS

OUT1

DTR

RTS

OUT2

INTRPT

RXRDY

ADS

TXRDY

SOUT

BAUDOUT

NC–No internal connection

D5 D6 D7

RCLK

SIN

CS0 CS1 CS2

NCD4D3D2D1

47 46 45 44 4348 42

1 2 3 4 5 6 7 8 9 10 11 12

14 15

PT/PFB PACKAGE

(TOP VIEW)

17 18 19 20

WR1

WR2

XIN

XOUT

RD1

40 39 3841

RD2

DCD

DSR

22 23 24

DDIS

CTS

36 35 34 33 32 31 30 29 28 27 26 25

ADS

TXRDY

NC MR OUT1 DTR RTS OUT2 INTRPT RXRDY A0 A1 A2 NC

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detailed description

autoflow control (see Figure 1)

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

Autoflow control is comprised of auto-CTS the transmitter FIFO can emit data. With auto-RTS and notifies the sending serial device. When RTS

and auto-RTS. With auto-CTS, the CTS input must be active before

, RTS becomes active when the receiver needs more data

is connected to CTS, data transmission does not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a TLC16C550C with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds the receiver FIFO read latency.

ACE1 ACE2

SIN SOUT

RTS

SOUT SIN

CTS

RTS

Parallel

to Serial

XMT

FIFO

Flow

Control

Serial to

Parallel

RCV

FIFO

Flow

Control

D7–D0

RCV

FIFO

XMT

FIFO

Serial to

Parallel

Flow

Control

Parallel

to Serial

Flow

Control

Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example

auto-RTS (see Figure 1)

D7–D0

Auto-RTS

data flow control originates in the receiver timing and control block (see functional block diagram) and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of 1, 4, or 8 (see Figure 3), RTS

is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because it may not recognize the deassertion of RTS

until after it has begun sending the additional byte. RTS

is automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register. When the trigger level is 14 (see Figure 4), RTS

present on the SIN line. RTS

auto-CTS

(see Figure 1)

The transmitter circuitry checks CTS

is reasserted when the RCV FIFO has at least one available byte space.

before sending the next data byte. When CTS is active, it sends the next byte. To stop the transmitter from sending the following byte, CTS last stop bit that is currently being sent (see Figure 2). The auto-CTS system. When flow control is enabled, CTS automatically controls its own transmitter. Without auto-CTS

is deasserted after the first data bit of the 16th character is

must be released before the middle of the

function reduces interrupts to the host

level changes do not trigger host interrupts because the device

, the transmitter sends any data present in the

transmit FIFO and a receiver overrun error may result.

enabling autoflow control and auto-CTS

Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to a 1. Autoflow incorporates both auto-RTS control register should be cleared (this assumes that a control signal is driving CTS

and auto-CTS. When only auto-CTS is desired, bit 1 in the modem

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TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

auto-CTS and auto-RTS functional timing

SOUT

CTS

NOTES: A. When CTS is low, the transmitter keeps sending serial data out.

B. If CTS

C. When CTS

Start Bits 0–7 Start Bits 0–7 Start Bits 0–7

goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but it does

not send the next byte.

goes from high to low, the transmitter begins sending data again.

Stop Stop Stop

Figure 2. CTS Functional Timing Waveforms

The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figures 3 and 4.

SIN

RTS

(RD RBR)

NOTES: A. N = RCV FIFO trigger level (1, 4, or 8 bytes)

B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS

Start Byte N Start Byte N+1 Start Byte

Stop Stop Stop

N N+1

Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1,4, or 8 Bytes

section.

SIN

RTS

(RD RBR)

NOTES: A. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the

sixteenth byte.

B. RTS

is asserted again when there is at least one byte of space available and no incoming byte is in processing or there is more than

one byte of space available.

C. When the receive FIFO is full, the first receive buffer register read reasserts RTS

Byte 14 Byte 15

RTS Released After the

First Data Bit of Byte 16

Start Byte 18 StopStart Byte 16 Stop

Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes

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functional block diagram

Data

Bus

Buffer

Select

and

Logic

Power Supply

D(7–0)

A0 A1 A2

CS0 CS1 CS2

ADS

MR RD1 RD2

WR1 WR2

DDIS

TXRDY

XIN

XOUT

RXRDY

8–1

28 27

12 13

14 25

35 21

22 18

19 23 24 16 17 29

40 20

Internal Data Bus

Control

S e

l e c

Receiver

Buffer

Line

Control

Divisor

Latch (LS)

Divisor

Latch (MS)

Line

Status

Transmitter

Holding

Modem

Control

Modem

Status

Interrupt

Enable

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

Receiver

FIFO

Transmitter

FIFO

Interrupt

Control

Logic

Baud

Generator

Receiver

Shift

Receiver

Timing and

Control

Transmitter

Timing and

Control

S e

l e c

Transmitter

Shift

Modem

Control

Logic

BAUDOUT

Autoflow Control (AFE)

36 33 37 38 39 34 31

SIN

RCLK

RTS

SOUT

CTS DTR DSR DCD RI OUT1 OUT2 INTRPT

Interrupt

Identification

FIFO

Control

NOTE A: Terminal numbers shown are for the N package.

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TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

Terminal Functions

TERMINAL

NAME

A0 A1 A2

ADS 25 28 24 I Address strobe. When ADS is active (low), A0, A1, and A2 and CS0, CS1, and CS2 drive the internal

BAUDOUT 15 17 12 O Baud out. BAUDOUT is a 16× clock signal for the transmitter section of the ACE. The clock rate is

CS0 CS1 CS2

CTS 36 40 38 I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of

D0 D1 D2 D3 D4 D5 D6 D7

DCD 38 42 40 I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD)

DDIS 23 26 22 O Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDIS can disable

DSR 37 41 39 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of

DTR 33 37 33 O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to

INTRPT 30 33 30 O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced.

MR 35 39 35 I Master reset. When active (high), MR clears most ACE registers and sets the levels of various output

NO.NNO.FNNO.

I/O

I Register select. A0–A2 are used during read and write operations to select the ACE register to read 27 26

43 44 45 46 47

2 3 4

from or write to. Refer to Table 1 for register addresses and refer to ADS

select logic directly; when ADS levels they were in when the low-to-high transition of ADS

established by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT

I Chip select. When CS0 and CS1 are high and CS2 is low , these three inputs select the ACE. When any

of these inputs are inactive, the ACE remains inactive (refer to ADS

the modem status register. Bit 0 (∆CTS) of the modem status register indicates that CTS states since the last read from the modem status register. If the modem status interrupt is enabled when CTS

changes levels and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used

in the auto-CTS

I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status

information between the ACE and the CPU.

of the modem status register. Bit 3 (∆ DCD) of the modem status register indicates that DCD changed states since the last read from the modem status register. If the modem status interrupt is enabled when DCD

an external transceiver.

the modem status register. Bit 1 (∆ DSR) of the modem status register indicates DSR levels since the last read from the modem status register. If the modem status interrupt is enabled when DSR

changes levels, an interrupt is generated.

establish communication. DTR register. DTR operation, or clearing the DTR bit.

Four conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INTRPT is reset (deactivated) either when the interrupt is serviced or as a result of a master reset.

signals (refer to Table 2).

mode to control the transmitter.

changes levels, an interrupt is generated.

is placed in the inactive level either as a result of a master reset, during loop mode

is high, the register select and chip select signals are held at the logic

may also be used for the receiver section by tying this output to RCLK.

is placed in the active level by setting the DTR bit of the modem control

DESCRIPTION

description.

occurred.

description).

has changed

has

has changed

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TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

Terminal Functions (Continued)

TERMINAL

NAME

OUT1 OUT2

RCLK 9 10 5 I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE. RD1

RD2

RI 39 43 41 I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the

RTS 32 36 32 O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive

RXRDY 29 32 29 O Receiver ready. Receiver direct memory access (DMA) signalling is available with RXRDY. When

SIN 10 11 7 I Serial data input. SIN is serial data input from a connected communications device SOUT 11 13 8 O Serial data output. SOUT is composite serial data output to a connected communication device. SOUT

TXRDY 24 27 23 O Transmitter ready. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO

WR1 WR2

XIN XOUT

NO.NNO.FNNO.

343138353431O Outputs 1 and 2. These are user-designated output terminals that are set to the active (low) level by

212224251920I Read inputs. When either RD1 or RD2 is active (low or high respectively) while the ACE is selected,

40 44 42 5-V supply voltage 20 22 18 Supply common 181920211617I Write inputs. When either WR1 or WR2 is active (low or high respectively) and while the ACE is

161718191415I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

I/O

setting respective modem control register (MCR) bits (OUT1 and OUT2). OUT1 inactive the (high) level as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR.

the CPU is allowed to read status information or data from a selected ACE register. Only one of these inputs is required for the transfer of data during a read operation; the other input should be tied to its inactive level (i.e., RD2 tied low or RD1

modem status register. Bit 2 (TERI) of the modem status register indicates that RI a low to a high level since the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated.

data. RTS (high) level either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR. In the auto-RTS

operating in the FIFO mode, one of two types of DMA signalling can be selected using the FIFO control register bit 3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is at least one character in the receiver FIFO or receiver holding register, RXRDY but there are no characters in the FIFO or holding register, RXRDY (FCR0 = 1, FCR3 = 1), when the trigger level or the time-out has been reached, RXRDY (low); when it has been active but there are no more characters in the FIFO or holding register, it goes inactive (high).

is set to the marking (high) level as a result of master reset.

mode, one of two types of DMA signalling can be selected using FCR3. When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit FIFO has been filled.

selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer data during a write operation; the other input should be tied to its inactive level (i.e., WR2 tied low or WR1

is set to the active level by setting the RTS modem control register bit and is set to the inactive

mode, RTS is set to the inactive level by the receiver threshold control logic.

DESCRIPTION

and OUT2 are set to

tied high).

has transitioned from

is active (low). When RXRDY has been active

goes inactive (high). In DMA mode 1

goes active

tied high).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V Input voltage range at any input, V Output voltage range, V Operating free-air temperature range, T

Storage temperature range, T Case temperature for 10 seconds, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N or PT package 260°C. . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

, TL16C550C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TL16C550CI –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions

low voltage (3.3 V nominal)

MIN NOM MAX UNIT

Supply voltage, V Input voltage, V High-level input voltage, VIH (see Note 2) 0.7 V Low-level input voltage, VIL (see Note 2) 0.3 V Output voltage, VO (see Note 3) 0 V High-level output current, IOH (all outputs) 1.8 mA Low-level output current, IOL (all outputs) 3.2 mA Input capacitance 1 pF Operating free-air temperature, T Junction temperature range, TJ (see Note 4) 0 25 115 °C Oscillator/clock speed 14 MHz NOTES: 2. Meets TTL levels, V

= 2 V and V

3. Applies for external output buffers

4. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is responsible for verifying junction temperature.

IHmin

= 0.8 V on nonhysteresis inputs

ILmax

3 3.3 3.6 V 0 V

0 25 70 °C

V V V V

†

standard voltage (5 V nominal)

MIN NOM MAX UNIT

Supply voltage, V Input voltage, V High-level input voltage, V Low-level input voltage, V Output voltage, VO (see Note 5) 0 V High-level output current, IOH (all outputs) 4 mA Low-level output current, IOL (all outputs) 4 mA Input capacitance 1 pF Operating free-air temperature, T Junction temperature range, TJ (see Note 6) 0 25 115 °C Oscillator/clock speed 16 MHz

5. Applies for external output buffers

6. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is responsible for verifying junction temperature.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4.75 5 5.25 V 0 V

0.7 V

0 25 70 °C

0.2 V

V V V V

TL16C550C, TL16C550CI

IlInput current

10µA

3.6 V, V

25 C

SIN, DSR, DCD, CTS, and RI at 2 V

ICCSu ly current

All oth

XTAL1 at 4 MH

MHz

25°C

All other terminals grounded IlInput current

10µA

5.25 V, V

25 C

SIN, DSR, DCD, CTS, and RI at 2 V

ICCSu ly current

All oth

XTAL1 at 4 MH

MHz

25°C

All other terminals grounded

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

low voltage (3.3 V nominal)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

‡

i(CLK)

o(CLK)

†

All typical values are at VCC = 3.3 V and TA = 25°C.

‡

These parameters apply for all outputs except XOUT.

High-level output voltage IOH = –1 mA 2.4 V

‡

Low-level output voltage IOL = 1.6 mA 0.5 V

High-impedance-state output current

Supply current

Clock input capacitance 15 20 pF Clock output capacitance Input capacitance Output capacitance

= 3.6 V, V

VI = 0 to 3.6 V, V

= 3.6 V VO = 0 to 3.6 V, Chip selected in write mode or chip deselect

= 3.6 V,

er inputs at 0.8 V,

No load on outputs, Baud rate = 50 kbit/s

VCC = 0, VSS = 0,

= 1

All other terminals

rounded

= 0,

All other terminals floating V

= 0

20 30 pF

6 10 pF

10 20 pF

±20 µA

8mA

standard voltage (5 V nominal)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

‡

i(CLK)

o(CLK)

†

All typical values are at VCC = 5 V and TA = 25°C.

‡

These parameters apply for all outputs except XOUT.

High-level output voltage IOH = –1 mA 2.4 V

‡

Low-level output voltage IOL = 1.6 mA 0.4 V

High-impedance-state output current

Supply current

Clock input capacitance 15 20 pF Clock output capacitance Input capacitance Output capacitance

= 5.25 V, V VI = 0 to 5.25 V,

= 5.25 V VO = 0 to 5.25 V, Chip selected in write mode or chip deselect

= 5.25 V,

er inputs at 0.8 V,

No load on outputs, Baud rate = 50 kbit/s

VCC = 0, VSS = 0,

= 1

All other terminals

rounded

= 0,

All other terminals floating V

= 0

±20 µA

10 mA

20 30 pF

6 10 pF

10 20 pF

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550C, TL16C550CI

f 16 MHz Max,

6, 78ns

6, 70ns

610ns

67ns

77ns

f 16 MHz, CLK

ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

system timing requirements over recommended ranges of supply voltage and operating free-air temperature

ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

t t t t t t t t t t t t t t t t t t t t t t t t t t t

†

Cycle time, read (tw7 + td8 + td9) RC 87 ns

Cycle time, write (tw6 + td5 + td6) WC 87 ns

Pulse duration, clock high t

Pulse duration, clock low t

Pulse duration, ADS low t

Pulse duration, WR t

Pulse duration, RD t

Pulse duration, MR t

Setup time, address valid before ADS↑ t

su1

Setup time, CS valid before ADS↑ t

su2

Setup time, data valid before WR1↓ or WR2↑ t

su3

Setup time, CTS↑ before midpoint of stop bit 17 10 ns

su4

Hold time, address low after ADS↑ t

Hold time, CS valid after ADS↑ t

Hold time, CS valid after WR1↑ or WR2↓ t

Hold time, address valid after WR1↑ or WR2↓ t

Hold time, data valid after WR1↑ or WR2↓ t

Hold time, chip select valid after RD1↑ or RD2↓ t

Hold time, address valid after RD1↑ or RD2↓ t

†

Delay time, CS valid before WR1↓ or WR2↑ t

†

Delay time, address valid before WR1↓ or WR2↑ t

†

Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ t

†

Delay time, CS valid to RD1↓ or RD2↑ t

†

Delay time, address valid to RD1↓ or RD2↑ t

Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ tRC 7 40 ns

Delay time, RD1↓ or RD2↑ to data valid t

d10

Delay time, RD1↑ or RD2↓ to floating data t

d11 Only applies when ADS is low

ADS

AS CS DS

AH CH

WCS

RCS

CSW

AW WC

CSR

RVD

f = 16 MHz Max VCC = 5 V

6, 7 9 ns

6 40 ns 7 40 ns

6 15 ns

6 5 ns 7 10 ns 7 20 ns

6 40 ns

7 CL = 75 pF 45 ns 7 CL = 75 pF 20 ns

1 µs

system switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 7)

dis(R)

NOTE 7: Charge and discharge times are determined by VOL, VOH, and external loading.

baud generator switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ t

= 75 pF

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

Pulse duration, BAUDOUT low t Pulse duration, BAUDOUT high t Delay time, XIN↑ to BAUDOUT↑ t Delay time, XIN↑↓ to BAUDOUT↓ t

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

RDD

LW HW

BLD

BHD

7 CL = 75 pF 20 ns

f = 16 MHz, CLK ÷ 2 VCC = 5 V

5 5 45 ns 5 45 ns

TL16C550C, TL16C550CI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

receiver switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 8)

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

d12

d13

d14

NOTE 8: In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receive FIFO and the status registers (interrupt identification

transmitter switching characteristics over recommended ranges of supply voltage and operating free-air temperature

d15

d16

d17

d18

d19

d20

d21

†

THRE = transmitter holding register empty; IIR = interrupt identification register.

Delay time, RCLK to sample t Delay time, stop to set INTRPT or read

RBR to LSI interrupt or stop to RXRDY Delay time, read RBR/LSR to reset INTRPT t

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

Delay time, initial write to transmit start t

Delay time, start to INTRPT t Delay time, WR (WR THR) to reset INTRPT t Delay time, initial write to INTRPT (THRE†) t Delay time, read IIR† to reset INTRPT

(THRE†) Delay time, write to TXRDY inactive t

Delay time, start to TXRDY active

↓

SCD

SINT

RINT

IRS

STI

WXI

SXA

8 10 ns

8, 9, 10,

11, 12

8, 9, 10,

11, 12

13 8 24

13 8 10 13 CL = 75 pF 50 ns 13 16 34

13 CL = 75 pF 35 ns 14,15 CL = 75 pF 35 ns 14,15 CL = 75 pF 9

CL = 75 pF 70 ns

baudout

cycles

baudout

cycles

baudout

cycles

baudout

cycles

RCLK

cycle

modem control switching characteristics over recommended ranges of supply voltage and

= 75 pF

operating free-air temperature, C

PARAMETER ALT. SYMBOL FIGURE MIN MAX UNIT

d22

d23

d24

d25

d26

d27

d28

d29

Delay time, WR MCR to output t Delay time, modem interrupt to set INTRPT t Delay time, RD MSR to reset INTRPT t

Delay time, CTS low to SOUT↓ 17 24

Delay time, RCV threshold byte to RTS↑ 18 2

Delay time, read of last byte in receive FIFO to RTS↓ 18 2

Delay time, first data bit of 16th character to RTS↑ 19 2

Delay time, RBRRD low to RTS↓ 19 2

MDO

SIM RIM

16 50 ns 16 35 ns 16 40 ns

baudout

cycles

baudout

cycles

baudout

cycles

baudout

cycles

baudout

cycles

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550C, TL16C550CI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

SLLS177E – MARCH 1994 – REVISED APRIL1998

PARAMETER MEASUREMENT INFORMATION

XIN

BAUDOUT

(1/1)

BAUDOUT

(1/2)

BAUDOUT

(1/3)

BAUDOUT

(1/N)

(N > 3)

2 XIN Cycles

(N–2) XIN Cycles

Figure 5. Baud Generator Timing Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

+ 27 hidden pages

TEXAS INSTRUMENTS TL16C550C, TL16C550CI Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual