TEXAS INSTRUMENTS TL16C550B, TL16C550BI Technical data
查询TL16C550B供应商
D
Capable of Running With All Existing
TL16C450 Software
D
After Reset, All Registers Are Identical to
the TL16C450 Register Set
D
In the FIFO Mode, Transmitter and Receiver
Are Each Buffered With 16-Byte FIFOs to
Reduce the Number of Interrupts to the
CPU
D
In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
D
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
16
to (2
Clock
D
Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream
D
Independent Receiver Clock Input
D
Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled
description
–1) and Generates an Internal 16×
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
D
Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (DC to 562 Kbit/s)
D
False-Start Bit Detection
D
Complete Status Reporting Capabilities
D
3-State Outputs Provide TTL Drive
Capabilities for Bidirectional Data Bus and
Control Bus
D
Line Break Generation and Detection
D
Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, Framing Error
Simulation
D
Fully Prioritized Interrupt System Controls
D
Modem Control Functions (CTS, RTS, DSR,
DTR
, RI, and DCD)
D
Faster Plug-In Replacement for National
Semiconductor NS16550A
The TL16C550B and the TL16C550BI are functional upgrades of the TL16C450 asynchronous
communications element (ACE). Functionally identical to the TL16C450 on power up (character mode
TL16C550B and TL16C550BI can be placed in an alternate mode (FIFO) to relieve the CPU of excessive
software overhead.
In this alternate FIFO mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte
in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and
maximize system efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (RXRDY
TXRDY
The TL16C550B and the TL16C550BI perform serial-to-parallel conversions on data received from a peripheral
device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read and report
on the status of the ACE at any point in the ACE operation. Reported status information includes: the type of
transfer operation in progress, the status of the operation, and any error conditions encountered.
) have been changed to allow signalling of DMA transfers.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
), the
and
†The TL16C550B and the TL16C550BI can also be reset to the TL16C450 mode under software control.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
description (continued)
The TL16C550B and the TL16C550BI ACE include programmable, on-board, baud rate generators. These
generators are capable of dividing a reference clock input by divisors from 1 to (2
16
–1) and producing a 16×
clock for driving the internal transmitter logic. Provisions are included to use this 16× clock to drive the receiver
logic. Also included in the ACE is a complete modem control capability and a processor interrupt system that
may be software tailored to user requirements to minimize the computing required to handle the
communications link.
The TL16C550B is available in a 40-pin DIP (N) package, 44-pin PLCC (FN) package, and 48-pin TQFP (PT)
package. The TL16C550BI is available in a 44-pin PLCC (FN) package.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
D0
D1
D2
D3
D4
D5
D6
D7
RCLK
SIN
SOUT
CS0
CS1
CS2
BAUDOUT
XIN
XOUT
WR1
WR2
V
SS
N PACKAGE
(TOP VIEW)
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
V
CC
RI
DCD
DSR
CTS
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
A0
A1
A2
ADS
TXRDY
DDIS
RD2
RD1
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2
BAUDOUT
FN PACKAGE
(TOP VIEW)
CC
D4D3D2D1D0NCV
54 321644
7
8
9
10
11
12
13
14
15
16
17
18 19
XIN
20 21 22 23
WR2
WR1
XOUT
SS
V
RI
24 25 26 27 28
NC
RD2
RD1
42 41 4043
DCD
DSR
CTS
MR
39
OUT1
38
DTR
37
RTS
36
OUT2
35
NC
34
INTRPT
33
RXRDY
32
A0
31
A1
30
A2
29
ADS
DDIS
TXRDY
BAUDOUT
NC–No internal connection
NC
D5
D6
D7
RCLK
NC
SIN
SOUT
CS0
CS1
CS2
NCD4D3D2D1
47 46 45 44 4348 42
1
2
3
4
5
6
7
8
9
10
11
12
14 15
13
NC
XIN
PT PACKAGE
(TOP VIEW)
17 18 19 20
16
WR1
WR2
XOUT
V
D0
SS
CC
V
RD1
RI
40 39 3841
21
RD2
DCD
DSR
22 23 24
NC
DDIS
NC
CTS
37
36
35
34
33
32
31
30
29
28
27
26
25
ADS
TXRDY
NC
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
A0
A1
A2
NC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
functional block diagram
S
e
l
e
c
t
Receiver
Buffer
Register
D7–D0
8–1
Internal
Data Bus
Data
Bus
Buffer
8
Receiver
FIFO
Receiver
Shift
Register
10
SIN
A0
A1
A2
CS0
CS1
CS2
ADS
MR
RD1
RD2
WR1
WR2
DDIS
TXRDY
XIN
XOUT
RXRDY
28
27
26
12
13
14
25
35
21
22
18
19
23
24
16
17
29
Select
and
Control
Logic
Line
Control
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
Interrupt
Enable
Register
Baud
Generator
Transmitter
FIFO
Interrupt
Control
Logic
Receiver
Timing and
Control
Line
Control
Register
S
e
l
e
c
t
Line
Control
Register
Modem
Control
Logic
9
15
11
32
36
33
37
38
39
34
31
30
RCLK
BAUDOUT
SOUT
RTS
CTS
DTR
DSR
DCD
RI
OUT1
OUT2
INTRPT
Terminal numbers shown are for the N package.
4
Interrupt
I/O
Register
FIFO
Control
Register
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
Terminal Functions
TERMINAL
NAME
A0
A1
A2
ADS 25 28 24 I Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select
BAUDOUT 15 17 12 O Baud out. BAUDOUT is a 16× clock signal for the transmitter section of the ACE. The clock rate is
CS0
CS1
CS2
CTS 36 40 38 I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of
D0
D1
D2
D3
D4
D5
D6
D7
DCD 38 42 40 I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD)
DDIS 23 26 22 O Driver disable. This output is active (high) when the CPU is not reading data. When active, this output
DSR 37 41 39 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of
DTR 33 37 33 O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to
INTRPT 30 33 30 O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced.
MR 35 39 35 I Master reset. When active (high), MR clears most ACE registers and sets the state of various output
OUT1
OUT2
RCLK 9 10 5 I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE.
NO.NNO.FNNO.
28
31
27
30
26
29
12
14
13
15
14
16
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
343138353431O Outputs 1 and 2. User-designated outputs that are set to their active low states by setting their
I/O
PT
28
I Register select. A0–A2 are used during read and write operations to select the ACE register to read
27
26
9
10
11
43
44
45
46
47
2
3
4
from or write to. Refer to Table 1 for register addresses, and refer to the address strobe (ADS
description.
signals (CS0, CS1, CS2
select signals are held in the state they are in when the low-to-high transition of ADS
established by the reference oscillator frequency divided by a divisor specified by the baud generator
divisor latches. BAUDOUT
I Chip select. When CS0 = high, CS1 = high, and CS2 = low, these three inputs select the ACE. When
any of these inputs are inactive, the ACE remains inactive. Refer to the ADS
the modem status register. Bit 0 (∆CTS) of the modem status register indicates that this signal has
changed states since the last read from the modem status register. If the modem status interrupt is
enabled when CTS
I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the ACE and the CPU.
of the modem status register. Bit 3 (∆DCD) of the modem status register indicates that this signal has
changed states since the last read from the modem status register. If the modem status interrupt is
enabled when DCD
can disable an external transceiver.
the modem status register. Bit 1 (∆DSR) of the modem status register indicates this signal has changed
states since the last read from the modem status register. If the modem status interrupt is enabled when
DSR
changes state, an interrupt is generated.
establish communication. DTR
register to a high level. DTR
loop mode operation, or clearing the DTR bit.
Four conditions that cause an interrupt to be issued are: a receiver error, received data is available or
timed out (FIFO mode only), the transmitter holding register is empty, or an enabled modem status
interrupt. The INTRPT output is reset (deactivated) either when the interrupt is serviced or as a result
of a master reset.
signals. Refer to Table 2.
respective modem control register bits (OUT1 and OUT2) high. OUT1
(high) states as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or
bit 3 (OUT2) of the modem control register.
) drive the internal select logic directly; when high, the register select and chip
can also be used for the receiver section by tying this output to RCLK.
changes state, an interrupt is generated.
changes state, an interrupt is generated.
is placed in the active state by setting the DTR bit of the modem control
is placed in the inactive state either as a result of a master reset, during
DESCRIPTION
) signal
occurs.
signal description.
and OUT2 are set to their inactive
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
Terminal Functions (Continued)
TERMINAL
NAME
RD1
RD2
RI 39 43 41 I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the
RTS 32 36 32 O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive
RXRDY 29 32 29 O Receiver ready output. Receiver direct memory access (DMA) signalling is available with this terminal.
SIN 10 11 7 I Serial data input. Input from a connected communications device
SOUT 11 13 8 O Composite serial data output. Output to a connected communication device. SOUT is set to the marking
TXRDY 24 27 23 O T ransmitter ready output. Transmitter DMA signalling is available with this terminal. When operating in
V
CC
V
SS
WR1
WR2
XIN
XOUT
NO.NNO.FNNO.
212224251920I Read inputs. When either input is active (low or high respectively) while the ACE is selected, the CPU
40 44 42 5-V supply voltage
20 22 18 Supply common
181920211617I Write inputs. When either input is active (high or low respectively) and while the ACE is selected, the
161718191415I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).
PT
I/O
is allowed to read status information or data from a selected ACE register. Only one of these inputs is
required for the transfer of data during a read operation; the other input should be tied in its inactive state
(i.e., RD2 tied low or RD1
modem status register. Bit 2 (TERI) of the modem status register indicates that the RI
transitioned from a low to a high state since the last read from the modem status register. If the modem
status interrupt is enabled when this transition occurs, an interrupt is generated.
data. RTS
(high) state either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS)
of the MCR.
When operating in the FIFO mode, one of two types of DMA signalling can be selected using the FIFO
control register bit 3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed.
Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1
supports multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO
has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is at least one
character in the receiver FIFO or receiver holding register, RXRDY
been active but there are no characters in the FIFO or holding register, RXRDY
In DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger level or the timeout has been reached, RXRDY
goes active (low); when it has been active but there are no more characters in the FIFO or holding
register, it goes inactive (high).
(set) state as a result of master reset.
the FIFO mode, one of two types of DMA signalling can be selected using FCR3. When operating in
the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a
transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple
transfers are made continuously until the transmit FIFO has been filled.
CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is
required to transfer data during a write operation; the other input should be tied in its inactive state (i.e.,
WR2 tied low or WR1
is set to its active state by setting the RTS modem control register bit and is set to its inactive
tied high).
tied high).
DESCRIPTION
input has
is active low. When RXRDY has
goes inactive (high).
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C550B, TL16C550BI
O erating free-air tem erature, T
A
IlInput current
CC
,
SS
,
10µA
,
,
V
CC
5.25 V, V
SS
0,
OZ
g
O
µ
V
CC
T
A
25 C
SIN, DSR, DCD, CTS, and RI at 2 V
ICCSu ly current
All oth
XTAL1 at 4 MH
10
mA
f
MHz
T
A
25°C
g
All other terminals grounded
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range at any input, V
Output voltage range, V
Continuous total power dissipation at (or below) 70°C 300 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
Operating free-air temperature range, T
Case temperature for 10 seconds, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N or PT package 260°C. . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS (ground).
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
: TL16C550B 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
TL16C550BI –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
p
CC
p
IH
IL
TL16C550B 0 70 °C
TL16C550BI –40 85 °C
4.75 5 5.25 V
2 V
–0.5 0.8 V
CC
V
†
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
‡
V
OH
V
OL
I
OZ
I
C
i(CLK)
C
o(CLK)
C
i
C
o
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
These parameters apply for all outputs except XOUT.
High-level output voltage IOH = –1 mA 2.4 V
‡
Low-level output voltage IOL = 1.6 mA 0.4 V
V
p
High-impedance-state output current
Supply current
Clock input capacitance 15 20 pF
Clock output capacitance
Input capacitance
Output capacitance
= 5.25 V, V
VI = 0 to 5.25 V,
V
= 5.25 V
VO = 0 to 5.25 V,
Chip selected in write mode or chip deselect
= 5.25 V,
er inputs at 0.8 V,
No load on outputs, Baud rate = 50 kbit/s
VCC = 0, VSS = 0,
= 1
All other terminals
,
rounded
= 0,
All other terminals floating
V
= 0
°
=
,
,
z,
=
,
°
20 30 pF
6 10 pF
10 20 pF
±20 µA
10 mA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
t
Cycle time, read (tw7 + td8 + td9) RC 87 ns
cR
t
Cycle time, write (tw6 + td5 + td6) WC 87 ns
cW
t
Pulse duration, clock high t
w1
t
Pulse duration, clock low t
w2
t
Pulse duration, address strobe low t
w5
t
Pulse duration, write strobe t
w6
t
Pulse duration, read strobe tRD 3 40 ns
w7
t
Pulse duration, master reset t
w8
t
Setup time, address valid before ADS↑ t
su1
t
Setup time, chip select valid before ADS↑ t
su2
t
Setup time, data valid before WR1↓ or WR2↑ t
su3
t
Hold time, address low after ADS↑ t
h1
t
Hold time, chip select valid after ADS↑ t
h2
t
Hold time, chip select valid after WR1↑ or WR2↓ t
h3
t
Hold time, address valid after WR1↑ or WR2↓ t
h4
t
Hold time, data valid after WR1↑ or WR2↓ t
h5
t
Hold time, chip select valid after RD1↑ or RD2↓ t
h6
t
Hold time, address valid after RD1↑ or RD2↓ t
h7
†
t
Delay time, chip select valid before WR1↓ or WR2↑ t
d4
†
t
Delay time, address valid before WR1↓ or WR2↑ t
d5
†
t
Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ t
d6
†
t
Delay time, chip select valid to RD1↓ or RD2↑ t
d7
†
t
Delay time, address valid to RD1↓ or RD2↑ t
d8
t
Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ tRC 3 40 ns
d9
t
Delay time, RD1↓ or RD2↑ to data valid t
d10
t
Delay time, RD1↑ or RD2↓ to floating data t
d11
†
Only applies when ADS is low
XH
XL
ADS
WR
MR
AS
CS
DS
AH
CH
WCS
WA
DH
RCS
RA
CSW
AW
WC
CSR
AR
RVD
HZ
1 f = 9 MHz maximum 40 ns
1 f = 9 MHz maximum 40 ns
2,3 9 ns
2 40 ns
1 µs
2,3 8 ns
2,3 8 ns
2 15 ns
2,3 0 ns
2,3 0 ns
2 10 ns
2 10 ns
2 5 ns
3 10 ns
3 20 ns
2 7 ns
2 7 ns
2 40 ns
3 7 ns
3 7 ns
3 CL = 75 pF 45 ns
3 CL = 75 pF 20 ns
system switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 2)
PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
t
dis(R)
NOTE 2: Charge and discharge time is determined by VOL, VOH, and external loading.
Disable time, RD1↑↓ or RD2↓↑ to DDIS↑↓ t
RDD
3 CL = 75 pF 20 ns
baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, C
PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
t
w3
t
w4
t
d1
t
d2
8
Pulse duration, BAUDOUT low t
Pulse duration, BAUDOUT high t
Delay time, XIN↑ to BAUDOUT↑ t
Delay time, XIN↑↓ to BAUDOUT↓ t
= 75 pF
L
LW
HW
BLD
BHD
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1 f = 9 MHz, CLK ÷ 2 80 ns
1 f = 9 MHz, CLK ÷ 2 80 ns
1 75 ns
1 65 ns
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 3)
PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
t
Delay time, RCLK to sample t
d12
Delay time, stop to set interrupt or read
t
d13
RBR to LSI interrupt or stop to RXRDY
t
Delay time, read RBR/LSR to reset interrupt low t
d14
NOTE 3: In the FIFO mode, the read cycle (RC) = 425 ns (minimum) between reads of the receiver FIFO and the status registers (interrupt
identification register or line status register).
↓
SCD
t
SINT
RINT
transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
Delay time, initial write (INTRPT low) to transmit
t
d15
start (SOUT low)
Delay time, stop (SOUT low) to interrupt (INTRPT
t
d16
high)
Delay time, WR THR high to reset interrupt
t
d17
(INTRPT low)
Delay time, initial WR THR low to THRE interrupt
t
d18
(INTRPT high)
Delay time, RD IIR low to reset THRE interrupt
t
d19
(INTRPT low)
Delay time, WR THR high to TXRDY high
t
d20
(inactive)
Delay time, start (SOUT low) to TXRDY low
t
d21
(active)
t
IRS
t
STI
t
HR
t
t
t
WXI
t
SXA
SI
IR
4 10 ns
4,5,6,7,8 1
4,5,6,7,8 CL = 75 pF 40 ns
9 8 24
9 8 9
9 CL = 75 pF 50 ns
9 16 32
9 CL = 75 pF 35 ns
10,11 CL = 75 pF 35 ns
10,11 CL = 75 pF 8
RCLK
cycle
baudout
cycles
baudout
cycles
baudout
cycles
baudout
cycles
modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, C
PARAMETER ALT. SYMBOL FIGURE MIN MAX UNIT
t
Delay time, WR MCR low to output (RTS, DTR, OUT1, OUT2) low or high t
d22
Delay time, modem interrupt (CTS, DSR, DCD) low to set interrupt
t
d23
(INTRPT) high
t
Delay time, RD MSR low to reset interrupt (INTRPT) low t
d24
= 75 pF
L
MDO
t
SIM
RIM
12 50 ns
12 35 ns
12 40 ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
t
w2
t
w4
t
d2
XIN
BAUDOUT
(1/1)
BAUDOUT
(1/2)
t
w1
t
d1
t
d1
t
w3
N
t
d2
BAUDOUT
(1/3)
BAUDOUT
(1/N)
(N > 3)
2 XIN Cycles
(N–2) XIN Cycles
Figure 1. Baud Generator Timing Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
t
w5
TL16C550B, TL16C550BI
ADS
A0–A2
CS0, CS1, CS2
WR1, WR2
D7–D0
†
Applicable only when ADS
50%
50%50%
t
su1
t
h1
Valid Valid
t
su2
50% 50%
is low.
Valid Valid
t
h3
t
t
d4
t
d5
50% 50%
t
su3
w6
Active
Valid Data
†
t
h2
†
†
t
h4
t
d6
t
h5
50%
50%50%
Figure 2. Write Cycle Timing Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
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