High-Speed Drive Controller for PNP Power
Transistor
D
Internal-Regulator Provides a Stable 1.5 V
Reference Supply
D
Low Start-Up Voltage 3.1 V
description
The TL1464I incorporates on a single monolithic chip all the functions required in the construction of a
pulse-width-modulation control circuit. Designed primarily for power supply control, the TL1464I contains an
on-chip 1.5 V regulator, four error amplifiers, an oscillator, two dead-time comparators, undervoltage lockout
circuitry, short circuit protection, standby control circuitry, and output circuits.
The external speed-up capacitors provide exceptional rise and fall time performance for the PNP power
transistor.
The TL1464I operates from 3.1 V supply voltage and 2 pair of four-outputs (CH-1/CH-3, CH-2/CH-4 the same
period) at the inverse phase of each other. As a result, the TL1464I provides high-efficiency power supply.
NOTE: When the STANDBY input is high (≥ 2.4 V), OUTPUT-2 to 4 are controlled individually. If STANDBY-2 input is low
(≤ 0.4 V), OUTPUT-2 is turned off. When CH-2 standby mode is released, CH-2 can do the soft-start function.
QUAD PULSE-WIDTH-MODULATION CONTROL CIRCUIT
D
Internal Short-Circuit Protection
D
Internal Undervoltage Lockout Protection
D
Internal Shut-Down Circuit by Channel
D
Controllable Base Current of External
Transistor
FUNCTION TABLE
INPUTS
VI ≥ 2.4 VHONONONON
VI ≥ 0.4 VHONSee NoteSee NoteSee Note
OUTPUT FUNCTIONS
TL1464I
SLVS266 – FEBRUAR Y 2000
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
TL1464I
QUAD PULSE-WIDTH-MODULATION CONTROL CIRCUIT
STANDBY21Output-1 to 4 control pin. Input L level voltage (0.4 V max). All outputs function and VREF are shutdown.
STANDBY -220Output-2 control pin. Input L level voltage (0.4 V max), output-2 function is shutdown.
STANDBY-319Output-3 control pin. Input L level voltage (0.4 V max), output-3 function is shutdown.
STANDBY-418Output-4 control pin. Input L level voltage (0.4 V max), output-4 function is shutdown.
V
CC
12Power supply pin
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage4 value are with respect to network ground terminal.
2. Using t1.6 × 50 × 50 mm glass epoxy resin.
recommended operating conditions
MINNOMMAXUNIT
Supply voltage, V
p
Output voltage, V
Current into feedback terminal, I
Feedback resistor, R
Boot-strap capacitor, C
Bias resistor, R
Bias capacitor, C
Timing resistor , R
Timing capacitor , C
Oscillation frequency, f
Operating free-air temperature, T
CC
p
p
(BIAS)
O
(NF)
(BIAS)
(T)
(T)
IC
p
I
(BOOT)
(OSC)
CH-1,2–0.1VCC–1.8
CH-3,40VCC–1.8
H level2.4V
L level0.4
(CAMP)
A
3.112V
CC
12V
–45µA
100kΩ
100500pF
1.220
30200pF
750kΩ
681000pF
0.052MHz
–2075°C
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TL1464I
Output voltage change with temperature
T
25°C
Frequency change with temperature
QUAD PULSE-WIDTH-MODULATION CONTROL CIRCUIT
SLVS266 – FEBRUAR Y 2000
electrical characteristics over recommended operating free-air temperature range, VCC = 6 V, f =
1 MHz (unless otherwise noted)
reference section
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
V
ref
R
(EGIN)
R
(EFL)
V
(RTC1)
R
(RTC2)
I
OS
undervoltage lockout section
V
IH
V
IL
V
hys
V
R
Output voltage (pin 16)TA = 25°C,I
Input regulationVOS = 3.1 V to 12 V,I
Output regulationI
p
Short-circuit output currentV
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Upper threshold voltage2.7V
Lower threshold voltage
Hysteresis
Reset threshold voltage (VCC)2.22.3V
p
= –0.1 mA to –1 mA17.5mV
(OR)
TA = 20°C to 25°C–0.2%±2%
TA = 25°C to 75°C–0.2%±2%
= 0 V48mA
ref
=
A
= –1 mA1.4851.501.515V
(OR)
= –1 mA212.5mV
(OR)
°
2.5V
0.10.2V
output voltage monitor section
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
V
IO(M)
I
(BOM)
V
(IOM)
Input offset voltage
Input bias currentVI = 0 V–200–500nA
Input voltage rangeVCC = 3.1 V ~ 12 V
protection control section
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
V
(tPC)
V
(stby)
V
I
I
(bPC)
Input threshold voltage (pin 15)TA = 25°C1.451.501.55V
Standby voltage (pin 15)4070100mV
Latched input voltage (pin 15)1030mV
Input source current (pin 15)TA = 25°C–1–3–6µA
oscillator section
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
f
(OSC)
f
(dev)
f
(dV)
f
(dT1)
f
(dT2)
FrequencyCt = 100 pF,Rt = 10 kΩ1MHz
Standard deviation of frequencyAll values are constant7%
Frequency change with voltageVCC = 3 V ~ 12 V1%
TA = 25°C (CH-1,2)0
VI = 1.5 V (pins 6 and 9),
TA = 25°C (CH-3,4)
VCC–1.8
p
TA = 20°C to 25°C–0.5%±4%
TA = 25°C to 75°C0.5%±4%
10.5
0 to
V
V
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
In ut threshold voltage
V
V
Common-mode input voltage
V
V
V
Maximum output voltage swing
V
I
Output current (sink)
mA
TL1464I
QUAD PULSE-WIDTH-MODULATION CONTROL CIRCUIT
SLVS266 – FEBRUAR Y 2000
electrical characteristics over recommended operating free-air temperature range, VCC = 6 V, f =
1 MHz (unless otherwise noted) (continued)
dead-time control section
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
I
(Idt)
I
(dt)
V
(dt)
V
IO
V
(tt00)
error-amplifier section
V
IO
I
IO
I
IB
ICR
A
(v)
B1Unity-gain bandwidth6MHz
CMRRCommon-mode rejection ratioVIC = –0.1 V ~ VCC – 1.8 V6080dB
V
Output current (sink)VID = –0.1 V, VO = 1.25 V0.51mA
Sink current (pin 24) (standby mode)
Output current (source)VID = 0.1 V, VO = 0.75 V–45–85µA
= 100 µA0.5V
(dt)
Zero duty cycle0.60.70.8
100% duty cycle1.31.41.5
–0.1 to
= 3.1 V ~ 12
CC
VI = 0.3 V (pin 24)
VI = 0 V (pin 20)
VCC–1.8
0 to
VCC–1.8
V
–0.1
ref
0.10.5mA
0.2
output section
(SINK)
p
total device
I
O(CS)
I
O(CA)
Standby supply currentStandby pin input voltage = 0 V1200µA
Average supply currentRt = 10 kΩ47mA
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
R
= 2.4 kΩ152025
(BIAS)
R
= 5.8 kΩ7.51012.5
(BIAS)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TL1464I
p
p
QUAD PULSE-WIDTH-MODULATION CONTROL CIRCUIT
SLVS266 – FEBRUAR Y 2000
WAVEFORM (see Note A)
OSCILLATOR
DEAD-TIME
INPUT VOLTAGE
ERROR AMP. OUTPUT
PWM COMP. OUTPUT
OUTPUT PIN WAVEFORM
REGULATED OUTPUT
VOLTAGE (see Note B)
SCP PIN WAVEFORM
SCP COMP. OUTPUT
POWER SUPPLY
VOLTAGE
OSCILLAT OR
WAVEFORM (see Note A)
ERROR AMP. OUTPUT
PWM COMP. OUTPUT
OUTPUT PIN WAVEFORM
REGULATED OUTPUT
VOLTAGE (see Note B)
SCP PIN WAVEFORM
SCP COMP. OUTPUT
POWER SUPPLY
VOLTAGE
2.7 V
2.7 V
V
A
V
A
Protection Enable Time, t
Figure 1. Timing Diagram (CH-1/CH-2)
V
A
V
A
Protection Enable Time, tpe = 477×103 Cpe (sec)
1.4 V
0.7 V
0 V
“H”
(sec)
e
“L”
“H”
“L”
0 V
V
ref
1.5 V
“H”
“L”
V
CC
0 V
1.4 V
0.7 V
“H”
“L”
“H”
“L”
0 V
V
ref
1.5 V
“H”
“L”
V
CC
0 V
+ 0.7 V
+ 0.7 V
DEAD-TIME 100%
V
A
t
pe
= 477×103 C
e
DEAD-TIME 100%
V
A
t
pe
Figure 2. Timing Diagram (CH-3/CH-4)
NOTES: A. Oscillator waveform of CH-1 and CH-2 is inverting output each other.
8
B. Va = input voltage of pin 29 (pin 24)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL1464I
QUAD PULSE-WIDTH-MODULATION CONTROL CIRCUIT
SLVS266 – FEBRUAR Y 2000
MECHANICAL DATA
PT (S-PQFP-G48) PLASTIC QUAD FLATPACK
37
48
0,50
1,45
1,35
36
0,27
0,17
25
24
13
1
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
12
0,08
M
0,05 MIN
0,13 NOM
Gage Plane
0,25
0°–7°
1,60 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. This may also be a thermally enhanced plastic package with leads conected to the die pads.
Seating Plane
0,10
0,75
0,45
4040052/C 11/96
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable DeviceStatus
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
TL1464IPTACTIVELQFPPT48250TBDCU NIPDAULevel-2-220C-1 YEAR
TL1464IPTG4ACTIVELQFPPT48250Green (RoHS &
no Sb/Br)
TL1464IPTRACTIVELQFPPT481000TBDCU NIPDAULevel-2-220C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAULevel-3-260C-168 HR
(3)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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