Texas Instruments TL1454IDR, TL1454EVM-085, TL1454ID, TL1454CPWR, TL1454CPWLE Datasheet
...
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
D
T wo Complete PWM Control Circuits
D
Outputs Drive MOSFETs Directly
D
Oscillator Frequency...50 kHz to 2 MHz
D
3.6-V to 20-V Supply-Voltage Range
D
Low Supply Current...3.5 mA Typ
D
Adjustable Dead-Time Control, 0% to 100%
D
1.25-V Reference
description
The TL1454 is a dual-channel pulse-width-modulation (PWM) control circuit, primarily intended for
low-power, dc/dc converters. Applications include
LCD displays, backlight inverters, notebook computers, and other products requiring small, high-frequency , dc/dc converters. Each PWM channel has its own
error amplifier, PWM comparator, dead-time control comparator, and MOSFET driver. The voltage reference,
oscillator, undervoltage lockout, and short-circuit protection are common to both channels.
Channel 1 is configured to drive n-channel MOSFETs in step-up or flyback converters, and channel 2 is
configured to drive p-channel MOSFETs in step-down or inverting converters. The operating frequency is set
with an external resistor and an external capacitor, and dead time is continuously adjustable from 0 to 100%
duty cycle with a resistive divider network. Soft start can be implemented by adding a capacitor to the dead-time
control (DTC) network. The error-amplifier common-mode input range includes ground, which allows the
TL1454 to be used in ground-sensing battery chargers as well as voltage converters.
AVAILABLE OPTIONS
PACKAGED DEVICES
†
T
A
SMALL OUTLINE
(D)
PLASTIC DIP
(N)
TSSOP
(PW)
CHIP FORM
(Y)
–20°C to 85°C TL1454CD TL1454CN TL1454CPWLE TL1454Y
–40°C to 85°C TL1454ID TL1454IN — —
†
The D package is available taped and reeled. Add the suffix R to the device name (e.g., TL1454CDR). The
PW package is available only left-end taped and reeled (indicated by the LE suffix on the device type; e.g.,
TL1454CPWLE).
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CT
RT
DTC1
IN1+
IN1–
COMP1
GND
OUT1
D, N OR PW PACKAGE
(TOP VIEW)
REF
SCP
DTC2
IN2+
IN2–
COMP2
V
CC
OUT2
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
functional block diagram
_
+
_
+
OSC
PWM
Comparator 1
Error
Amplifier 1
To Internal
Circuitry
2.5 V
1.25 V
1 V
1 V
SCP
V
CC
GND
DTC1 DTC2
143
15
7
16
4
5
13
12
6
11
10
21
CTRT
OUT1
OUT2
8
V
CC
UVLO
and
SCP Latch
IN1+
IN1–
IN2+
IN2–
COMP1
COMP2
REF
1.8 V
1.2 V
SCP
Comparator 1
Voltage
REF
9
V
CC
0.65 V
0.65 V
1.25 V
PWM
Comparator 2
Error
Amplifier 2
SCP
Comparator 2
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TL1454Y chip information
This chip, when properly assembled, displays characteristics similar to the TL1454C. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
TL1454Y
(2)
(14)
(1)
(3)
(4)
(5)
(6)
(7)
(8)
(16)
(13)
(12)
(11)
(10)
(9)
REF
DTC2
IN2+
IN2–
COMP2
V
CC
OUT2OUT1
COMP1
IN1–
IN1+
RT
CT
GND
86
108
(1)
(2) (3)
(4) (5) (6) (7)
(10)(11)
(12)(13)(14)(15)
(16)
(8)
(9)
(15)
SCP
DTC1
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
theory of operation
reference voltage
A linear regulator operating from V
CC
generates a 2.5-V supply for the internal circuits and the 1.25-V reference,
which can source a maximum of 1 mA for external loads. A small ceramic capacitor (0.047 µF to 0.1 µF) between
REF and ground is recommended to minimize noise pickup.
error amplifier
The error amplifier generates the error signal used by the PWM to adjust the power-switch duty cycle for the
desired converter output voltage. The signal is generated by comparing a sample of the output voltage to the
voltage reference and amplifying the difference. An external resistive divider connected between the converter
output and ground, as shown in Figure 1, is generally required to obtain the output voltage sample.
The amplifier output is brought out on COMP to allow the frequency response of the amplifier to be shaped with
an external RC network to stabilize the feedback loop of the converter. DC loading on the COMP output is limited
to 45 µA (the maximum amplifier source current capability).
Figure 1 illustrates the sense-divider network and error-amplifier connections for converters with positive output
voltages. The divider network is connected to the noninverting amplifier input because the PWM has a phase
inversion; the duty cycle decreases as the error-amplifier output increases.
_
+
IN–
IN+
R3
R1
R2
COMP
To PWM
V
O
Compensation
Network
REF
Converter
Output
TL1454
Figure 1. Sense Divider/Error Amplifier
Configuration for Converters with Positive Outputs
The output voltage is given by:
VO+
V
ref
ǒ
1
)
R1
R2
Ǔ
where V
ref
= 1.25 V.
The dc source resistance of the error-amplifier inputs should be 10 kΩ or less and approximately matched to
minimize output voltage errors caused by the input-bias current. A simple procedure for determining appropriate
values for the resistors is to choose a convenient value for R3 (10 kΩ or less) and calculate R1 and R2 using:
R1+
R3V
O
VO–V
ref
R2+
R3V
O
V
ref
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
error amplifier
R1 and R2 should be tight-tolerance (±1% or better) devices with low and/or matched temperature coefficients
to minimize output voltage errors. A device with a ±5% tolerance is suitable for R3.
_
+
IN–
IN+
R2
COMP
To PWM
V
O
Compensation
Network
REF
R1
R3
Converter
Output
Figure 2. Sense Divider/Error Amplifier Configuration for Converters with Negative Outputs
Figure 2 shows the divider network and error-amplifier configuration for negative output voltages. In general,
the comments for positive output voltages also apply for negative outputs. The output voltage is given by:
VO+*
R1V
ref
R
2
The design procedure for choosing the resistor value is to select a convenient value for R2 (instead of R3 in
the procedure for positive outputs) and calculate R1 and R3 using:
R1+*
R2V
O
V
ref
R3+
R1R
2
R1)
R
2
V alues in the 10-kΩ to 20-kΩ range work well for R2. R3 can be omitted and the noninverting amplifier connected
to ground in applications where the output voltage tolerance is not critical.
oscillator
The oscillator frequency can be set between 50 kHz and 2 MHz with a resistor connected between RT and GND
and a capacitor between CT and GND (see Figure 3). Figure 6 is used to determine R
T
and CT for the desired
operating frequency. Both components should be tight-tolerance, temperature-stable devices to minimize
frequency deviation. A 1% metal-film resistor is recommended for R
T
, and a 10%, or better, NPO ceramic
capacitor is recommended for C
T
.
R
T
C
T
RT CT
TL1454
21
Figure 3. Oscillator Timing
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
dead-time control (DTC) and soft start
The two PWM channels have independent dead-time control inputs so that the maximum power-switch duty
cycles can be limited to less then 100%. The dead-time is set with a voltage applied to DTC; the voltage is
typically obtained from a resistive divider connected between the reference and ground as shown in Figure 4.
Soft start is implemented by adding a capacitor between REF and DTC.
The voltage, V
DT
, required to limit the duty cycle to a maximum value is given by:
VDT+
V
O(max)
*
D
ǒ
V
O(max)
*
V
O(min)
Ǔ
*
0.65
where V
O(max)
and V
O(min)
are obtained from Figure 9, and D is the maximum duty cycle.
Predicting the regulator startup or rise time is complicated because it depends on many variables, including:
input voltage, output voltage, filter values, converter topology , and operating frequency. In general, the output
will be in regulation within two time constants of the soft-start circuit. A five-to-ten millisecond time constant
usually works well for low-power converters.
The DTC input can be grounded in applications where achieving a 100% duty cycle is desirable, such as a buck
converter with a very low input-to-output differential voltage. However, grounding DTC prevents the
implementation of soft start, and the output voltage overshoot at power-on is likely to be very large. A better
arrangement is to omit R
DT1
(see Figure 4) and choose R
DT2
= 47 kΩ. This configuration ensures that the duty
cycle can reach 100% and still allows the designer to implement soft start using C
SS
.
C
SS
REF
TL1454
R
DT1
DTC
R
DT2
16
Figure 4. Dead-Time Control and Soft Start
PWM comparator
Each of the PWM comparators has dual inverting inputs. One inverting input is connected to the output of the
error amplifier; the other inverting input is connected to the DTC terminal. Under normal operating conditions,
when either the error-amplifier output or the dead-time control voltage is higher than that for the PWM triangle
wave, the output stage is set inactive (OUT1 low and OUT2 high), turning the external power stage off.
undervoltage-lockout (UVLO) protection
The undervoltage-lockout circuit turns the output circuit off and resets the SCP latch whenever the supply
voltage drops too low (to approximately 2.9 V) for proper operation. A hysteresis voltage of 200 mV eliminates
false triggering on noise and chattering.
short-circuit protection (SCP)
The TL1454 SCP function prevents damage to the power switches when the converter output is shorted to
ground. In normal operation, SCP comparator 1 clamps SCP to approximately 185 mV. When one of the
converter outputs is shorted, the error amplifier output (COMP) will be driven below 1 V to maximize duty cycle
and force the converter output back up. When the error amplifier output drops below 1 V, SCP comparator 1
releases SCP, and capacitor, C
SCP
, which is connected between SCP and GND, begins charging. If the
error-amplifier output rises above 1 V before C
SCP
is charged to 1 V , SCP comparator 1 discharges C
SCP
and
normal operation resumes. If C
SCP
reaches 1 V , SCP comparator 2 turns on and sets the SCP latch, which turns
off the output drives and resets the soft-start circuit. The latch remains set until the supply voltage is lowered
to 2 V or less, or C
SCP
is discharged externally.
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
short-circuit protection (SCP) (continued)
The SCP time-out period must be greater than the converter start-up time or the converter will not start. Because
high-value capacitor tolerances tend to be ±20% or more and IC resistor tolerances are loose as well, it is best
to choose an SCP time-out period 10-to-15 times greater than the converter startup time. The value of C
SCP
may be determined using Figure 6, or it can be calculated using:
C
SCP
+
T
SCP
80.3
where C
SCP
is in µF and T
SCP
is the time-out period in ms.
output stage
The output stage of the TL1454 is a totem-pole output with a maximum source/sink current rating of 40 mA and
a voltage rating of 20 V . The output is controlled by a complementary output AND gate and is turned on (sourcing
current for OUT1, sinking current for OUT2) when all the following conditions are met: 1) the oscillator triangle
wave voltage is higher than both the DTC voltage and the error-amplifier output voltage, 2) the
undervoltage-lockout circuit is inactive, and 3) the short-circuit protection circuit is inactive.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
(see Note 1) 23 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error amplifier input voltage: IN1+, IN1–, IN2+, IN2– 23 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage: OUT1, OUT2 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current: OUT1, OUT2 ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak output current: OUT1, OUT2 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: C suffix –20°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network GND.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D 950 mW 7.6 mW/°C 608 mW 494 mW
N 1250 mW 10.0 mW/°C 800 mW 650 mW
PW 500 mW 4.0 mW/°C 320 mW 260 mW
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
recommended operating conditions
MIN MAX UNIT
Supply voltage, V
CC
3.6 20 V
Error amplifier common-mode input voltage –0.2 1.45 V
Output voltage, V
O
20 V
Output current, I
O
±40 mA
COMP source current –45 µA
COMP sink current 100 µA
Reference output current 1 mA
COMP dc load resistance 100 kΩ
Timing capacitor , C
T
10 4000 pF
Timing resistor , R
T
5.1 100 kΩ
Oscillator frequency 50 2000 kHz
p
p
TL1454C –20 85
°
Operating free-air temperature, T
A
TL1454I –40 85
°C
electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,
f
osc
= 500 kHz (unless otherwise noted)
reference
TL1454
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
p
IO = 1 mA, TA = 25°C 1.23 1.25 1.28
V
ref
Output voltage, REF
IO = 1 mA 1.2 1.31
V
Input regulation VOC = 3.6 V to 20 V, IO = 1 mA 2 6 mV
Output regulation IO = 0.1 mA to 1 mA 1 7.5 mV
p
p
TA = T
A(min)
to 25°C, IO = 1 mA –12.5 –1.25 12.5
Output voltage change with temperature
TA = 25°C to 85°C, IO = 1 mA –12.5 –2.5 12.5
mV
I
OS
Short-circuit output current V
ref
= 0 V 30 mA
undervoltage lockout (UVLO)
TL1454
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
V
IT+
Positive-going threshold voltage 2.9 V
V
IT–
Negative-going threshold voltage
TA = 25°C
2.7 V
V
hys
Hysteresis, V
IT+
– V
IT–
100 200 mV
short-circuit protection (SCP)
TL1454
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
V
IT
Input threshold voltage TA = 25°C 0.95 1 1.05 V
V
stby
†
Standby voltage
p
p
140 185 230 mV
V
I(latched)
Latched-mode input voltage
No pullup
60 120 mV
V
IT(COMP)
Comparator threshold voltage COMP1, COMP2 1 V
Input source current TA = 25°C, V
O(SCP)
= 0 –5 –15 –20 µA
†
This symbol is not presently listed within EIA/JEDEC standards for semiconductor symbology.
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,
f
osc
= 500 kHz (unless otherwise noted) (continued)
oscillator
TL1454
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
f
osc
Frequency CT = 120 pF, RT = 10 kΩ 500 kHz
Standard deviation of frequency 50 kHz
Frequency change with voltage VCC = 3.6 V to 20 V, TA = 25°C 5 kHz
p
TA = T
A(min)
to 25°C –2 ±20
Frequency change with temperature
TA = 25°C to 85°C –10 ±20
kH
z
Maximum ramp voltage 1.8 V
Minimum ramp voltage 1.1 V
dead-time control (DTC)
TL1454
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
p
Duty cycle = 0% 1 1.1 1.2
VITInput threshold voltage
Duty cycle = 100% 0.4 0.5 0.6
V
V
I(latched)
Latched-mode input voltage 1.2 V
I
IB
Common-mode input bias current DTC1, IN1+ ≈ 1.2 V 4 µA
Latched-mode (source) current TA = 25°C –100 µA
error-amplifier
TL1454
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
V
IO
Input offset voltage 6 mV
I
IO
Input offset current
VO = 1.25 V , VIC = 1.25 V
100 nA
I
IB
Input bias current –160 –500 nA
V
ICR
Input voltage range VCC = 3.6 V to 20 V –0.2 to 1.40 V
A
V
Open-loop voltage gain RFB = 200 kΩ 70 80 dB
Unity-gain bandwidth 3 MHz
CMRR Common-mode rejection ratio 60 80 dB
V
OM(max)
Positive output voltage swing 2.3 2.43
V
OM(min)
Negative output voltage swing 0.63 0.8
V
I
O+
Output sink current VID = –0.1 V, VO = 1.20 V 0.1 0.5 mA
I
O–
Output source current VID = 0.1 V, VO = 1.80 V –45 –70 µA
output
TL1454
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
p
IO = –8 mA VCC–2 4.5
VOHHigh-level output voltage
IO = –40 mA VCC–2 4.4
V
p
IO = 8 mA 0.1 0.4
VOLLow-level output voltage
IO = 40 mA 1.8 2.5
V
t
rv
Output voltage rise time
p
°
220
t
fv
Output voltage fall time
C
L
=
2000 pF
,
T
A
=
25°C
220
ns
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,
f
osc
= 500 kHz (unless otherwise noted) (continued)
supply current
TL1454
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
I
CC(stby)
Standby supply current
RT open, CT = 1.5 V, No load,
VO (COMP1, COMP2) = 1.25 V ,
3.1 6 mA
I
CC(average)
Average supply current
RT = 10 kΩ,
50% duty cycle,
CT = 120 pF,
Outputs open
3.5 7 mA
electrical characteristics, VCC = 6 V, f
osc
= 500 kHz, TA = 25°C (unless otherwise noted)
reference
TL1454Y
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
V
ref
Output voltage, REF IO = 1 mA, 1.25 V
Input regulation VOC = 3.6 V to 20 V, IO = 1 mA 2 mV
Output regulation IO = 0.1 mA to 1 mA 1 mV
p
p
IO = 1 mA –1.25
Output voltage change with temperature
IO = 1 mA –2.5
mV
I
OS
Short-circuit output current V
ref
= 0 V 30 mA
undervoltage lockout (UVLO)
TL1454Y
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
V
IT+
Positive-going threshold voltage 2.9 V
V
IT–
Negative-going threshold voltage 2.7 V
V
hys
Hysteresis, V
IT+
– V
IT–
200 mV
short-circuit protection (SCP)
TL1454Y
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
V
IT
Input threshold voltage 1 V
V
stby
†
Standby voltage
p
p
185 mV
V
I(latched)
Latched-mode input voltage
No pullup
60 mV
V
IT(COMP)
Comparator threshold voltage COMP1, COMP2 1 V
Input source current V
O(SCP)
= 0 –15 µA
†
This symbol is not presently listed within EIA/JEDEC standards for semiconductor symbology.
oscillator
TL1454Y
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
f
osc
Frequency CT = 120 pF, RT = 10 kΩ 500 kHz
Standard deviation of frequency 50 kHz
Frequency change with voltage VCC = 3.6 V to 20 V 5 kHz
p
–2
Frequency change with temperature
–10
kH
z
Maximum ramp voltage 1.8 V
Minimum ramp voltage 1.1 V
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
electrical characteristics, VCC = 6 V , f
osc
= 500 kHz, TA = 25°C (unless otherwise noted) (continued)
dead-time control (DTC)
TL1454Y
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
p
Duty cycle = 0% 1.1
VITInput threshold voltage
Duty cycle = 100% 0.5
V
V
I(latched)
Latched-mode input voltage 1.2 V
Latched-mode (source) current –100 µA
error-amplifier
TL1454Y
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
I
IB
Input bias current VO = 1.25 V , VIC = 1.25 V –160 nA
A
V
Open-loop voltage gain RFB = 200 kΩ 80 dB
Unity-gain bandwidth 3 MHz
CMRR Common-mode rejection ratio 80 dB
V
OM(max)
Positive output voltage swing 2.43
V
OM(min)
Negative output voltage swing 0.63
V
I
O+
Output sink current VID = –0.1 V, VO = 1.20 V 0.5 mA
I
O–
Output source current VID = 0.1 V, VO = 1.80 V –70 µA
output
TL1454Y
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
p
IO = –8 mA 4.5
VOHHigh-level output voltage
IO = –40 mA 4.4
V
p
IO = 8 mA 0.1
VOLLow-level output voltage
IO = 40 mA 1.8
V
t
rv
Output voltage rise time
p
220
t
fv
Output voltage fall time
C
L
=
2000 pF
220
ns
supply current
TL1454Y
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
I
CC(stby)
Standby supply current
RT open, CT = 1.5 V, No load,
VO (COMP1, COMP2) = 1.25 V ,
3.1 mA
I
CC(average)
Average supply current
RT = 10 kΩ,
50% duty cycle,
CT = 120 pF,
Outputs open
3.5 mA
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
1.8 V
1.2 V
1 V
2.5 V
1 V
0 V
SCP
V
CC
Dead-Time 100%
(tpe)
2.9-V Typical
Lockout threshold
H
L
OUT1
Dead-Time 100%
H
L
H
L
SCP Comparator
Output
OUT2
Oscillator
COMP
SCP Reference
DTC
0 V
Figure 5. Timing Diagram
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TYPICAL CHARACTERISTICS
Figure 6
100 k
10 k
1 k
OSCILLATOR FREQUENCY
vs
TIMING RESISTANCE
RT – Timing Resistance – Ω
f – Oscillator Frequency – Hz
1 k 10 k 100 k
10 M
1 M
CT = 10 pF
CT = 120 pF
CT = 3900 pF
VCC = 6 V
TA = 25°C
CT = 1000 pF
CT = 300 pF
Figure 7
t – Oscillation Period –
OSCILLATOR PERIOD
vs
TIMING CAPACITANCE
10
–1
10
0
10
5
CT – Timing Capacitance – pF
sµ
10
1
10
0
10
1
VCC = 6 V
RT = 5.1 kΩ
TA = 25°C
10
2
10
2
10
3
10
4
Figure 8
– Oscillator Frequency – kHz
510
500
490
480
520
OSCILLATOR FREQUENCY
vs
FREE-AIR TEMPERATURE
530
–50 0 50 100
TA – Free-Air Temperature – °C
VCC = 6 V
RT = 10 kΩ
CT = 120 pF
osc
f
Figure 9
1.5
1
0.5
2
PWM Triangle W aveform Amplitude – V
PWM TRIANGLE WAVEFORM AMPLITUDE
vs
TIMING CAPACITANCE
10
0
10
1
10
2
10
3
Timing Capacitance – pF
10
4
VCC = 6 V
RT = 5.1 kΩ
TA = 25°C
V
O(min)
V
O(max)
1.9
1.8
1.7
1.6
1.4
1.3
1.2
1.1
0.9
0.8
0.7
0.6
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TYPICAL CHARACTERISTICS
Figure 10
1
0.8
0.6
0.4
DTC Input Threshold Voltage – V
1.2
1.4
DTC INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
0 50 100
–50
VCC = 6 V
RT = 5.1 kΩ
CT = 1000 pF
VIT (0% Duty Cycle)
VIT (100% Duty Cycle)
Figure 11
– SCP Time-Out Period – s
SCP TIME-OUT PERIOD
vs
SCP CAPACITANCE
SCP Capacitance – µF
SCP
t
1
0.5
0
0 5 10 15
1.5
2
20 25
VCC = 6 V
TA = 25°C
Figure 12
1
0.98
0.96
0.94
– SCP Threshold V oltage – V
1.02
SCP THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
1.04
0 50 100
V
IT
TA – Free-Air Temperature – °C
–50
VCC = 6 V
Figure 13
2
1.5
1
– SCP Latch Reset V oltage – V
2.5
3
SCP LATCH RESET VOLTAGE
vs
FREE-AIR TEMPERATURE
3.5
V
I(reset)
TA – Free-Air Temperature – °C
–25 0 25 50 75 100–50
VCC = 6 V
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TYPICAL CHARACTERISTICS
Figure 14
2
1.5
1
– UVLO Threshold Voltage – V
2.5
3
UVLO THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
3.5
–25 0 25 50 75 100
V
IT(H)
V
IL(L)
V
IT(H)
V
IT(L)
TA – Free-Air Temperature – °C
–50
Figure 15
80
60
20
0
0
0.5
1
Duty Cycle – %
100
DUTY CYCLE
vs
DTC INPUT VOLTAGE
VCC = 6 V
CT = 120 pF
RT = 10 kΩ
TA = 25°C
V
I(DTC)
– DTC Input Voltage – V
1.5
120
40
0.25
0.75
1.25
0.5
0
04080
– Error-Amplifier Maximum Output Voltage – V
1
ERROR-AMPLIFIER MAXIMUM OUTPUT VOLTAGE
vs
SOURCE CURRENT
1.5
120
V
OM +
Source Current – µA
VCC = 6 V
VID = 0.1 V
TA = 25°C
2
2.5
– Error-Amplifier Minimum Output Voltage – V
ERROR-AMPLIFIER MINIMUM OUTPUT VOLTAGE
vs
SINK CURRENT
0 0.5 1 1.5
V
OM –
VCC = 6 V
VID = 0.1 V
Sink Current – mA
0.5
0
1
1.5
2
2.5
Figure 16 Figure 17
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TYPICAL CHARACTERISTICS
Figure 18
1
0.5
0
1.5
1 k 10 k 100 k 1M 10 M 100 M
– Error Amplifier Maximum Peak-to-Peak
f – Frequency – Hz
ERROR AMPLIFIER MAXIMUM
PEAK-TO-PEAK OUTPUT VOLTAGE SWING
vs
FREQUENCY
V
O(PP)
VCC = 6 V
TA = 25°C
Output Voltage Swing – V
2
2.5
Figure 19
0.4
0.3
– Error-Ampplifier Minimum Output Voltage Swing – V
0.5
ERROR-AMPLIFIER MINIMUM OUTPUT
VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
0.6
V
OM+
TA – Free-Air Temperature – °C
–25 0 25 50 75 100–50
VCC = 6 V
No Load
Amplifier 1
0.7
0.8
–20
100 1 k 10 k 100 k 1M 10 M
Error Amplifier Open-Loop Gain – dB
f – Frequency – Hz
ERROR AMPLIFIER OPEN-LOOP GAIN AND PHASE SHIFT
vs
FREQUENCY
0
20
40
60
80
–180°
–144°
–108°
–72°
–36°
–0°
Phase Shift
VCC = 6 V
TA = 25°C
Gain
Phase Shift
Figure 20
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TYPICAL CHARACTERISTICS
2.4
2.35
– Error-Ampplifier Positive Output Voltage Swing – V
2.45
ERROR-AMPLIFIER POSITIVE OUTPUT
VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
2.5
V
OM+
T
– Free-Air Temperature – °C
–25 0 25 50 75 100–50
VCC = 6 V
No Load
Amplifier 1
Figure 21
Figure 22
4
3
2
1
5
HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
6
020406080
I
O
– Output Current – mA
– High-Level Output Voltage – V
V
OH
VCC = 6 V
TA = 25°C
Figure 23
4
3.5
3
– High-Level Output Voltage – V
4.5
5
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
5.5
V
OH
TA – Free-Air Temperature – °C
VCC = 6 V
–25 0 25 50 75 100–50
IO = 40 mA
IO = 8 mA
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TYPICAL CHARACTERISTICS
Figure 24
4
3
2
1
5
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
6
020406080
I
OL
– Low-Level Output Current – mA
– Low-Level Output Voltage – V
V
OL
VCC = 6 V
TA = 25°C
Figure 25
100
50
0
150
200
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
250
TA – Free-Air Temperature – °C
–25 0 25 50 75 100–50
VCC = 6 V
IO = 8 mA
– Low-Level Output Voltage – mV
V
OL
Figure 26
1.5
1
0.5
2
2.5
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
3
TA – Free-Air Temperature – °C
–25 0 25 50 75 100–50
VCC = 6 V
IO = 40 mA
– Low-Level Output Voltage – V
V
OL
Figure 27
4
3
2
1
5
AVERAGE SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
6
–50 –25 0 25 50 75
TA – Free-Air Temperature – °C
– Average Supply Current – mA
I
CC(a)
VCC = 6 V
RT = 10 kΩ
CT = 1.5 V
COMP1, COMP2 = 1.25 V
No Load
100
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TYPICAL CHARACTERISTICS
Figure 28
4
3
2
1
5
STANDBY SUPPLY CURRENT
vs
SUPPLY VOLTAGE
6
0 5 10 15 20 25
VCC – Supply Voltage – V
– Standby Supply Current – mA
I
CC(stby)
VCC = 6 V
RT = Open
CT = 1.5 V
COMP1, COMP2 = 1.25 V
No Load
TA = 25°C
Figure 29
4
3
2
1
– 50 0 50
– Standby Supply Current – mA
5
6
100
I
CC(stby)
VCC = 6 V
CT = 1.5 V
RT = Open
COMP1, COMP2 = 1.25 V
No Load
STANDBY SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
Figure 30
0.5
0
1
– Reference Voltage – V
1.5
REFERENCE VOLTAGE
vs
SUPPLY VOLTAGE
V
ref
VCC – Supply Voltage – V
0 5 10 15 20 25
TA = 25°C
Figure 31
1.24
1.23
– Reference Voltage – V
1.25
REFERENCE VOLTAGE
vs
SUPPLY VOLTAGE
1.26
V
ref
VCC – Supply Voltage – V
0 5 10 15 20 25
IO = 1mA
TA = 25°C
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TYPICAL CHARACTERISTICS
1.25
1.24
1.23
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
1.26
–25 0 25 50 75 100
– Reference Voltage – V
TA – Free-Air Temperature – °C
V
ref
–50
VCC = 6 V
IO = –1 mA
Figure 32
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/B 10/94
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Four center pins are connected to die mount pad
E. Falls within JEDEC MS-012
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
MECHANICAL DATA
N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE
4040049/C 7/95
16 PIN SHOWN
0.310 (7,87)
0.290 (7,37)
Seating Plane
0.010 (0,25) NOM
14 Pin Only
9
8
0.070 (1,78) MAX
A
0.035 (0,89) MAX
0.020 (0,51) MIN
16
1
0.015 (0,38)
0.021 (0,53)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.240 (6,10)
0.260 (6,60)
0.100 (2,54)
M
0.010 (0,25)
0°–15°
20
0.975
(24,77)
(23,88)
0.940
18
0.920
0.850
14
0.775
(19,69)
0.745
(18,92)
16
0.775
(19,69)
(18,92)
0.745
PINS **
A MIN
DIM
A MAX
(23.37)
(21.59)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001)
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT
SLVS086B – APRIL 1995 – REVISED NOVEMBER 1997
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
MECHANICAL DATA
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040064/B 10/94
14 PIN SHOWN
Seating Plane
0,10 MIN
1,20 MAX
1
A
7
14
0,17
4,70
4,30
8
6,10
6,70
0,32
0,70
0,40
0,25
Gage Plane
0,15 NOM
0,65
M
0,13
0°–8°
0,10
PINS **
A MIN
A MAX
DIM
2,90
3,30
8
4,90
5,30
14
6,80
6,404,90
5,30
16
7,70
20
8,10
24
9,60
10,00
28
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
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