Texas Instruments TL084CD, TL084CJ, TL084BCN, TL084ID, TL084CPWR Datasheet
...
TL081, TL081A, TL081B, TL082, TL082A, TL082B
TL082Y, TL084, TL084A, TL084B, TL084Y
JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low Power Consumption
D
Wide Common-Mode and Differential
Voltage Ranges
D
Low Input Bias and Offset Currents
D
Output Short-Circuit Protection
D
Low Total Harmonic
Distortion . . . 0.003% Typ
D
High Input Impedance...JFET-Input Stage
D
Latch-Up-Free Operation
D
High Slew Rate...13 V/µs Typ
D
Common-Mode Input Voltage Range
Includes V
CC+
description
The TL08x JFET-input operational amplifier family is designed to offer a wider selection than any previously
developed operational amplifier family. Each of these JFET-input operational amplifiers incorporates
well-matched, high-voltage JFET and bipolar transistors in a monolithic integrated circuit. The devices feature
high slew rates, low input bias and offset currents, and low offset voltage temperature coefficient. Offset
adjustment and external compensation options are available within the TL08x family.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from –40°C to 85°C. The Q-suffix devices are characterized for operation from –40°C to 125°C.
The M-suffix devices are characterized for operation over the full military temperature range of –55°C to 125°C.
symbols
+
–
+
–
OFFSET N1
IN+
IN–
OUT
IN+
IN–
OUT
TL082 (EACH AMPLIFIER)
TL084 (EACH AMPLIFIER)
TL081
OFFSET N2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
TL081, TL081A, TL081B, TL082, TL082A, TL082B
TL082Y, TL084, TL084A, TL084B, TL084Y
JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NC – No internal connection
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN–
1IN+
V
CC+
2IN+
2IN–
2OUT
4OUT
4IN–
4IN+
V
CC–
3IN+
3IN–
3OUT
TL084, TL084A, TL084B
D, J, N, PW, OR W PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4IN+
NC
V
CC
–
NC
3IN+
1IN+
NC
V
CC+
NC
2IN+
TL084M . . . FK PACKAGE
(TOP VIEW)
1IN –
1OUT
NC
3OUT
3IN –
4OUT
4IN –
2IN –
2OUT
NC
3212019
910111213
4
5
6
7
8
18
17
16
15
14
NC
V
CC+
NC
OUT
NC
NC
IN–
NC
IN+
NC
TL081M . . . FK PACKAGE
(TOP VIEW)
NC
OFFSET N1
NC
OFFSET N2
NC
NC
NC
NC
NC
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
NC
2OUT
NC
2IN–
NC
NC
1IN–
NC
1IN+
NC
TL082M . . . FK PACKAGE
(TOP VIEW)
NC
1OUT
NC
2IN +
NC
NC
NC
NC
1
2
3
4
8
7
6
5
OFFSET N1
IN–
IN+
V
CC–
NC
V
CC+
OUT
OFFSET N2
TL081, TL081A, TL081B
D, JG, P, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN–
1IN+
V
CC–
V
CC+
2OUT
2IN–
2IN+
TL082, TL082A, TL082B
D, JG, P, OR PW PACKAGE
(TOP VIEW)
V
CC –
V
CC+
V
CC –
1
2
3
4
5
10
9
8
7
6
NC
OFFSET N1
IN–
IN+
V
CC–
NC
NC
V
CC+
OUT
OFFSET N2
TL081M
U PACKAGE
(TOP VIEW)
1
2
3
4
5
10
9
8
7
6
NC
1OUT
1IN–
1IN+
V
CC–
NC
V
CC+
2OUT
2IN–
2IN+
TL082M
U PACKAGE
(TOP VIEW)
TL081, TL081A, TL081B, TL082, TL082A, TL082B
TL082Y, TL084, TL084A, TL084B, TL084Y
JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• 3
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
VIOmax
AT 25°C
SMALL
OUTLINE
(D008)
SMALL
OUTLINE
(D014)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(J)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(N)
PLASTIC
DIP
(P)
TSSOP
(PW)
FLAT
PACK
(U)
FLAT
PACK
(W)
CHIP
FORM
(Y)
15 mV
6 mV
3 mV
TL081CD
TL081ACD
TL081BCD
— — — — —
TL081CP
TL081ACP
TL081BCP
TL081CPW
— — —
0°C
to
70°C
15 mV
6 mV
3 mV
TL082CD
TL082ACD
TL082BCD
— — — — —
TL082CP
TL082ACP
TL082BCP
TL082CPW
— —
TL082Y
15 mV
6 mV
3 mV
—
TL084CD
TL084ACD
TL084BCD
— — —
TL084CN
TL084ACN
TL084BCN
—
TL084CPW
— —
TL084Y
–40°C
to
85°C
6 mV
6 mV
6 mV
TL081ID
TL082ID
TL084ID
TL084ID
— — —
TL084IN
TL081IP
TL082IP
— — — —
–40°C
to
125°C
9 mV
—
TL084QD
— — — — — — — — —
–55°C
to
125°C
6 mV
6 mV
9 mV
— —
TL081MFK
TL082MFK
TL084MFK
TL084MJ
TL081MJG
TL082MJG
— — —
TL081MU
TL082MU
TL084MW
—
The D package is available taped and reeled. Add R suffix to the device type (e.g., TL081CDR).
TL081, TL081A, TL081B, TL082, TL082A, TL082B
TL082Y, TL084, TL084A, TL084B, TL084Y
JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic (each amplifier)
C1
V
CC+
IN+
V
CC–
OFFSET N1
1080 Ω
1080 Ω
IN–
TL081 Only
64 Ω
128 Ω
64 Ω
OUT
Component values shown are nominal.
OFFSET N2
TL081, TL081A, TL081B, TL082, TL082A, TL082B
TL082Y, TL084, TL084A, TL084B, TL084Y
JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL082Y chip information
These chips, when properly assembled, display characteristics similar to the TL082. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (4) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
+
–
1OUT
1IN+
1IN–
V
CC+
(8)
(6)
(3)
(2)
(5)
(1)
–
+
(7)
2IN+
2IN–
2OUT
(4)
V
CC–
61
61
(7) (6) (5)
(4)(8)
(3)(2)(1)
TL081, TL081A, TL081B, TL082, TL082A, TL082B
TL082Y, TL084, TL084A, TL084B, TL084Y
JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL084Y chip information
These chips, when properly assembled, display characteristics similar to the TL084. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (11) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
+
–
1OUT
1IN+
1IN–
V
CC+
(4)
(6)
(3)
(2)
(5)
(1)
–
+
(7)
2IN+
2IN–
2OUT
(11)
V
CC–
+
–
3OUT
3IN+
3IN–
(13)
(10)
(9)
(12)
(8)
–
+
(14)
4OUT
4IN+
4IN–
105
62
(13) (12) (11) (10) (9)
(8)
(7)
(6)(4)(3)
(2)
(1)
(14)
TL081, TL081A, TL081B, TL082, TL082A, TL082B
TL082Y, TL084, TL084A, TL084B, TL084Y
JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
TL08_C
TL08_AC
TL08_BC
TL08_I TL084Q TL08_M UNIT
Supply voltage, V
CC+
(see Note 1) 18 18 18 18 V
Supply voltage VCC– (see Note 1) –18 –18 –18 –18 V
Differential input voltage, VID (see Note 2) ± 30 ± 30 ±30 ± 30 V
Input voltage, VI (see Notes 1 and 3) ±15 ±15 ±15 ±15 V
Duration of output short circuit (see Note 4) unlimited unlimited unlimited unlimited
Continuous total power dissipation See Dissipation Rating Table
Operating free-air temperature range, T
A
0 to 70 – 40 to 85 – 40 to 125 – 55 to 125 °C
Storage temperature range, T
stg
– 65 to 150 – 65 to 150 – 65 to 150 – 65 to 150 °C
Case temperature for 60 seconds, T
C
FK package 260 °C
Lead temperature 1,6 mm (1/16 inch) from case for 60
seconds
J or JG package 300 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10
seconds
D, N, P, or
PW package
260 260 260 °C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between V
CC+
and V
CC–
.
2. Differential voltages are at IN+ with respect to IN–.
3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING
FACTOR
DERATE
ABOVE T
A
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D (8 pin) 680 mW 5.8 mW/°C 32°C 460 mW 373 mW N/A
D (14 pin) 680 mW 7.6 mW/°C60°C 604 mW 490 mW 186 mW
FK 680 mW 11.0 mW/°C88°C 680 mW 680 mW 273 mW
J 680 mW 11.0 mW/°C88°C 680 mW 680 mW 273 mW
JG 680 mW 8.4 mW/°C69°C 672 mW 546 mW 210 mW
N 680 mW 9.2 mW/°C76°C 680 mW 597 mW N/A
P 680 mW 8.0 mW/°C65°C 640 mW 520 mW N/A
PW (8 pin) 525 mW 4.2 mW/°C25°C 336 mW N/A N/A
PW (14 pin) 700 mW 5.6 mW/°C25°C 448 mW N/A N/A
U 675 mW 5.4 mW/°C25°C 432 mW 351 mW 135 mW
W 680 mW 8.0 mW/°C 65°C 640 mW 520 mW 200 mW
Template Release Date: 7–11–94
TL081, TL081A, TL081B, TL082, TL082A, TL082B
TL082Y, TL084, TL084A, TL084B, TL084Y
JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
electrical characteristics, V
CC±
= ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
T
A
†
TL081C
TL082C
TL084C
TL081AC
TL082AC
TL084AC
TLO81BC
TL082BC
TL084BC
TL081I
TL082I
TL084I
UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
p
25°C 3 15 3 6 2 3 3 6
VIOInput offset voltage
V
O
=
0
R
S
= 50
Ω
Full range 20 7.5 5 9
mV
α
VIO
T emperature
coefficient of input
offset voltage
VO = 0 RS = 50 Ω Full range 18 18 18 18 µV/°C
25°C 5 200 5 100 5 100 5 100 pA
I
IO
I
nput offset curren
t
‡
V
O
=
0
Full range 2 2 2 10 nA
25°C 30 400 30 200 30 200 30 200 pA
I
IB
I
nput bias curren
t
‡
V
O
=
0
Full range 10 7 7 20 nA
V
ICR
Common-mode input
voltage range
25°C ±11
–12
to
15
±11
–12
to
15
±11
–12
to
15
±11
–12
to
15
V
RL = 10 kΩ 25°C ±12 ±13.5 ±12 ±13.5 ±12 ±13.5 ±12 ± 13.5
V
OM
Maximum peak
p
RL ≥ 10 kΩ
±12 ±12 ±12 ±12
V
out ut voltage swing
RL ≥ 2 kΩ
Full range
±10 ±12 ±10 ±12 ±10 ±12 ±10 ±12
Large-signal
VO = ±10 V, RL ≥ 2 kΩ 25°C 25 200 50 200 50 200 50 200
A
VD
diff
erential voltage
amplification
VO = ±10 V,
RL ≥ 2 kΩ Full range 15 25 25 25
V/mV
B
1
Unity-gain bandwidth 25°C 3 3 3 3 MHz
r
i
Input resistance 25°C 10
12
10
12
10
12
10
12
Ω
Common-mode VIC = V
ICR
min,
°
CMRR
rejection ratio VO = 0, RS = 50 Ω
25°C7086758675867586
dB
Supply voltage
VCC = ±15 V to ± 9 V,
°
k
SVR
rejection ratio
(∆V
CC±
/∆VIO)
VO = 0, RS = 50 Ω
25°C7086808680868086
dB
I
CC
Supply current
(per amplifier)
VO = 0, No load 25°C 1.4 2.8 1.4 2.8 1.4 2.8 1.4 2.8 mA
VO1/VO2Crosstalk attenuation AVD = 100 25°C 120 120 120 120 dB
†
All characteristics are measured under open-loop conditions with zero common-mode voltage unless otherwise specified. Full range for TA is 0°C to 70°C for TL08_C, TL08_AC,
TL08_BC and –40°C to 85°C for TL08_I.
‡
Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive as shown in Figure 17. Pulse techniques must be used
that maintain the junction temperature as close to the ambient temperature as possible.
TL081, TL081A, TL081B, TL082, TL082A, TL082B
TL082Y, TL084, TL084A, TL084B, TL084Y
JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS081E – FEBRUARY 1977 – REVISED FEBRUARY 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, V
CC ±
= ±15 V (unless otherwise noted)
TL081M, TL082M TL084Q, TL084M
PARAMETER
TEST CONDITIONS
†
T
A
MIN TYP MAX MIN TYP MAX
UNIT
p
25°C 3 6 3 9
VIOInput offsetvoltage
V
O
= 0,
R
S
= 50
Ω
Full range 9 15
mV
α
VIO
Temperature
coefficient of input
offset voltage
VO = 0 RS = 50 Ω Full range 18 18 µV/°C
25°C 5 100 5 100 pA
I
IO
I
nput offset curren
t
‡
V
O
=
0
125°C 20 20 nA
25°C 30 200 30 200 pA
I
IB
I
nput bias curren
t
‡
V
O
=
0
125°C 50 50 nA
V
ICR
Common-mode input
voltage range
25°C ±11
±12
to
15
±11
± 12
to
15
V
RL = 10 kΩ 25°C ±12 ±13.5 ±12 ±13.5
V
OM
Maximum peak
p
RL ≥ 10 kΩ
±12 ±12
V
out ut voltage swing
RL ≥ 2 kΩ
Full range
±10 ±12 ±10 ±12
Large-signal
VO = ±10 V , RL ≥ 2 kΩ 25°C 25 200 25 200
A
VD
diff
erential voltage
amplification
VO = ±10 V ,
RL ≥ 2 kΩ Full range 15 15
V/mV
B
1
Unity-gain bandwidth 25°C 3 3 MHz
r
i
Input resistance 25°C 10
12
10
12
Ω
CMRR
Common-mode
rejection ratio
VIC = V
ICR
min,
VO = 0, RS = 50 Ω
25°C 80 86 80 86 dB
k
SVR
Supply voltage
rejection ratio
(∆V
CC±
/∆VIO)
VCC = ±15 V to ±9 V,
VO = 0, RS = 50 Ω
25°C 80 86 80 86 dB
I
CC
Supply current
(per amplifier)
VO = 0, No load 25°C 1.4 2.8 1.4 2.8 mA
VO1/VO2Crosstalk attenuation AVD = 100 25°C 120 120 dB
†
All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified.
‡
Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive as shown in
Figure 17. Pulse techniques must be used that maintain the junction temperatures as close to the ambient temperature as is possible.
operating characteristics, V
CC±
= ±15 V, T
A
= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX
UNIT
VI = 10 V, RL = 2 kΩ, CL = 100 pF, See Figure 1 8
∗
13
SR Slew rate at unity gain
VI = 10 V,
RL = 2 kΩ, CL = 100 pF,
∗
V/µs
TA = – 55°C to 125°C,
See Figure 1
5
∗
t
r
Rise time
p
0.05 µs
Overshoot factor
V
I
=
20 mV
,
R
L
=
2 kΩ
,
C
L
=
100 pF
,
See Figure 1
20%
Equivalent input noise
f = 1 kHz 18 nV/√Hz
V
n
Equivalent in ut noise
voltage
R
S
= 20
Ω
f = 10 Hz to 10 kHz 4 µV
I
n
Equivalent input noise
current
RS = 20 Ω, f = 1 kHz 0.01 pA/√Hz
THD Total harmonic distortion
VIrms = 6 V,
f = 1 kHz
AVD = 1, RS ≤ 1 kΩ, RL ≥ 2 kΩ,
0.003%
∗On products compliant to MIL-PRF-38535, this parameter is not production tested.
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