Texas Instruments TIR2000PAG, TIR2000EVM Datasheet
TIR2000
Data Manual
High-Speed Serial Infrared Controller
With 64-Byte FIFO
Printed on Recycled Paper
SLLS248A
June 1998
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 1998, Texas Instruments Incorporated
iii
Contents
Section Title Page
1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Functional Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Terminal Assignments 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Ordering Information 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Functional Description 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Modes of Operation 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 Fast-Speed Infrared (FIR) mode (IrDA 1.1) 2–2. . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2 Medium-Speed Infrared (MIR) mode (IrDA 1.1) 2–5. . . . . . . . . . . . . . . . . . . . . .
2.1.3 Slow-Speed Infrared (SIR) mode (IrDA 1.0) 2–8. . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4 SHARP Infrared (IR) mode 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5 TV mode 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.6 Universal Asynchronous Receiver Transmitter (UART) mode 2–13. . . . . . . . .
2.1.7 DMA Operation 2–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Register Definitions for the UART, SIR and SHARP Modes 3–1. . . . . . . . . . . . . . . . . . . .
3.1 Receiver-Buffer Register (RBR) – (read only) 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Transmitter Holding Register (THR) – (write only) 3–1. . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Interrupt Enable Register (IER) – (read and write) 3–1. . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Interrupt Identification Register (IIR) - (read only) 3–2. . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 FIFO-Control Register (FCR) – (write only) 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Line-Control Register (LCR) - (read and write) 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Modem Control Register (MCR) - (read and write) 3–4. . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Line Status Register (LSR) - (read only) 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 Modem Status Register (MSR) - (read only) 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 Scratch Register (SCR) - (read and write) 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Baud-Rate Divisor Latch LSB (DLL) - (read and write) 3–6. . . . . . . . . . . . . . . . . . . . . .
3.12 Baud-Rate Divisor Latch MSB (DLM) - (write only) 3–6. . . . . . . . . . . . . . . . . . . . . . . . .
4 Register Definitions for the MIR, FIR and TV Modes 4–1. . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Receiver Buffer Register (RBR) – (read only) 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Transmitter Holding Register (THR) – (write only) 4–1. . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Interrupt Enable Register (IER) – (read and write only) 4–1. . . . . . . . . . . . . . . . . . . . . .
4.4 Interrupt Identification Register (IIR) – (read only) 4–2. . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 FIFO Control Register (FCR) – (write only) 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Line Status Register (LSR) – (read only) 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Auxiliary Baud–Rate Divisor Lower Register (ABDL) – (write only) 4–6. . . . . . . . . . . .
4.8 Auxiliary Baud–Rate Divisor Higher Register (ABDH) – (write only) 4–6. . . . . . . . . . .
4.9 Mode Definition Register (MDR) – (read and write) 4–6. . . . . . . . . . . . . . . . . . . . . . . . .
4.9.1 Sleep Mode 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
4.9.2 Low-Power Mode 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Configuration Control Register (CCR) – (write only) 4–7. . . . . . . . . . . . . . . . . . . . . . . .
4.11 Bank 0 Registers 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11.1 Transmit Frame-Length Register Low (TXFLL) – (write only) 4–7. . . . . . . . . . .
4.11.2 Transmit Frame-Length Register High (TXFLH) – (write only) 4–8. . . . . . . . . .
4.11.3 Received Frame-Length Register Low(RXFLL) – (write only) 4–8. . . . . . . . . .
4.11.4 Received Frame-Length Register High (RXFLH) – (write only) 4–8. . . . . . . . .
4.11.5 Preamble Length Register (PLR) – (write only) 4–8. . . . . . . . . . . . . . . . . . . . . . .
4.11.6 Auxiliary Control Register (ACREG) – (read and write only) 4–9. . . . . . . . . . . .
4.11.7 Status FIFO Line Status Register (SFLSR) – (read only) 4–10. . . . . . . . . . . . .
4.11.8 Status FIFO Register Low (SFREGL) – (read only) 4–10. . . . . . . . . . . . . . . . . .
4.11.9 Status FIFO Register High (SFREGH) – (read only) 4–10. . . . . . . . . . . . . . . . .
4.12 Bank 1 Registers 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12.1 TV Configuration Register (TVCFG) 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12.2 TV Demodulation Configuration Register (TVDMCFG) 4–11. . . . . . . . . . . . . . .
4.12.3 TV Modulation Configuration Register (TVMDCFG) 4–12. . . . . . . . . . . . . . . . .
4.13 Bank 2 Registers 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13.1 Prescaler Register (PRESC) 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13.2 Interrupt Configuration Register (ICR) – (write only) 4–13. . . . . . . . . . . . . . . . .
4.13.3 DMA Channel Select Register (DCSR) – (write only) 4–14. . . . . . . . . . . . . . . .
4.14 Bank 3 Registers 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14.1 General Purpose I/O Direction Register (GPIODIR) – (write only) 4–14. . . . .
4.14.2 General Purpose I/O Data Register (GPIODAT) – (read and write) 4–15. . . .
4.14.3 General Purpose Function Select Register (GPFSR) – (write only) 4–15. . . .
4.14.4 Ir Mode Configuration Register 1 (IRCFG) – (read and write) 4–15. . . . . . . . .
5. Electrical Characteristics 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Absolute Maximum Ratings 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Recommended Operating Conditions 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low voltage (3.3 V nominal) 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard voltage (5 V nominal) 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Timing Requirements 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Operating Characteristics 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 Switching Characteristics 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 Timing Diagrams 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6. Application Information 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Transceiver Connections 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Operating Modes 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix A Mechanical Data A–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
List of Illustrations
Figure Title Page
1–1 Functional Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 Terminal Assignments 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Basic Configuration for Ir Communication 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 SIR Encoding 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 SHARP Ir Encoding 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Example of Auto-flow Contol (Auto-RTS
and Auto-CTS) 2–14. . . . . . . . . . . . . . . . . . . . . . .
2–5 CTS
Functional Timing Diagram 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 RTS
Functional Timing, RCV-FIFO Trigger 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Standard ISA Write-Cycle Timing Diagram 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Standard ISA Read-Cycle Timing Diagram 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Typical TIR2000 Configuration 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 HP/TI Transceiver Connection 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 Temic Transceivers 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
List of Tables
Table Title Page
4–1 RX Demodulation Carrier Frequency (low range TVCFG[4] bit = 0) 4–11. . . . . . . . . . . . . .
4–2 RX Demodulation Carrier Frequency (high range TVCFG[4] bit = 1) 4–12. . . . . . . . . . . . .
4–3 TX Modulation Carrier Frequency 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 TX Modulation Carrier Pulse Duration 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–1
1 Introduction
The TIR2000 is a serial communication controller with full infrared support which is also compatible to the
TL16C550C and the TL16C750 UART devices. This device also supports the Sharp-IR, HPSIR, MIR, FIR
and TV modes. The controller has a 64-byte FIFO which reduces the CPU of excessive software overhead.
Also a 64-byte FIFO meets the minimum frame size requirements simplifying the software driver design.
DMA and interrupt support for all operations have been included in this architecture. The TIR2000 offers
programmable registers for routing interrupt DMA handshake signals. While in UART mode, the 64-byte
FIFO and selectable auto-flow control for RTS and CTS increases system efficiency and baud rate.
• IrDA 1.0 mode with a data rate up to 115.2 Kbps
• IrDA 1.1 mode with a data rate up to 1.15 Mbps
• IrDA 1.1 mode with a data rate up to 4 Mbps
• Sharp ASK infrared mode
• Consumer television remote control mode (RC5, RC5 extended, NEC, RC6, and RECS80)
1.1 Features
• Full infrared support
– Infrared Data Association (IrDA) 1.0 supports up to 115.2 kbps
– IrDA 1.1 supports 1.15 Mbps and 4 Mbps
– Sharp Amplitude Shift Keying (ASK)
– TV remote control mode
• Industry Standard Architecture (ISA) compatible bus interface
• Selectable 16- or 64-byte FIFO
• Full duplex infrared transmission and reception
• Controlled transmit start
• Supports back-to-back transactions
• Supports multiple optical transceivers
• Controlled Serial Interaction Pulse (SIP) generation
• Supports 11 IRQ options and 3 DMA configurations
• Power management support
• 8 general purpose I/O terminals
• Fully compatible with TL16C450, TL16C550C, TL16C750 UARTs
• Automatic fallback to TL16C550C mode
• UART baud rate up to 1 Mbps
• Auto-flow control in UART mode
• 3.3-V or 5-V operation
• Available in 64-pin TQFP package
1–2
1.2 Functional Block Diagram
ISA
INTERFACE
UART
Controller
64-Byte
FIFO
UART
Interface
Mode Select
SIN
CS
A (3–0)
D (7–0)
IRQ3–7,
9–12, 14, 15
DACK0, 1, 3
RESET
TC
WR
RD
DRQ0, 1, 3
Configuration
and
Status
Registers
SIR
Logic
Sharp
Logic
TV Remote
Logic
MIR
Logic
FIR
Logic
GPIO (7–0)
Prescaler
48-MHz
Oscillator
SOUT
RTS
DTR
CTS
DSR
DCD
RI
IRTX
IRRVL
IRRVH
XIN
XOUT
TEST
49
51
52
30
39–36
9–6, 4–1
32
33
35
31
11–16, 18–22
23–25
27–29
48–45, 43–40
58 59 61
53
54
55
56
57
62
63
64
Figure 1–1. Functional Block Diagram
1–3
1.3 Terminal Assignments
D0
D1
D2
D3
GND
D4
D5
D6
D7
GND
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ9
PAG PACKAGE
(TOP VIEW)
17 18 19
GPIO7
GPIO6
GPIO5
GPIO4
V
CC
GPIO3
GPIO2
GPIO1
GPIO0
A3
A2
A1
A0
RESET
GND
WR
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
21 22 23 24
GND
CTS
63 62 61 60 5964 58
IRTX
DTR
RTS
SOUTRIDCD
GND
DACK0
DACK1
DACK3
IRQ11
IRQ12
IRQ14
IRQ15
DRQ0
DRQ1
DRQ3
56 55 5457
25 26 27 28 29
53 52
SIN
TEST
51 50 49
30 31 32
CS
TC
RD
XOUT
DSR
XIN
IRRVH
IRRVL
IRQ10
V
CC
V
CC
Figure 1–2. Terminal Assignments
1.4 Ordering Information
PACKAGE
T
A
QUAD FLAT PACK
(PAG)
0°C to 70°C TIR2000P AG
1–4
1.5 Terminal Functions
TERMINALS
NAME NO.
I/O
DESCRIPTION
A0 – A3 36–39 I Address bus. The CPU uses A0 -A3 and the CS signal to select the internal register
of the TIR2000. A0 -A3 are decoded to select a particular register.
CS 30 I Chip select. The CPU uses CS to select the TIR2000 for read/write transactions.
CTS 54 I Clear to send. CTS is a modem-status signal. Its condition can be checked by reading
bit 4 (CTS) of the modem-status register (MSR). Bit 0 (∆CTS) of the MSR indicates
that CTS
has changed states since the last read from the MSR. When modem-status
interrupt is enabled, CTS
changes states, and the auto-CTS mode is not enabled, an
interrupt is generated. CTS
is also used in the auto-CTS mode to control the
transmitter.
D0–D7 1–4,
6–9
I/O Data bus. These bidirectional data lines are connected to the CPU for data transfer
between the TIR2000 and the CPU. D0 is the LSB and D7 is the MSB.
DACK0,
DACK1
,
DACK3
27–29 I DMA acknowledge. DACK0, DACK1, and DACK3 are DMA active low signals that
are the corresponding acknowledge signals, for the DMA request signals which are
DRQ0, DRQ1 and DRQ3.
DCD 56 I Data carrier detect. DCD is a modem-status signal. Its condition can be checked by
reading bit 7 (DCD) of the MSR. Bit 3 (∆DCD) of the MSR indicates that DCD
has
changed states since the last read from the MSR. When the modem-status interrupt
is enabled and DCD
changes state, an interrupt is generated.
DRQ0, DRQ1,
DRQ3
23–25 O DMA requests. DRQ0, DRQ1 and DRQ3 are used for DMA requests that are active
high and are used to signal the DMA controller that data transfer between the
TIR2000 and memory is required. When the DMA is enabled, one of the three
channels configurable through the DMA channel select register (DCSR) can be
selected.
DSR 55 I Data set ready. DSR is a modem-status signal. Its condition can be checked by
reading bit 5 (DSR) of the MSR. Bit 1 (∆DSR) of the MSR indicates the DSR
has
changed states since the last read from the MSR. When the modem-status interrupt
is enabled and the DSR
changes states, an interrupt is generated.
DTR 61 O Data terminal ready. When low, DTR informs a modem or data set that the UART is
ready to establish communication. DTR
is placed in the active state by setting the
DTR bit of the modem-control register to one. DTR
is placed in the inactive condition
as a result of a master reset, during loop mode operation, or clearing of the DTR bit.
GND 5, 10,
26, 34,
50
Ground (0 V). GND terminals must be tied to ground for proper operation.
GPIO0–GPIO3,
GPIO4–GPIO7
40–43,
45–48
I/O General purpose I/O terminals. GPIO0–GPIO7 terminals are programmable
general-purpose input/output terminals.
IRQ3–IRQ7,
IRQ9–IRQ12,
IRQ14, IRQ15
11–16,
18–22
O Interrupt signals. These active-high interrupts are activated based on the IRQ
configuration register.
IRRVH 64 I Infrared receive. IRRVH is an input connected to the IR transceiver module that
receives data in the high-speed modes (1.15 Mbps and 4 Mbps mode).
1–5
1.5 Terminal Functions (Continued)
IRRVL 63 I Infrared receive. IRRVL is connected to the IR transceiver module and receives data
in the slow-speed mode such as the SIR, Sharp Ir, and TV remote-control modes.
IRTX 62 O Infrared transmit. IRTX is an output terminal connected to the IR transceiver module
and transmits data out from the TIR2000.
RD 32 I Read. RD is an active-low signal that indicates when the CPU reads data from the
TIR2000.
RESET 35 I Reset. When active (high), RESET is used for system reset operation.
RI 57 I Ring indicator. RI is a modem-status signal. Its condition can be checked by reading
bit 6 (RI) of the MSR. Bit 2 (TERI) of the MSR indicates that RI
has transitioned from
a low to a high level since the last read from the MSR. If the modem-status interrupt
is enabled when this transition occurs, an interrupt is generated.
RTS 59 O Request to send. When low, R TS informs the modem or data set that the ACE is ready
to receive data. RTS
is set low by setting the RTS MCR bit and is set to its inactive (high)
level either as a result of a master reset, during loop mode operations, or by clearing
bit 1 (RTS) of the MCR. In the auto-RTS
mode, RTS is set low by the receiver threshold
control logic.
SIN 53 I Serial data. SIN is the input from a connected communications device.
SOUT 58 O Composite serial data output. SOUT is connected to a communication device. SOUT
is set to the marking (high) level as a result of master reset.
TC 31 I T erminal count. TC comes from the DMA controller and indicates the end of the block
transfer.
TEST 52 I Test terminal. TEST is used for test purposes only and should be tied low in normal
operation.
VCC 17, 44,
60
5-V or 3-V supply voltage.
WR 33 I Write. WR is an active low signal that indicates that the CPU is writing data to the
TIR2000.
Xin, Xout 49, 51 I/O Crystal connectors. A 48-MHz crystal should be connected across these terminals.
1–6
(This page has been left blank intentionally.)
2–1
2 Functional Description
2.1 Modes of Operation
The TIR2000 operates in six different modes. For proper operation, the device must be programmed
correctly for each mode. The various modes of operation include:
• Fast-speed infrared (IrDA FIR) mode
• Medium-speed infrared (IrDA MIR) mode
• Slow-speed infrared (IrDA SIR) mode
• SHARP Infrared (IR) mode
• TV mode
• Universal asynchronous receiver transmitter (UART) mode
Basic data communication involves at least two devices. During the data transmit mode, the first device
transmits data and the second device receives the transmitted data. During the receive mode, the second
device transmits the data and the first device receives the data. When the device is configured for the UART
mode, both data transmission and data receive can occur simultaneously , but during the infrared (IR) modes
either the data transmit or data receive is possible at any time but not simultaneously . A basic configuration
for two communicating devices in the infrared mode is shown in Figure 2–1.
TIR2000
Ir
Xcvr
TIR2000
Ir
Xcvr
Ir Pulse
Machine 1 Machine 2
Transmit
TIR2000
Ir
Xcvr
TIR2000
Ir
Xcvr
Ir Pulse
Machine 1 Machine 2
Receive
Figure 2–1. Basic Configuration for Ir Communication
The TIR2000 has internal programmable registers. Some of the registers are common to all modes of
operation and some are specific to a particular mode of operation. The device is accessed with the industry
standard architecture (ISA) address bus SA[15–0]. An outside address decoder uses ISA signals
(SA[15–4], AEN) and generates the chip select (CS
) signal for the TIR2000 device. The lower address bits
SA[3–0] are directly connected to the device. The internal address decoder decodes SA[3–0] lower address
bits to access the different registers.
2–2
2.1.1 Fast-Speed Infrared (FIR) mode (IrDA 1.1)
During the FIR mode, data transfer takes place between the CPU and peripheral devices at the baud-rate
speed of 4 Mbps. An FIR transmit frame starts with the Preamble, followed by a Start Flag, Frame Data,
CRC-32, and Stop Flag. The details of the frame format can be found in the Infrared Data Association (IrDA)
document physical layer link specification
Preamble Start Flag Frame Data CRC-32 Stop Flag
The peripheral device that is in the data-transmission mode attaches the Preamble, Start Flag, CRC-32, and
the Stop Flag. It also encodes the transmit data into the 4PPM format. During data receive, the peripheral
device in the data-receive mode recovers the data-receive clock, removes the Start Flag, decodes the
4PPM incoming data and determines the frame boundary with the reception of a Stop Flag. It also checks
for errors such as illegal pulse-position-modulation (4PPM) symbols, cyclic reduncy check (CRC) errors and
frame-length errors. At the end of a frame reception, the CPU reads the LSR-status register to find the errors,
if any, of the received frame.
Data cannot be transmitted and received by the same device at the same time. When the CPU wants to send
data, the peripheral device needs to be programmed for data transmission. When the CPU receives data
from the peripheral device, the peripheral device needs to be programmed for data receive. Some registers
are common to both data transmit and data receive and need to be programmed only once. Use the following
programming sequence for these registers:
1. Program the interrupt configuration register (ICR) in order to:
• Select the IRQ channel
• Select either totem-pole or open-drain output
• Select an active high or an active low for an interrupt when the totem-pole configuration is
selected.
2. Write a 6 to the PRESC register. This divides a 48-MHz input clock by 6 and generates a 8-MHz
internal clock for the FIR mode of operation.
2.1.1.1 FIR Data-Transmission Mode
The following register programming steps should be performed for transmission in the FIR mode:
1. Program the mode definition register (MDR) in order to :
• Select the FIR mode
• Enable/disable the low-power mode. For normal operation, enable the low-power mode.
• Enable/disable the sleep mode. For normal operation, disable the sleep mode.
• Enable/disable the store-and-controlled transmission (SCT). For normal operation, disable
the SCT.
• Enable/disable the software control on a 2-µs infrared pulse. For normal operation, disable
the software control.
• Select the frame closing method (frame-length method or set-EOT bit method).
2. Program the preamble length register (PLR) in order to:
• Select the number of preambles. The default value is 16.
• Select the TX FIFO trigger level
3. When the frame-length method is selected for frame termination, program the TXFLL and the
TXFLH registers for the frame length value.
2–3
4. Reset the TX FIFO. This includes:
• Write to the LCR register so that the LCR[7] bit is a 1. The LCR[7] bit must be a 1 to be able to
write to the FCR[5] bit.
• Program the FCR register to select 64-/16-bytes of the TX FIFO, the non-DMA/DMA mode of
operation, select the TX FIFO trigger level and to clear the TX FIFO.
• Write the LCR register to set the LCR[7] bit to a 0 for normal operation.
5. Program the IER register to enable only the transmitter related interrupts and disable the
remaining interrupts. Enable the following:
For programmed I/O mode
• Transmitter FIFO below threshold level interrupt enable (IER[1])
• Transmitter underrun interrupt enable (IER[7])
For DMA mode
• Status FIFO time-out interrupt enable (IER[2])
• Status FIFO threshold interrupt enable (IER[4])
• Transmitter underrun interrupt enable (IER[6])
6. Write a 1 to the ACREG[7] bit to enable data transmission
7. Write a 1 to the MCR[3] bit. This enables the selected IRQ channel.
2.1.1.1.1 Frame-Closing Methods
There are two ways a transmission frame can be properly terminated: frame-length method and set-EOT
bit method. The two methods are described as follows:
• Frame-Length method: This method is selected when the MDR[7] bit equals 0. The CPU writes
the frame-length value to the TXFLH and TXFLL registers. The device automatically attaches an
end flag to the frame when the number of bytes transmitted becomes equal to the TXFLH and
TXFLL value.
• Set-EOT bit method: This method is selected when the MDR[7] bit equals 1. The CPU writes a
1 to the EOT bit of the ACREG[0] register just before it writes the last byte to the TX FIFO. When
the CPU writes the last byte to the TX FIFO, the device internally sets the tag bit for that particular
byte in the TX FIFO. As the peripheral device in the transmit mode reads bytes from the TX FIFO,
the flag-bit information is used to attach an end flag and properly terminate the frame.
2.1.1.1.2 Store and Controlled Data Transmission
In the store and controlled transmission (SCT), the CPU initially writes (stores) the data in the TX FIFO. After
the CPU writes a part of the frame (for a bigger frame) or the whole frame (a small frame such as a
supervisory frame), it enables another bit (ACREG[2] in this case) to start transmission. The SCT is effective
when the CPU writes a 1 to the MDR[5] bit. This method of transmission is different from the normal mode
of transmission (MDR[5] = 0) where transmission of data starts right after the CPU writes the first byte to
the TX FIFO. The SCT sends short frames without a TX underrun.
2–4
2.1.1.1.3 1.6-µs Infrared (IR)-Pulse Select Method
During the MIR and FIR mode of operation, the transmitter sends a 1.6-µs pulse at least once every 500
ms. The purpose of this special pulse is to inform the slow device (in SIR mode) that the high-speed device
involved in data transaction is currently occupied. When the MDR[6] bit is a 0 (the default value), the
peripheral device in the transmit mode always sends a 1.6-µs pulse at the end of a transmission frame.
However, when bit MDR[6] is a 1, the transmission of a 1.6-µs pulse depends on the ACREG[3] bit value.
The CPU keeps a timer and sets the ACREG[3] bit at least once in every 500 ms. When the MDR[6] bit is
a 1, the peripheral device in the transmit mode sends a 1.6-µs pulse only if the ACREG[3] bit is a 1. The
advantage to this approach over the default value sent-always-1.6-µs pulse-at-the-end approach is that the
peripheral device in the transmit mode need not send the special 1.6-µs pulse at the end of every frame.
Sending a 1.6-µs pulse at the end of every frame may increase overhead, mainly in the MIR mode.
2.1.1.1.4 Data-Transmission Underrun
An underrun during data transmission occurs when the CPU fails to supply the data to the TX FIFO and the
TX FIFO becomes empty before the end of the frame is transmitted. When an underrun occurs, the device
closes the frame with an end-flag but attaches an incorrect CRC value. The receiving device detects the
CRC error and discards the frame. The device sets an internal flag and further transmission of data is
disabled. The CPU must reset the TX FIFO and read the RESUME register. This read operation clears the
internal flag.
2.1.1.2 FIR Data-Receive Mode
The following register programming steps are required to receive data in FIR mode:
1. Program the mode definition register (MDR) to:
• Select the FIR mode
• Enable the low-power mode
• Disable the sleep mode
2. Program the RXFLL and RXFLH registers for the receive-frame length value. The maximum
length of a frame is 2048 bytes. The RXFLL register stores the lower eight bits and the RXFLH
register stores the remaining bits. When the intended maximum receive-frame length is n,
program the RXFLH and RXFLL registers to be n + 5.
3. Reset the RX FIFO. This includes:
• Write to the LCR register that the LCR[7] bit is a 1. The LCR[7] bit must be a 1 to be able to
write to the FCR[5] bit.
• Program the FCR register to select 64-/16-bytes of the RX FIFO, the non-DMA/DMA mode of
operation, select the RX FIFO trigger level and to clear the RX FIFO.
• Write the LCR register to set the LCR[7] bit to a 0 for normal operation.
4. Program the IER register to enable only the receive related interrupts and disable the remaining
interrupts. Enable the following:
• RX threshold interrupt (IER[0] bit)
• The last byte from the RX FIFO interrupt (IER[2] bit)
• The RX FIFO overrun interrupt (IER[3] bit)
• The received end of the frame interrupt (IER[7] bit)
2–5
5. Write a 1 to the ACREG[6] to enable data receive.
6. Write a 1 to the MCR[3] bit. This enables the selected IRQ channel.
This completes the programming of the registers for data receive and now the device is ready to receive
data. The device decodes the serial data, converts it from serial data to parallel data and stores the data
bytes in the RX FIFO. When the stored data in the RX FIFO reaches the set threshold level, the device
interrupts the CPU. When the CPU is interrupted, it reads the IIR to identify the source of the interrupt. When
the source of the interrupt is the IIR[0] bit and not the IIR[7] bit, the CPU goes to the threshold mode.
2.1.1.2.1 Threshold Mode
During threshold mode, the CPU reads a number of bytes (determined by the RX FIFO threshold level) from
the RX FIFO. An example: When the RX threshold value is set to be 16, the CPU can perform 16 consecutive
read operations from the RX FIFO. When the source of interrupts is the IIR[7] bit, the CPU goes to the byte
mode.
2.1.1.2.2 Byte Mode
The CPU will read the majority of the frame in the threshold mode. However, the last bits of data may not
fall on the exact threshold boundary and will not be able to interrupt the CPU with the IIR[0] bit. The device
interrupts the CPU with the IIR[7] bit when the machine in the data-receive mode detects the end of a frame.
The CPU disables the IER[0] bit and reads one byte from the RX FIFO each time and checks for the interrupt
(IIR[2]) bit. When the CPU reads the last byte of a frame from the RX FIFO, the device interrupts the CPU
with the IIR[2] bit. Once the CPU receives the IIR[2] bit, it should not read further from the RX FIFO and that
is the end of the frame. The last four bytes that the CPU read from the RX FIFO are the CRC value and not
the actual data. The CPU enables the IER[0] bit. After the CPU reads the last byte of a frame from the RX
FIFO, it reads the LSR register to determine the sources or errors, if any, for that frame. When the source
of the interrupt is the IIR[3] bit, there has been an overrun while receiving data and the CPU will service the
overrun.
2.1.1.2.3 Data-Receive Overrun
An overrun occurs during data receive if the CPU cannot timely read out data from the RX FIFO and the RX
FIFO is overwritten. When an overrun occurs, the device interrupts the CPU with the IIR[3] bit and discards
the remaining portion of the frame. When an overrun occurs, the device sets an internal flag and the receive
operation of the next frame is disabled. Before the next frame can be received, the CPU must reset the RX
FIFO and read the RESUME register. This read operation clears the internal flag.
2.1.2 Medium-Speed Infrared (MIR) mode (IrDA 1.1)
During the medium speed infrared (MIR) mode, data transfer takes place between the CPU and peripheral
devices at a speed of 1.15 Mbs. A MIR transmit frame starts with a minimum of two Start Flags followed by
the Frame Data, CRC–16 and ends with a Stop Flag.
Start Flag Frame Data CRC-16 Stop Flag
The peripheral device in the data transmission mode of operation attaches the Start Flags, CRC-16, and
a Stop Flag. It also looks for five consecutive ones in the frame data and automatically inserts a zero after
five consecutive ones. This operation is known as bit stuffing. On a receive operation, the machine in the
data receive mode recovers the receive clock, removes the Start Flag, de-stuffs the incoming data and
determines frame boundary with the reception of the Stop Flag. It also checks for errors such as frame abort,
CRC error and frame-length error. At the end of a frame reception, the CPU reads the LSR status register
to find out if any errors occurred with the received frame.
The device can both transmit and receive data, but cannot do both at the same time. When the CPU wants
to send data, the perpheral device must be programmed for data transmission. When the CPU receives data
from the peripheral device, the perpheral device must be programmed for data receive. Some registers are
common to both data transmit and data receive and are programmed only once. Use the following
programming sequence for these registers:
2–6
1. Program the interrupt configuration register (ICR) in order to:
• Select the IRQ channel
• Select either totem-pole or open-drain output
• Select an active high or an active low for an interrupt when the totem-pole configuration is
selected.
2. In the MIR mode, the 48-MHz input clock is automatically divided by 1.5 to generate the 28x MIR
clock. However, a 6 should be written to the PRES register which is used as the base clock for
the status FIFO timeout interrupt.
2.1.2.1 MIR-Data Transmission Mode
The following register programming steps are performed for transmission in the MIR mode:
1. Program the mode-definition register (MDR) to:
• Select the MIR mode
• Enable/disable the low-power mode. The low-power mode is enabled for normal operation.
• Enable/disable the sleep mode. The sleep mode is disabled for normal operation.
• Enable/disable the store and controlled transmission. The SCT is disabled for normal
operation.
• Enable/disable the software control on the 1.6-µs infrared pulse. The software control is
disabled during normal operation.
• Select the frame closing method (frame-length method or set–EOT bit method)
2. Program the PLR to:
• Select the number of Start Flags. The default value is two.
• Select the TX FIFO trigger level.
3. When the frame-length method is selected for frame closing, program the TXFLL and the TXFLH
registers for the frame length.
4. Reset the TX FIFO:
• Write the LCR register so that the LCR[7] bit is a 1. The LCR[7] bit must be a 1 in order to write
to the FCR[5] bit.
• Program the FCR to select 64-/16-bytes of TX FIFO, non-DMA/DMA mode of operation , and
to clear the TX FIFO.
• Write the LCR register so that the LCR[7] bit is a 0 for normal operation.
5. Program the IER register to enable only the transmission related interrupts and disable the
remaining interrupts. The TX threshold interrupt and the TX underrun interrupt are enabled.
6. Write a 1 to the ACREG[7] bit to enable data transmission.
7. Write a 1 to the MCR[3] bit to enable the selected IRQ channel.
2–7
When the CPU receives an interrupt, it reads the IIR to identify the source of the interrupt. When the source
of the interrupt is an IIR[1] bit, the CPU requires the following:
• Disable the IER[1] bit.
• Write data bytes (maximum number limited to the number selected by the TX FIFO trigger
level) to the TX FIFO.
• Enable the IER[1] bit.
When the source of the interrupt is the IIR[5] bit, there has been an underrun while transmitting data and
the CPU needs to service the underrun. See paragraph 2.1.1.1.4
.
2.1.2.2 MIR Data Receive Mode
The following register programming steps are required to receive data in MIR mode:
1. Program the mode definition register (MDR) in order to:
• Select the MIR mode
• Disable the low power mode
• Disable the sleep mode
2. Program the RXFLL and RXFLH registers for maximum receive-frame length value. The
maximum length of a frame is 2048 bytes. The RXFLL register stores the lower eight bits and the
RXFLH register stores the remaining upper bits. When the intended maximum receive-frame
length is n, program the RXFLH and RXFLL registers to be n + 3.
3. Reset the RX FIFO. This includes:
• Write to the LCR register so that the LCR[7] bit is a 1. LCR[7] bit must be a 1 to be able to write
to the FCR[5] bit.
• Program the FCR register to select 64-/16- bytes of the RX FIFO, the non-DMA/DMA mode
of operation, select the RX FIFO trigger level and to clear the RX FIFO.
• Write the LCR register to set the LCR[7] bit to a 0 for normal operation.
4. Program the IER register to enable only the receive related interrupts and disable the remaining
interrupts. Enable the following:
• RX threshold interrupt (IER[0] bit)
• The last byte from the RX FIFO interrupt (IER[2] bit)
• The RX FIFO overrun interrupt (IER[3] bit)
• The received end of the frame interrupt (IER[7] bit)
5. Write a 1 to the ACREG[6] bit to enable data receive.
6. Write a 1 to the MCR[3] bit to enable the selected IRQ channel.
This completes the programming of the registers for data receive and now the device is ready to receive
data.When the CPU is interrupted, it reads the IIR to identify the source of the interrupt. When the source
of the interrupt is the IIR[7] bit, the CPU goes to the byte mode. See paragragh 2.1.1.2.2. The CRC value
is the last two bytes instead of the last four bytes as in the FIR data-transmission mode.
When the source of the interrupt is the IIR[0] bit and not the IIR[7] bit, the CPU goes into the threshold mode.
See paragraph 2.1.1.2.1. If the source of the interrupt is the IIR[4] bit, there has been an overrun while
receiving data and the CPU will need to service the overrun. See paragraph 2.1.1.2.3.
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