Texas Instruments TIBPAL22V10-10CNT, TIBPAL22V10-10CFN Datasheet

TIBPAL22V10-10C

HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS015 – D3972, FEBRUARY 1992

• Second-Generation PLD Architecture

• High-Performance Operation:

f

(External Feedback) . . . 71 MHz

max

Propagation Delay . . . 10 ns Max

• Increased Logic Power – Up to 22 Inputs

and 10 Outputs

• Increased Product Terms – Average of 12

Per Output

• Variable Product Term Distribution

Allows More Complex Functions to Be
Implemented

• Each Output Is User Programmable for

Registered or Combinational Operation,
Polarity, and Output Enable Control

• Power-Up Clear on Registered Outputs

• TTL-Level Preload for Improved Testability

• Extra Terms Provide Logical Synchronous

Set and Asynchronous Reset Capability

• Fast Programming, High Programming

Yield, and Unsurpassed Reliability Ensured
Using Ti-W Fuses

• AC and DC Testing Done at the Factory

Utilizing Special Designed-In Test Features

• Dependable Texas Instruments Quality and

Reliability

• Package Options Include Plastic

Dual-In-Line and Chip Carrier Packages

description

NT PACKAGE

(TOP VIEW)

NC

24
23
22
21
20
19
18
17
16
15
14
13

CC

V

I

V

CC

I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I

I/O/Q

25
24
23
22
21
20
19

I/O/Q

I/O/Q

CLK/I

GND

I
I
I

NC

I
I
I

– No internal connection

NC
Pin assignments in operating mode

1

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

I

11
12

FN PACKAGE

(TOP VIEW)

I

I

CLK/INCI/O/Q

3212827

426

5
6
7
8
9

10

11

12 13

14 15 16 1718

I

I

GND

I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q

The TIBP AL22V10-10C is a programmable array logic device featuring high speed and functional equivalency
when compared to presently available devices. They are implemented with the familiar sum-of-products
(AND-OR) logic structure featuring the new concept “Programmable Output Logic Macrocell”. These
IMPACT-X circuits combine the latest Advanced Low-Power Schottky technology with proven titanium­tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic.

These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and
programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered
and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are
enabled through the use of individual product terms.

Further advantages can be seen in the introduction of variable product term distribution. This technique
allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This
variable allocation of terms allows far more complex functions to be implemented than in previously available
devices.

This device is covered by U.S. Patent 4,410,987.
IMPACT-X is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1992, Texas Instruments Incorporated

1

TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS015 – D3972, FEBRUARY 1992

description (continued)

Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These
functions are common to all registers. When the synchronous set product term is a logic 1, the output registers
are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term
is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on
the polarity selected during programming. Output registers can be preloaded to any desired state during testing.
Preloading permits full logical verification during product testing.

With features such as programmable output logic macrocells and variable product term distribution, the
TIBPAL22V10-10C offers quick design and development of custom LSI functions with complexities of 500 to
800 equivalent gates. Since each of the ten output pins may be individually configured as inputs on either a
temporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and
10 outputs are possible.

A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is
applied to the device. Registered outputs selected as active-low power up with their outputs high. Registered
outputs selected as active-high power up with their outputs low.

A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once
blown, the verification circuitry is disabled and all other fuses will appear to be open.

The TIBPAL22V10-10C is characterized for operation from 0°C to 75°C.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

functional block diagram (positive logic)

TIBPAL22V10-10C

SRPS015 – D3972, FEBRUARY 1992

CLK/I

C1
1S
R

Output

Logic

Macrocell

EN

EN

EN

EN

EN

EN

EN

EN

EN

EN

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

10

10

12

14

16

16

14

12

10

Set
Reset

8

8

1

10

10

&

44 x 132

22

11

I

10

22

denotes fused inputs

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

4

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logic diagram (positive logic)

1

CLK/I

First
Fuse
Numbers

I

I

2

3

0 4 8 1216202428

0

396

440

880

924

1452

1496

Increment

32 36 40

Macro­cell

P = 5808
R = 5809

Macro­cell

P = 5810
R = 5811

Macro­cell

P = 5812
R = 5813

Macro­cell

Asynchronous Reset
(to all registers)

23

I/O/Q

22

I/O/Q

21

I/O/Q

20

I/O/Q

SRPS015 – D3972, FEBRUARY 1992

TIBPAL22V10-10C

HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

2112

4

I

2156

2860

5

I

P = 5814
R = 5815

Macro­cell

P = 5816
R = 5817

19

I/O/Q

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2904

Macro­cell

18

I/O/Q

HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

3608

6

I

3652

4268

7

I

4312

4840

8

I

4884

P = 5818
R = 5819

Macro­cell

P = 5820
R = 5821

Macro­cell

P = 5822
R = 5823

Macro­cell

17

16

15

I/O/Q

I/O/Q

I/O/Q

5324

9

I

5368

5720

10

I

5764

11

I

P = 5824
R = 5825

Macro­cell

P = 5826
R = 5827

14

I/O/Q

Synchronous Set
(to all registers)

13

I

SRPS015 – D3972, FEBRUARY 1992

TIBPAL22V10-10C

Fuse number = First Fuse number + Increment

5

Inside each MACROCELL the ”P” fuse is the polarity fuse and the ”R” fuse is the register fuse.

TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS015 – D3972, FEBRUARY 1992

output logic macrocell diagram

Output Logic Macrocell

MUX

2

From Clock Buffer

I = 0

AR

SS

AR = asynchronous reset
SS = synchronous set

R
1D

C1

1S

MUX

1

1

G1

S1

S0

3
0

1

0

1

G

3

0

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265