Datasheet TIBPAL16R8-15MWB, TIBPAL16R8-15MJ, TIBPAL16R8-15MJB, TIBPAL16R8-15MFKB, TIBPAL16R6-15MWB Datasheet (Texas Instruments)

TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M

HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

High-Performance Operation:

Propagation Delay . . . 15 ns Max

D

Power-Up Clear on Registered Devices (All
Register Outputs are Set High, but Voltage
Levels at the Output Pins Go Low)

D

Package Options Include Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (J) 300-mil DIPs

D

Dependable Texas Instruments Quality and
Reliability

DEVICE

I

INPUTS

3-STATE

O OUTPUTS

REGISTERED

Q OUTPUTS

I/O

PORTS

PAL16L8 10 2 0 6
PAL16R4 8 0 4 (3-state buffers) 4
PAL16R6 8 0 6 (3-state buffers) 2
PAL16R8 8 0 8 (3-state buffers) 0

description

These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices. These
IMP ACT-X circuits combine the latest Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable,
high-performance substitutes for conventional
TTL logic. Their easy programmability allows for
quick design of custom functions and typically
results in a more compact circuit board. In
addition, chip carriers are available for futher
reduction in board space.

The TIBPAL16’ M series is characterized for
operation over the full military temperature range
of –55°C to 125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  1996, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.

Pin assignments in operating mode

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

I
I
I
I
I
I
I
I
I

GND

V

CC

O
I/O
I/O
I/O
I/O
I/O
I/O
O
I

TIBPAL16L8’

J OR W PACKAGE

(TOP VIEW)

3 2 1 20 19

910111213

4
5
6
7
8

18
17
16
15
14

I/O
I/O
I/O
I/O
I/O

I
I
I
I
I

TIBPAL16L8’

FK PACKAGE

(TOP VIEW)

I

I

I

O

I/O

O

I

GND

I

V

CC

TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Pin assignments in operating mode

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

CLK

I
I
I
I
I
I
I
I

GND

V

CC

I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE

(TOP VIEW)

TIBPAL16R4’

J OR W PACKAGE

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

CLK

I
I
I
I
I
I
I
I

GND

V

CC

I/O
Q
Q
Q
Q
Q
Q
I/O
OE

(TOP VIEW)

TIBPAL16R6’

J OR W PACKAGE

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

CLK

I
I
I
I
I
I
I
I

GND

V

CC

Q
Q
Q
Q
Q
Q
Q
Q
OE

(TOP VIEW)

TIBPAL16R8’

J OR W PACKAGE

I

I

CLK

I/O

I/O

I/O

I

GND

V

CC

OE

3212019

910111213

4
5
6
7
8

18
17
16
15
14

I/O
Q
Q
Q
Q

I
I
I
I
I

(TOP VIEW)

TIBPAL16R4’

FK PACKAGE

I

I

CLK

I/O

Q

I/O

I

GND

V

CC

3212019

910111213

4
5
6
7
8

18
17
16
15
14

Q
Q
Q
Q
Q

I
I
I
I
I

(TOP VIEW)

OE

TIBPAL16R6’

FK PACKAGE

I

I

CLK

Q

Q

Q

I

GND

V

CC

OE

3212019

910111213

4
5
6
7
8

18
17
16
15
14

Q
Q
Q
Q
Q

I
I
I
I
I

(TOP VIEW)

TIBPAL16R8’

FK PACKAGE

TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M

HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagrams (positive logic)

TIBPAL16L8’

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I

EN

≥1

&

32 X 64

10 16

166

7

7

7

7

7

7

7

7

6

16 x

denotes fused inputs

TIBPAL16R4’

Q

I/O

I/O

I/O

I/O

I

EN

816

164

7

7

7

8

8

8

7

4

16 x

≥1

&

32 X 64

≥1

8

Q

Q

Q

4

1D

I = 1

2

CLK

C1

EN 2

OE

4

TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagrams (positive logic)

TIBPAL16R6’

Q

I/O

I/O

I

EN

816

162

7

8

8

8

7

2

16 x

≥1

&

32 X 64

≥1

8

Q

Q

Q

6

1D

I = 1

2

CLK

C1

EN 2

OE

6

8

Q

8

Q

denotes fused inputs

TIBPAL16R8’

Q

I

816

168

8

8

8

8

16 x

8

Q

Q

Q

1D

I = 1

2

CLK

C1

EN 2

8

Q

8

Q

&

32 X 64

≥1

OE

8

Q

8

Q

TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M

HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TIBPAL16L8-15M logic diagram (positive logic)

0 4 8 12 16 20 24 28 31

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

O

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

13

O

12

I

11

Increment

I

1

Fuse number = First fuse number + Increment

0
32
64
96

128
160
192
224

256
288
320
352
384
416
448
480

512
544
576
608
640
672
704
736

768
800
832
864
896
928
960
992

1024
1056
1088
1120
1152
1184
1216
1248

1280
1312
1344
1376
1408
1440
1472
1504

1536
1568
1600
1632
1664
1696
1728
1760

1792
1824
1856
1888
1920
1952
1984
2016

First
Fuse
Numbers

TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TIBPAL16R4-15M logic diagram (positive logic)

0 4812 16 20 24 28 31

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I/O

19

I/O

18

Q

17

Q

16

Q

15

Q

14

I/O

13

I/O

12

11

Increment

CLK

1

Fuse number = First fuse number + Increment

0
32
64
96

128
160
192
224

256
288
320
352
384
416
448
480

512
544
576
608
640
672
704
736

768
800
832
864
896
928
960
992

1024
1056
1088
1120
1152
1184
1216
1248

1280
1312
1344
1376
1408
1440
1472
1504

1536
1568
1600
1632
1664
1696
1728
1760

1792
1824
1856
1888
1920
1952
1984
2016

First
Fuse
Numbers

C1

1D

I = 1

C1

1D

I = 1

C1

1D

I = 1

C1

1D

I = 1

OE

TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M

HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TIBPAL16R6-15M logic diagram (positive logic)

0 4 8 12 16 20 24 28 31

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I/O

19

Q

17

Q

16

Q

15

Q

14

I/O

12

11

Increment

CLK

1

Fuse number = First fuse number + Increment

0
32
64
96

128
160
192
224

256
288
320
352
384
416
448
480

512
544
576
608
640
672
704
736

768
800
832
864
896
928
960
992

1024
1056
1088
1120
1152
1184
1216
1248

1280
1312
1344
1376
1408
1440
1472
1504

1536
1568
1600
1632
1664
1696
1728
1760

1792
1824
1856
1888
1920
1952
1984
2016

First
Fuse
Numbers

C1

1D

I = 1

C1

1D

I = 1

C1

1D

I = 1

C1

1D

I = 1

OE

Q

18

C1

1D

I = 1

Q

13

C1

1D

I = 1

TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TIBPAL16R8-15M logic diagram (positive logic)

0 4 8 12 16 20 24 28 31

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

Q

17

Q

16

Q

15

Q

14

11

Increment

CLK

1

Fuse number = First fuse number + Increment

0
32
64
96

128
160
192
224

256
288
320
352
384
416
448
480

512
544
576
608
640
672
704
736

768
800
832
864
896
928
960
992

1024
1056
1088
1120
1152
1184
1216
1248

1280
1312
1344
1376
1408
1440
1472
1504

1536
1568
1600
1632
1664
1696
1728
1760

1792
1824
1856
1888
1920
1952
1984
2016

First
Fuse
Numbers

C1

1D

I = 1

C1

1D

I = 1

C1

1D

I = 1

C1

1D

I = 1

OE

Q

18

C1

1D

I = 1

Q

13

C1

1D

I = 1

Q

19

C1

1D

I = 1

Q

12

C1

1D

I = 1

TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M

HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions

MIN NOM MAX UNIT

V

CC

Supply voltage 4.5 5 5.5 V

V

IH

High-level input voltage 2 5.5 V

V

IL

Low-level input voltage 0.8 V

I

OH

High-level output current –2 mA

I

OL

Low-level output current 12 mA

f

clock

Clock frequency 0 50 MHz

High 9

twPulse duration, clock (see Note 2)

Low 10

ns

t

su

Setup time, input or feedback before clock↑ 15 ns

t

h

Hold time, input or feedback after clock↑ 0 ns

T

A

Operating free-air temperature –55 25 125 °C

NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, f

clock

. The minimum pulse durations specified are

only for clock high or low, but not for both simultaneously.

electrical characteristics over recommended operating free-air temperature range

TIBPAL16R4-15M

PARAMETER

TEST CONDITIONS

MIN TYP‡MAX

UNIT

V

IK

VCC = 4.5 V, II = –18 mA –1.5 V

V

OH

VCC = 4.5 V, IOH = –2 mA 2.4 3.3 V

V

OL

VCC = 4.5 V, IOL = 12 mA 0.35 0.5 V

Outputs

20

I

OZH

I/O ports

V

CC

= 5.5 V,

V

O

= 2.7

V

100

µ

A

Outputs

–20

I

OZL

I/O ports

V

CC

= 5.5 V,

V

O

= 0.4

V

–250

µ

A

Pin 1, 11

0.2

I

I

All others

V

CC

= 5.5 V,

V

I

= 5.5

V

0.1

mA

Pin 1, 11 50

I

IH

I/O ports

VCC = 5.5 V, VI = 2.7 V

100

µA

All others 25

I

IL

VCC = 5.5 V, VI = 0.4 V –0.25 mA

I

OS

§

VCC = 5.5 V, VO = 0.5 V –30 –250 mA

I

CC

VCC = 5.5 V, VI = 0, Outputs open 170 220 mA

‡

All typical values are at VCC = 5 V, TA = 25°C.

§

Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid
test equipment degradation.

TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range

TIBPAL16L8-15M
TIBPAL16R6-15M

PARAMETER

TEST CONDITIONS

TIBPAL16R8-15M

UNIT

MIN TYP†MAX

V

IK

VCC = 4.5 V, II = –18 mA –1.5 V

V

OH

VCC = 4.5 V, IOH = –2 mA 2.4 3.3 V

V

OL

VCC = 4.5 V, IOL = 12 mA 0.35 0.5 V

Outputs

20

I

OZH

I/O ports

V

CC

= 5.5 V,

V

O

= 2.7

V

100

µ

A

Outputs

–20

I

OZL

I/O ports

V

CC

= 5.5 V,

V

O

= 0.4

V

–250

µ

A

Pin 1, 11

0.2

I

I

All others

V

CC

= 5.5 V,

V

I

= 5.5

V

0.1

mA

Pin 1, 11 50

I

IH

I/O ports

VCC = 5.5 V, VI = 2.7 V

100

µA
All others 20
I/O ports

–0.25

I

IL

All others

V

CC

=

5.5 V

,

V

I

=

0.4 V

–0.2

mA

I

OS

‡

VCC = 5.5 V, VO = 0.5 V –30 –250 mA

I

CC

VCC = 5.5 V, VI = 0, Outputs open 170 220 mA

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid
test equipment degradation.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

TEST CONDITIONS MIN TYP†MAX UNIT

f

max

§

50 MHz

t

pd

I, I/O O, I/O

8 15 ns

t

pd

CLK↑ Q R1 = 390 Ω, 7 12 ns

t

en

OE↓ Q R2 = 750 Ω, 8 12 ns

t

dis

OE↑ Q See Figure 1 7 12 ns

t

en

I, I/O O, I/O 8 15 ns

t

dis

I, I/O O, I/O 8 15 ns

†

All typical values are at VCC = 5 V, TA = 25°C.

§

Maximum operating frequency and propagation delay are specified for the basic building block. When using feedback, limits must be calculated
accordingly.

TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M

HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

programming information

Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.

The TIBPAL16R4-15M with date codes prior to 9616A must be programmed according to programming
algorithms/specifications corresponding to the TIBP AL16R4-12C. The TIBPAL16R4-15M with date code 9616A
or newer must be programmed according to programming algorithms/specifications corresponding to the
TIBPAL16R4-10C.

Regardless of date code, the TIBPAL16L8-15M, TIBPAL16R6-15M, and TIBPAL16R8-15M must be
programmed according to programming algorithms/specifications corresponding to the TIBPAL16L8-12C,
TIBPAL16R6-12C, and TIBPAL16R8-12C, respectively. Failure to do so may damage the devices.

Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming T exas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at [phone].

T able 1. Programming Reference Table

(see Note 3)

DEVICE

DESC SMD

NUMBER

FAMILY/PINOUT

CODE

TIBPAL16L8-15MJB 5962-8515509RA 9A/17
TIBPAL16L8-15MFKB 5962-85155092A 9A/717
TIBPAL16L8-15MWB 5962-8515509SA 9A/17
TIBPAL16R4-15MJB 5962-8515512RA A1/24
TIBPAL16R4-15MFKB 5962-85155122A 0A1/724
TIBPAL16R4-15MWB 5962-8515512SA A1/24
TIBPAL16R6-15MJB 5962-8515511RA 9A/24
TIBPAL16R6-15MFKB 5962-85155112A 9A/724
TIBPAL16R6-15MWB 5962-8515511SA 9A/24
TIBPAL16R8-15MJB 5962-8515510RA 9A/24
TIBPAL16R8-15MFKB 5962-85155102A 9A/724
TIBPAL16R8-15MWB 5962-8515510SA 9A/24

NOTE 3: Programming information for TIBPAL16R4-15M with date codes

9616A or newer. Programming information for TIBPAL16L8-15M,
TIBPAL16R6-15M, and TIBPAL16R8-15M regardless of date code.

TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT  PAL



CIRCUITS

SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

t

su

S1

From Output

Under Test

Test

Point

R2

C

L

(see Note A)

LOAD CIRCUIT FOR

3-STATE OUTPUTS

3 V

0

1.5 V

1.5 V

t

h

1.5 V

Timing

Input

Data

Input

Input

In-Phase

Output

Out-of-Phase

Output

(see Note D)

t

pd

t

pd

t

pd

t

pd

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

V

OH

V

OH

V

OL

V

OL

3 V

0

3 V

0

1.5 V 1.5 V

1.5 V 1.5 V

t

w

High-Level

Pulse

Low-Level

Pulse

Output

Control
(low-level
enabling)

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

1.5 V 1.5 V

3 V

0

≈ 3.3 V

V

OL

V

OH

VOH – 0.5 V

≈ 0 V

t

en

t

en

t

dis

t

dis

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

1.5 V

1.5 V

1.5 V

R1

3 V

3 V

0

0

VOL + 0.5 V

5 V

NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for t

dis

.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 10 MHz, tr and tf ≤ 2 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.

Figure 1. Load Circuit and Voltage Waveforms

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