Datasheet THS 7347 Datasheet (Texas Instruments)

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3.3V

2:1

Input1

0.1 Fm

In A

InB

Input2

75 W

ADC

Sync

TIP

Clamp

+Offset

AC-

BIAS

1kW 878 W

675 W

150 W

Out

SAG

47 Fm

33 Fm

75 W

Monitor Output

75 W

SDA

SCL

Disable

= OPEN

3-Channel RGBHV Video Buffer with I2C™ Control, 2:1 Input Mux,

Monitor Pass-Through, and Selectable Input Bias Modes

FEATURES APPLICATIONS

• 3-Video Amplifiers for CVBS, S-Video, EDTV,

HDTV Y'P'

• H/V Sync Paths with Adjustable Schmitt

Trigger

• 2:1 Input Mux

• I2C Control of All Functions on Each Channel

• Unity-Gain Buffer Path for ADC Buffering: – 500-MHz Bandwidth, 1200-V/ µ s Slew Rate

• Monitor Pass-Through Function:

– 500-MHz Bandwidth, 1300-V/ µ s Slew Rate – 6-dB Gain with SAG Correction Capable – High Output Impedance in Disable State

• Selectable Input Bias Modes: – AC-Coupled with Sync-Tip Clamp – AC-Coupled with Bias – DC-Coupled with Offset Shift – DC-Coupled

• +2.7-V to +5-V Single-Supply Operation

• Total Power Consumption: 265 mW at 3.3 V

• Disable Function Reduces Current to 0.1 µ A

• Rail-to-Rail Output:

– Output Swings Within 0.1 V of the Rails,

Allowing AC- or DC-Output Coupling

• Lead-free, RoHS TQFP Package

, G'B'R', and R'G'B' Video

BP'R

THS7347

SLOS531 – MAY 2007

• Projectors

• Professional Video Systems

• LCD/ DLP

DESCRIPTION

Fabricated using the revolutionary complementary silicon-germanium (SiGe) BiCom3 process, the THS7347 is a low-power, single-supply 2.7-V to 5-V 3-channel integrated video buffer with horizontal (H) and vertical (V) sync signal paths. It incorporates a 500-MHz bandwidth, 1200-V/ µ s unity-gain buffer ideal for driving analog-to-digital converters (ADCs) and video decoders. In parallel with the unity-gain buffer, a monitor pass-through path allows for passing the input signal on to other systems. This path has a 6-dB gain, 500-MHz bandwidth, 1300V/ µ s slew rate, SAG correction capability, and high output impedance while disabled.

Each channel of the THS7347 is individually I2C-configurable for all functions, including controlling the 2:1 input mux. Its rail-to-rail output stage allows for both ac- and dc-coupling applications.

/LOCS Input Buffering

3.3 V Single-Supply Projector Input System with Monitor Pass-Through

PowerPAD is a trademark of Texas Instruments. DLP is a registered trademark of Texas Instruments. I2C is a trademark of NXP Semiconductors, Inc. All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

(1 of 3 R'G'B' Channels Shown)

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THS7347

SLOS531 – MAY 2007

DESCRIPTION, CONTINUED

As part of the THS7347 flexibility, the device input can be selected for ac- or dc-coupled inputs. The ac-coupled modes include a sync-tip clamp option for CVBS/Y'/G'B'R' with sync or a fixed bias for the C'/P' channels without sync. The dc input options include a dc input or a dc+Offset shift to allow for a full sync dynamic range at the output with 0 V input.

The THS7347 is available in a lead-free, RoHS-compliant TQFP package.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

/P'

/R'G'B'

PACKAGING/ORDERING INFORMATION

(1)

PACKAGED DEVICES PACKAGE TYPE TRANSPORT MEDIA, QUANTITY

THS7347IPHP Tray, 250

THS7347IPHPR Tape and reel, 1000

HTQFP-48 PowerPAD™

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com .

ABSOLUTE MAXIMUM RATINGS

Over operating free-air temperature range (unless otherwise noted)

stg

(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

(2) The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process. (3) The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this

Supply voltage, GND to VAor GND to V

Input voltage –0.4 to VAor V Continuous output current ± 80 mA Continuous power dissipation See Dissipation Rating Table Maximum junction temperature, any condition

(2)

Maximum junction temperature, continuous operation, long term reliability Storage temperature range –65 to +150 ° C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 ° C

HBM 1500 V

ESD ratings CDM 1500 V

MM 100 V

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.

temperature may result in reduced reliability and/or lifetime of the device.

(1)

THS7347 UNIT

5.5 V

+150 ° C

(3)

+125 ° C

DISSIPATION RATINGS

POWER RATING

= +125 ° C)

PACKAGE ( ° C/W) ( ° C/W) TA= +25 ° C TA= +85 ° C

HTQFP-48 with PowerPAD (PHP) 1.2 35 2.85 W 1.14 W

(1) This data was taken with a PowerPAD standard 3-inch by 3-inch, 4-layer printed circuit board (PCB) with internal ground plane

connections to the PowerPAD.

(2) Power rating is determined with a junction temperature of +125 ° C. This temperature is the point where distortion starts to substantially

increase and long-term reliability starts to be reduced. Thermal management of the final PCB should strive to keep the junction temperature at or below +125 ° C for best performance and reliability.

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RECOMMENDED OPERATING CONDITIONS

Digital supply voltage 2.7 5 V

Analog supply voltage. Must be equal to or greater than V

Ambient temperature –40 +85 ° C

THS7347

SLOS531 – MAY 2007

MIN NOM MAX UNIT

VDD 5 V

ELECTRICAL CHARACTERISTICS, V

= V

= 3.3 V

RL= 150 Ω 5 pF to GND for Monitor Output, 19 k Ω || 8 pF Load to GND for Buffer Output, SAG pin shorted to Monitor Output Pin, unless otherwise noted.

TYP OVER TEMPERATURE

PARAMETER TEST CONDITIONS +25 ° C +25 ° C +70 ° C +85 ° C UNIT TYP

AC PERFORMANCE

Small-signal Buffer output 500 MHz Typ bandwidth VO= 0.2 V (–3 dB)

–1 dB Flatness VO= 0.2 V

Large-signal Buffer output VO= 1 V bandwidth (–3 dB)

Slew rate

Group delay at 100 kHz

Differential gain NTSC/PAL

Differential phase NTSC/PAL

Total harmonic Buffer output VO= 1 V distortion f = 1 MHz

Signal-to-noise ratio No weighting, up to 100 MHz

Channel-to-channel crosstalk

MUX Isolation f = 100 MHz

Gain

Settling time VIN= 1 VPP; 0.5% Settling

Output impedance f = 10 MHz

DC PERFORMANCE

Output offset voltage Bias = dc

Average offset voltage drift

Bias output voltage

Sync tip clamp voltage

Monitor output 450 MHz Typ Buffer output 425 MHz Typ

Monitor output 375 MHz Typ

Monitor output VO= 2 V Buffer output VO= 1 V

Monitor output VO= 2 V Buffer output 1.2 ns Typ Monitor output 1.2 ns Typ Buffer output 0.05/0.05 % Typ Monitor output 0.1/0.1 % Typ Buffer output 0.1/0.15 degrees Typ Monitor output 0.15/0.2 degrees Typ

Monitor output VO= 2 V Buffer output 63 dB Typ

Monitor output 65 dB Typ Buffer output –40 dB Typ Monitor output –36 dB Typ Buffer output 64 dB Typ Monitor output 66 dB Typ Buffer output f = 100 kHz; VO= 1 V Monitor output f = 100 kHz; VO= 2 V Buffer output 6 ns Typ Monitor output 6 ns Typ Buffer output 0.3 Ω Typ Monitor output 0.4 Ω Typ

Buffer output 15 ± 80 ± 85 ± 85 mV Max Monitor output 20 ± 120 ± 125 ± 125 mV Max Buffer output 20 µ V/ ° C Typ Monitor output 20 µ V/ ° C Typ

Buffer output

Monitor output

Buffer output 290 200/380 195/385 190/390 mV Min/Max Monitor output 300 200/400 195/405 190/410 mV Min/Max

f = 100 MHz

Bias = dc

Bias = dc + shift, VIN= 0 V 255 175/335 165/345 160/350 mV Min/Max Bias = ac 1.0 0.85/1.15 0.8/1.2 0.8/1.2 V Min/Max Bias = dc + shift, VIN= 0 V 235 145/325 135/335 130/340 mV Min/Max Bias = ac 1.7 1.55/1.85 1.5/1.9 1.5/1.9 V Min/Max

Bias = ac STC, clamp voltage

PP PP

475 MHz Typ 240 MHz Typ

1050 V/ µ s Typ 1050 V/ µ s Typ

–58 dB Typ –57 dB Typ

0 dB Typ 6 5.8/6.25 5.75/6.3 5.75/6.35 dB Min/Max

0 ° C to –40 ° C to MIN/MAX/

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THS7347

SLOS531 – MAY 2007

ELECTRICAL CHARACTERISTICS, V

= V

= 3.3 V (continued)

RL= 150 Ω 5 pF to GND for Monitor Output, 19 k Ω || 8 pF Load to GND for Buffer Output, SAG pin shorted to Monitor Output Pin, unless otherwise noted.

TYP OVER TEMPERATURE

PARAMETER TEST CONDITIONS +25 ° C +25 ° C +70 ° C +85 ° C UNIT TYP

DC PERFORMANCE, continued

Input bias current Bias = dc; (–) implies IBout of the pin –1.3 –3.0 –3.5 –3.5 µ A Max Average bias current drift Bias = dc 10 nA/ ° C Typ

Bias = ac STC, low bias 2.3 0.9/3.6 0.8/3.8 0.7/3.9 µ A Min/Max

Sync tip clamp bias current Bias = ac STC, mid bias 5.8 3.8/8.0 3.7/8.2 3.6/8.3 µ A Min/Max

Bias = ac STC, high bias 8.1 5.7/10.8 5.6/11.0 5.5/11.1 µ A Min/Max

INPUT CHARACTERISTICS

Input voltage range Bias = dc 0 to 2 V Typ

Input resistance

Input capacitance 1.5 pF Typ

OUTPUT CHARACTERISTICS: MONITOR OUTPUT

High output voltage swing

Low output voltage swing

Output current RL= 10 Ω to 1.65 V

OUTPUT CHARACTERISTICS: BUFFER OUTPUT

High output voltage swing (Limited by input range and G = 0 dB)

Low Output voltage swing (Limited by input range and G = 0 dB)

Output Current

POWER SUPPLY: ANALOG

Maximum operating voltage V Minimum operating voltage V Maximum quiescent current VA, dc + shift mode, VIN= 100 mV 80 100 103 105 mA Max Minimum quiescent current VA, dc + shift mode, VIN= 100 mV 80 60 57 55 mA Min Power supply rejection (+PSRR) Buffer output 50 dB Typ

POWER SUPPLY: DIGITAL

Maximum operating voltage V Minimum operating voltage V Maximum quiescent current VDD, VIN= 0 V 0.65 1.2 1.3 1.4 mA Max Minimum quiescent current VDD, VIN= 0 V 0.65 0.35 0.3 0.25 mA Min

DISABLE CHARACTERISTICS: ALL CHANNELS DISABLED

Quiescent current All channels disabled 0.1 µ A Typ Turn-on time delay (tON) 5 µ s Typ Turn-on time delay (t

Sourcing 80 50 47 45 mA Min Sinking 75 50 47 45 mA Min

Sourcing RL= 10 Ω to GND 80 50 47 45 mA Min Sinking RL= 10 Ω to 1.65 V 75 50 47 45 mA Min

) 2 µ s Typ

OFF

Bias = ac bias mode 25 k Ω Typ Bias = dc, dc + shift, ac STC 3 M Ω Typ

RL= 150 Ω to 1.65 V 3.15 2.9 2.8 2.8 V Min RL= 150 Ω to GND 3.05 2.85 2.75 2.75 V Min RL= 75 Ω to 1.65 V 3.05 V Typ RL= 75 Ω to GND 2.9 V Typ RL= 150 Ω to 1.65 V 0.15 0.25 0.28 0.29 V Max RL= 150 Ω to GND 0.1 0.18 0.21 0.22 V Max RL= 75 Ω to 1.65 V 0.25 V Typ RL= 75 Ω to GND 0.08 V Typ

2 1.8 1.75 1.75 V Min

Load = 19 k Ω 8 pF to 1.65 V

0.05 0.12 0.13 0.14 V Max

A A

DD DD

Time for lSto reach 50% of final value after I2C control is initiated

3.3 5.5 5.5 5.5 V Max

3.3 2.7 2.7 2.7 V Min

3.3 5.5 5.5 5.5 V Max

3.3 2.7 2.7 2.7 V Min

0 ° C to –40 ° C to MIN/MAX/

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THS7347

SLOS531 – MAY 2007

ELECTRICAL CHARACTERISTICS, V

= V

= 3.3 V (continued)

RL= 150 Ω 5 pF to GND for Monitor Output, 19 k Ω || 8 pF Load to GND for Buffer Output, SAG pin shorted to Monitor Output Pin, unless otherwise noted.

TYP OVER TEMPERATURE

PARAMETER TEST CONDITIONS +25 ° C +25 ° C +70 ° C +85 ° C UNIT TYP

H/V SYNC CHARACTERISTICS: R

Schmitt trigger adjust pin voltage Reference for Schmitt trigger 1.47 1.35/1.6 1.3/1.65 1.27/1.68 V Min/Max Schmitt trigger threshold range Allowable range for Schmitt trigger adjust 0.9 to 2 V Typ

Schmitt trigger VT+ 0.25 V Typ

Schmitt trigger VT– –0.3 V Typ Schmitt trigger threshold pin input

resistance H/V Sync input impedance 10 M Ω Typ H/V Sync high output voltage 1 k Ω to GND 3.15 3.05 3.0 3.0 V Min H/V Sync low output voltage 1 k Ω to GND 0.01 0.05 0.1 0.1 V Max H/V Sync source current 10 Ω to GND 50 35 30 30 mA Min H/V Sync sink current 10 Ω to 3.3 V 35 25 23 21 mA Min H/V Delay Delay from Input to output 6.5 ns Typ H/V to buffer output skew 5 ns Typ

= 1 k Ω To GND

Load

Positive-going input voltage threshold relative to Schmitt trigger threshold

Negative-going input voltage threshold relative to Schmitt trigger threshold

Input resistance into Control pin 10 k Ω Typ

(1)

(1) Schmitt trigger threshold is defined by (VT+ – VT–)/2.

0 ° C to –40 ° C to MIN/MAX/

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THS7347

SLOS531 – MAY 2007

ELECTRICAL CHARACTERISTICS, V

= V

= 5 V

RL= 150 Ω || 5pF to GND for Monitor Output, 19k Ω || 8pF Load to GND for Buffer Output, SAG pin shorted to Monitor Output Pin, unless otherwise noted.

TYP OVER TEMPERATURE

PARAMETER TEST CONDITIONS +25 ° C +25 ° C +70 ° C +85 ° C UNIT TYP

AC PERFORMANCE

Small-signal Buffer output 550 MHz Typ bandwidth VO= 0.2 V (–3 dB)

–1 dB Flatness VO= 0.2 V

Large-signal Buffer output VO= 1 V bandwidth (–3 dB)

Slew rate

Group delay at 100 kHz

Differential gain NTSC/PAL

Differential phase NTSC/PAL

Total harmonic Buffer output VO= 1 V distortion f = 1 MHz

Signal-to-noise ratio No weighting, up to 100 MHz

Channel-to-channel crosstalk

MUX Isolation f = 100 MHz

Gain

Settling time VIN= 1 VPP; 0.5% Settling

Output impedance f = 10 MHz

DC PERFORMANCE

Output offset voltage Bias = dc

Average offset voltage drift

Bias output voltage

Sync tip clamp voltage

Input bias current Bias = dc; (–) implies IBout of the pin –1.4 –3.0 –3.5 –3.5 µ A Max Average bias current drift Bias = dc 10 nA/ ° C Typ

Sync tip clamp bias current Bias = ac STC, mid bias 6.2 3.9/8.4 3.8/8.6 3.7/8.7 µ A Min/Max

Monitor output 500 MHz Typ Buffer output 450 MHz Typ

Monitor output 400 MHz Typ

Monitor output VO= 2 V Buffer output VO= 1 V

Monitor output VO= 2 V Buffer output 1.15 ns Typ Monitor output 1.15 ns Typ Buffer output 0.05/0.05 % Typ Monitor output 0.1/0.1 % Typ Buffer output 0.05/0.05 degrees Typ Monitor output 0.05/0.05 degrees Typ

Monitor output VO= 2 V Buffer output 63 dB Typ

Buffer output 15 ± 80 ± 85 ± 85 mV Max Monitor output 20 ± 120 ± 125 ± 125 mV Max Buffer output 20 µ V/ ° C Typ Monitor output 20 µ V/ ° C Typ

Buffer output

Monitor output

Buffer output 295 205/385 200/390 195/395 mV Min/Max Monitor output 300 200/400 195/405 190/410 mV Min/Max

f = 100 MHz

Bias = dc

Bias = dc + shift, VIN= 0 V 265 185/345 175/355 170/360 mV Min/Max Bias = ac 1.5 1.3/1.65 1.25/1.7 1.25/1.7 V Min/Max Bias = dc + shift, VIN= 0 V 235 145/325 135/335 130/340 mV Min/Max Bias = ac 2.65 2.5/2.8 2.45/2.85 2.45/2.85 V Min/Max

Bias = ac STC, clamp voltage

Bias = ac STC, low bias 2.4 0.9/3.9 0.8/4.0 0.7/4.1 µ A Min/Max

Bias = ac STC, high bias 8.6 6/11.2 5.8/11.4 5.7/11.5 µ A Min/Max

PP PP

525 MHz Typ 325 MHz Typ

1200 V/ µ s Typ 1350 V/ µ s Typ

–71 dB Typ –67 dB Typ

0 dB Typ 6 5.8/6.25 5.75/6.3 5.75/6.35 dB Min/Max

0 ° C to –40 ° C to MIN/MAX/

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THS7347

SLOS531 – MAY 2007

ELECTRICAL CHARACTERISTICS, V

= V

= 5 V (continued)

RL= 150 Ω || 5pF to GND for Monitor Output, 19k Ω || 8pF Load to GND for Buffer Output, SAG pin shorted to Monitor Output Pin, unless otherwise noted.

TYP OVER TEMPERATURE

PARAMETER TEST CONDITIONS +25 ° C +25 ° C +70 ° C +85 ° C UNIT TYP

INPUT CHARACTERISTICS

Input voltage range Bias = dc 0 to 3.4 V Typ

Input resistance

Input capacitance 1.5 pF Typ

OUTPUT CHARACTERISTICS: MONITOR OUTPUT

High output voltage swing

Low output voltage swing

Output current RL= 10 Ω to 2.5 V

OUTPUT CHARACTERISTICS: BUFFER OUTPUT

High output voltage swing (Limited by input range and G = 0 dB)

Low output voltage swing (Limited by input range and G = 0 dB)

Output current

POWER SUPPLY: ANALOG

Maximum operating voltage V Minimum operating voltage V Maximum quiescent current VA, dc + shift mode, VIN= 100 mV 90 112 115 117 mA Max Minimum quiescent current VA, dc + shift mode, VIN= 100 mV 90 68 65 63 mA Min Power supply rejection (+PSRR) Buffer Output 46 dB Typ

POWER SUPPLY: DIGITAL

Maximum operating voltage V Minimum operating voltage V Maximum quiescent current VDD, VIN= 0 V 1 2 3 3 mA Max Minimum quiescent current VDD, VIN= 0 V 1 0.5 0.4 0.4 mA Min

DISABLE CHARACTERISTICS: ALL CHANNELS DISABLED

Quiescent current All channels disabled 1 µ A Typ Turn-on time delay (tON) 5 µ s Typ Turn-on time delay (t

Sourcing 110 85 80 75 mA Min Sinking 110 85 80 75 mA Min

Sourcing RL= 10 Ω to GND 110 85 80 75 mA Min Sinking RL= 10 Ω to 2.5 V 110 85 80 75 mA Min

) 2 µ s Typ

OFF

Bias = ac bias mode 25 k Ω Typ Bias = dc, dc + shift, ac STC 3 M Ω Typ

RL= 150 Ω to 2.5 V 4.8 4.65 4.6 4.6 V Min RL= 150 Ω to GND 4.7 4.55 4.5 4.5 V Min RL= 75 Ω to 2.5 V 4.7 V Typ RL= 75 Ω to GND 4.6 V Typ RL= 150 Ω to 2.5 V 0.2 0.25 0.28 0.30 V Max RL= 150 Ω to GND 0.1 0.19 0.23 0.24 V Max RL= 75 Ω to 2.5 V 0.24 V Typ RL= 75 Ω to GND 0.085 V Typ

3.4 3.1 3.0 3.0 V Min

Load = 19 k Ω 8 pF to 2.5 V

0.05 0.12 0.13 0.14 V Max

A A

DD DD

Time for lSto reach 50% of final value after I2C control is initiated

5.0 5.5 5.5 5.5 V Max

5.0 2.7 2.7 2.7 V Min

5.0 5.5 5.5 5.5 V Max

5.0 2.7 2.7 2.7 V Min

0 ° C to –40 ° C to MIN/MAX/

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THS7347

SLOS531 – MAY 2007

ELECTRICAL CHARACTERISTICS, V

= V

= 5 V (continued)

RL= 150 Ω || 5pF to GND for Monitor Output, 19k Ω || 8pF Load to GND for Buffer Output, SAG pin shorted to Monitor Output Pin, unless otherwise noted.

TYP OVER TEMPERATURE

PARAMETER TEST CONDITIONS +25 ° C +25 ° C +70 ° C +85 ° C UNIT TYP

H/V SYNC CHARACTERISTICS: R

Schmitt trigger adjust pin voltage Reference for Schmitt trigger 1.54 1.43/1.65 1.38/1.7 1.35/1.73 V Min/Max Schmitt trigger threshold range Allowable range for Schmitt trigger adjust 0.9 to 2 V Typ

Schmitt trigger VT+ 0.25 V Typ

Schmitt trigger VT– –0.3 V Typ Schmitt trigger threshold pin input

resistance H/V Sync input impedance 10 M Ω Typ H/V Sync high output voltage 1 k Ω to GND 4.8 4.7 4.6 4.6 V Min H/V Sync low output voltage 1 k Ω to GND 0.01 0.05 0.1 0.1 V Max H/V Sync source current 10 Ω to GND 90 60 55 55 mA Min H/V Sync sink current 10 Ω to 5 V 50 30 27 25 mA Min H/V Delay Delay from input to output 6.5 ns Typ H/V to buffer output skew 5 ns Typ

= 1 k Ω To GND

Load

Positive-going input voltage threshold relative to Schmitt trigger threshold

Negative-going input voltage threshold relative to Schmitt trigger threshold

Input resistance into Control pin 10 k Ω Typ

(1)

(1) Schmitt trigger threshold is defined by (VT+ – VT–)/2.

0 ° C to –40 ° C to MIN/MAX/

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TIMING REQUIREMENTS FOR I2C INTERFACE

w(H)

w(L)

su(1)

h(1)

SCL

SDA

su(2)

h(2)

su(3)

(buf)

SCL

SDA

StartCondition StopCondition

At V

= 2.7 V to 5 V.

(1) (2)

STANDARD MODE FAST MODE

PARAMETER MIN MAX MIN MAX UNIT

SCL

w(H)

w(L)

su(1)

h(1)

(buf)

su(2)

h(2)

su(3)

Clock frequency, SCL 0 100 0 400 kHz Pulse duration, SCL high 4 0.6 µ s Pulse duration, SCL low 4.7 1.3 µ s Rise time, SCL and SDA 1000 300 ns Fall time, SCL and SDA 300 300 ns Setup time, SDA to SCL 250 100 ns Hold time, SCL to SDA 0 0 ns Bus free time between stop and start conditions 4.7 1.3 µ s Setup time, SCL to start condition 4.7 0.6 µ s Hold time, start condition to SCL 4 0.6 µ s Setup time, SCL to stop condition 4 0.6 µ s Capacitive load for each bus line 400 400 pF

(1) The THS7347 I2C address = 01011(A1)(A0)(R/ W). See the Applications Information section for more information. (2) The THS7347 was designed to comply with version 2.1 of the I2C specification.

THS7347

SLOS531 – MAY 2007

Figure 1. SCL and SDA Timing

Figure 2. Start and Stop Conditions

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V-Sync

InputB

Sync

TIP

Clamp

+Offset

AC-

BIAS

1kW

878 W

675 W

150 W

2:1

SCHMITT TRIGGER

ADJUST

+1.4V

10kW

SDA

I2C,

SCL

Channel3Buffer

Output(ToADC)

Channel3Monitor Output

Channel3SAG

Vertical Sync MonitorOUTPUT

AGND

DGND

PUCMUX

MODE

MUX

SELECT

Disable =OPEN

Channel1Buffer Output(ToADC)

Channel1Monitor Output

Channel1SAG

Disable =OPEN

2:1

Sync

TIP

Clamp

+Offset

AC-

BIAS

Sync

TIP

Clamp

+Offset

AC-

BIAS

Channel1

InputB

Channel2

InputB

Channel3

InputB

H-Sync InputB

V-Sync

InputA

Channel1

InputA

Channel2

InputA

Channel3

InputA

H-Sync InputA

Channel2Buffer Output(ToADC)

Channel2Monitor Output

Channel2SAG

I2C,

HorizontalSync BufferOUTPUT

HorizontalSync MonitorOUTPUT

Vertical Sync BufferOUTPUT

THS7347

SLOS531 – MAY 2007

FUNCTIONAL BLOCK DIAGRAM

NOTE: The I2C address of the THS7347 is 01011(A1)(A0)(R/ W).

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CH.1,INPUTA

CH.2,INPUTA

CH.3,INPUTA

H-SYNC,INPUTA

V-SYNC,INPUTA

AGND

CH.1,INPUTB

CH.2,INPUTB

CH.3,INPUTB

H-SYNC,INPUTB

V-SYNC,INPUTB

AGND

CH.1,BUFFEROUTPUT

AGND

+VA

CH.2,BUFFEROUTPUT

CH.3,BUFFEROUTPUT

CH.2,BUFFEROUTPUT

CH.3,BUFFEROUTPUT

AGND

+VA

H-SYNCBUFFEROUTPUT

THS7347

AGND

SCHMITT-TRIGGERADJ.

MUXMODE

MUXSELECT

I2C,A0

PUC

I2C,A1

VDD

SDA

DGND

SCL

V-SYNCBUFFEROUTPUT

AGND

CH.1,MONITOROUTPUT

CH.1,SAG

CH.2,MONITOROUTPUT

H-SYNCMON.OUTPUT

CH.2,SAG

V-SYNCMON.OUTPUT

CH.3,MONITOROUTPUT

+VA

CH.3,SAG

AGND

THS7347

SLOS531 – MAY 2007

PIN CONFIGURATION

THS7347IPHP

HTQFP-48 (PHP)

(Top View)

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THS7347

SLOS531 – MAY 2007

PIN CONFIGURATION (continued)

TERMINAL FUNCTIONS

TERMINAL

NAME NO.

CH. 1, INPUT A 1 I Video Input Channel 1, Input A CH. 2, INPUT A 2 I Video Input Channel 2, Input A CH. 3, INPUT A 3 I Video Input Channel 3, Input A H-SYNC, INPUT A 4 I Horizontal Sync, Input A V-SYNC, INPUT A 5 I Vertical Sync, Input A CH. 1, INPUT B 7 I Video Input Channel 1, Input B CH. 2, INPUT B 8 I Video Input Channel 2, Input B CH. 3, INPUT B 9 I Video Input Channel 3, Input B H-SYNC, INPUT B 10 I Horizontal Sync, Input B V-SYNC, INPUT B 11 I Vertical Sync, Input B

I2C, A1

I2C, A0

SDA 19 I/O

SCL 20 I

PUC 21 I high) to set buffer outputs to OFF and monitor outputs ON with ac-bias configuration on Channels 1 to 3

MUX MODE 15 I

MUX Select 16 I

CH. 1, BUFFER OUTPUT 35, 36 O

CH. 2, BUFFER OUTPUT 31, 32 O

CH. 3, BUFFER OUTPUT 27, 28 O H-SYNC BUFFER

OUTPUT V-SYNC BUFFER

OUTPUT CH. 1, SAG 45 O CH. 1, OUTPUT 46 O Video Monitor Pass-Through Output Channel 1 from either CH. 1, INPUT A or CH. 1, INPUT B. CH. 2, SAG 43 O CH. 2, OUTPUT 44 O Video Monitor Pass-Through Output Channel 2 from either CH. 2, INPUT A or CH. 2, INPUT B. CH. 3, SAG 41 O CH. 3, OUTPUT 42 O Video Monitor Pass-Through Output Channel 3 from either CH. 3, INPUT A or CH. 3, INPUT B.

H-SYNC MONITOR OUTPUT

V-SYNC MONITOR OUTPUT

AGND I +VA 29, 33, 38, 48 I Analog Positive Power Supply Input pins. Connect to 2.7 V to 5 V. Must be equal to or greater than VDD.

VDD 22 I DGND 23 I

Schmitt Trigger Adjust 14 I

17 I

18 I

25 O Horizontal Sync Buffer Output. Connect to ADC/Scalar H-sync input.

24 O Vertical Sync Buffer Output. Connect to ADC/Scalar V-sync input.

40 O Horizontal Sync Monitor Pass-Through Output.

39 O Vertical Sync Monitor Pass-Through Output.

6, 12, 13, 26, Ground Reference pin for analog signals. Internally, these pins connect to DGND, although it is

30, 34, 37, 47 recommended to have the AGND and DGND connected to the proper signals for best results.

I/O DESCRIPTION

I2C Slave Address Control Bit A1. Connect to VDDfor a logic 1 preset value or GND for a logic 0 preset value.

I2C Slave Address Control Bit A0. Connect to VDDfor a logic 1 preset value or GND for a logic 0 preset value.

Serial data line of the I2C bus. Pull-up resistor should have a minimum value = 2 k Ω and a maximum value = 19 k Ω . Pull up to VDD.

I2C bus clock line. Pull-up resistor should have a minimum value = 2 k Ω and a maximum value = 19 -k Ω . Pull up to VDD.

Power-Up Condition. Connect to GND for all channels disabled upon power-up. Connect to VDD(logic and both H-Sync/V-Sync enabled.

Sets the MUX configuration control. Connect to logic low for MUX Select (pin 16) control of the MUX. Connect to logic high for I2C control of the MUX.

Controls the MUX selection when MUX MODE (pin 15) is set to logic low. Connect to logic low for MUX selector set to Input A. Connect to logic high for MUX selector set to Input B.

Output Channel 1 from either CH. 1, INPUT A or CH. 1, INPUT B. Connect to ADC/Scalar/Decoder. Both pins should be connected together on the PCB.

Output Channel 2 from either CH. 2, INPUT A or CH. 2, INPUT B. Connect to ADC/Scalar/Decoder. Both pins should be connected together on the PCB.

Output Channel 3 from either CH. 3, INPUT A or CH. 3, INPUT B. Connect to ADC/Scalar/Decoder. Both pins should be connected together on the PCB.

Video Monitor Pass-Through Output Channel 1 SAG Correction pin. If SAG is not used, connect Directly to CH. 1, OUTPUT pin 46.

Video Monitor Pass-Through Output Channel 2 SAG Correction pin. If SAG is not used, connect Directly to CH. 2, OUTPUT pin 44.

Video Monitor Pass-Through Output Channel 3 SAG Correction pin. If SAG is not used, connect Directly to CH. 3, OUTPUT pin 42.

Digital Positive Supply pin for I2C circuitry and H-Sync/V-Sync outputs. Connect to 2.7 V to 5 V. Digital GND pin for HV circuitry and I2C circuitry.

Defaults to 1.45 V (TTL compatible). Connect to external voltage reference to adjust H-Sync/V-Sync input thresholds from 0.9 V to 2 V range.

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APPLICATIONS INFORMATION

The THS7347 is targeted for RGB+HV video buffer applications. Although it can be used for numerous other applications, the needs and requirements of the video signal were the most important design parameters of the THS7347. Built on the revolutionary complementary silicon-germanium (SiGe) BiCom3 process, the THS7347 incorporates many features not typically found in integrated video parts while consuming very low power. Each channel configuration is completely independent of the other channels. This architecture allows for any configuration for each channel to be dictated by the end user, rather than the part dictating what the configuration must be—resulting in a highly flexible system.

The THS7347 has the following features:

• I2C interface for easy interfacing to the system.

• Single-supply 2.7-V to 5-V operation with low quiescent current of 80 mA at 3.3 V.

• 2:1 input mux.

• Input configuration accepts dc, dc + shift, ac bias, or ac sync-tip clamp selection.

• 500-MHz unity-gain buffer amplifier to drive ADC/Scalar/Decoder.

• Monitor Pass-Through path has an internal fixed gain of 2 V/V (+6 dB) amplifier that can drive two video lines

per channel with dc coupling, traditional ac coupling, or SAG-corrected ac coupling.

• While disabled, the Monitor Pass-Through path has a very high output impedance (> 500 k Ω || 8 pF)

• Power-Up Control (PUC) allows the THS7347 to be fully disabled or have the Monitor Pass-Through function

(with ac-bias mode on all channels) enabled upon initial device power-up.

• Mux is controlled by either I2C or a general-purpose input/output (GPIO) pin, based on the MUX Mode pin logic.

• H-Sync and V-Sync paths have an externally-adjustable Schmitt trigger threshold

• Disable mode reduces quiescent current to as low as 0.1- µ A.

OPERATING VOLTAGE

The THS7347 is designed to operate from 2.7 V to 5 V over a -40 ° C to +85 ° C temperature range. The impact on performance over the entire temperature range is negligible because of the implementation of thin film resistors and high-quality, low temperature coefficient capacitors.

A 0.1- µ F to 0.01- µ F capacitor should be placed as close as possible to the power-supply pins. Failure to do so may result in the THS7347 outputs ringing or oscillating. Additionally, a large capacitor, such as 100 µ F, should be placed on the power-supply line to minimize issues with 50-Hz/60-Hz line frequencies.

INPUT VOLTAGE

The THS7347 input range allows for an input signal range from ground to approximately (V because of the internal fixed gain of 2 V/V (+6 dB), the output is generally the limiting factor for the allowable linear input range. For example, with a 5-V supply, the linear input range is from GND to 3.4 V. As a result of the gain, the linear output range limits the allowable linear input range from GND to 2.5 V at most.

+ – 1.6 V). However,

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External

Input/

Output

Internal

Circuitry

S+

THS7347

SLOS531 – MAY 2007

APPLICATIONS INFORMATION (continued)

INPUT OVERVOLTAGE PROTECTION

The THS7347 is built using a very high-speed complementary bipolar and CMOS process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All input and output device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 3 .

Figure 3. Internal ESD Protection

These diodes provide moderate protection to input overdrive voltages above and below the supplies. The protection diodes can typically support 30 mA of continuous current when overdriven.

TYPICAL CONFIGURATION

A typical application circuit usng the THS7347 as an ac-coupled input video buffer is shown in Figure 4 . It shows the THS7347 driving a video ADC (such as the TVP7000 ) with 0-dB gain and also driving an output line with 6-dB gain. The Horizontal and Vertical Sync signals are also driven to the ADC and the Monitor Output separately. Although the computer resolution R’G’B’HV signals are shown, these channels can easily be the high-definition video (HD), enhanced-definition (ED), or standard-definition (SD) Y’P’BP’R(sometimes labeled Y’U’V’ or incorrectly labeled Y’C’BC’R) channels. These channels could also be S-Video Y’/C’ channels and the composite video baseband signal (CVBS). Note that the R’G’B’ channels could be professional/broadcast G’B’R’ signals or other R’G’B’ variations based on the placement of the sync signals that are commonly called R’G’sB’ (sync on Green) or R’sG’sB’s (sync on all signals).

The second set of inputs (B-Channels) shown are connected to another set of inputs. Again, these inputs can be either HD, ED, SD, or R'G'B'/G'B'R' video signals. The THS7347 flexibility allows for virtually any input signal to be driven into the THS7347 regardless of the other set of inputs. Simple control of the I2C configures the THS7347 for any conceivable combination. For example, the THS7347 can be configured to have Channel 1 Input connected to input A while Channel 2 and Channel 3 are connected to input B. See the multiple application notes sections explaining the I2C interface later in this document for details on configuring these options.

Note that the Y' term is used for the luma channels throughout this document, rather than the more common luminance (Y) term. The reason for this usage is to account for the true definition of luminance as stipulated by the CIE (International Commission on Illumination). Video departs from true luminance because a nonlinear term, gamma, is added to the true RGB signals to form R'G'B' signals. These R'G'B' signals are then utilized to mathematically create luma (Y'). Therefore, true luminance (Y) is not maintained, and thus the difference in terminology arises.

This rationale is also utilized for the chroma (C') term. Chroma is derived from the nonlinear R'G'B' terms and therefore it is also nonlinear. True chominance (C) is derived from linear RGB, and thus the difference between chroma (C') and chrominance (C) exists. The color difference signals (P' to denote the nonlinear (gamma-corrected) signals.

/ P'

/U'/V') are also referenced this way

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75 W

Red

Green

Blue

75 W

5 W

75 W

5 W

75 W

Monitor Output

+3.3V +1.8V

1 2

3 4

5 6

8 9

10 11

13 14 15 16 17 18 19 20 21 22 23 24

36 35

34 33

32 31

30 29

28 27

26 25

48 47 46 45 44 43 42 41 40 39 38 37

3.3V3.3V

I C

2.2 mF

0.1 mF

1.4kW

806 W

100

22 pF

INPUT2

INPUT1

V =3.3Vto5V

0.1 Fm

H-Syncand

V-Sync

NotUsed

P’

Y’

P’

Y’

Component

480i

576i 480p 576p 720p

1080i

1080p

G’B’R’

H-Sync

V-Sync

806 W

1.4kW

75 W

2.2 mF

0.1 Fm

ADC

Scalar/

Decoder

THS7347

SLOS531 – MAY 2007

APPLICATIONS INFORMATION (continued)

R'G'B' (commonly labeled RGB) is also called G'B'R' (again commonly labeled as GBR) in professional video systems. The SMPTE component standard stipulates that the luma information is placed on the first channel, the blue color difference is placed on the second channel, and the red color difference signal is placed on the third channel. This approach is consistent with the Y'P' sync information and the green channel (G') also carries the sync information, it makes logical sense that G' be placed first in the system. Since the blue color difference channel (P' channel (P'

) is last, then it also makes logical sense to place the B' signal on the second channel and the R'

signal on the third channel, respectively. Thus, hardware compatibility is better achieved when using G'B'R' rather than R'G'B'. Note that for many G'B'R' systems, sync is embedded on all three channels; this configuration may not always be the case for all systems.

nomenclature. Because the luma channel (Y') carries the

BP'R

) is next and the red color difference

AC-Coupled Inputs and DC-Coupled Output Configuration

BP'R

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(1) Inputs and/or outputs can be ac- or dc-coupled if desired. (2) H-Sync and V-Sync input resistance as shown above = 2.2k Ω , but may be changed to any desired resistance. (3) If the Monitor or Buffer PCB trace is >25 mm, it is recommended to place at least a 10- Ω resistor in series with each

signal to reduce PCB parasitic issues

Figure 4. Typical R'G'B'HV and Y'P'

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Start

Condition

Stop

Condition

SDA

SCL

THS7347

SLOS531 – MAY 2007

APPLICATIONS INFORMATION (continued)

I2C INTERFACE NOTES

The I2C interface is used to access the internal registers of the THS7347. I2C is a two-wire serial interface developed by Philips Semiconductor (see the I2C Bus Specification, Version 2.1, January 2000 ). The THS7347 was designed in compliance with version 2.1 specifications. The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through open-drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The THS7347 works as a slave and supports the standard mode transfer (100 kbps) and fast mode transfer (400 kbps) as defined in the I2C Bus Specification. The THS7347 has been tested to be fully functional with the high-speed mode (3.4 Mbps) but it is not specified at this time.

Figure 5 shows the basic I2C start and stop access cycles.

The basic access cycle consists of the following:

• A start condition

• A slave address cycle

• Any number of data cycles

• A stop condition

Figure 5. I2C Start and Stop Conditions

GENERAL I2C PROTOCOL

• The master initiates data transfer by generating a start condition. The start condition exists when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 5 . All I2C-compatible devices should recognize a start condition.

• The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit R/ W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 6 ). All devices recognize the address sent by the master and compare it to the respective internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 7 ) by pulling the SDA line low during the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a communication link with a slave has been established.

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SCL

SDA

DataLine

Stable;

DataValid

ChangeofData Allowed

Start

Condition

ClockPulsefor

Acknowledgement

Acknowledge

Not Acknowledge

DataOutput byReceiver

DataOutput

byTransmitter

SCL From

Master

1 2

8 9

SCL

SDA

MSB

Slave Address Data

Stop

1 2 3 4 5 6 7 8 99 1 2 3 4 5 6 7 8 9

Acknowledge Acknowledge

APPLICATIONS INFORMATION (continued)

Figure 6. I2C Bit Transfer

THS7347

SLOS531 – MAY 2007

Figure 7. I2C Acknowledge

• The master generates further SCL cycles to either transmit data to the slave (R/ W bit 1) or receive data from the slave (R/ W bit 0). In either case, the receiver must acknowledge the data sent by the transmitter. So, an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary (see Figure 8 ).

Figure 8. I2C Address and Data Cycles

• To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 5 ). This transaction releases the bus and stops the communication link with the addressed slave. All I2C-compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start

condition followed by a matching address.

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A =No Acknowledge(SDA High) A = Acknowledge S=StartCondition P =StopCondition W=Write R=Read

A A PDATA DATA

S Slave Address

FromTransmitter

FromReceiver

ACK

Acknowledge

(FromReceiver)

ICDevice Addressand

Read/WriteBit

R/W D7

D6 D0 D0

ACK

Stop

Condition

Acknowledge

(Receiver)

LastDataByte

SDA

D1 D1

FirstData

Byte

Start

Condition

Acknowledge

(Transmitter)

ACK

Other

DataBytes

A =No Acknowledge(SDA High) A = Acknowledge S=StartCondition P =StopCondition W=Write R=Read

A A PDATA DATA

S Slave Address

Transmitter

Receiver

A62A0

ACK

Acknowledge

(From

Receiver)

ICDevice Addressand

Read/WriteBit

R/W D7

ACK

Stop

Condition

Acknowledge

(From

Transmitter)

LastDataByte

SDA

ACK

FirstData

Byte

Start

Condition

Not

Acknowledge

(Transmitter)

Other

DataBytes

THS7347

SLOS531 – MAY 2007

APPLICATIONS INFORMATION (continued)

During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle, so that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting device after the last byte is transferred. Figure 9 and Figure 10 show an example of a write cycle. Note that the THS7347 does not allow multiple write transfers to occur. See the example, Writing to the THS7347, in

Section 12 for more information.

Figure 9. I2C Write Cycle

Figure 10. Multiple Byte Write Transfer

During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its address. Following this initial acknowledge by the slave, the master device becomes a receiver and acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from the slave, the not acknowledge ( A) condition is initiated by the master by keeping the SDA signal high just before it asserts the stop (P) condition. This sequence terminates a read cycle, as shown in Figure 11 and

Figure 12 . Note that the THS7347 does not allow multiple read transfers to occur. See the example, Reading

from the THS7347, in Section 12 for more information.

Figure 11. I2C Read Cycle

Figure 12. Multiple Byte Read Transfer

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APPLICATIONS INFORMATION (continued)

Slave Address

Both the SDA and the SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors should range from 2 k Ω to 19 k Ω in order to comply with the I2C specification. When the bus is free, both lines are high. The address byte is the first byte received following the START condition from the master device. The first five bits (MSBs) of the address are factory-preset to 01011. The next two bits of the THS7347 address are controlled by the logic levels appearing on the I2C, A1 and I2C, A0 pins. The I2C, A1 and I2C, A0 address inputs can be connected to V address is set by the state of these pins and is not latched. Thus, a dynamic address control system could be used to incorporate several devices on the same system. Up to four THS7347 devices can be connected to the same I2C bus without requiring additional glue logic. Table 1 lists the possible addresses for the THS7347.

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 (A1) Bit 1 (A0) Bit 0 (R/ W)

0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 1 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 0 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1 0 0 1 0 1 1 1 1 1

for logic 1, GND for logic 0, or actively driven by TTL/CMOS logic levels. The device

Table 1. THS7347 Slave Addresses

FIXED ADDRESS ADDRESS PINS BIT

SELECTABLE WITH READ/WRITE

Channel Selection Register Description (Subaddress) and Power-Up Condition (PUC) Pin

The THS7347 operates using only a single-byte transfer protocol similar to that illustrated in Figure 9 and

Figure 11 . The internal subaddress registers and the functionality of each are given in Table 2 . When writing to

the device, it is required to send one byte of data to the corresponding internal subaddress. If control of all three channels is desired, then the master must cycle through all the subaddresses (channels) one at a time; see the example, Writing to the THS7347 (in Section 12 ) for the proper procedure of writing to the THS7347.

During a read cycle, the THS7347 sends the data in its selected subaddress (or channel) in a single transfer to the master device requesting the information. See the Reading from the THS7347 example (in Section 12 ) for the proper procedure on reading from the THS7347.

On power-up, the THS7347 registers are dictated by the Power-Up Control (PUC) pin. If the PUC pin is tied to GND, the THS7347 powers up in a fully disabled state. If the PUC pin is tied to VDD, upon power-up the THS7347 is configured in the following state: ADC buffers disabled, monitor pass-through enabled, and ac-bias on, for all three input channels. It remains in the state dictated by the PUC unti a valid write sequence is completed.

Table 2. THS7347 Channel Selection Register Bit Assignments

Channel 1 0000 0001 Channel 2 0000 0010 Channel 3 0000 0011

Channel H Sync, Channel V Sync, and

Disable Controls

BIT ADDRESS

0000 0100

)

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Channel Register Bit Descriptions

Each bit of the subaddress (channel selection) control register as described in the previous section allows the user to individually control the THS7347 functionality. This process allows the user to control the functionality of each channel independently with regard to the other channels. The bit description for Channel 1 through Channel 3 is shown in Table 3 , while the H/V sync channels and the analog channel states are described in

Table 4 .

Table 3. THS7347 Channel Register (Channel 1 through Channel 3) Bit Decoder Table.

Use with Register Bit Codes (0000 0001), (0000 0010), and (0000 0011)

BIT FUNCTION BIT VALUE(S) RESULT

(MSB)

6, 5, 4, 3 MUX Selection

2, 1, 0

(LSB)

Sync-Tip Clamp Filter

Input Mode

Operation

0 500-kHz filter on the STC circuit

1 5-MHz filter on the STC circuit 0 0 0 0 MUX Input A 0 0 0 1 MUX Input A 0 0 1 0 MUX Input A 0 0 1 1 MUX Input A 0 1 0 0 MUX Input A 0 1 0 1 MUX Input B 0 1 1 0 MUX Input B 0 1 1 1 MUX Input B 1 0 0 0 MUX Input B 1 0 0 1 MUX Input B 1 0 1 0 Reserved; do not care 1 0 1 1 Reserved; do not care 1 1 0 0 Reserved; do not care 1 1 0 1 Reserved; do not care 1 1 1 0 Reserved; do not care 1 1 1 1 Reserved; do not care

0 0 0 Disables both monitor and buffer paths of the respective

channel/register 0 0 1 Channel Mute 0 1 0 Input Mode = dc 0 1 1 Input Mode = dc + Shift 1 0 0 Input Mode = ac-bias 1 0 1 Input Mode = ac-STC with low bias 1 1 0 Input Mode = ac-STC with mid bias 1 1 1 Input Mode = ac-STC with high bias

Bit 7 (MSB): Controls the sync-tip clamp filter. Useful only when AC-STC input mode is selected. Bits 6, 5, 4, 3: Selects the Input MUX channel. Bits 2, 1, and 0 (LSB): Configures the channel mode and operation. See Table 4 , Bits 6 and 5, for more

information with respect to the enable/disable state.

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Table 4. THS7347 Channel Register (H/V Sync Channel + Analog Channels State) Bit Decoder Table.

Use in Conjunction With Register Bit Code (0000 0100)

BIT FUNCTION VALUE(S) RESULT

(MSB)

6 Mode

4, 3 Vertical Sync Channel MUX Selection

2, 1 Horizontal Sync Channel MUX Selection

(LSB)

Reserved; Do not care X Reserved; do not care

Monitor Pass-Through Path Disable

(Use in Conjunction with Table 3 )

Buffer Path Disable Mode

(Use in Conjunction with Table 3 )

H/V Sync Paths Disable Mode

BIT

0 Disables all monitor channels regardless of bits 2:0 of Register 1

through Register 3

1 Enables monitor channels functions dictated by each programmed

0 Disables all buffer channels regardless of bits 2:0 of Register 1

through Register 3

1 Enables buffer channel functions dictated by each programmed

register code 0 0 MUX Input A 0 1 MUX Input B 1 0 Reserved; do not care 1 1 Reserved; do not care 0 0 MUX Input A 0 1 MUX Input B 1 0 Reserved; do not care 1 1 Reserved; do not care

0 Disable H-Sync and V-Sync Channels 1 Enable H-Sync and V-Sync Channels

THS7347

SLOS531 – MAY 2007

Bit (MSB) 7: Reserved; do not care. Bit 6: Master Monitor Path Disable. Disables all monitor channels regardless of what is programmed into

each register channel (1 to 3). Bit 5: Master Buffer Path Disable. Disables all buffer channels regardless of what is programmed into each

Bits 4, 3: Selects the Input MUX channel for the Vertical Sync. Bits 2, 1: Selects the Input MUX channel for the Horizontal Sync. Bit 0 (LSB): Enables or disables the H-Sync and V-Sync Channels.

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WRITE AND READ EXAMPLES

These examples illustrate the proper way to write to and read from the THS7347.

WRITING TO THE THS7347

An I2C master initiates a write operation to the THS7347 by generating a start condition (S) followed by the THS7347 I2C address, in MSB-first order, followed by a '0' to indicate a write cycle. After receiving an acknowledge from the THS7347, the master presents the subaddress (channel) it wants to write, consisting of one byte of data, MSB first. The THS7347 acknowledges the byte after completion of the transfer. Finally, the master presents the data it wants to write to the register (channel) and the THS7347 acknowledges the byte. The I2C master then terminates the write operation by generating a stop condition (P). Note that the THS7347 does not support multi-byte transfers. To write to all three channels (or registers), this procedure must be repeated for each register, one series at a time (that is, repeat steps 1 through 8 for each channel).

Step 1 0 I2C Start (Master) S

Step 2 7 6 5 4 3 2 1 0 I2C General Address (Master) 0 1 0 1 1 X X 0

Where each X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either V

Step 3 9 I2C Acknowledge (Slave) A

Step 4 7 6 5 4 3 2 1 0 I2C Write Channel Address (Master) 0 0 0 0 0 Addr Addr Addr

or GND.

Where Addr is determined by the values shown in Table 2 .

Step 5 9 I2C Acknowledge (Slave) A

Step 6 7 6 5 4 3 2 1 0 I2C Write Data (Master) Data Data Data Data Data Data Data Data

Where Data is determined by the values shown in Table 3 .

Step 7 9 I2C Acknowledge (Slave) A

Step 8 0 I2C Stop (Master) P

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READING FROM THE THS7347

The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master initiates a write operation to the THS7347 by generating a start condition (S) followed by the THS7347 I2C address, in MSB-first order, followed by a '0' to indicate a write cycle. After receiving an acknowledge from the THS7347, the master presents the subaddress (channel) of the register it wants to read. After the cycle is acknowledged (A), the master terminates the cycle immediately by generating a stop condition (P).

The second phase is the data phase. In this phase, an I2C master initiates a read operation to the THS7347 by generating a start condition followed by the THS7347 I2C address, in MSB-first order, followed by a '1' to indicate a read cycle. After an acknowledge from the THS7347, the I2C master receives one byte of data from the THS7347. After the data byte has been transferred from the THS7347 to the master, the master generates a not-acknowledge ( A) followed by a stop. As with the Write function, to read all channels, steps 1 through 11 must be repeated for each channel desired.

THS7347 Read Phase 1:

Step 1 0

I2C Start (Master) S Step 2 7 6 5 4 3 2 1 0

I2C General Address (Master) 0 1 0 1 1 X X 0

Where each X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either V

Step 3 9 I2C Acknowledge (Slave) A

Step 4 7 6 5 4 3 2 1 0 I2C Read Channel Address (Master) 0 0 0 0 0 Addr Addr Addr

or GND.

Where Addr is determined by the values shown in Table 2 .

Step 5 9 I2C Acknowledge (Slave) A

Step 6 0 I2C Start (Master) P

THS7347 Read Phase 2:

Step 7 0

I2C Start (Master) S Step 8 7 6 5 4 3 2 1 0

I2C General Address (Master) 0 1 0 1 1 X X 1

Where each X Logic state is defined by I2C-A1 and I2C-A0 pins being tied to either V

Step 9 9 I2C Acknowledge (Slave) A

or GND.

Step 10 7 6 5 4 3 2 1 0 I2C Read Data (Slave) Data Data Data Data Data Data Data Data

Where Data is determined by the logic values contained in the Channel Register.

Step 11 9 I2C Not-Acknowledge (Master) A

Step 12 0 I2C Stop (Master) P

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PACKAGE OPTION ADDENDUM

www.ti.com

29-May-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

THS7347IPHP ACTIVE HTQFP PHP 48 250 Green (RoHS &

no Sb/Br)

THS7347IPHPR ACTIVE HTQFP PHP 48 1000 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-3-260C-168 HR

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-May-2007

TAPE AND REEL INFORMATION

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

Device Package Pins Site Reel

Diameter

(mm)

THS7347IPHPR PHP 48 TAI 330 16 9.6 9.6 1.5 12 16 Q2

Reel

Width

(mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

26-May-2007

Pin1

Quadrant

TAPE AND REEL BOX INFORMATION

Device Package Pins Site Length (mm) Width (mm) Height (mm)

THS7347IPHPR PHP 48 TAI 346.0 346.0 33.0

Pack Materials-Page 2

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Datasheet THS 7347 Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES APPLICATIONS

DESCRIPTION

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DESCRIPTION, CONTINUED

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS

RECOMMENDED OPERATING CONDITIONS

TIMING REQUIREMENTS FOR I2C INTERFACE

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

APPLICATIONS INFORMATION

OPERATING VOLTAGE

INPUT VOLTAGE

INPUT OVERVOLTAGE PROTECTION

TYPICAL CONFIGURATION

I2C INTERFACE NOTES

GENERAL I2C PROTOCOL

Slave Address

Channel Selection Register Description (Subaddress) and Power-Up Condition (PUC) Pin

Channel Register Bit Descriptions

WRITE AND READ EXAMPLES

WRITING TO THE THS7347

READING FROM THE THS7347