TEXAS INSTRUMENTS THS6042, THS6043 Technical data

查询THS6042CDDA供应商

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

D Remote Terminal ADSL Line Driver

– Ideal for Both Full Rate ADSL and G.Lite
– Compatible With 1:1 Transformer Ratio

D Low 2.1 pA/√Hz Noninverting Current Noise

– Reduces Noise Feedback Through

Hybrid Into Downstream Channel

D Wide Supply Voltage Range ±5 V to ±15 V

– Ideal for ±12-V Operation

D Wide Output Swing

– 43-Vpp Differential Output Voltage,

R

= 200 Ω, ±12-V Supply

L

D High Output Current

– 350 mA (typ)

THS6042

V

CC–

SOIC (D) AND

(TOP VIEW)

1
2
3
4

8
7
6
5

V

CC+

D2 OUT
D2 IN–
D2 IN+

SOIC PowerPAD (DDA) PACKAGE

D1 OUT

D1 IN–
D1 IN+

D High Speed

– 120 MHz (–3 dB, G=1, ±12 V, R
– 1200 V/µs Slew Rate (G = 4, ±12 V)

= 25 Ω)

L

D Low Distortion, Single-Ended, G = 4

– –79 dBc (250 kHz, 2 V

, 100-Ω load)

pp

D Low Power Shutdown (THS6043)

– 300-µA Total Standby Current

D Thermal Shutdown and Short-Circuit

Protection

D Standard SOIC, SOIC PowerP AD  and

TSSOP PowerP AD Package

D Evaluation Module Available

THS6043

V

CC–

N/C

GND

N/C

SOIC (D) AND

(TOP VIEW)

1

14

2

13

3

12

4

11

5

10
6
7

9
8

V

CC+

D2 OUT
D2 IN–
D2 IN+
N/C
SHUTDOWN
N/C

TSSOP PowerPAD (PWP) PACKAGE

D1 OUT

D1 IN–
D1 IN+

description

The THS6042/3 is a high-speed line driver ideal for driving signals from the remote terminal to the central office
in asymmetrical digital subscriber line (ADSL) applications. It can operate from a ±12-V supply voltage while
drawing only 8.2 mA of supply current per channel. It offers low –79 dBc total harmonic distortion driving a 100-Ω
load (2 Vpp). The THS6042/3 offers a high 43-Vpp differential output swing across a 200-Ω load from a ±12-V
supply. The THS6043 features a low-power shutdown mode, consuming only 300 µA quiescent current per
channel. The THS6042/3 is packaged in standard SOIC, SOIC PowerP AD, and TSSOP PowerP AD packages.

+12 V

210 Ω

0.68 µF

THS6042

Driver 1

VI+

VI–

+
_

750 Ω

THS6042

Driver 2

+
_

–12 V

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

750 Ω

50 Ω

50 Ω

1:1

15.7 dBm
Delivered

to Telephone

Line

100 Ω

DEVICE

THS6052/3
THS6092/3
OPA2677
THS6062

OPA2822

RELATED PRODUCTS

DESCRIPTION

175-mA, ±12 ADSL CPE line driver

275-mA, +12 V ADSL CPE line driver

380-mA, +12 V ADSL CPE line driver

±15 V to ± 5 V Low noise ADSL receiver
±6 V to 5 V Low noise ADSL receiver

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2001, Texas Instruments Incorporated

1

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

AVAILABLE OPTIONS

PACKAGED DEVICE

T

A

0°C to 70°C THS6042CD THS6042CDDA THS6043CD THS6043CPWP

–40°C to 85°C THS6042ID THS6042IDDA THS6043ID THS6043IPWP —

SOIC-8

(D)

SOIC-8 PowerPAD

(DDA)

SOIC-14

(D)

TSSOP-14

(PWP)

EVALUATION

MODULES

THS6042EVM
THS6043EVM

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, V
Input voltage ± V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC+

to V

33 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC–

†

CC

Output current (see Note 1) 450 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Differential input voltage ± 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum junction temperature 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Total power dissipation at (or below) 25°C free-air temperature See Dissipation Ratings Table. . . . . . . . . . .

Operating free-air temperature, T

: Commercial 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

Industrial –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature, T

: Commercial –65°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Industrial –65°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The THS6042 and THS6043 may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected

to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPAD
thermally enhanced package.

DISSIPATION RATING TABLE

TA = 25°C

PACKAGE

D-8 95°C/W
DDA 45.8°C/W
D-14 66.6°C/W
PWP 37.5°C/W 1.4°C/W 3.3 W

‡

This data was taken using the JEDEC proposed high-K test PCB. For the JEDEC low-K test
PCB, the ΘJA is168°C/W for the D–8 package and 122.3°C/W for the D–14 package.

θ

JA

‡
‡
‡

θ

JC

38.3°C/W

9.2°C/W

26.9°C/W

‡
‡
‡

TJ = 150°C

POWER RATING

1.32 W

2.73 W

1.88 W

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS6042, THS6043

L

CC

(–3 dB)

R

L

Ω

V

5 V

()

G = 4, R

F

750 Ω

µ

R

100 Ω

G 4, R

L

100 Ω,

(

)

(R

F

390 Ω)

G 4,

R

L

Ω,

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

Operating free-air temperature, T

CC+

to V

CC–

A

electrical characteristics over recommended operating free-air temperature range, TA = 25°C,
V

= ±12 V, R

CC

(FEEDBACK)

dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Small-signal bandwidth

BW

SR Slew rate (see Note 2)

NOTE 2: Slew rate is defined from the 25% to the 75% output levels.

–

= 750 Ω, RL = 100 Ω (unless otherwise noted)

RL = 25 Ω

RL = 100 Ω

RL = 25 Ω

25

=

L

Dual supply ±5 ±15
Single supply 10 30
C-suffix 0 70
I-suffix –40 85

G = 1, RF = 560 Ω 120
G = 2, RF = 500 Ω
G = 4, RF = 390 Ω
G = 4, RF = 390 Ω
G = 8, RF = 280 Ω

G = 2, RF = 390 Ω,

=

O

pp

pp

G = 4, R
VO = 12 V

G = 4, RF = 750 Ω,
VO = 5 V

= 750 Ω,

=

pp

pp

VCC = ±6 V, ±12 V

VCC = ±6 V, ±12 V

VCC = ±15 V 1000
VCC = ±12 V 900
VCC = ±6 V 600

,

VCC = ±15 V 1400
VCC = ±12 V 1200

VCC = ±6 V 600

95
75

100

65

MHz

V/µs

V

°C

noise/distortion performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Total harmonic distortion

THD

V

I

n

single-ended configuration

(RF = 390 Ω)

=

Input voltage noise VCC = ±6 V, ±12 V f = 10 kHz 2.2 nV/√Hz

n

Input current noise

Crosstalk

+Input
–Input

V

= 2 V –79

G = 4, RL = 100 Ω,
VCC = ±12 V, f = 250 kHz

G = 4, RL = 25 Ω,
VCC = ±6 V, f = 250 kHz

VCC = ±6 V, ±12 V, ±15 V f = 10 kHz
f = 250 kHz , VCC = ±6 V, ±12 V,

RF = 430 Ω, RL = 100 Ω
f = 250 kHz , VCC = ±6 V, ±12 V,

RF = 390 Ω, RL = 25 Ω

25

O(pp)

V

= 16 V –75

O(pp)

V

= 2 V –72

O(pp)

V

= 7 V –68

O(pp)

VO = 2 Vpp, G = 4

2.1
11

–71

–65

dBc

pA/√Hz

dBc

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

THS6042, THS6043

V

OS

V

CC

±12 V

Single ended

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

electrical characteristics over recommended operating free-air temperature range, TA = 25°C,

= ±12 V, R

V

CC

(FEEDBACK)

dc performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input offset voltage

V

OS

I

IB

Z

OL

Differential offset voltage
Offset drift TA = full range 20 µV/°C

– Input bias current

+ Input bias current VCC = ±6 V, ±12 V

Differential input bias current
Open-loop transimpedance RL = 1 kΩ VCC = ±6 V, ±12 V 1 MΩ

input characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

ICR

CMRR Common-mode rejection ratio VCC = ±6 V, ±12 V

R

I

C

i

Input common-mode voltage range

Input resistance
Input capacitance 2 pF

output characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

I
I

r

O

O
OS

o

Output voltage swing

Output current
Short-circuit current RL = 0 Ω, VCC = ±12 V 400 mA

Output resistance Open loop 15

= 750 Ω, RL = 100 Ω (unless otherwise noted) (continued)

TA = 25°C 9.5 16
TA = full range 21
TA = 25°C 1 5
TA = full range 7

TA = 25°C 3.5 10
TA = full range 12
TA = 25°C 1 5
TA = full range 6
TA = 25°C 3.5 10
TA = full range 12

TA = 25°C ±9.6 ±10.1
TA = full range ±9.5
TA = 25°C ±3.7 ±4.2
TA = full range ±3.6
TA = 25°C 59 68
TA = full range 55

15 Ω

VCC = ±12 V ±7.5 ±9.1
VCC = ±6 V ±4.1 ±4.6
VCC = ±12 V ±10.3 ±10.8
VCC = ±6 V ±4.5 ±4.9

VCC = ±6 V 230 260

Single ended
100-mV overdrive

VCC = ±6 V, ±12 V

±6 V,

VCC = ±12 V

VCC = ±6V

+ Input 1.5 MΩ
– Input

RL = 25 Ω

RL = 100 Ω
RL = 25 Ω, VCC = ± 12 V 300 350

RL = 10 Ω,

mV

mA

µA

V

V

V

Ω

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

electrical characteristics over recommended operating free-air temperature range, TA = 25°C,

= ±12 V, R

V

CC

(FEEDBACK)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

CC

I

CC

PSRR Power supply rejection ratio

Operating range

Quiescent current (each driver)

shutdown characteristics (THS6043 only)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

IL(SHDN)

V

IH(SHDN)

I

CC(SHDN)

t

DIS

t

EN

I

IL(SHDN)

I

IH(SHDN)

NOTE 3: Disable/enable time is defined as the time from when the shutdown signal is applied to the SHDN pin to when the supply current has

Shutdown pin voltage for power up

Shutdown pin voltage for power down
Total quiescent current when in shutdown state VCC = ±6 V, ±12 V 0.3 0.7 mA

Disable time (see Note 3) VCC = ±12 V 0.5 µs
Enable time (see Note 3) VCC = ±12 V 0.2 µs
Shutdown pin input bias current for power up VCC = ±6 V, ±12 V 40 100 µA

Shutdown pin input bias current for power down VCC = ±6 V, ±12 V V

reached half of its final value.

= 750 Ω, RL = 100 Ω (unless otherwise noted) (continued)

Dual supply ±4.5 ±16.5
Single supply

VCC = ±12 V

VCC = ±6 V

VCC = ±12 V

VCC = ±6 V

VCC = ±6 V, ±12 V, GND = 0 V
(GND Pin as Reference)

VCC = ±6 V, ±12 V, GND = 0 V
(GND pin as reference)

TA = 25°C 8.2 10.5
TA = full range 11.5
TA = 25°C 7.4 9.5
TA = full range 10.5
TA = 25°C –65 –72
TA = full range –62
TA = 25°C –62 –69
TA = full range –60

(SHDN)

= 3.3 V 50 100 µA

9 33

2 V

V

mA

dB

0.8 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

Table of Graphs

Small and large signal output vs Frequency 1 – 6

Harmonic distortion

Vn, InVoltage noise and current noise vs Frequency 19

Quiescent current vs Free-air temperature 20
V Positive output voltage headroom vs Free-air temperature 21
V Negative output voltage headroom vs Free-air temperature 22
V

O

z

o

V

IO

I

IB

CMRR Common-mode rejection ratio vs Frequency 28

SR Slew rate vs Output voltage step 30

Output voltage headroom vs Output current 23

Closed loop output impedance vs Frequency 24

Quiescent current in shutdown mode vs Free-air temperature 25

Input offset voltage and

differential input offset voltage

Input bias current vs Free-air temperature 27

Crosstalk vs Frequency 29

Shutdown response 31

Transimpedance and phase vs Frequency 32

Overdrive recovery 33, 34

Small and large signal pulse response 35, 36

FIGURE

vs Output voltage

vs Frequency

vs Free-air temperature 26

7, 8, 9

13, 14, 15

10, 11, 12,

16, 17, 18

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

THS6042, THS6043

24

)

PP

18

12

6

0

–6

–12

Small and Large Signal Output – dB(V

–18

–24

10 K 100 K

30

)

PP

24

18

12

SMALL AND LARGE SIGNAL OUTPUT

vs

FREQUENCY

VO = 8 V

VO = 2 V

VO = 0.5 V

VO = 0.125 V

PP

VCC = ±12 V
G = 4
Rf = 750 Ω
RL = 100 Ω

PP

PP

PP

1 M

f – Frequency – Hz

10 M 100 M

Figure 1

SMALL AND LARGE SIGNAL OUTPUT

vs

FREQUENCY

VO = 16 V

VO = 4 V

PP

PP

VCC = ±12 V
G = 8
Rf = 280 Ω
RL = 100 Ω

1 G

24

)

18

PP

12

6

0

–6

–12

–18

Small and Large Signal Output – dB(V

–24

10 K 100 K

30

)

24

PP

18

12

SMALL AND LARGE SIGNAL OUTPUT

vs

FREQUENCY

VO = 8 V

VO = 2 V

VO = 0.5 V

VO = 0.125 V

PP

VCC = ±12 V
G = 4
Rf = 390 Ω
RL = 100 Ω

PP

PP

PP

1 M

f – Frequency – Hz

10 M 100 M

Figure 2

SMALL AND LARGE SIGNAL OUTPUT

vs

FREQUENCY

VO = 16 V

VO = 4 V

PP

PP

VCC = ±12 V
G = 8
Rf = 750 Ω
RL = 100 Ω

1 G

6

0

–6

Small and Large Signal Output – dB(V

–12

–18

10 K 100 K

VO = 1 V

VO = 0.25 V

PP

PP

1 M

f – Frequency – Hz

10 M 100 M

Figure 3

6

VO = 1 V

0

–6

VO = 0.25 V

–12

Small and Large Signal Output – dB(V

1 G

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

–18

10 K 100 K

PP

PP

1 M

f – Frequency – Hz

Figure 4

10 M 100 M

1 G

7

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

24

)

18

PP

12

6

0

–6

–12

–18

Small and Large Signal Output – dB(V

–24

10 K 100 K

–70

SMALL AND LARGE SIGNAL OUTPUT

vs

FREQUENCY

VO = 8 V

VO = 2 V

VO = 0.5 V

VO = 0.125 V

PP

VCC = ±6 V
G = 4
Rf = 750 Ω
RL = 25 Ω

PP

PP

PP

1 M

f – Frequency – Hz

10 M 100 M

Figure 5

HARMONIC DISTORTION

vs

OUTPUT VOLTAGE

1 G

24

)

18

PP

12

6

0

–6

–12

–18

Small and Large Signal Output – dB(V

–24

10 K 100 K

–70

SMALL AND LARGE SIGNAL OUTPUT

vs

FREQUENCY

VO = 8 V

VO = 2 V

VO = 0.5 V

VO = 0.125 V

PP

VCC = ±6 V
G = 4
Rf = 390 Ω
RL = 25 Ω

PP

PP

PP

1 M

f – Frequency – Hz

10 M 100 M

Figure 6

HARMONIC DISTORTION

vs

OUTPUT VOLTAGE

1 G

–75

–80

–85

–90

Harmonic Distortion – dBc

–95

–100

0246810121416

2nd Order

VCC = ±15 V
Gain = 4
RL = 100 Ω
Rf = 390 Ω
f = 250 KHz

3rd Order

VO – Output Voltage – V

PP

Figure 7

Harmonic Distortion – dBc

–75

–80

–85

–90

–95

–100

0 2 4 6 8 10121416

2nd Order

VCC = ±10 V
Gain = 4
RL = 100 Ω
Rf = 390 Ω
f = 250 KHz

3rd Order

VO – Output Voltage – V

PP

Figure 8

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

THS6042, THS6043

HARMONIC DISTORTION

vs

OUTPUT VOLTAGE

–70

VCC = ±5.4 V
Gain = 4
RL = 100 Ω

–75

Rf = 390 Ω
f = 250 KHz

–80

–85

–90

Harmonic Distortion – dBc

–95

–100

01234567

VO – Output Voltage – V

2nd Order

3rd Order

PP

Figure 9

HARMONIC DISTORTION

vs

FREQUENCY

–30

VCC = ±10 V
Gain = 4
RL = 100 Ω

–40

–50

Rf = 390 Ω
VO = 2 V

PP

2nd Order

HARMONIC DISTORTION

vs

FREQUENCY

–30

VCC = ±15 V
Gain = 4
RL = 100 Ω

–40

Rf = 390 Ω
VO = 2 V

–50

–60

–70

–80

Harmonic Distortion – dBc

–90

–100

100 k 1 M 10 M 100 M

PP

f – Frequency – Hz

2nd Order

3rd Order

Figure 10

HARMONIC DISTORTION

vs

FREQUENCY

–30

VCC = ±5.4 V
Gain = 4
RL = 100 Ω

–40

–50

Rf = 390 Ω
VO = 2 V

PP

2nd Order

–60

–70

3rd Order

–80

Harmonic Distortion – dBc

–90

–100

100 k 1 M 10 M 100 M

f – Frequency – Hz

Figure 11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

–60

–70

3rd Order

–80

Harmonic Distortion – dBc

–90

–100

100 k 1 M 10 M 100 M

f – Frequency – Hz

Figure 12

9

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

HARMONIC DISTORTION

vs

OUTPUT VOLTAGE

–70

2nd Order

–75

–80

–85

–90

Harmonic Distortion – dBc

–95

–100

0 2 4 6 8 10 12 14

VO – Output Voltage – V

3rd Order

VCC = ±15 V
Gain = 4
RL = 25 Ω
Rf = 390 Ω
f = 250 KHz

Figure 13

HARMONIC DISTORTION

vs

OUTPUT VOLTAGE

–70

PP

HARMONIC DISTORTION

vs

OUTPUT VOLTAGE

–70

–75

–80

–85

–90

Harmonic Distortion – dBc

–95

–100

02468101214

2nd Order

VCC = ±10 V
Gain = 4
RL = 25 Ω
Rf = 390 Ω
f = 250 KHz

3rd Order

VO – Output Voltage – V

PP

Figure 14

HARMONIC DISTORTION

vs

FREQUENCY

–30

2nd Order

–75

–80

–85

–90

Harmonic Distortion – dBc

–95

–100

01234567

VO – Output Voltage – V

2nd Order

VCC = ±5.4 V
Gain = 4
RL = 25 Ω
Rf = 390 Ω
f = 250 KHz

3rd Order

PP

Figure 15

–40

–50

–60

3rd Order

–70

–80

Harmonic Distortion – dBc

–90

–100

100 k 1 M 10 M 100 M

f – Frequency – Hz

VCC = ±15 V
Gain = 4
RL = 25 Ω
Rf = 390 Ω
VO = 2 V

PP

Figure 16

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

THS6042, THS6043

HARMONIC DISTORTION

vs

FREQUENCY

–30

–40

–50

–60

–70

–80

Harmonic Distortion – dBc

–90

–100

100 k 1 M 10 M 100 M

2nd Order

3rd Order

f – Frequency – Hz

VCC = ±10 V
Gain = 4
RL = 25 Ω
Rf = 390 Ω
VO = 2 V

PP

Figure 17

VOLTAGE NOISE AND CURRENT NOISE

vs

FREQUENCY

100

VCC = ±5 V to ±15 V
TA = 25°C

HARMONIC DISTORTION

vs

FREQUENCY

–30

–40

–50

–60

–70

–80

Harmonic Distortion – dBc

–90

–100

100 k 1 M 10 M 100 M

2nd Order

3rd Order

f – Frequency – Hz

VCC = ±5.4 V
Gain = 4
RL = 25 Ω
Rf = 390 Ω
VO = 2 V

PP

Figure 18

QUIESCENT CURRENT

vs

FREE-AIR TEMPERATURE

10

Per Amplifier

9.5

Hz

nV/ Hz– Voltage Noise –V

10

– Current Noise – pA/

n

n

I

1

10 100 1 k 10 k 100 k

V

n

IN–

IN+

f – Frequency – Hz

Figure 19

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9

8.5

8

7.5

7

Quiescent Current – mA

6.5

6

5.5
–40 –20 0 20 40 60 80 100

VCC = ±12 V

VCC = ±6 V

TA – Free-Air Temperature – °C

Figure 20

11

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

POSITIVE OUTPUT VOLTAGE HEADROOM

vs

FREE-AIR TEMPERATURE

1.35

1.25

1.15

Positive Output Voltage Headroom – V

1.05

(+VCC – VO)

1.3

1.2

1.1

–40 –20 0 20 40 60 80 100

VCC = ±6 V, RL = 25 Ω

VCC = ±12 V, RL = 100 Ω

VCC = ±6 V, RL = 100 Ω

TA – Free-Air Temperature – °C

Figure 21

OUTPUT VOLTAGE HEADROOM

vs

OUTPUT CURRENT

4

| VCC | – | VO |
VCC = ±12 V and ±6 V

3.5

3

NEGATIVE OUTPUT VOLTAGE HEADROOM

vs

FREE-AIR TEMPERATURE

Negative Output Voltage Headroom – V

–1.05

–1.1

–1.15

–1.2

–1.25

–1.3

–1.35

(–VCC – VO)

VCC = ±6 V, RL = 100 Ω

VCC = ±12 V, RL = 100 Ω

VCC = ±6 V, RL = 25 Ω

–40 –20 0 20 40 60 80 100

TA – Free-Air Temperature – °C

Figure 22

CLOSED LOOP OUTPUT IMPEDANCE

vs

FREQUENCY

100

Ω

VCC = ± 5 V to ± 15 V
RL = 100 Ω
Rf = 750 Ω

10

Gain = 8

12

2.5

2

Output Voltage Headroom – | V |

1.5

1

0 100 200 300 400 500

IO – Output Current – | mA |

Figure 23

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Gain = 4

1

Gain = 2

0.1

– Closed Loop Output Impedance – Z

o

0.01
100 K 1 M 10 M 100 M 1 G

f – Frequency – Hz

Figure 24

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

THS6042, THS6043

QUIESCENT CURRENT IN SHUTDOWN MODE

vs

FREE-AIR TEMPERATURE

0.4

Aµ

Quiscent Current In Shutdown Mode –

Both Amplifiers

0.35

0.3

0.25

0.2

0.15
–40 –20 0 20 40 60 80 100

VCC = ± 12 V

VCC = ± 6 V

TA – Free-Air Temperature – °C

Figure 25

INPUT BIAS CURRENT

vs

FREE-AIR TEMPERATURE

5

VCC = ±6 V to ± 12 V

4.5

4

Aµ

3.5
3

2.5

I

IB–

INPUT OFFSET VOLTAGE AND

DIFFERENTIAL INPUT OFFSET VOLTAGE

vs

FREE-AIR TEMPERATURE

12

VCC = ± 6 V to ± 12 V

11

10

9

V

OS

– Input Offset Voltage – mV

IO

V

8

7

–40 –20 0 20 40 60 80 100

TA – Temperature – °C

Differential V

OS

Figure 26

COMMON-MODE REJECTION RATIO

vs

FREQUENCY

80

Gain = 2

70

60

50

Rf = 1 kΩ

VCC = +6 V
RL = 25 Ω

VCC = +12 V
RL = 100 Ω

0.5

0.4

0.3

0.2

0.1

0

Differential Input Offset Voltage – mV

2

– Input Bias Current –

1.5

IB

I

1

0.5
0

–40 –20 0 20 40 60 80 100

I

IB+

TA – Temperature – °C

Figure 27

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40

30

CMRR – Common-Mode Rejection Ratio – dB

20

10 k 100 k 1 M 10 M 100 M

f – Frequency – Hz

Figure 28

13

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

CROSSTALK

vs

FREQUENCY

0

VCC = ±6 V to ±12 V
Gain = 4

–10

–20

–30

–40

–50

Crosstalk – dB

–60

–70

–80
–90

100 k 1 M 10 M 100 M

f – Frequency – Hz

Rf = 390 Ω

RL = 25 Ω

Rf = 430 Ω

RL = 100 Ω

Figure 29 Figure 30

SHUTDOWN RESPONSE

7

6

5

4

V

(SHDN)

3

1

–1

–3

Ω

SLEW RATE

vs

OUTPUT VOLTAGE STEP

1800

Gain = 4
RL = 100 Ω
Rf = 750 Ω

0

0 2 4 6 8 10121416

Output Voltage Step – V

SR – Slew Rate –

sµ
V/

1600

1400

1200

1000

800

600

400

200

VCC = ±15 V

VCC = ±12 V

VCC = ±6 V

TRANSIMPEDANCE AND PHASE

vs

FREQUENCY

140

VCC = ±5 V to ±15 V
RL = 1 kΩ

120

Transimpedance

100

45

0

–45

3

2

– Output Voltage – V

O

1

V

0

–1

048

14

V

O

t – Time – µs

12 16 20

Figure 31

–5

–7

Gain = 8
VCC +12 V
Rf = 750 Ω
RL = 100 Ω

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–9

–11

–13

80

60

Transimpedance – dB

Shutdown Pin Voltage – V

40

20

1 K 10 K 100 K 1 M 10 M 100 M 1 G

Phase

f – Frequency – Hz

Figure 32

–90

Phase – Degrees

–135

–180

–225

350 mA, ±12 V ADSL CPE LINE DRIVERS

Input Voltage

V

V

I

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

THS6042, THS6043

OVERDRIVE RECOVERY

16

12

8

V

I

4

0

–4

– Output Voltage – V

O

–8

V

–12

–16

0 40 80 120 160 200

Gain = –8
VCC = ±12 V
Rf = 750 Ω
RL = 100 Ω

t – Time – ns

V

O

Figure 33 Figure 34

SMALL AND LARGE SIGNAL PULSE RESPONSE

0.6
Gain = –8
VCC = ±12 V

0.4

Rf = 750 Ω
RL = 100 Ω

6

4

2

1.5

1

0.5

0

–0.5

–1

–1.5

–2

OVERDRIVE RECOVERY

16

V

I

12

8

4

–

0

–4

– Output Voltage – V

–

O

–8

V

–12

–16

0 40 80 120 160 200

t – Time – ns

Gain = 8
VCC = ±12 V
Rf = 750 Ω
RL = 100 Ω

V

O

SMALL AND LARGE SIGNAL PULSE RESPONSE

0.6

0.4

Large Signal

Small Signal

Gain = 8
VCC = ±12 V
Rf = 750 Ω
RL = 100 Ω

2

1.5

1

0.5

0

–0.5

–1

–1.5

–2

6

4

– Input Voltage – V

I

V

0.2

0

–0.2

Small Signal Output – V

–0.4

–0.6

0 40 80 120 160 200

Small Signal

Large Signal

t – Time – ns

Figure 35

2

0

–2

–4

–6

0.2

0

–0.2

Large Signal Output – V

Small Signal Output – V

–0.4

–0.6

0 40 80 120 160 200

t – Time – ns

2

0

–2

Large Signal Output – V

–4

–6

Figure 36

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15

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

APPLICATION INFORMATION

The THS6042/3 contain two independent operational amplifiers. These amplifiers are current feedback
topology amplifiers made for high-speed operation. They have been specifically designed to deliver the full
power requirements of ADSL and therefore can deliver output currents of at least 230 mA at full output voltage.

The THS6042/3 are fabricated using the Texas Instruments 30-V complementary bipolar process, HVBiCOM.
This process provides excellent isolation and high slew rates that result in the device’s excellent crosstalk and
extremely low distortion.

ADSL

The THS6042/3 were primarily designed as line drivers for ADSL (asymmetrical digital subscriber line). The
driver output stage has been sized to provide full ADSL power levels of 13 dBm onto the telephone lines.
Although actual driver output peak voltages and currents vary with each particular ADSL application, the
THS6042/3 are specified for a minimum full output current of 230 mA at ±6 V and 300 mA at the full output
voltage of ±12 V . This performance meets the demanding needs of ADSL at the client side end of the telephone
line. A typical ADSL schematic is shown in Figure 37.

The ADSL transmit band consists of 255 separate carrier frequencies each with its own modulation and
amplitude level. With such an implementation, it is imperative that signals put onto the telephone line have as
low a distortion as possible. This is because any distortion either interferes directly with other ADSL carrier
frequencies or creates intermodulation products that interfere with other ADSL carrier frequencies.

The THS6042/3 have been specifically designed for ultra low distortion by careful circuit implementation and
by taking advantage of the superb characteristics of the complementary bipolar process. Driver single-ended
distortion measurements are shown in Figures 7 – 15. In the differential driver configuration, the second order
harmonics tend to cancel out. Thus, the dominant total harmonic distortion (THD) is primarily due to the third
order harmonics. Additionally , distortion should be reduced as the feedback resistance drops. This is because
the bandwidth of the amplifier increases, which allows the amplifier to react faster to any nonlinearities in the
closed-loop system. Another significant point is the fact that distortion decreases as the impedance load
increases. This is because the output resistance of the amplifier becomes less significant as compared to the
output load resistance.

Even though the THS6042/3 are designed to drive ADSL signals that have a maximum bandwidth of 1.1 MHz,
reactive loading from the transformer can cause some serious issues. Most transformers have a resonance
peak typically occurring from 20 MHz up to 150 MHz depending on the manufacturer and construction
technique. This resonance peak can cause some serious issues with the line driver amplifier such as small
high-frequency oscillations, increased current consumption, and/or ringing. Although the series termination
resistor helps isolate the transformer’s resonance from the line-driver amplifier, additional means may be
necessary to eliminate the effects of a reactive load. The simplest way is to add a snubber network, also known
as a zoebel network, in parallel with the transformer as shown by R

(SNUB)

and C

(SNUB)

in Figure 36. At high
frequencies, where the transformer’s impedance becomes very high at its resonance frequency (ex: 1 kΩ @
100 MHz), the snubber provides a resistive load to the circuit. The value for R

(SNUB)

should initially be set to
the impedance presented by the transformer within its pass-band. An example of this would be to use a 100-Ω
resistor for a 1:1 transformer or a 25-Ω resistor for a 1:2 transformer. The value for C

(SNUB)

should be chosen
such that the –3 dB frequency is about 5 times less than the resonance frequency . For example,if the resonance
frequency is at 100 MHz, the impedance of C
of C

(SNUB)

= 1 / (2π f R

(SNUB)

), or approximately 82 pF . This should only be used as a starting point. The final

(SNUB)

should be equal to R

(SNUB)

at 20 MHz. This leads to a value

values will be dictated by actual circuit testing.

16

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THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

APPLICATION INFORMATION

ADSL (continued)

One problem in the ADSL CPE area is noise. It is imperative that signals received off the telephone line have
as high a signal-to-noise ratio (SNR) as possible. This is because of the numerous sources of interference on
the line. The best way to accomplish this high SNR is to have a low-noise receiver such as the THS6062 or
OPA2822 on the front-end. Even if the receiver has very low noise characteristics, noise could be dominated
by the line driver amplifier. The THS6042/3 were primarily designed to circumvent this issue.

The ADSL standard, ANSI T1.413, stipulates a noise power spectral density of –140 dBm/Hz, which is
equivalent to 31.6 nV/√Hz
actual ADSL system testing has indicated that the noise power spectral density may be required to have ≤ –150
dBm/Hz, or ≤ 10 nV/√Hz
THS6042/3, with an equivalent input noise of 2.2 nV/√Hz
with a low 2.1 pA/√Hz
resistors, the THS6042/3 ensures that the received signal SNR is as high as possible.

for a 100-Ω system. Although many amplifiers can reach this level of performance,

. With a transformer ratio of 1:2, this number reduces to less than 5 nV/√Hz. The

, is an excellent choice for this application. Coupled

noninverting current noise, a very low 1 1 pA/√Hz inverting current noise, and low value

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17

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

APPLICATION INFORMATION

ADSL (continued)

+12 V

1 µF

0.68 µF

THS6042

VI+

210 Ω

VI–

Driver 1

THS6042

Driver 2

+
_

+
_

–12 V

750 Ω

750 Ω

0.1 µF

0.1 µF

+
10 µF

10 µF

+

50 Ω

50 Ω

R

(SNUB)

C

(SNUB)

1:1

1 kΩ

499 Ω

1 kΩ

Telephone Line

499 Ω

+12 V

–

+

499 Ω

100 Ω

THS6062
Receiver 1

0.1 µF

V

O+

18

499 Ω

–

+

–12 V

0.1 µF

Figure 37. THS6042 ADSL Application With 1:1 Transformer Ratio

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THS6062
Receiver 2

V

O–

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

APPLICATION INFORMATION

noise calculations and noise figure

Noise can cause errors on very small signals. This is especially true for the amplifying small signals. The noise
model for current feedback amplifiers (CFB) is the same as voltage feedback amplifiers (VFB). The only
difference between the two is that the CFB amplifiers generally specify different current noise parameters for
each input, while VFB amplifiers usually only specify one noise current parameter. The noise model is shown
in Figure 38. This model includes all of the noise sources as follows:

• e

= Amplifier internal voltage noise (nV/√Hz)

n

• IN+ = Noninverting current noise (pA/√Hz)

• IN– = Inverting current noise (pA/√Hz)

• e

The total equivalent input noise density (e

Where:

= Thermal voltage noise associated with each resistor (eRx = 4 kTRx)

Rx

e

ǒ

)

IN ) R

Rs

R

e

ni

e

+

ni

S

Ǹ

2

ǒ

Ǔ

e

n

k = Boltzmann’s constant = 1.380658 × 10
T = Temperature in degrees Kelvin (273 +°C)
R

|| RG = Parallel resistance of RF and R

F

e

IN+

IN–

Figure 38. Noise Model

Ǔ

S

n

) is calculated by using the following equation:

ni

2

ǒ

)

IN– ǒRFø R

+
_

e

R

G

Noiseless

e

Rf

Rg

G

–23

G

e

no

R

F

2

Ǔ

Ǔ

) 4kTRs) 4kTǒRFø R

Ǔ

G

To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the
overall amplifier gain (A

eno+ eniAV+ e

As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing R
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (R
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.

) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares

S

).

V

R

ǒ

ni

F

1 )

Ǔ

(Noninverting Case)

R

G

), the input noise is reduced considerably because of the parallel

G

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19

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

APPLICATION INFORMATION

noise calculations and noise figure (continued)

This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.

e

ǒ

e

Rs

1 )

2

ȳ

ni

ȧ

2

Ǔ

ȴ

ȡ
ȧ
Ȣ

2

Ǔ

ǒ

)

IN ) R

4kTR

S

ǒ

e

n

ȳ

ȣ

2

Ǔ

ȧ

S

ȧ

ȧ

Ȥ

ȧ
ȧ
ȧ

ȴ

16

14

12

10

8

f = 10 kHz
TA = 25°C

ȱ

NF + 10log

ȧ
Ȳ

Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:

ȱ
ȧ

ȧ

NF + 10log

ȧ
ȧ
ȧ

Ȳ

Figure 39 shows the noise figure graph for the THS6042/3.

20

6

Noise Figure – dB

4

2

0

10 100 1 k 10 k

RS – Source Resistance – Ω

Figure 39. Noise Figure vs Source Resistance

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THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

APPLICATION INFORMATION

device protection features

The THS6042/3 have two built-in features that protect the devices against improper operation. The first
protection mechanism is output current limiting. Should the output become shorted to ground, the output current
is automatically limited to the value given in the data sheet. While this protects the output against excessive
current, the device internal power dissipation increases due to the high current and large voltage drop across
the output transistors. Continuous output shorts are not recommended and could damage the device.

The second built-in protection feature is thermal shutdown. Should the internal junction temperature rise above
approximately 180_C, the device automatically shuts down. Such a condition could exist with improper heat
sinking or if the output is shorted to ground. When the abnormal condition is fixed, the internal thermal shutdown
circuit automatically turns the device back on.

thermal information – PowerPAD

The THS6042/3 are available packaged in thermally-enhanced PowerPAD packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 40(a) and Figure 40(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 40(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.

The PowerP AD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device. This
is discussed in more detail in the PCB design considerations section of this document.

The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.

DIE

Side View (a)

DIE

End View (b)

NOTE A: The thermal pad is electrically isolated from all terminals in the package.

Thermal

Pad

Bottom View (c)

Figure 40. Views of Thermally Enhanced PWP Package

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21

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

APPLICATION INFORMATION

PCB design considerations

Proper PCB design techniques in two areas are important to assure proper operation of the THS6042/3. These
areas are high-speed layout techniques and thermal-management techniques. Because the devices are
high-speed parts, the following guidelines are recommended.

D Ground plane – It is essential that a ground plane be used on the board to provide all components with a

low inductive ground connection. Although a ground connection directly to a terminal of the THS6042/3 is
not necessarily required, it is highly recommended that the thermal pad of the package be tied to ground.
This serves two functions. It provides a low inductive ground to the device substrate to minimize internal
crosstalk and it provides the path for heat removal.

D Input stray capacitance – To minimize potential problems with amplifier oscillation, the capacitance at the

inverting input of the amplifiers must be kept to a minimum. T o do this, PCB trace runs to the inverting input
must be as short as possible, the ground plane must be removed under any etch runs connected to the
inverting input, and external components should be placed as close as possible to the inverting input. This
is especially true in the noninverting configuration. An example of this can be seen in Figure 41, which shows
what happens when a 2.2-pF capacitor is added to the inverting input terminal in the noninverting
configuration. The bandwidth increases dramatically at the expense of peaking. This is because some of
the error current is flowing through the stray capacitor instead of the inverting node of the amplifier. While
the device is in the inverting mode, stray capacitance at the inverting input has a minimal effect. This is
because the inverting node is at a virtual ground and the voltage does not fluctuate nearly as much as in
the noninverting configuration. This can be seen in Figure 42, where a 22-pF capacitor adds only 0.9 dB
of peaking. In general, as the gain of the system increases, the output peaking due to this capacitor
decreases. While this can initally appear to be a faster and better system, overshoot and ringing are more
likely to occur under fast transient conditions. So, proper analysis of adding a capacitor to the inverting input
node should always be performed for stable operation.

Output Amplitude – dB

6

4

2

0

–2

–4

–6

–8

–10

100 k

VCC = ±12 V
Gain = 1
RL = 50 Ω
VO = 0.1 V

C in

V

I

1 M 10 M 100 M

OUTPUT AMPLITUDE

vs

FREQUENCY

Ci = 2.2 pF

Ci = 0 pF
(Stray C Only)

750 Ω

–

V

+

50 Ω

f – Frequency – Hz

O

50 Ω

Figure 41

1 G

Output Amplitude – dB

2

1

0

–1

–2

–3

–4

–5

–6

–7

100 k

VCC = ±12 V
Gain = –1
RL = 50 Ω
VO = 0.1 V

V

I

R

50 Ω

1 M 10 M 100 M

OUTPUT AMPLITUDE

vs

FREQUENCY

Ci = 22 pF

Ci = 0 pF
(Stray C Only)

750 Ω

g

–

+

C in

f – Frequency – Hz

V

RL = 50 Ω

Figure 42

O

1 G

22

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THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

APPLICATION INFORMATION

PCB design considerations (continued)

D Proper power supply decoupling – Use a minimum of a 6.8-µF tantalum capacitor in parallel with a 0.1-µF

ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several
amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the
supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible
to the supply terminal. As this distance increases, the inductance in the connecting etch makes the capacitor
less effective. The designer should strive for distances of less than 0.1 inches between the device power
terminal and the ceramic capacitors.

D Differential power supply decoupling – The THS6042/3 were designed for driving low-impedance

differential signals. The 50-Ω load which each amplifier drives causes large amounts of currents to flow from
amplifier to amplifier. Power supply decoupling for differential current signals must be accounted for to
ensure low distortion of the THS6042/3. By simply connecting a 0.1-µF to 1-µF ceramic capacitor from the
+V

pin to the –VCC pin, differential current loops will be minimized (see Figure 37). This will help keep

CC

the THS6042/3 operating at peak performance.

Because of its power dissipation, proper thermal management of the THS6042/3 is required. Even though the
THS6042 and THS6043 PowerPADs are different, the general methodology is the same. Although there are
many ways to properly heatsink these devices, the following steps illustrate one recommended approach for
a multilayer PCB with an internal ground plane. Refer to Figure 43 for the following steps.

Thermal pad area (0.15 x 0.17) with 6 vias
(Via diameter = 13 mils)

Figure 43. THS6043 PowerPAD PCB Etch and Via Pattern – Minimum Requirements

1. Place 6 holes in the area of the thermal pad. These holes should be 13 mils in diameter. They are kept small
so that solder wicking through the holes is not a problem during reflow.

2. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This will
help dissipate the heat generated from the THS6042/3. These additional vias may be larger than the 13 mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal-pad
area to be soldered, therefore, wicking is generally not a problem.

3. Connect all holes to the internal ground plane.

4. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology . Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
However, in this application, low thermal resistance is desired for the most ef ficient heat transfer. Therefore,
the holes under the THS6042/3 package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated through hole.

5. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area with
its 6 holes. The bottom-side solder mask should cover the 6 holes of the thermal pad area. This eliminates
the solder from being pulled away from the thermal pad area during the reflow process.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

23

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

APPLICATION INFORMATION

PCB design considerations (continued)

6. Apply solder paste to the exposed thermal pad area and all of the operational amplifier terminals.

7. With these preparatory steps in place, the THS6042/3 is simply placed in position and run through the solder
reflow operation as any standard surface-mount component. This results in a part that is properly installed.

The actual thermal performance achieved with the THS6042/3 in their PowerPAD packages depends on the
application. In the previous example, if the size of the internal ground plane is approximately 3 inches × 3 inches,
then the expected thermal coefficient, θ
package, 66.6°C/W for the SOIC–14 (D) package, and 37.5°C/W for the PWP package. Although the maximum
recommended junction temperature (T
T o ensure optimal performance, the junction temperature should be kept below 125°C. Above this temperature,
distortion will tend to increase. Figure 44 shows the recommended power dissipation with a junction
temperature of 125°C. If no solder is used to connect the PowerPAD to the PCB, the θ
dramatically with a vast reduction in power dissipation capability. For a given θ
temperature, the power dissipation is calculated by the following formula:

T

MAX–TA

P

ǒ

+

D

q

Ǔ

JA

, is about 95°C/W for the SOIC–8 (D) package, 45.8 °C/W for the DDA

JA

) is listed as 150°C, performance at this elevated temperature will suffer .

J

will increase

and a maximum junction

JA

JA

Where:

P

= Power dissipation of THS6042/3 (watts)

D

T

= Maximum junction temperature allowed in the design (125°C recommended)

MAX

T

= Free-ambient air temperature (°C)

A

θ

= θJC + θ

JA

CA

θJC = Thermal coefficient from junction to case (D–8 =38.3°C/W, DDA = 9.2°C/W,

D–14 = 26.9°C/W, PWP = 1.4°C/W)

θ

= Thermal coefficient from case to ambient

CA

5

4

3

2

1

Maximum Power Dissipation – W

0

–40 –20 0 20 40 60 80 100

NOTE: Results are with no air flow and PCB size = 3”× 3”

2 oz. trace and copper pad with solder unless otherwise noted.

PWP
θJA = 37.5 °C/W

DDA
θJA = 45.8 °C/W

D-14
θJA = 66.6 °C/W

D-8

θJA = 95 °C/W

Ta – Free-Air Temperature – °C

TJ = 125 °C

24

Figure 44. Maximum Power Dissipation vs Free-Air Temperature

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

APPLICATION INFORMATION

PCB design considerations (continued)

The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially multiamplifier devices. Because these devices have linear output stages (Class-AB), most
of the heat dissipation is at low output voltages with high output currents. Figure 45 and Figure 46 show this
effect, along with the quiescent heat, with an ambient air temperature of 50°C. Obviously, as the ambient
temperature increases, the limit lines shown will drop accordingly . The area under each respective limit line is
considered the safe operating area. Any condition above this line will exceed the amplifier’s limits and failure
may result. When using V

However, when using V
The other key factor when looking at these graphs is how the devices are mounted on the PCB. The PowerP AD
devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane
to fully use the heat dissipation properties of the PowerP AD. The standard SOIC package, on the other hand,
is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the
device, θ

decreases and the heat dissipation capability increases. The currents and voltages shown in these

JA

graphs are for the total package.

= ±6 V, there is generally not a heat problem, even with SOIC packages.

CC

= ±12 V , the SOIC package is severely limited in the amount of heat it can dissipate.

CC

MAXIMUM RMS OUTPUT CURRENT

vs

RMS OUTPUT VOLTAGE (DUE TO THERMAL LIMITS)

1000

Both Channels
TJ = 150°C
TA = 50°C

100

SO-8 Package

– Maximum RMS Output Current – mA

O

I

10

0123456

θJA = 95°C/W
High-K Test PCB

VO – RMS Output Voltage – V

Maximum Output

Current Limit Line

DDA
θJA = 45.8°C/W

SO-14 Package
θJA = 67°C/W
High-K Test PCB

VCC = ±6 V

PWP
θJA = 37.5°C/W

Figure 45

MAXIMUM RMS OUTPUT CURRENT

vs

RMS OUTPUT VOLTAGE (DUE TO THERMAL LIMITS)

1000

Both Channels
TJ = 150°C
TA = 50°C

θJA = 37.5°C/W

θJA = 45.8°C/W

100

– Maximum RMS Output Current – mA

O

I

10

024681012

DDA

SO-8 Package

θJA = 95°C/W

High-K Test PCB

VO – RMS Output Voltage – V

Maximum Output

Current Limit Line

PWP

VCC = ±12 V

SO-14 Package

θJA = 67°C/W

High-K Test PCB

Safe

Operating

Area

Figure 46

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

25

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

APPLICATION INFORMATION

recommended feedback and gain resistor values

As with all current feedback amplifiers, the bandwidth of the THS6042/3 is an inversely proportional function
of the value of the feedback resistor. This can be seen from Figures 1 to 6. The recommended resistors for the
optimum frequency response are shown in T able 1. These should be used as a starting point and once optimum
values are found, 1% tolerance resistors should be used to maintain frequency response characteristics.
Because there is a finite amount of output resistance of the operational amplifier, load resistance can play a
major part in frequency response. This is especially true with these drivers, which tend to drive low-impedance
loads. This can be seen in Figures 1–6. As the load resistance increases, the output resistance of the amplifier
becomes less dominant at high frequencies. To compensate for this, the feedback resistor may need to be
changed. For most applications, a feedback resistor value of 750 Ω is recommended, which is a good
compromise between bandwidth and phase margin that yields a very stable amplifier.

Table 1. Recommended Feedback (R

GAIN

1

2, –1

4
8

VCC = ±6 V VCC = ±12 V VCC = ±6 V VCC = ±12 V

680 Ω 560 Ω 620 Ω 510 Ω
470 Ω 430 Ω 430 Ω 390 Ω
270 Ω 240 Ω 270 Ω 240 Ω
200 Ω 200 Ω 200 Ω 200 Ω

) Values for Optimum Frequency Response

f

RL = 25 Ω RL = 100 Ω

Consistent with current feedback amplifiers, increasing the gain is best accomplished by changing the gain
resistor, not the feedback resistor . This is because the bandwidth of the amplifier is dominated by the feedback
resistor value and internal dominant-pole capacitor. The ability to control the amplifier gain independently of the
bandwidth constitutes a major advantage of current feedback amplifiers over conventional voltage feedback
amplifiers. Therefore, once a frequency response is found suitable to a particular application, adjust the value
of the gain resistor to increase or decrease the overall amplifier gain.

Finally, it is important to realize the effects of the feedback resistance on distortion. Increasing the resistance
decreases the loop gain and may increase the distortion. Decreasing the feedback resistance too low may
increase the bandwidth, but an increase in the load on the output may cause distortion to increase instead of
decreasing. It is also important to know that decreasing load impedance increases total harmonic distortion
(THD). Typically, the third order harmonic distortion increases more than the second order harmonic distortion.
This is illustrated in Figure 10 to 12 and Figures 16 to 18.

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

APPLICATION INFORMATION

shutdown control

The THS6043 is essentially the same amplifier as the THS6042. The only difference is the added flexibility of
a shutdown circuit. When the shutdown pin signal is low, the THS6043 is active. But, when a shutdown pin is
high (≥2 V), the THS6043 is turned off. The shutdown logic is not latched and should always have a signal
applied to it. T o help ensure a fixed logic state, an internal 50 kΩ resistor to GND is utilized. An external resistor ,
such as a 3.3 kΩ, to GND may be added to help improve noise immunity within harsh environments. If no
external resistor is utilized and SHDN pin is left unconnected, the THS6043 defaults to a power-on state. A
simplified circuit can be seen in Figure 47.

+V

CC

To Internal
Bias Circuitry
Control

SHDN

50 kΩ

GND

–V

CC

GND

Figure 47. Simplified THS6043 Shutdown Control Circuit

One aspect of the shutdown feature, which is often over-looked, is that the amplifier does not have a large output
impedance while in shutdown mode. This is due to the R

and R

F

resistors. This effect is true for any amplifier

G

connected as an amplifier with gains >1. The internal circuitry may be powered down and in a high-impedance
state, but the resistors are always there. This allows the signal to flow through these resistors and into the ground
connection. Figure 48 shows the results of the output impedance with no feedback resistor and a typically
configured amplifier.

1000

Ω

100

10

1

Shutdown Mode Impedance – k

0.1

0.01
10 K 100 K

Open Loop

Gain = –8
RF = 750 Ω

f – Frequency – Hz

VCC = ±5 V to ±15 V

1 M

10 M 100 M

1 G

Figure 48. Output Impedance In Shutdown Mode

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

27

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

APPLICATION INFORMATION

driving a capacitive load

Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS6042/3 has been internally compensated to maximize its bandwidth
and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on
the output decreases the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 5 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 49. Keep in mind that stray capacitance on the output is also considered
capacitive loading, whether or not it is there on purpose. A minimum value of 5 Ω should work well for most
applications. In ADSL systems, setting the series resistor value to 12.4 Ω both isolates any capacitance loading
and provides the proper line impedance matching at the source end.

750 Ω

100 Ω

Input

_

12.4 Ω

Output

+

C

(Stray)

+ C

L

Figure 49. Driving a Capacitive Load

general configurations

A common error for the first-time CFB user is to create a unity gain buffer amplifier by shorting the output directly
to the inverting input. A CFB amplifier in this configuration oscillates and is not recommended. The THS6042/3,
like all CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing capacitors
directly from the output to the inverting input is not recommended. This is because, at high frequencies, a
capacitor has a very low impedance. This results in an unstable amplifier and should not be considered when
using a current-feedback amplifier. Because of this, integrators and simple low-pass filters, which are easily
implemented on a VFB amplifier, have to be designed slightly dif ferently . If filtering is required, simply place an
RC-filter at the noninverting terminal of the operational-amplifier (see Figure 50).

R

G

V

I

R1

C1

R

F

V

O

+ ǒ1)

–

+

V

O

V

I

f

–3dB

+

R

F

R

G

1

2pR1C1

ǒ

Ǔ

1 ) sR1C1

1

Ǔ

28

Figure 50. Single-Pole Low-Pass Filter

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THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

APPLICATION INFORMATION

general configurations (continued)

If a multiple pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is
because the filtering elements are not in the negative feedback loop and stability is not compromised. Because
of their high slew-rates and high bandwidths, CFB amplifiers can create very accurate signals and help minimize
distortion. An example is shown in Figure 51.

C1

V

I

R2R1

C2

R

G

+
_

R

F

R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)

1

+

2pRC

R

F

1

2 –

(

)

Q

R

f

–3dB

G

=

Figure 51. 2-Pole Low-Pass Sallen-Key Filter

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29

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0.050 (1,27)

14

1

0.069 (1,75) MAX

A

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

0.004 (0,10)

DIM

8

7

PINS **

0.010 (0,25)

0.157 (4,00)

0.150 (3,81)

M

0.244 (6,20)

0.228 (5,80)

Seating Plane

0.004 (0,10)

8

14

0.008 (0,20) NOM

0°–ā8°

16

Gage Plane

0.010 (0,25)

0.044 (1,12)

0.016 (0,40)

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

30

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.197

(5,00)

0.189

(4,80)

0.344

(8,75)

0.337

(8,55)

0.394

(10,00)

0.386

(9,80)

4040047/D 10/96

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

MECHANICAL DATA

DDA (S–PDSO–G8) Power P AD t PLASTIC SMALL-OUTLINE

1,27

85

14

4,98
4,80

0,49
0,35

3,99
3,81

1,68 MAX

M

0,10

6,20
5,84

Seating Plane

Thermal Pad
(See Note D)

0,20 NOM

0°–8°

Gage Plane

0,25

0,89
0,41

1,55
1,40

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.

This pad is electrically and thermally connected to the backside of the die and possibly selected leads.

PowerPAD is a trademark of Texas Instruments.

0,13
0,03

0,10

4202561/A 02/01

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31

THS6042, THS6043

350 mA, ±12 V ADSL CPE LINE DRIVERS

SLOS264G – MARCH 2000 – REVISED DECEMBER 2001

MECHANICAL INFORMATION

PWP (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE

20-PIN SHOWN

0,65

20

1

1,20 MAX

0,30

0,19

11

4,50
4,30

10

A

0,15
0,05

PINS **

DIM

M

0,10

6,60
6,20

Seating Plane

0,10

1614

Thermal Pad
(See Note D)

20

0,15 NOM

0°–ā8°

Gage Plane

0,25

0,75
0,50

2824

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically

and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MO-153

PowerPAD is a trademark of Texas Instruments.

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4073225/E 03/97

32

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