TEXAS INSTRUMENTS THS4120, THS4121 Technical data

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THS4121

D, DGN, OR DGK PACKAGE

(TOP VIEW)

1
2
3
4

8
7
6
5

V

IN−

V

OCM

V

DD

V

OUT+

V

IN+

NC
GND
V

OUT−

THS4120

D, DGN, OR DGK PACKAGE

(TOP VIEW)

1
2
3
4

8
7
6
5

V

IN−

V

OCM

V

DD

V

OUT+

V

IN+

PD
GND
V

OUT−

+

DIGITAL
OUTPUT

V

IN

−

+ −

DV

DD

V

OCM

AV

SS

AV

DD

A

IN

A

IN

V

DD

V

ref

3.3 V

TYPICAL A/D APPLICATION CIRCUIT

HIGH-SPEED FULLY DIFFERENTIAL I/O AMPLIFIERS

FEATURES KEY APPLICATIONS

• High Performance

– 100 MHz, –3 dB Bandwidth
– 50 V/µs Slew Rate
– 75 dB Total Harmonic Distortion at 1 MHz

(V

= 2 V

O

– 5.4 nV/ √ Hz Input-Referred Noise (10 kHz)

• Differential Input/Differential Output

– Balanced Outputs Reject Common-Mode

Noise

– Differential Reduced Second Harmonic

Distortion

• Power Supply Range

– V

= 3.3 V

DD

)

PP

THS4120
THS4121

SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004

• Simple Single-Ended To Differential

Conversion

• Differential ADC Driver/Differential

Antialiasing

• Differential Transmitter and Receiver

• Output Level Shifter

DESCRIPTION

The THS412x is one in a family of fully differen­tial-input, differential-output devices fabricated using
Texas Instruments' state-of-the-art submicron CMOS
process.

The THS412x consists of a true fully-differential
signal path from input to output. This results in THS4121 1 –
excellent common-mode noise rejection and
improved total harmonic distortion.

RELATED DEVICES

DEVICE

(1) See the TI Web site for additional high-speed amplifier devices.

(1)

THS413x 150 MHz, 51 V/µs, 1.3 nV/ √ Hz 5 V to 30 V ± 2.5 to ± 15
THS414x 160 MHz, 450 V/µs, 6.5 nV/ √ Hz 5 V to 30 V ± 2.5 to ± 15
THS415x 150 MHz, 650 V/µs, 7.6 nV/ √ Hz 5 V to 30 V ± 2.5 to ± 15

DESCRIPTION

HIGH-SPEED DIFFERENTIAL I/O FAMILY

DEVICE POWERDOWN

THS4120

(1) For proper functiionality, an external 10-k Ω pullup resistor is

required between the PD pin and the positive supply.

SINGLE SUPPLY SPLIT SUPPLY

VOLTAGE RANGE VOLTAGE RANGE

(1)

NUMBER OF

CHANNELS

1 Yes

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2001–2004, Texas Instruments Incorporated

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THS4120
THS4121

SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

0 ° C to 70 ° C

–40 ° C to 85 ° C

SMALL OUTLINE(D)

THS4120CD THS4120CDGN ARL THS4120CDGK ATZ THS4120EVM
THS4121CD THS4121CDGN ASB THS4121CDGK ATO THS4121EVM

THS4120ID THS4120IDGN ARM THS4120IDGK ARN –
THS4121ID THS4121IDGN ASC THS4121IDGK ASN –

MSOP PowerPAD™ MSOP

(DGN) SYMBOL (DGK) SYMBOL

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage, GND to V

V

Input voltage ± V

I

I

Output current (sink)

O

V

Differential input voltage ± V

ID

Continuous total power dissipation See Dissipation Rating Table

T

Maximum junction temperature

J

T

Maximum junction temperature, continuous operation, long-term reliability

J

T

Operating free-air temperature

A

T

Storage Temperature –65 ° C to 150 ° C

stg

Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds 300 ° C

ESD ratings CDM 1500 V

(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The THS412x may incorporate a PowerPad™ on the underside of the chip. This acts as a heatsink and must be connected to a

thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the

PowerPad™ thermally enhanced package.
(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may

result in reduced reliability and/or lifetime of the device.

DD

(2)

(3)

C suffix 0 ° C to 70 ° C
I suffix –40 ° C to 85 ° C

HBM 4000 V

MM 200 V

(1)

(4)

EVALUATION

MODULES

UNIT

3.6 V

DD

110 mA

DD

150 ° C
125 ° C

DISSIPATION RATING TABLE

PACKAGE θ

(1)

( ° C/W) θJC( ° C/W)

JA

POWER RATING

TA= 25 ° C TA= 85 ° C

D 97.5 38.3 1.02 W 410 mW
DGN 58.4 4.7 1.71 W 685 mW
DGK 260 54.2 385 mW 154 mW

(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of 125 ° C. This is the point where distortion

starts to substantially increase. Thermal management of the final PCB should strive to keep the
junction temperature at or below 125 ° C for best performance and long-term reliability.

2

(2)

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RECOMMENDED OPERATING CONDITIONS

V

T

Supply voltage V

DD

Operating free-air temperature ° C

A

Split supply ± 1.5 ± 1.65 ± 1.75
Single supply 3 3.3 3.5
C suffix 0 70
I suffix –40 85

ELECTRICAL CHARACTERISTICS

V

= 3.3 V, RL= 800 Ω , TA= 25 ° C (unless otherwise noted)

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DYNAMIC PERFORMANCE

BW Small-signal bandwidth (–3 dB) V
SR Slew rate

t

s

Settling time to 0.1% 60
Settling time to 0.01% 292

(2)

DISTORTION PERFORMANCE

Total harmonic distortion

THD Differential input, differential output V

Gain = 1, Rf= 200 Ω , RL= 800 Ω , VO= 2 V

PP

Total harmonic distortion

THD Differential input, differential output V

Gain = 1, Rf= 200 Ω , RL= 800 Ω , VO= 4 V

PP

Spurious free dynamic range (SFDR)
Differential input, differential output, VO= 4 V

PP

Third intermodulation distortion VI= 0.071 V

NOISE PERFORMANCE

V
I

n

Input voltage noise f = 10 kHz 5.4 nV/ √ Hz

n

Input current noise f = 10 kHz 1 fA/ √ Hz

DC PERFORMANCE

Open-loop gain dB

Input offset voltage

V

S

Input offset voltage, referred to V

OCM

Offset voltage drift TA= full range 25 µV/ ° C

I

IB

I

OS

Input bias current 1.2 pA
Input offset current 100 fA
Current offset drift TA= full range 5 fA/ ° C

(1) The full range temperature is 0 ° C to 70 ° C for the C suffix, and –40 ° C to 85 ° C for the I suffix.
(2) Slew rate is measured differentially from an output level range of 25% to 75%.

(1)

= 3.3 V, Gain = 1, Rf= 200 Ω 100 MHz

DD

V

= 3.3 V, Gain = 1 55 V/µs

DD

Differential step voltage = 2 VPP, Gain = 1 ns

= 3.3 V, f = 1 MHz –75 dB

DD

= 3.3 V, f = 1 MHz –66 dB

DD

Rf= 200 Ω , f = 1 MHz –69 dB

RMS

TA= 25 ° C 60 66
TA= full range 66
TA= 25 ° C 3 8
TA= full range 4 9
TA= 25 ° C 5 13
TA= full range 14

TA= full range

THS4120
THS4121

SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004

MIN TYP MAX UNIT

Gain = 1, f = 10 MHz –75 dBc

mV

3

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THS4120
THS4121

SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004

ELECTRICAL CHARACTERISTICS (Continued)

V

= 3.3 V, RL= 800 Ω , TA= 25 ° C (unless otherwise noted)

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT CHARACTERISTICS

CMRR Common-mode rejection ratio TA= full range 64 96 dB

V

r
C
r

Common-mode input voltage range TA= full range to V

ICR

Input resistance (dc level) Measured into each input terminal 820 M Ω

i

Input capacitance, closed loop 3 pF

i

Output resistance See Figure 16 1 Ω

o

OUTPUT CHARACTERISTICS

V
V
I
I

High-level output Voltage VIC= VDD/2, V

OH

Low-level output Voltage VIC= VDD/2, V

OL

Output current (sink), RL= 7 Ω V

O

Output current (source), RL= 7 Ω V

O

= 3.3 V, TA= 25 ° C 80 100 mA

DD

= 3.3 V, TA= 25 ° C 20 25 mA

DD

POWER SUPPLY

V

I

Supply voltage range Single supply 3.3 V

DD

Quiescent current (per amplifier) V

DD

= 3.3 V mA

DD

PSRR Power supply rejection ratio TA= 25 ° C 68 85 dB

POWER-DOWN CHARACTERISTICS (THS4120 ONLY)

Power-down voltage level

(2)

Power-down quiescent current µA

t
t
z

Turn-on time delay 4.8 µs

on

Turn-off time delay 3 ns

off

Output impedance f = 1 MHz 1 k Ω

o

Enable >1.4
Power-down <1.2
TA= 25 ° C 120
TA= full range 130

50% of final supply current value

(1)

0.65 to

V

- 0.1

DD

= 3.3 V, TA= 25 ° C 3.05 3.15 V

DD

= 3.3 V, TA= 25 ° C 0.25 0.15 V

DD

0.35
V

DD

TA= 25 ° C 11 13.5
TA= full range 16

V

(1) The full range temperature is 0 ° C to 70 ° C for the C suffix, and –40 ° C to 85 ° C for the I suffix.
(2) For detail information on the power-down circuit, see the power-down section in the application section of this data sheet.

4

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−1.5

−1

−0.5

0

0.5

1

1.5

0 20 40 60 80

t − Time − ns

VDD = 3.3 V ,
VO = 2 VPP,
TA= 25°C
G = 1
RL = 800 Ω

− Output Voltage − VV
O

Rising Edge

Falling Edge

−4

−2

−1

0

1

2

100 k 1M 10 M 100 M 1G

G = 1
VI = 22.5 mV

RMS

VDD = 3.3 V

Rf = 270 Ω

Rf = 200 Ω

Gain − dB

f − Frequency − Hz

Rf = 390 Ω

Rf = 150 Ω

−3

SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004

TYPICAL CHARACTERISTICS

Table of Graphs

Small-signal frequency response 1

SR Slew rate 2

THD Total harmonic distortion

Harmonic distortion

Third intermodulation distortion vs Output voltage 10

V

Output voltage vs Load resistance 11

O

Settling time 12
V
V

Voltage noise vs Frequency 13

n

Output offset voltage vs Common-mode input voltage 14

OO

CMMR Common-mode rejection ratio vs Frequency 15
z

os

z

o

Single-ended output impedance (closed loop) vs Frequency 16

Single-ended (V

) input impedance vs Frequency 17

OCM

vs Frequency 3
vs Output voltage 4
vs Frequency 5, 6, 7
vs Output voltage 8, 9

THS4120
THS4121

FIGURE

SMALL-SIGNAL FREQUENCY RESPONSE SLEW RATE

Figure 1. Figure 2.

5

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VO − Output Voltage − V

−90

−80

−70

−60

−50

0 1 2 3 4 5

VDD = 3.3 V ,
f = 1 MHz
Rf = 200 Ω,
RL = 800 Ω

Differential Input /
Differential Output

Single Input /
Differential Output

THD − Total Harmonic Distortion − dB

−80

−70

−60

−50

−40

−30

−20

100 k 1 M 10 M

THD − Total Harmonic Distortion − dB

f − Frequency − Hz

Differential Input/
Differential Output

Single−Ended Input /

Differential Output

VDD = 3.3 V ,
VO = 4 V

PP

Rf = 200 Ω,
RL = 800 Ω
G = 1

−120

−110

−100

−90

−80

−70

−60

−50

−40

100 k 1 M 10 M

Harmonic Distortion − dB

f − Frequency − Hz

5th_HD

4th_HD

3rd_HD

3rd_HD

VDD = 3.3 V ,
VO = 2 VPP,
RL = 800 Ω,
Rf = 270 Ω,
G = 1

3rd_HD2nd_HD

Differential Input /
Differential Output

−120

−110

−100

−90

−80

−70

−60

−50

−40

−30

5th_HD

4th_HD

3rd_HD

2nd_HD

100 k 1 M 10 M

Harmonic Distortion − dB

f − Frequency − Hz

VDD = 3.3 V ,
VO = 4 VPP,
RL = 800 Ω,
Rf = 200 Ω,
G = 1

Differential Input /
Differential Output

THS4120
THS4121

SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004

TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION

TOTAL HARMONIC DISTORTION HARMONIC DISTORTION

vs vs

FREQUENCY OUTPUT VOLTAGE

Figure 3. Figure 4.

THS4121 THS4121

vs vs

FREQUENCY FREQUENCY

6

Figure 5. Figure 6.

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−100

−90

−80

−70

−60

−50

−40

−30

−20

100 k 1 M 10 M

Harmonic Distortion − dB

f − Frequency − Hz

5th_HD

4th_HD

3rd_HD

2nd_HD

VDD = 3.3 V ,
VO = 4 VPP,
RL = 800 Ω,
Rf = 200 Ω,
G = 1

Single Input / Differential Output

Harmonic Distortion − dB

VDD = 3.3 V ,
f = 1 MHz,
RL = 800 Ω,
Rf = 200 Ω,
G = 1

VO − Output Voltage − V

−120

−110

−100

−90

−80

−70

−60

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

3rd_HD

2nd_HD

Differential Input /
Differential Output

−120

−110

−100

−90

−80

−70

−60

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

Harmonic Distortion − dB

5th_HD

4th_HD

3rd_HD

2nd_HD

VDD = 3.3 V ,
f = 1 MHz,
RL = 800 Ω,
Rf = 200 Ω,
G = 1

Single Input / Differential Output

VO − Output Voltage − V

−90

−80

−70

−60

−50

−40

−30

−20

−10

−25 −20 −15 −10 −5 0 5 10

Third Intermodulation Distortion − dBc

VO − Output Voltage − V

f = 10 MHz

f = 5 MHz

VDD = 3.3 V ,
f = 1 MHz
Rf = 270 Ω,
RL = 800 Ω

THS4120
THS4121

SLOS319D – FEBRUARY 2001 – REVISED OCTOBER 2004

HARMONIC DISTORTION HARMONIC DISTORTION

HARMONIC DISTORTION THIRD INTERMODULALTION DISTORTION

THS4121 THS4121

vs vs

FREQUENCY OUTPUT VOLTAGE

Figure 7. Figure 8.

THS4121

vs vs

OUTPUT VOLTAGE OUTPUT VOLTAGE

Figure 9. Figure 10.

7