THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
D
C-Stable Amplifiers Drive Any Capacitive
Load
D
High Speed
– 165 MHz Bandwidth (–3 dB); CL = 0 pF
– 100 MHz Bandwidth (–3 dB); CL = 100 pF
– 35 MHz Bandwidth (–3 dB); C
L
– 400 V/µs Slew Rate
D
Unity Gain Stable
D
High Output Drive, IO = 100 mA (typ)
D
Very Low Distortion
– THD = –75 dBc (f = 1 MHz, RL = 150 Ω)
– THD = –89 dBc (f = 1 MHz, R
D
Wide Range of Power Supplies
= 1 kΩ)
L
– VCC = ±5 V to ±15 V
D
Available in Standard SOIC or MSOP
PowerPAD Package
D
Evaluation Module Available
description
The THS4041 and THS4042 are single/dual,
high-speed voltage feedback amplifiers capable
of driving any capacitive load. This makes them
ideal for a wide range of applications including
driving video lines or buffering ADCs. The devices
feature high 165-MHz bandwidth and 400-V/µsec
slew rate. The THS4041/2 are stable at all gains
for both inverting and noninverting configurations.
For video applications, the THS4041/2 offer
excellent video performance with 0.01% differential gain error and 0.01° differential phase error.
These amplifiers can drive up to 100 mA into a
20-Ω load and operate off power supplies ranging
from ±5V to ±15V.
RELATED DEVICES
RELATED DEVICES
DEVICE DESCRIPTION
THS4011/2 290-MHz Low Distortion High-Speed Amplifier
THS4031/2 100-MHz Low Noise High-Speed Amplifier
THS4081/2 175-MHz Low Power High-Speed Amplifiers
= 1000 pF
THS4041
D AND DGN PACKAGE
(TOP VIEW)
NULL
IN–
IN+
V
CC
NC – No internal connection
1OUT
1IN–
1IN+
V
CC
Cross Section View Showing
10
8
6
4
2
0
–2
VCC = ±15 V
–4
Gain = 1
Output Amplitude – dB
–6
RF = 200 Ω
RL = 150 Ω
–8
V
–10
1
2
3
4
–
THS4042
D AND DGN PACKAGE
(TOP VIEW)
1
2
3
4
–
PowerPAD Option (DGN)
OUTPUT AMPLITUDE
FREQUENCY
CL = 1000 pF
CL = 0.1 µF
O(PP)=62 mV
f – Frequency – Hz
vs
8
7
6
5
8
7
6
5
CL = 0 pF
CL = 100 pF
100M
NULL
V
CC
OUT
NC
V
CC
2OUT
2IN–
2IN+
+
+
1G10M100k 1M
CAUTION: The THS4041 and THS4042 provide ESD protection circuitry. However , permanent damage can still occur if this device
is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance
degradation or loss of functionality.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Insruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
THS4041, THS4042
0°C to 70°C
40°C to 85°C
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
°
°
°
–
†
The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4041CDGNR).
°
NUMBER OF
CHANNELS
1 THS4041CD THS4041CDGN ACO THS4041EVM
2 THS4042CD THS4042CDGN ACC THS4042EVM
1 THS4041D THS4041IDGN ACP —
2 THS4042ID THS4042IDGN ACD —
PLASTIC
SMALL OUTLINE
(D)
†
PLASTIC
MSOP
(DGN)
†
functional block diagram
MSOP
SYMBOL
V
CC
8
EVALUATION
MODULE
Null
1
IN–
IN+
2
3
8
6
OUT
Figure 2. THS4041 – Single Channel
1IN–
1IN+
2IN–
2IN+
2
1
3
6
5
4
VCC–
1OUT
7
2OUT
Figure 1. THS4042 – Dual Channel
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage, VCC ±16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
±V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
Output current, IO 150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VIO ±4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature, T
: C-suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
I-suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, T
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
CC
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4041, THS4042
PACKAGE
JA
JC
A
Suppl
oltage, V
and V
V
Operating free-air temperature, T
°C
Gain
1
MH
yg
Gain
2
MHzBW
Bandwidth for 0.1 dB flatness
Gain
1
MH
Full
h
§
MH
SR
Sl
‡
V/µs
Settling time to 0.1%
Gain
1
ns
t
Settling time to 0.01%
Gain
1
ns
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
DISSIPATION RATING TABLE
θ
(°C/W)
D 167
‡
DGN
†
This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC proposed
High-K test PCB, the θJA is 95°C/W with a power rating at TA = 25°C of 1.32 W.
‡
This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. × 3 in.
PC. For further information, refer to
†
58.4 4.7 2.14 W
Application Information
recommended operating conditions
pp
y v
p
CC+
CC–
p
A
Dual supply ±4.5 ±16
Single supply 9 32
C-suffix 0 70
I-suffix –40 85
electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted)
θ
(°C/W)
38.3 740 mW
section of this data sheet.
T
= 25°C
POWER RATING
MIN NOM MAX UNIT
°
dynamic performance
PARAMETER TEST CONDITIONS
VCC = ±15 V Rf = 200 Ω
Dynamic performance small-signal bandwidth
(–3 dB)
power bandwidt
ew rate
s
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
‡
Slew rate is measured from an output level range of 25% to 75%.
§
Full power bandwidth = slew rate / 2 π V
O(Peak)
VCC = ±5 V Rf = 200 Ω
VCC = ±15 V Rf = 1.3 kΩ
VCC = ±5 V Rf = 1.3 kΩ
VCC = ±15 V Rf = 200 Ω
VCC = ±5 V Rf = 200 Ω
V
O(pp)
V
O(pp)
VCC = ±15 V, 20-V step, Gain = 5 400
VCC = ±5 V, 5-V step, Gain = –1 325
VCC = ±15 V, 5-V step
VCC = ±5 V, 2-V step
VCC = ±15 V, 5-V step
VCC = ±5 V, 2-V step
.
†
=
=
=
= 20 V, VCC = ±15 V 6.3
= 5 V, VCC = ±5 V 20
= –
= –
MIN TYP MAX UNIT
165
150
60
60
45
45
120
120
250
280
z
z
z
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
THS4041, THS4042
V
±15 V
THD
Total harmonic distortion
O( )
,
dBc
V
V
Differential gain error
,
Differential phase error
,
CC
,
O
,
Open loop gain
dB
CC
,
O
,
VOSInput offset voltage
V
±15 V
mV
IIBInput bias current
V
±5 V or ±15 V
A
IOSInput offset current
V
±15 V
nA
V
Common-mode input voltage range
V
CMRR
Common mode rejection ratio
T
full range
dB
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
electrical characteristics at TA = 25°C, VCC = ±15 V , RL = 150 Ω (unless otherwise noted) (continued)
noise/distortion performance
PARAMETER TEST CONDITIONS
Vpp = 2 V,
f = 1 MHz, Gain = 2
V
Input voltage noise VCC = ±5 V or ±15 V, f = 10 kHz 14 nV/√Hz
n
I
Input current noise VCC = ±5 V or ±15 V, f = 10 kHz 0.9 pA/√Hz
n
Gain = 2, NTSC,
40 IRE modulation,,±100 IRE ramp
p
Channel-to-channel crosstalk
(THS4042 only)
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
Gain = 2, NTSC,
40 IRE modulation,,±100 IRE ramp
VCC = ±5 V or ±15 V, f = 1 MHz Gain = 2 –64 dB
dc performance
PARAMETER TEST CONDITIONS
V
= ±15 V, V
p
p
p
Offset voltage drift VCC = ±5 V or ±15 V TA = full range 10 µV/°C
p
p
Offset current drift TA = full range 0.3 nA/°C
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
RL = 1 k Ω
V
= ±5 V, V
RL = 250 Ω
= ±5 V or
CC
=
CC
= ±5 V or
CC
=
CC
= ±5
CC
= ±10 V,
= ±2.5 V,
†
RL = 150 Ω –75
RL = 1 kΩ –89
RL = 150 Ω –75
RL = 1 kΩ –86
VCC = ±15 V 0.01%
VCC = ±5 V
VCC = ±15 V 0.01°
VCC = ±5 V
†
TA = 25°C 74 80
TA = full range 69
TA = 25°C 69 76
TA = full range 66
TA = 25°C 2.5 10
TA = full range 13
TA = 25°C 2.5 6
TA = full range 8
TA = 25°C 35 250
TA = full range 400
MIN TYP MAX UNIT
0.01%
0.02°
MIN TYP MAX UNIT
µ
input characteristics
PARAMETER TEST CONDITIONS
ICR
r
i
C
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
4
Input resistance 1 MΩ
Input capacitance 1.5 pF
i
†
p
VCC = ±15 V ±13.8 ±14.3
VCC = ±5 V ±3.8 ±4.3
VCC = ±15 V, V
VCC = ±5 V, V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ICR
ICR
= ±12 V
= ±2.5 V
=
A
MIN TYP MAX UNIT
70 90
80 100
THS4041, THS4042
V
VOOutput voltage swing
R
kΩ
V
I
O
‡
R
Ω
mA
VCCSuppl
oltage operating range
V
V
±15 V
ICCSupply current (per amplifier)
mA
V
V
PSRR
Power supply rejection ratio
V
±15 V
dB
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
electrical characteristics at TA = 25°C, VCC = ±15 V , RL = 150 Ω (unless otherwise noted) (continued)
output characteristics
PARAMETER TEST CONDITIONS
VCC = ±15 V RL = 250 Ω ±11.5 ±13
p
O
I
SC
R
O
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
‡
Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily loaded or
shorted. See the absolute maximum ratings section of this data sheet for more information.
utput current
Short-circuit current
Output resistance Open loop 13 Ω
‡
VCC = ±5 V RL = 150 Ω ±3.2 ±3.5
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V 150 mA
power supply
PARAMETER TEST CONDITIONS
pp
y v
pp
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
pp
p
p
p
Dual supply ±4.5 ±16.5
Single supply 9 33
=
CC
= ±5
CC
= ±5 V or
CC
†
= 1
L
= 20
L
†
TA = 25°C 8 9.5
TA = full range 11
TA = 25°C 7 8.5
TA = full range 10
TA = 25°C 75 84
TA = full range 70
MIN TYP MAX UNIT
±13 ±13.6
±3.5 ±3.8
80 100
50 65
MIN TYP MAX UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
TYPICAL CHARACTERISTICS
OPEN LOOP GAIN AND
PHASE RESPONSE
100
80
60
40
20
Open Loop Gain – dB
0
–20
FREQUENCY
Phase
f – Frequency – Hz
OUTPUT AMPLITUDE
10
CL = 1000 pF
8
CL = 0.1 µF
6
4
2
0
–2
VCC = ±15 V
–4
Gain = 1
Output Amplitude – dB
–6
RF = 200 Ω
RL = 150 Ω
–8
V
O(PP)=62 mV
–10
vs
VCC = ±15 V and ±5 V
Gain
1M100k1k 10k
10M 1G100M
Figure 3
vs
FREQUENCY
CL = 0 pF
CL = 100 pF
f – Frequency – Hz
100M
Figure 6
0
–30
–60
–90
–120
Phase – Degrees
–150
–180
1G10M100k 1M
2
1
0
–1
–2
–3
VCC = ±15 V
–4
Output Amplitude – dB
Gain = 1
RF = 200 Ω
–5
VO = 0.2 Vrms
–6
10
8
6
4
2
0
–2
VCC = ±15 V
–4
Gain = 1
Output Amplitude – dB
RF = 200 Ω
–6
RL = 150 Ω
–8
V
O(PP)=62 mV
–10
OUTPUT AMPLITUDE
vs
FREQUENCY
RL = 1 kΩ
RL = 150 Ω
f – Frequency – Hz
100M10M100k 1M
Figure 4
OUTPUT AMPLITUDE
vs
FREQUENCY
CL = 0.01 µF
CL = 10 pF
f – Frequency – Hz
100M
Figure 7
1G
1G10M100k 1M
0.4
0.3
0.2
0.1
–0.0
–0.1
–0.2
Output Amplitude – dB
VCC = ±15 V
Gain = 1
–0.3
RF = 200 Ω
VO = 0.2 Vrms
–0.4
2
1
0
–1
–2
–3
–4
Output Amplitude – dB
VCC = ±5 V
Gain = 1
–5
RF = 200 Ω
VO = 0.2 Vrms
–6
OUTPUT AMPLITUDE
vs
FREQUENCY
RL = 1 kΩ
RL = 150 Ω
f - Frequency - Hz
100M
Figure 5
OUTPUT AMPLITUDE
vs
FREQUENCY
RL = 1 kΩ
RL = 150 Ω
f – Frequency – Hz
100M
Figure 8
1G10M100k 1M
1G10M100k 1M
0.4
0.3
0.2
0.1
–0.0
–0.1
–0.2
Output Amplitude – dB
–0.3
–0.4
6
OUTPUT AMPLITUDE
vs
FREQUENCY
RL = 1 kΩ
RL = 150 Ω
VCC = ±5 V
Gain = 1
RF = 200 Ω
VO = 0.2 Vrms
f – Frequency – Hz
Figure 9
100M
OUTPUT AMPLITUDE
vs
FREQUENCY
1G10M100k 1M
10
CL = 1000 pF
8
CL = 0.1 µF
6
4
2
0
–2
VCC = ±5 V
–4
Gain = 1
Output Amplitude – dB
–6
RF = 200 Ω
RL = 150 Ω
–8
V
O(PP)=62 mV
–10
f – Frequency – Hz
CL = 0 pF
CL = 100 pF
Figure 10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
100M
1G10M100k 1M
10
8
6
4
2
0
–2
VCC = ±5 V
–4
Gain = 1
Output Amplitude – dB
–6
RF = 200 Ω
RL = 150 Ω
–8
V
O(PP)=62 mV
–10
OUTPUT AMPLITUDE
vs
FREQUENCY
CL = 0.01 µF
CL = 10 pF
f – Frequency – Hz
100M
Figure 11
1G10M100k 1M
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
TYPICAL CHARACTERISTICS
THS4041, THS4042
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
8
7
6
5
4
3
2
Output Amplitude – dB
VCC = ±15 V
Gain = 2
1
RF = 1.3 kΩ
VO = 0.4 Vrms
0
2
1
0
–1
–2
–3
VCC = ±5 V
–4
Output Amplitude – dB
Gain = 2
RF = 1.3 kΩ
–5
VO = 0.4 Vrms
–6
OUTPUT AMPLITUDE
vs
FREQUENCY
RL = 1 kΩ
RL = 150 Ω
f – Frequency – Hz
10M100k 1M
Figure 12
OUTPUT AMPLITUDE
vs
FREQUENCY
RL = 1 kΩ
RL = 150 Ω
f – Frequency – Hz
Figure 15
100M
100M10M100k 1M
OUTPUT AMPLITUDE
16
CL = 0.1 µF RF = 1.3 kΩ
14
12
10
8
6
4
2
Output Amplitude – dB
0
VCC = ±15 V
–2
Gain = 2
–4
OUTPUT AMPLITUDE
16
CL = 0.1 µF
14
12
10
8
6
4
2
Output Amplitude – dB
0
–2
–4
vs
FREQUENCY
RL = 150 Ω
V
O(PP)
CL = 1000 pF
f – Frequency – Hz
Figure 13
vs
FREQUENCY
VCC = ±5 V
Gain = 2
RF = 1.3 kΩ
RL = 150 Ω
V
O(PP)
CL = 1000 pF
f – Frequency – Hz
Figure 16
= 125 mV
CL = 10 pF
100M
=125 mV
CL = 10 pF
100M
1G10M100k 1M
1G10M100k 1M
16
14
12
10
8
6
4
VCC = ±15 V
2
Gain = 2
Output Amplitude – dB
0
RF = 1.3 kΩ
RL = 150 Ω
–2
V
O(PP)
–4
16
14
12
10
8
6
4
VCC = ±5 V
2
Output Amplitude – dB
Gain = 2
0
RF = 1.3 kΩ
RL = 150 Ω
–2
V
O(PP)
–4
OUTPUT AMPLITUDE
vs
FREQUENCY
CL = 0.01 µF
CL = 100 pF
= 125 mV
f – Frequency – Hz
100M
Figure 14
OUTPUT AMPLITUDE
vs
FREQUENCY
CL = 0.01 µF
= 125 mV
f – Frequency – Hz
CL = 100 pF
100M
Figure 17
1G10M100k 1M
1G10M100k 1M
2
1
0
–1
–2
–3
VCC = ±15 V
–4
Output Amplitude – dB
Gain = –1
RF = 2 kΩ
–5
VO = 0.2 Vrms
–6
OUTPUT AMPLITUDE
vs
FREQUENCY
RL = 1 kΩ
RL = 150 Ω
f – Frequency – Hz
Figure 18
OUTPUT AMPLITUDE
vs
FREQUENCY
10
CL = 0.1 µF
8
6
4
2
0
–2
–4
Output Amplitude – dB
–6
–8
100M10M100k 1M
–10
f – Frequency – Hz
VCC = ±15 V
Gain = –1
RF = 2 kΩ
RL = 150 Ω
V
O(PP)=62 mV
CL = 1000 pF
CL = 10 pF
100M
Output Amplitude – dB
–10
1G10M100k 1M
Figure 19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OUTPUT AMPLITUDE
FREQUENCY
10
8
6
CL = 0.01 µF
4
2
0
–2
VCC = ±15 V
–4
Gain = –1
–6
RF = 2 kΩ
RL = 150 Ω
–8
V
O(PP)=62 mV
f – Frequency – Hz
Figure 20
vs
CL = 100 pF
100M
1G10M100k 1M
7
THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
TYPICAL CHARACTERISTICS
OUTPUT AMPLITUDE
2
1
0
–1
–2
–3
VCC = ±5 V
–4
Output Amplitude – dB
Gain = –1
RF = 2 kΩ
–5
VO = 0.2 Vrms
–6
OUTPUT OVERSHOOT
60
50
40
30
20
Output Overshoot – %
10
0
CAPACITIVE LOAD
VCC = ±15 V & ±5 V
Gain = 1
RF = 200 Ω
RL = 150 Ω
1 10 100
vs
FREQUENCY
RL = 1 kΩ
RL = 150 Ω
f – Frequency – Hz
Figure 21
vs
Capacitive Load – pF
Figure 24
100M10M100k 1M
1 V Step
5 V Step
1k 10k
OUTPUT AMPLITUDE
10
CL = 0.1 µF
8
6
4
2
0
–2
–4
Output Amplitude – dB
–6
–8
–10
OUTPUT OVERSHOOT
CAPACITIVE LOAD
50
VCC = ±15 V & ±5 V
Gain = –1
40
RF = 2 kΩ
RL = 150 Ω
30
20
Output Overshoot – %
10
0
1 10 100
vs
FREQUENCY
VCC = ±5 V
Gain = –1
RF = 2 kΩ
RL = 150 Ω
V
O(PP)=62 mV
CL = 1000 pF
f – Frequency – Hz
100M
Figure 22
vs
1 V Step
5 V Step
Capacitive Load – pF
Figure 25
CL = 10 pF
1k 10k
10
8
6
4
2
0
–2
–4
Output Amplitude – dB
–6
–8
1G10M100k 1M
–10
TOTAL HARMONIC DISTORTION
–40
–50
–60
–70
–80
–90
THD – Total Harmonic Distortion – dB
–100
OUTPUT AMPLITUDE
vs
FREQUENCY
CL = 0.01 µF
VCC = ±5 V
Gain = –1
RF = 2 kΩ
RL = 150 Ω
V
O(PP)=62 mV
f – Frequency – Hz
Figure 23
vs
FREQUENCY
VCC = ±15 V
Gain = 2
V
= 2 V
O(pp)
RL = 150 Ω
f – Frequency – Hz
Figure 26
CL = 100 pF
100M
RL = 1 kΩ
1G10M100k 1M
20M10M100k 1M
–40
–50
–60
–70
Distortion – dB
–80
–90
–100
8
DISTORTION
FREQUENCY
VCC = ±15 V
Gain = 2
RL = 150 Ω
V
= 2 V
O(pp)
2nd Harmonic
f – Frequency – Hz
Figure 27
vs
3rd Harmonic
DISTORTION
vs
FREQUENCY
–40
VCC = ±15 V
Gain = 2
–50
RL = 1 kΩ
V
= 2 V
O(pp)
–60
–70
Distortion – dB
–80
–90
20M10M100k 1M
–100
2nd Harmonic
3rd Harmonic
f – Frequency – Hz
Figure 28
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DISTORTION
vs
FREQUENCY
–40
VCC = ±5 V
Gain = 2
–50
RL = 150 Ω
V
= 2 V
O(pp)
–60
–70
Distortion – dB
–80
–90
20M10M100k 1M
–100
2nd Harmonic
3rd Harmonic
f – Frequency – Hz
20M10M100k 1M
Figure 29
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
TYPICAL CHARACTERISTICS
THS4041, THS4042
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
DISTORTION
vs
FREQUENCY
–40
VCC = ±5 V
Gain = 2
–50
RL = 1 kΩ
V
= 2 V
O(pp)
–60
–70
Distortion – dB
–80
–90
–100
2nd Harmonic
3rd Harmonic
f – Frequency – Hz
20M10M100k 1M
Figure 30
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
0.5
Gain = 2
RF = 1.3 kΩ
40 IRE-NTSC Modulation
0.4
Worst Case ±100 IRE Ramp
0.3
VCC = ±15 V
0.2
Differential Gain – %
0.1
0
12 3
Number of 150-Ω Loads
VCC = ±5 V
Figure 33
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
0.4°
Gain = 2
RF = 1.3 kΩ
0.35°
40 IRE-PAL Modulation
Worst Case ±100 IRE Ramp
0.3°
0.25°
0.2°
0.15°
Differential Phase
0.1°
0.05°
0°
12 3
Number of 150-Ω Loads
VCC = ±15 VVCC = ±5 V
Figure 36
DISTORTION
vs
OUTPUT VOLTAGE
–40
VCC = ±15 V
Gain = 5
–50
RL = 150 Ω
f = 1 MHz
–60
–70
Distortion (dB)
–80
–90
0 5 10 15 20
2nd Harmonic
3rd Harmonic
VO – Output Voltage – V
Figure 31
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
0.4°
Gain = 2
RF = 1.3 kΩ
0.35°
40 IRE-NTSC Modulation
Worst Case ±100 IRE Ramp
0.3°
0.25°
0.2°
0.15°
Differential Phase
0.1°
VCC = ±5 V
0.05°
0°
12 3
Number of 150-Ω Loads
VCC = ±15 V
Figure 34
CLOSED-LOOP
OUTPUT IMPEDANCE
vs
FREQUENCY
100
VCC = ±5 V & ±15 V
Gain = 2
RF = 1 kΩ
10
1
– Output Impedance – Ω
O
Z
0.1
f – Frequency – Hz
1G10M100k 1M 100M
Figure 37
DISTORTION
vs
OUTPUT VOLTAGE
–50
VCC = ±15 V
Gain = 5
RL = 1 kΩ
–60
f = 1 MHz
–70
–80
Distortion (dB)
–90
–100
50101520
VO – Output Voltage – V
2nd Harmonic
3rd Harmonic
Figure 32
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
0.6
Gain = 2
RF = 1.3 kΩ
0.5
40 IRE-PAL Modulation
Worst Case ±100 IRE Ramp
0.4
0.3
0.2
Differential Gain – %
0.1
0
12 3
Number of 150-Ω Loads
VCC = ±15 V
VCC = ±5 V
Figure 35
PSRR
vs
FREQUENCY
80
70
60
50
40
30
20
10
PSRR – Power Supply Rejection Ratio – dB
0
VCC = ±15 V & ±5 V
+VCC & –VCC Responses
f – Frequency – Hz
100M10M100k 1M
Figure 38
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9
THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
TYPICAL CHARACTERISTICS
CMRR
vs
FREQUENCY
90
80
70
60
50
40
30
20
10
0
CMRR – Common Mode Rejection Ratio – dB
VCC = ±15 V & ±5 V
RF = 1 kΩ
V
= 2 V
I(pp)
f – Frequency – Hz
Figure 39
SLEW RATE
vs
FREE-AIR TEMPERATURE
500
RL = 150 Ω
450
400
350
300
SR – Slew Rate – V/µ s
250
200
–20–40 0 20 40 60 80 100
TA – Free-Air Temperature – °C
VCC = ±15 V
V
) = 20 V
O(PP
VCC = ±5 V
V
O(PP
) = 5 V
Figure 42
CROSSTALK
vs
FREQUENCY
–20
VCC = ±15 V & ±5 V
Gain = 2
–30
RF = 2.7 kΩ
RL = 150 Ω
–40
–50
–60
Crosstalk – dB
–70
–80
100M10M100k 1M
–90
f – Frequency – Hz
100M10M100k 1M
Figure 40
SETTING TIME
vs
OUTPUT STEP
300
280
260
240
220
Gain = –1
200
RF = 360 Ω
180
Settling Time – ns
160
140
120
100
VCC = ±15 V & ±5 V
0.1%
12345
VO – Output Step Voltage – V
VCC = ±5 V
0.01%
VCC = ±15 V
0.01%
Figure 43
VOLTAGE & CURRENT NOISE
vs
FREQUENCY
1k
Hz
Hz
100
nV/– Voltage Noise –V
10
– Current Noise – pA/
1
n
n
I
0.10
VCC = ±15 V & ±5 V
TA = 25°C
I
N
100 1k 10k10 100k
f – Frequency – Hz
Figure 41
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
0.0
–0.5
–1.0
–1.5
– Input Offset Voltage – mV
V
VCC = ±15 V
–2.0
IO
–2.5
–20–40 0 20 40 60 80 100
TA – Free-Air Temperature – °C
Figure 44
V
VCC = ±5 V
N
FREE-AIR TEMPERATURE
2.55
2.50
µA
2.45
2.40
2.35
– Input Bias Current –
2.30
IB
I
2.25
–20–40 0 20 40 60 80 100
10
INPUT BIAS CURRENT
vs
VCC = ±5 V & ±15 V
TA – Free-Air Temperature – °C
Figure 45
COMMON-MODE INPUT VOLTAGE
vs
SUPPLY VOLTAGE
15
± V
- Common-Mode Input Voltage –
V
ICR
TA = 25°C
13
11
9
7
5
3
75 9 11 13 15
±VCC – Supply Voltage – V
Figure 46
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OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
14
TA = 25°C
12
V
10
8
6
- Output Voltage -V
O
4
2
±VCC – Supply Voltage – V
RL = 1 kΩ
RL = 150 Ω
75111315
9
Figure 47
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
TYPICAL CHARACTERISTICS
THS4041, THS4042
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
15
13
V
11
9
7
- Output Voltage -V
5
O
3
1
(0.5 V / Div)
– Output Voltage – V
O
V
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VCC = ±15 V
RL = 1 kΩ
–20–40 0 20 40 60 80 100
TA – Free-Air Temperature – °C
VCC = ±15 V
RL = 250 Ω
VCC = ±5 V
RL = 1 kΩ
VCC = ±15 V
RL = 150 Ω
Figure 48
1-V FALLING EDGE
RESPONSE
CL = 0.01 µF
VCC = ±5 V
Gain = 1
R
= 200 Ω
F
R
= 150 Ω
L
CL = 1000 pF
CL = 100 pF
CL = 10 pF
SUPPLY CURRENT
SUPPLY VOLTAGE
10
9
TA = 85°C
8
TA = 25°C
7
TA = –40°C
– Supply Current – mA
CC
6
I
5
75 9 11 13 15
± VCC – Supply Voltage – V
5-V FALLING EDGE
(1 V/Div)
– Output Voltage – V
O
V
vs
Figure 49
RESPONSE
CL = 10 pF
VCC = ±15 V
Gain = 1
RF = 200 Ω
RL = 150 Ω
CL = 1000 pF
CL = 100 pF
1-V FALLING EDGE
RESPONSE
CL = 0.01 µF
(0.5 V / Div)
– Output Voltage – V
O
V
0 50 100 150 200
Figure 50
5-V FALLING EDGE
RESPONSE
(1 V/Div)
– Output Voltage – V
O
V
t – Time – ns
CL = 10 pF
VCC = ±15 V
Gain = 1
R
= 200 Ω
F
R
= 150 Ω
L
CL = 1000 pF
CL = 100 pF
CL = 10 pF
250
VCC = ±5 V
Gain = 1
RF = 200 Ω
RL = 150 Ω
CL = 1000 pF
CL = 100 pF
300
0 50 100 150 200
4
3
2
1
0
–1
– Output Voltage – V
O
–2
V
–3
–4
0 100 200
250
t – Time – ns
Figure 51
5-V AND 1-V STEP
RESPONSE
5–V Step
1–V Step
VCC = ±15 V
Gain = –1
RF = 2 kΩ
RL = 150 Ω
CL = 1000 pF
300 400
t – Time – ns
Figure 54
300 350
0 50 100 150 200
t – Time – ns
Figure 52
5-V AND 1-V STEP
RESPONSE
4
3
2
1
0
–1
– Output Voltage – V
O
–2
V
–3
–4
0 100 200
1–V Step
VCC = ±5 V
Gain = –1
RF = 2 kΩ
RL = 150 Ω
CL = 1000 pF
t – Time – ns
Figure 55
5–V Step
300 400
250
500
0 50 100 150 200
t – Time – ns
Figure 53
CAPACITIVE LOAD
RESPONSE
4
3
2
1
0
–1
– Output Voltage – V
O
–2
V
–3
–4
0.0 0.5 1.0
Gain = –1
VCC = ±15 V
RL = 150 Ω
CL = 0.01 µF
Gain = 1
t – Time – µs
Figure 56
250
1.5 2.0 2.5 3.0
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11
THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
TYPICAL CHARACTERISTICS
4
3
2
1
0
–1
– Output Voltage – V
O
–2
V
–3
–4
0.0 0.5 1.0
CAPACITIVE LOAD
RESPONSE
Gain = –1
VCC = ±5 V
RL = 150 Ω
CL = 0.01 µF
Gain = 1
1.5 2.0 2.5 3.0
t – Time – µs
Figure 57
20-VOLT STEP RESPONSE
15
10
5
0
VCC = ±15 V
Gain = 5
RF = 1.3 kΩ
RL = 150 Ω
0.8
0.6
0.4
0.2
0.0
–0.2
– Output Voltage – V
O
–0.4
V
–0.6
–0.8
1-VOLT STEP RESPONSE
VCC = ±15 V
Gain = 1
RF = 200 Ω
RL = 150 Ω
0 100
200
t – Time – ns
Figure 58
300 400
3
2
1
0
1-VOLT STEP RESPONSE
0.6
0.4
0.2
0.0
–0.2
– Output Voltage – V
O
V
–0.4
–0.6
VCC = ±5 V
Gain = 1
RF = 200 Ω
RL = 150 Ω
0 100
Figure 59
5-V STEP RESPONSE
VCC = ±5 V
Gain = 1
RF = 200 Ω
RL = 150 Ω
200
t – Time – ns
300 400
–5
– Output Voltage – V
O
V
–10
–15
0 200
400
600 1000800
t – Time – ns
Figure 60
–1
– Output Voltage – V
O
V
–2
–3
0 100
t – Time – ns
Figure 61
300200
400
500
12
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THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
APPLICATION INFORMATION
theory of operation
The THS404x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built
using a 30-V , dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing
fTs of several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high
slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 62.
(7) VCC+
(6) OUT
IN– (2)
IN+ (3)
(4) VCC–
NULL (1) NULL (8)
Figure 62. THS4041 Simplified Schematic
noise calculations and noise figure
Noise can cause errors on very small signals. This is especially true when amplifying small signals, where
signal-to-noise ration (SNR) is very important. The noise model for the THS404x is shown in Figure 63. This
model includes all of the noise sources as follows:
• e
= Amplifier internal voltage noise (nV/√Hz)
n
• IN+ = Noninverting current noise (pA/√Hz)
• IN– = Inverting current noise (pA/√Hz)
• e
= Thermal voltage noise associated with each resistor (eRx = 4 kTRx)
Rx
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13
THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
APPLICATION INFORMATION
noise calculations and noise figure (continued)
e
)
Rs
ǒ
IN
)
R
e
ni
The total equivalent input noise density (eni) is calculated by using the following equation:
eni+ǒe
Where:
S
Ǹ
2
Ǔ
n
k = Boltzmann’s constant = 1.380658 × 10
T = Temperature in degrees Kelvin (273 +°C)
RF || RG = Parallel resistance of RF and R
e
n
IN+
IN–
Figure 63. Noise Model
2
Ǔ
R
)ǒIN–
S
Noiseless
+
_
e
Rf
e
Rg
R
G
ǒRFø
R
G
–23
G
R
F
Ǔ
Ǔ
2
)
e
no
4kTRs)
4kTǒRFø
Ǔ
R
G
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV).
R
eno+
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
For more information on noise analysis, please refer to the
Circuits Applications Report
eniAV+
ǒ
e
ni
(literature number SLVA043).
F
)
Ǔ
(noninverting case)
R
G
Noise Analysis
section in
Operational Amplifier
1
14
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THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
APPLICATION INFORMATION
noise calculations and noise figure (continued)
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
ȱ
NF
+
10log
ȧ
ȧ
ǒ
e
Ȳ
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:
ȱ
ȧ
NF
+
10log
ȧ
ȧ
1
ȧ
ȧ
Ȳ
Figure 64 shows the noise figure graph for the THS404x.
e
)
ni
Rs
ȡ
ȧ
Ȣ
2
2
Ǔ
ǒ
ȳ
ȧ
ȧ
ȴ
2
Ǔ
e
)ǒIN
n
40
35
30
25
20
15
Noise Figure (dB)
10
5
0
2
ȣ
)
4kTR
S
SOURCE RESISTANCE
f = 10 kHz
TA = 25°C
100 1k 10k10 100k
Source Resistance – Ω
Ǔ
R
ȧ
S
Ȥ
NOISE FIGURE
vs
ȳ
ȧ
ȧ
ȧ
ȧ
ȧ
ȴ
Figure 64. Noise Figure vs Source Resistance
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15
THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
APPLICATION INFORMATION
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS404x has been internally compensated to maximize its bandwidth and
slew rate performance. Typically when the amplifier is compensated in this manner , capacitive loading directly
on the output will decrease the device’s phase margin, leading to high frequency ringing or oscillations.
However, the THS404x has added internal circuitry that senses a capacitive load and adds extra compensation
to the internal dominant pole. As the capacitive load increases, the amplifier remains stable. But, it is not
uncommon to see a small amount of peaking in the frequency response. There are typically two ways to
compensate for this. The first is to simply increase the gain of the amplifier. This helps by increasing the phase
margin to keep peaking minimized. The second is to place an isolation resistor in series with the output of the
amplifier, as shown in Figure 65. A minimum value of 20 Ω should work well for most applications. For example,
in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance loading
and provides the proper line impedance matching at the source end. For more information about driving
capacitive loads, refer to the
Amp Circuits Application Report
Output Resistance and Capacitance
(literature number: SLOA013).
1.3 kΩ
section of the
Parasitic Capacitance in Op
1.3 kΩ
Input
_
THS404x
+
20 Ω
C
LOAD
Output
Figure 65. Driving a Capacitive Load for Extra Stability
offset nulling
The THS404x has very low input offset voltage for a high-speed amplifier . However, if additional correction is
required, an offset nulling function has been provided on the THS4041. The input offset can be adjusted by
placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply . This
is shown in Figure 66.
VCC+
0.1 µF
+
THS4041
_
16
10 kΩ
0.1 µF
VCC–
Figure 66. Offset Nulling Schematic
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THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
APPLICATION INFORMATION
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
R
F
I
R
G
IB–
+
V
I
R
S
I
IB+
R
VOO+
V
ǒ
IO
Figure 67. Output Offset Voltage Model
1
) ǒ
F
Ǔ
"
I
Ǔ
R
G
IB
–
+
1
) ǒ
R
R
R
ǒ
)
S
V
O
F
Ǔ
"
I
Ǔ
G
IB–RF
optimizing unity gain response
Internal frequency compensation of the THS404x was selected to provide very wideband performance yet still
maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated
in this manner there is usually peaking in the closed loop response and some ringing in the step response for
very fast input edges, depending upon the application. This is because a minimum phase margin is maintained
for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 200 Ω should
be used as shown in Figure 68. Additional capacitance can also be used in parallel with the feedback resistance
if even finer optimization is required.
Input
+
THS404x
_
Output
200 Ω
Figure 68. Noninverting, Unity Gain Schematic
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17
THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high frequency performance of the THS404x, follow proper printed-circuit board high
frequency design techniques. A general set of guidelines is given below. In addition, a THS404x evaluation
board is available to use as a guide for layout or for evaluating the device performance.
D
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D
Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D
Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
D
Short trace runs/compact part placements – Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
D
Surface-mount passive components – Using surface-mount passive components is recommended for high
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
general PowerPAD design considerations
The THS404x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerP AD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted [see Figure 69(a) and Figure 69(b)]. This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see Figure 69(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away
from the thermal pad.
The PowerP AD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerP AD package represents a breakthrough in combining the small area and ease of assembly of the
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
DIE
THS4041, THS4042
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
Side View (a)
DIE
End View (b) Bottom View (c)
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Thermal
Pad
Figure 69. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink this device, the following steps illustrate the recommended
approach.
Thermal pad area (68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils)
Figure 70. PowerPAD PCB Etch and Via Pattern
1. Prepare the PCB with a top side etch pattern as shown in Figure 70. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter . Keep them small
so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS404xDGN IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology . Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however , low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the THS404xDGN package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the THS404xDGN IC is simply placed in position and run through
the solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
19
THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The actual thermal performance achieved with the THS404xDGN in its PowerPAD package depends on the
application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches,
then the expected thermal coefficient, θJA, is about 58.4_C/W. For comparison, the non-PowerPAD version of
the THS404x IC (SOIC) is shown. For a given θJA, the maximum power dissipation is shown in Figure 71 and
is calculated by the following formula:
T
MAX–TA
Where:
ǒ
q
= Maximum power dissipation of THS404x IC (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
= θ
+ θ
JC
CA
P
T
MAX
T
A
θ
JA
PD+
D
θJC= Thermal coefficient from junction to case (°C/W)
θCA= Thermal coefficient from case to ambient air (°C/W)
Ǔ
JA
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
3.5
3
2.5
SOIC Package
High-K Test PCB
θJA = 98°C/W
2
1.5
1
Maximum Power Dissipation – W
NOTE A: Results are with no air flow and PCB size = 3”× 3”
SOIC Package
0.5
Low-K Test PCB
θJA = 167°C/W
0
–40 –20 0 20 40
DGN Package
θJA = 58.4°C/W
2 oz. Trace And Copper Pad
With Solder
TA – Free-Air Temperature – °C
TJ = 150°C
DGN Package
θJA = 158°C/W
2 oz. Trace And
Copper Pad
Without Solder
60 80 100
Figure 71. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerP AD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief,
PowerPAD Thermally Enhanced Package.
This document can be
found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be
ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially mutiamplifier devices. Because these devices have linear output stages (Class A-B), most
of the heat dissipation is at low output voltages with high output currents. Figure 72 to Figure 75 show this effect,
along with the quiescent heat, with an ambient air temperature of 50°C. Obviously , as the ambient temperature
increases, the limit lines shown will drop accordingly. The area under each respective limit line is considered
the safe operating area. Any condition above this line will exceed the amplifier’s limits and failure may result.
When using V
= ±15 V, the SOIC package is severely limited in the amount of heat it can dissipate. The other key factor when
looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely
useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat
dissipation properties of the PowerP AD. The SOIC package, on the other hand, is highly dependent on how it
is mounted on the PCB. As more trace and copper area is placed around the device, θ
heat dissipation capability increases. The currents and voltages shown in these graphs are for the total package.
For the dual amplifier package (THS4042), the sum of the RMS output currents and voltages should be used
to choose the proper package. The graphs shown assume that both amplifier’s outputs are identical.
= ±5 V , there is generally not a heat problem, even with SOIC packages. But, when using V
CC
decreases and the
JA
CC
THS4041
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
200
VCC = ±5 V
Tj = 150°C
180
TA = 50°C
160
140
120
100
SO-8 Package
80
θJA = 167°C/W
Low-K Test PCB
60
40
– Maximum RMS Output Current – mA
O
I
20
||
0
012 3
| VO | – RMS Output Voltage – V
Maximum Output
Current Limit Line
Package With
θJA < = 120°C/W
Safe Operating
Area
45
Figure 72
THS4041
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1000
TJ = 150°C
TA = 50°C
Maximum Output
DGN Package
θJA = 58.4°C/W
100
– Maximum RMS Output Current – mA
O
I
||
10
0369
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
| VO | – RMS Output Voltage – V
Current Limit Line
VCC = ±15 V
SO-8 Package
θJA = 98°C/W
High-K Test PCB
Safe Operating
Area
12 15
Figure 73
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
THS4042
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
200
180
160
140
120
Package With
θJA ≤ 60°C/W
Maximum Output
Current Limit Line
100
80
60
40
– Maximum RMS Output Current – mA
O
I
20
||
0
012 3
SO-8 Package
θJA = 98°C/W
High-K Test PCB
| VO | – RMS Output Voltage – V
Safe Operating Area
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
VCC = ±5 V
TJ = 150°C
TA = 50°C
Both Channels
45
Figure 74
THS4042
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1000
VCC = ±15 V
TJ = 150°C
TA = 50°C
Both Channels
100
Maximum Output
Current Limit Line
22
10
– Maximum RMS Output Current – mA
O
I
||
DGN Package
θJA = 58.4°C/W
Safe Operating Area
1
0369
| VO | – RMS Output Voltage – V
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
Figure 75
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SO-8 Package
θJA = 98°C/W
High-K Test PCB
12 15
THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
APPLICATION INFORMATION
evaluation board
An evaluation board is available for the THS4041 (literature number SLOP219) and THS4042 (literature number
SLOP233). This board has been configured for very low parasitic capacitance in order to realize the full
performance of the amplifier. A schematic of the evaluation board is shown in Figure 76. The circuitry has been
designed so that the amplifier may be used in either an inverting or noninverting configuration. For more
information, please refer to the
evaluation board, contact your local TI sales office or distributor.
THS4041 EVM User’s Guide
VCC+
C3
0.1 µF
R4
1.3 kΩ
or the
+
NULL
THS4042 EVM User’s Guide
C2
6.8 µF
. To order the
IN+
IN–
R3
49.9 Ω
+
THS4041
_
NULL
R2
1.3 kΩ
R1
49.9 Ω
C4
0.1 µF
VCC–
+
Figure 76. THS4041 Evaluation Board
R5
49.9 Ω
OUT
C1
6.8 µF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
23
THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
MECHANICAL INFORMATION
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
14
1
0.069 (1,75) MAX
0.050 (1,27)
A
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.004 (0,10)
8
7
0.010 (0,25)
0.157 (4,00)
0.150 (3,81)
M
0.244 (6,20)
0.228 (5,80)
Seating Plane
0.004 (0,10)
PINS **
DIM
A MAX
A MIN
0.008 (0,20) NOM
Gage Plane
0°–8°
8
0.197
(5,00)
0.189
(4,80)
14
0.344
(8,75)
0.337
(8,55)
0.010 (0,25)
0.044 (1,12)
0.016 (0,40)
4040047/D 10/96
16
0.394
(10,00)
0.386
(9,80)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4041, THS4042
165-MHz C-STABLE HIGH-SPEED AMPLIFIERS
SLOS237B– MA Y 1999 – REVISED FEBRUAR Y 2000
MECHANICAL INFORMATION
DGN (S-PDSO-G8) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,65
8
1
1,07 MAX
3,05
2,95
0,38
0,25
5
3,05
2,95
4
Seating Plane
0,15
0,05
0,25
4,98
4,78
M
0,10
Thermal Pad
(See Note D)
0,15 NOM
0°–6°
Gage Plane
0,25
0,69
0,41
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments Incorporated.
4073271/A 01/98
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
25
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