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+
−
75 Ω
75 Ω
75 Ω
75 Ω
75 Ω
n Lines
V
O(1)
V
O(n)
75-Ω Transmission Line
V
I
1 kΩ
−15 V
15 V
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
VIDEO DISTRIBUTION AMPLIFIER APPLICATION
0
0.05
0.1
0.15
0.2
0.25
0.3
0 1 2 3 4 5 6 7 8
Number of 150 Ω Loads
Differential Gain − %
PAL
NTSC
Gain = 2,
RF = 1 kΩ,
VS = ±15 V,
40 IRE − NTSC and PAL,
Worst Case ±100 IRE Ramp
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0 1 2 3 4 5 6 7 8
Number of 150 Ω Loads
Differential Phase −
PAL
NTSC
Gain = 2,
RF = 1 kΩ,
VS = ±15 V,
40 IRE − NTSC and PAL,
Worst Case ±100 IRE Ramp
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
1 kΩ
查询THS3110供应商
LOW-NOISE, HIGH-VOLTAGE, CURRENT-FEEDBACK,
FEATURES DESCRIPTION
• Low Noise
– 2 pA/ √ Hz Noninverting Current Noise
– 10 pA/ √ Hz Inverting Current Noise
– 3 nV/ √ Hz Voltage Noise
• High Output Current Drive: 260 mA
• High Slew Rate: 1300 V/ µs (R
V
= 8 V
O
)
PP
• Wide Bandwidth: 90 MHz (G = 2, R
• Wide Supply Range: ± 5 V to ± 15 V
• Power-Down Feature: (THS3110 Only)
APPLICATIONS
• Video Distribution
• Power FET Driver
• Pin Driver
• Capacitive Load Driver
= 100 Ω,
L
OPERATIONAL AMPLIFIERS
= 100 Ω)
L
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
The THS3110 and THS3111 are low-noise,
high-voltage, current-feedback amplifiers designed to
operate over a wide supply range of ± 5 V to ± 15 V for
today's high performance applications.
The THS3110 features a power-down pin (PD) that
puts the amplifier in low power standby mode, and
lowers the quiescent current from 4.8 mA to 270 µA.
These amplifiers provide well-regulated ac
performance characteristics. The unity gain
bandwidth of 100 MHz allows for good distortion
characteristics below 10 MHz. Coupled with high
1300-V/ µs slew rate, the THS3110 and THS3111
amplifiers allow for high output voltage swings at high
frequencies.
The THS3110 and THS3111 are offered in a 8-pin
SOIC (D), and the 8-pin MSOP (DGN) packages with
PowerPAD™.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2003, Texas Instruments Incorporated
www.ti.com
1
2
3
4
8
7
6
5
NC
V
IN−
V
IN+
V
S−
NC
V
S+
V
OUT
NC
D, DGNTOP VIEWD, DGNTOP VIEW
NC = No Internal Connection
1
2
3
4
8
7
6
5
REF
V
IN−
V
IN+
V
S−
PD
V
S+
V
OUT
NC
NC = No Internal Connection
THS3110 THS3111
Note: The device with the power down option defaults to the ON state if no signal is applied to the PD pin. Additionallly, the REF pin
functional range is from VS− to (VS+ − 4 V).
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling procedures and installation procedures can cause damage.
AVAILABLE OPTIONS
T
A
0 ° C to 70 ° C BJB
-40 ° C to 85 ° C BIR
0 ° C to 70 ° C BJA
-40 ° C to 85 ° C BIS
(1) Available in tape and reel. The R suffix standard quantity is 2500 (e.g. THS3110CDGNR).
(2) The PowerPAD is electrically isolated from all other pins.
PLASTIC SMALL OUTLINE SOIC (D) PLASTIC MSOP (DGN)
THS3110CD THS3110CDGN
THS3110CDR THS3110CDGNR
THS3110ID THS3110IDGN
THS3110IDR THS3110IDGNR
THS3111CD THS3111CDGN
THS3111CDR THS3111CDGNR
THS3111ID THS3111IDGN
THS3111IDR THS3111IDGNR
PACKAGED DEVICE
(1) (2)
SYMBOL
DISSIPATION RATING TABLE
POWER RATING
TJ= 125 ° C
PACKAGE Θ
(1)
D-8
(2)
DGN-8
(1) This data was taken using the JEDEC standard low-K test PCB. For the JEDEC proposed high-K test PCB, the Θ
power rating at TA= 25 ° C of 1.05 W.
(2) This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 inch x 3 inch PCB. For further information, refer to
the Application Informationsection of this data sheet.
( ° C/W) Θ
JC
38.3 95 1.05 W 421 mW
4.7 58.4 1.71 W 685 mW
( ° C/W)
JA
TA= 25 ° C TA= 85 ° C
2
JA
is 95 ° C/W with
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THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Supply voltage V
Operating free-air temperature, T
A
Operating junction temperature, continuous operating temperature, T
Normal storage temperature, T
stg
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)
Supply voltage, VS-to V
Input voltage, V
Differential input voltage, V
Output current, I
Continuous power dissipation See Dissipation Ratings Table
Maximum junction temperature, T
Maximum junction temperature, continuous operation, long term reliability, T
Operating free-air temperature, T
Storage temperature, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 ° C
ESD ratings:
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under, , recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The THS3110 and THS3111 may incorporate a PowerPAD™ on the underside of the chip. This acts as a heatsink and must be
connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the
PowerPAD™ thermally enhanced package.
(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
S+
I
(2)
O
ID
(3)
J
A
stg
HBM 900
CDM 1500
MM 200
Dual supply ± 5 ± 15
Single supply 10 30
Commercial 0 70
Industrial -40 85
J
-40 125
-40 85
(1)
300 mA
150 ° C
(4)
J
125 ° C
Commercial 0 ° C to 70 ° C
Industrial -40 ° C to 85 ° C
-65 ° C to 125 ° C
UNIT
± 4 V
33 V
± V
S
° C
3
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THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS
VS= ±15 V, RF= 1 k Ω,R
PARAMETER TEST CONDITIONS
AC PERFORMANCE
Small-signal bandwidth, -3 dB
0.1 dB bandwidth flatness G = 2, RF= 1.15 k Ω , VO= 200 mV
Large-signal bandwidth G = 5, RF= 806 Ω , VO= 4 V
Slew rate (25% to 75% level) V/µs TYP
Slew rate 900 V/µs MAX
Rise and fall time G = -5, VO= 10-V step, RF= 806 Ω 8 ns TYP
Settling time to 0.1% G = -2, VO= 2 VPPstep 27
Settling time to 0.01% G = -2, VO= 2 VPPstep 250
Harmonic distortion
2nd Harmonic distortion
3rd Harmonic distortion
Input voltage noise f > 20 kHz 3 nV / √ Hz TYP
Noninverting input current noise f > 20 kHz 2 pA / √ Hz TYP
Inverting input current noise f > 20 kHz 10 pA / √ Hz TYP
Differential gain
Differential phase
DC PERFORMANCE
Transimpedance VO= ± 3.75 V, Gain = 1 1.6 1 0.7 0.7 M Ω MIN
Input offset voltage 1.5 6 8 8 mV MAX
Average offset voltage drift ± 10 ± 10 µV/ ° C TYP
Noninverting input bias current 1 4 6 6 µA MAX
Average bias current drift ± 10 ± 10 nA/ ° C TYP
Inverting input bias current 1.5 15 20 20 µA MAX
Average bias current drift ± 10 ± 10 nA/ ° C TYP
Input offset current 2.5 15 20 20 µA MAX
Average offset current drift ± 30 ± 30 nA/ ° C TYP
INPUT CHARACTERISTICS
Input common-mode voltage range ± 13.3 ± 13 ± 12.5 ± 12.5 V MIN
Common-mode rejection ratio VCM= ± 12.5 V 68 62 60 60 dB MIN
Noninverting input resistance 41 M Ω TYP
Noninverting input capacitance 0.4 pF TYP
OUTPUT CHARACTERISTICS
Output voltage swing V MIN
Output current (sourcing) RL= 25 Ω 260 200 175 175 mA MIN
Output current (sinking) RL= 25 Ω 260 200 175 175 mA MIN
Output impedance f = 1 MHz, Closed loop 0.15 Ω TYP
= 100 Ω, and G = 2 (unless otherwise noted)
L
TYP OVER TEMPERATURE
25 ° C 25 ° C UNIT
G = 1, RF= 1.5 k Ω , VO= 200 mV
G = 2, RF= 1 k Ω , VO= 200 mV
G = 5, RF= 806 Ω , VO= 200 mV
G = 10, RF= 604 Ω , VO= 200 mV
G = 1, VO= 4-V step, RF= 1.5 k Ω 800
G = 2, VO= 8-V step, RF= 1 k Ω 1300
Recommended maximum SR for
repetitive signals
G = 2,
RF= 1 k Ω ,
VO= 2 VPP,
f = 10 MHz
G = 2,
RL= 150 Ω , TYP
RF= 1 k Ω
VCM= 0 V
VCM= 0 V
VCM= 0 V
VCM= 0 V
RL= 1 k Ω ± 13.5 ± 13 ± 12.5 ± 12.5
RL= 100 Ω ± 13.4 ± 12.5 ± 12 ± 12
(1)
PP
PP
PP
PP
PP
PP
RL= 100 Ω 52
RL= 1 k Ω 53
RL= 100 Ω 48
RL= 1 k Ω 68
NTSC 0.011%
PAL 0.013%
NTSC 0.029 °
PAL 0.033 °
100
90
87
66
45
95
0 ° C to -40 ° C to MIN/TYP/
70 ° C 85 ° C MAX
MHz TYP
ns TYP
dBc TYP
(1) For more information, see the Application Information section of this data sheet.
4
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THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
VS= ±15 V, RF= 1 k Ω,R
PARAMETER TEST CONDITIONS
POWER SUPPLY
Specified operating voltage ± 15 ± 16 ± 16 ± 16 V MAX
Maximum quiescent current 4.8 6.5 7.5 7.5 mA MAX
Minimum quiescent current 4.8 3.8 2.5 2.5 mA MIN
Power supply rejection (+PSRR) VS+= 15.5 V to 14.5 V, VS-= 15 V 83 75 70 70 dB MIN
Power supply rejection (-PSRR) VS+= 15 V, VS-= -15.5 V to -14.5 V 78 70 66 66 dB MIN
POWER-DOWN CHARACTERISTICS
Power-down voltage level V MAX
Power-down quiescent current PD = 0V 270 450 500 500 µA MAX
VPDquiescent current µA TYP
Turnon time delay 90% of final value 4
Turnoff time delay 10% of final value 6
Input impedance 3.4 || 1.7 k Ω || pF TYP
= 100 Ω, and G = 2 (unless otherwise noted)
L
Enable, REF = 0 V ≤ 0.8
Power-down , REF = 0 V ≥ 2
VPD= 0 V, REF = 0 V, 11
VPD= 3.3 V, REF = 0 V 11
TYP OVER TEMPERATURE
25 ° C 25 ° C UNIT
0 ° C to -40 ° C to MIN/TYP/
70 ° C 85 ° C MAX
µs TYP
5
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THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS
VS= ±5 V, RF= 1.15 Ω, RL= 100 Ω, and G = 2 (unless otherwise noted)
TYP OVER TEMPERATURE
PARAMETER TEST CONDITIONS
AC PERFORMANCE
G = 1, RF= 1.5 k Ω , VO= 200 mV
Small-signal bandwidth, -3 dB
0.1 dB bandwidth flatness G = 2, RF= 1.15 k Ω , VO= 200 mV
Large-signal bandwidth G = 5, RF= 806 Ω , VO= 4 V
Slew rate (25% to 75% level) V/µs TYP
Slew rate 900 V/µs MAX
Rise and fall time G = -5, VO= 5-V step, RF= 806 Ω 7 ns TYP
Settling time to 0.1% G = -2, VO= 2 VPPstep 20
Settling time to 0.01% G = -2, VO= 2 VPPstep 200
Harmonic distortion
2nd Harmonic distortion
3rd Harmonic distortion
Input voltage noise f > 20 kHz 3 nV / √ Hz TYP
Noninverting input current noise f > 20 kHz 2 pA / √ Hz TYP
Inverting input current noise f > 20 kHz 10 pA / √ Hz TYP
Differential gain
Differential phase
DC PERFORMANCE
Transimpedance VO= ± 1.25 V, Gain = 1 1.6 1 0.7 0.7 M Ω MIN
Input offset voltage 3 6 8 8 mV MAX
Average offset voltage drift ± 10 ± 10 µV/ ° C TYP
Noninverting input bias current 1 4 6 6 µA MAX
Average bias current drift ± 10 ± 10 nA/ ° C TYP
Inverting input bias current 1 8 10 10 µA MAX
Average bias current drift ± 10 ± 10 nA/ ° C TYP
Input offset current 1 6 8 8 µA MAX
Average offset current drift ± 20 ± 20 nA/ ° C TYP
INPUT CHARACTERISTICS
Input common-mode voltage range ± 3.2 ± 2.9 ± 2.8 ± 2.8 V MIN
Common-mode rejection ratio VCM= ± 2.5 V 65 62 58 58 dB MIN
Noninverting input resistance 35 M Ω TYP
Noninverting input capacitance 0.5 pF TYP
OUTPUT CHARACTERISTICS
Output voltage swing V MIN
Output current (sourcing) RL= 10 Ω 220 150 125 125 mA MIN
Output current (sinking) RL= 10 Ω 220 150 125 125 mA MIN
Output impedance f = 1 MHz, Closed loop 0.15 Ω TYP
G = 2, RF= 1.15 k Ω , VO= 200 mV
G = 5, RF= 806 Ω , VO= 200 mV
G = 10, RF= 604 Ω , VO= 200 mV
G = 1, VO= 4-V step, RF= 1.5 k Ω 640
G = 2, VO= 4-V step, RF= 1 k Ω 700
Recommended maximum SR for
repetitive signals
G = 2,
RF= 1 k Ω ,
VO= 2 VPP,
f = 10 MHz
G = 2,
RL= 150 Ω , TYP
RF= 1 k Ω
VCM= 0 V
VCM= 0 V
VCM= 0 V
VCM= 0 V
RL= 1 k Ω ± 4 ± 3.8 ± 3.6 ± 3.6
RL= 100 Ω ± 3.8 ± 3.7 ± 3.5 ± 3.5
(1)
PP
PP
PP
PP
PP
PP
RL= 100 Ω 55
RL= 1 k Ω 56
RL= 100 Ω 45
RL= 1 k Ω 62
NTSC 0.011%
PAL 0.015%
NTSC 0.020 °
PAL 0.033 °
25 ° C 25 ° C UNIT
85
78
80
60
15
80
0 ° C to -40 ° C to MIN/TYP/
70 ° C 85 ° C MAX
MHz TYP
ns TYP
dBc TYP
(1) For more information, see the Application Information section of this data sheet.
6
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THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
VS= ±5 V, RF= 1.15 Ω, RL= 100 Ω, and G = 2 (unless otherwise noted)
TYP OVER TEMPERATURE
PARAMETER TEST CONDITIONS
POWER SUPPLY
Specified operating voltage ± 5 ± 4.5 ± 4.5 ± 4.5 V MIN
Maximum quiescent current 4 6 7 7 mA MAX
Minimum quiescent current 4 3.2 2 2 mA MIN
Power supply rejection (+PSRR) VS+= 5.5 V to 4.5 V, VS-= 5 V 80 72 67 67 dB MIN
Power supply rejection (-PSRR) VS+= 5 V, VS-= -5.5 V to -4.5 V 75 67 62 62 dB MIN
POWER-DOWN CHARACTERISTICS
Power-down voltage level V MAX
Power-down quiescent current PD = 0 V 200 450 500 500 µA MAX
VPDquiescent current µA TYP
Turnon time delay 90% of final value 4
Turnoff time delay 10% of final value 6
Input impedance 3.4 || 1.7 k Ω || pF TYP
Enable, REF = 0 V ≤ 0.8
Power-down , REF = 0 V ≥ 2
VPD= 0 V, REF = 0 V, 11
VPD= 3.3 V, REF = 0 V 11
25 ° C 25 ° C UNIT
0 ° C to -40 ° C to MIN/TYP/
70 ° C 85 ° C MAX
µs TYP
7
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THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
± 15-V graphs
Noninverting small signal gain frequency response 1, 2
Inverting small signal gain frequency response 3
0.1 dB flatness 4
Noninverting large signal gain frequency response 5
Inverting large signal gain frequency response 6
Frequency response capacitive load 7
Recommended R
2nd Harmonic distortion vs Frequency 9
3rd Harmonic distortion vs Frequency 10
Harmonic distortion vs Output voltage swing 11, 12
Slew rate vs Output voltage step 13, 14, 15, 16
Noise vs Frequency 17
Settling time 18, 19
Quiescent current vs Supply voltage 20
Output voltage vs Load resistance 21
Input bias and offset current vs Case temperature 22
Input offset voltage vs Case temperature 23
Transimpedance vs Frequency 24
Rejection ratio vs Frequency 25
Noninverting small signal transient response 26
Inverting large signal transient response 27
Overdrive recovery time 28
Differential gain vs Number of loads 29
Differential phase vs Number of loads 30
Closed loop output impedance vs Frequency 31
Power-down quiescent current vs Supply voltage 32
Turnon and turnoff time delay 33
± 5-V graphs
Noninverting small signal gain frequency response 34
Inverting small signal gain frequency response 35
0.1 dB flatness 36
Noninverting large signal gain frequency response 37
Inverting large signal gain frequency response 38
Slew rate vs Output voltage step 39, 40, 41, 42
2nd Harmonic distortion vs Frequency 43
3rd Harmonic distortion vs Frequency 44
Harmonic distortion vs Output voltage swing 45, 46
Noninverting small signal transient response 47
Inverting small signal transient response 48
Overdrive recovery time 49
Rejection ratio vs Frequency 50
ISO
vs Capacitive load 8
8
www.ti.com
-4
-2
0
2
4
6
8
10
12
14
16
18
20
22
24
100 k 1 M 10 M 100 M 1 G
f - Frequency - Hz
Noninverting Gain - dB
G = 1, RF = 1.5 kΩ
G = 10, RF = 604 Ω
G = 5, RF = 806 Ω
G = 2, RF = 1.15 kΩ
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±15 V
0
1
2
3
4
5
6
7
8
9
1 M 10 M 100 M 1 G
f - Frequency - Hz
Noninverting Gain - dB
RF = 649 Ω
Gain = 2,
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±15 V
RF = 1.15 kΩ
RF = 1.5 kΩ
-4
-2
0
2
4
6
8
10
12
14
16
18
20
22
24
1 M 10 M 100 M 1 G
f - Frequency - Hz
Inverting Gain - dB
G = -10, RF = 649 Ω
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±15 V
G = -1, RF = 1 kΩ
G = -5, RF = 909 Ω
G = -2, RF = 1.1 kΩ
-4
-2
0
2
4
6
8
10
12
14
16
1 M 10 M 100 M 1 G
f - Frequency - Hz
G = -5, RF = 806 Ω
G =-1, RF = 1 kΩ
RL = 100 Ω,
VO = 2 VPP,
VS = ±15 V
Inverting Gain - dB
5.6
5.7
5.8
5.9
6
6.1
6.2
6.3
6.4
100 k 1 M 10 M 100 M
Gain = 2,
RF = 1.15 kΩ,
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±15 V
f - Frequency - Hz
Noninverting Gain - dB
0
2
4
6
8
10
12
14
16
1 M 10 M 100 M 1 G
f - Frequency - Hz
Noninverting Gain - dB
G = 5, RF = 806 Ω
G = 2, RF = 1 kΩ
RL = 100 Ω,
VO = 4 VPP,
VS = ±15 V
0
10
20
30
40
50
60
10 100
C
L
- Capacitive Load - pF
Recommended R Ω
Gain = 5,
RL = 100 Ω,
VS = ±15 V
ISO
-
-2
0
2
4
6
8
10
12
14
16
10 M 100 M
Capacitive Load - MHz
Signal Gain - dB
Gain = 5,
RL = 100 Ω
VS = ±15 V
R
(ISO)
= 39.2 Ω
CL = 47 pF
R
(ISO)
= 28 Ω
CL = 100 pF
R
(ISO)
= 54.9 Ω
CL = 10 pF
R
(ISO)
= 54.9 Ω, CL = 22 pF
200 M
‘
-90
-80
-70
-60
-50
-40
-30
1 M 10 M 100 M
f - Frequency - Hz
2nd Harmonic Destortion - dBc
VO = 2 VPP,
RL = 100 Ω,
VS = ±15 V
100 k
-100
G = -2, RF = 1 kΩ
RL = 1 kΩ,
G = 5, RF = 806 Ω
G = 2, RF = 1 kΩ
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS ( ±15 V)
NONINVERTING SMALL SIGNAL NONINVERTING SMALL SIGNAL INVERTING SMALL SIGNAL
FREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE
Figure 1. Figure 2. Figure 3.
0.1 dB FLATNESS FREQUENCY RESPONSE FREQUENCY RESPONSE
NONINVERTING LARGE SIGNAL INVERTING LARGE SIGNAL
Figure 4. Figure 5. Figure 6.
FREQUENCY RESPONSE vs vs
RECOMMENDED R
ISO
2nd HARMONIC DISTORTION
CAPACITIVE LOAD Capacitive LOAD FREQUENCY
Figure 7. Figure 8. Figure 9.
9
www.ti.com
-100
-95
-90
-85
-80
-75
-70
0 1 2 3 4 5 6 7 8 9 10
Harmonic Distortion - dBc
VO - Output Voltage Swing - V
PP
Gain = 2,
RF = 1 kΩ,
RL = 100Ω,
f= 1 MHz
VS = ±15 V
HD3
HD2
-70
-65
-60
-55
-50
-45
-40
0 1 2 3 4 5 6 7 8 9 10
Harmonic Distortion - dBc
VO - Output Voltage Swing - V
PP
Gain = 2,
RF = 1 kΩ,
RL = 100 Ω,
f = 8 MHz
VS = ±15 V
HD3
HD2
-90
-80
-70
-60
-50
-40
-30
1 M 10 M 100 M
f - Frequency - Hz
2nd Harmonic Destortion - dBc
VO = 2 VPP,
RL = 100 Ω,
VS = ±15 V
100 k
-100
G = -2,
RF = 1 kΩ
RL = 1 kΩ,
G = 5, RF = 806 Ω
G = 2,
RF = 1 kΩ
0
200
400
600
800
1000
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
SR - Slew Rate - V/
V
O
- Output Voltage -V
PP
sµ
Gain = 1
RL = 100 Ω
RF = 1.5 kΩ
VS = ±15 V
Fall
Rise
0
200
400
600
800
1000
1200
1400
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
SR - Slew Rate - V/
V
O
- Output Voltage -V
PP
sµ
Fall
Rise
Gain = 1
RL = 1 kΩ
R
F
= 1.5 kΩ
VS = ±15 V
0
200
400
600
800
1000
1200
1400
0 1 2 3 4 5 6 7 8 9 10
SR - Slew Rate - V/
V
O
- Output Voltage -V
PP
sµ
Fall
Rise
Gain = 2
R
L
=100 Ω
RF =1 kΩ
VS = ±15 V
-1.5
-1
-0.5
0
0.5
1
1.5
0 2 4 6 8 10 12 14 16 18
t - Time - ns
- Output Voltage - VV
O
Gain = -2
RL = 100 Ω
RF = 1.1 kΩ
VS = ±15 V
Rising Edge
Falling Edge
0
200
400
600
800
1000
1200
1400
1600
0 1 2 3 4 5 6 7 8 9
10
SR - Slew Rate - V/
V
O
- Output Voltage -V
PP
sµ
Fall
Rise
Gain = 2
R
L
=1 kΩ
RF =1 kΩ
VS = ±15 V
1
10
100
10 100 1 k 10 k 100 k
f - Frequency - Hz
- Current Noise -
V
n
I
n
- Voltage Noise -
pA/ Hz
nV/ Hz
I
n+
V
n
I
n-
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS ( ±15 V) (continued)
3rd HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING
Figure 10. Figure 11. Figure 12.
SLEW RATE SLEW RATE SLEW RATE
vs vs vs
OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP
OUTPUT VOLTAGE STEP FREQUENCY SETTLING TIME
10
Figure 13. Figure 14. #IMPLIED #IMPLIED.
SLEW RATE NOISE
vs vs
#IMPLIED #IMPLIED. Figure 15. Figure 16.
www.ti.com
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
3
0 2 4 6 8 10 12 14 16 18 20
t - Time - ns
- Output Voltage - VV
O
Gain = -2
RL = 100 Ω
RF = 1.1 kΩ
VS = ±15 V
Rising Edge
Falling Edge
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
10 100 1000
R
L
- Load Resistance - Ω
- Output Voltage - VV
O
VS = ±15 V
TA = -40° to 85°C
0
1
2
3
4
5
6
2 3 4 5 6 7 8 9 10 11 12 13 14 15
- Quiescent Current - mAI
Q
VS - Supply Voltage - ±V
TA = 25 °C
TA = -40 °C
TA = 85 °C
-40
0
0.5
1
1.5
2
2.5
3
3.5
4
-30-20-10 0 10 20 30 40 50 60 70 80 90
VS = ±5 V
VS = ±15 V
T
C
- Case Temperature - °C
- Input Offset Voltage - mV
V
OS
0
0.5
1
1.5
2
2.5
3
3.5
-40 -30-20 -10 0 10 20 30 40 50 60 70 80 90
- Input Bias Current -
TC - Case Temperature - °C
VS = ±15 V
- Input Offset Current -
I
IB-
I
IB
Aµ
I
OS
Aµ
I
IB+
I
OS
0
20
40
60
80
100
120
100 k 1 M 10 M 100 M 1 G
Transimpedance Gain - dB Ohms
f - Frequency - Hz
VS = ±15 V
VS = ±5 V
0 10 20 30 40 50 60 70 80
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
t - Time - ns
- Output Voltage - VV
O
Output
Input
Gain = -5,
RL = 100 Ω,
RF = 909 Ω,
VS = ±15 V
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0 10 20 30 40 50 60 70 80
t - Time - ns
- Output Voltage - VV
O
Output
Input
Gain = 2,
RL = 100 Ω,
RF = 1 kΩ,
VS = ±15 V
0
10
20
30
40
50
60
100 k
1 M
10 M
100 M
70
CMRR
VS = ±15 V
Rejection Ratio - dB
f - Frequency - Hz
PSRR-
PSRR+
TYPICAL CHARACTERISTICS ( ±15 V) (continued)
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
QUIESCENT CURRENT OUTPUT VOLTAGE
vs vs
SETTLING TIME SUPPLY VOLTAGE LOAD RESISTANCE
Figure 17. #IMPLIED #IMPLIED. Figure 18.
INPUT BIAS AND
OFFSET CURRENT INPUT OFFSET VOLTAGE TRANSIMPEDANCE
vs vs vs
CASE TEMPERATURE CASE TEMPERATURE FREQUENCY
Figure 19. Figure 20. Figure 21.
REJECTION RATIO
vs NONINVERTING SMALL SIGNAL INVERTING LARGE SIGNAL
FREQUENCY TRANSIENT RESPONSE TRANSIENT RESPONSE
Figure 22. Figure 23. Figure 24.
11
www.ti.com
-20
-15
-10
-5
0
5
10
15
20
0 0.2 0.4 0.6 0.8 1
-5
-2.5
0
2.5
5
t - Time - µs
- Input Voltage - VV
I
Gain = 4,
RL = 100 Ω,
RF = 681 Ω,
VS = ±15 V
- Output Voltage - VV
O
0
0.05
0.1
0.15
0.2
0.25
0.3
0 1 2 3 4 5 6 7 8
Number of 150 Ω Loads
Differential Gain - %
PAL
NTSC
Gain = 2,
RF = 1 kΩ,
VS = ±15 V,
40 IRE - NTSC and PAL,
Worst Case ±100 IRE Ramp
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0 1 2 3 4 5 6 7 8
Number of 150 Ω Loads
Differential Phase -
PAL
NTSC
Gain = 2,
RF = 1 kΩ,
VS = ±15 V,
40 IRE - NTSC and PAL,
Worst Case ±100 IRE Ramp
−0.5
0
0.5
1
1.5
0 0.1 0.2 0.3 0.4 0.5
−1
0
1
2
3
4
5
6
t − Time − ms
− Output Voltage Level − VV
O
Powerdown Pulse
PowerDown Pulse − V
Output Voltage
0.6 0.7
Gain = 5,
VI = 0.1 Vdc
RL = 100 Ω
VS = ±15 V and ±5 V
0
50
100
150
200
250
300
350
3 5 7 9 11 13 15
TA = -40°C
V
S
- Supply Voltage - ±V
Powerdown Quiescent Current -
TA = 85°C
Aµ
TA = 25°C
0.01
0.1
1
10
100
100 k 1 M 10 M 100 M 1 G
f - Frequency - Hz
Gain = 2,
RF = 1 kΩ,
RF = 100 Ω,
VS = ±15 V
Z
O
- Closed-Loop Output Impedance -
Ω
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS ( ±15 V) (continued)
DIFFERENTIAL GAIN DIFFERENTIAL PHASE
vs vs
OVERDRIVE RECOVERY TIME NUMBER OF LOADS NUMBER OF LOADS
Figure 25. Figure 26. Figure 27.
CLOSED-LOOP OUTPUT POWER-DOWN QUIESCENT
IMPEDANCE CURRENT
vs vs TURNON AND TURNOFF
FREQUENCY SUPPLY VOLTAGE TIME DELAY
12
#IMPLIED #IMPLIED. Figure 28. Figure 29.
www.ti.com
100 M
-4
-2
0
2
4
6
8
10
12
14
16
18
20
22
24
1 M 10 M 1 G
f - Frequency - Hz
Inverting Gain - dB
G = -1, RF = 1 kΩ
G = -10, RF = 649 Ω
G = -5, RF = 909 Ω
G = -2, RF = 1.1 kΩ
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±5 V
100 M
−4
−2
0
2
4
6
8
10
12
14
16
18
20
22
24
1 M 10 M 1 G
f − Frequency − Hz
Noninverting Gain − dB
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±5 V
G = 10, RF = 604 Ω
G = 5, RF = 806 Ω
G = 2, RF = 1.15 kΩ
G = 1, RF = 1.5 kΩ
5.6
5.7
5.8
5.9
6
6.1
6.2
6.3
6.4
100 k
1 M
10 M 100 M
Gain = 2,
RF = 1.15 kΩ,
RL = 100 Ω,
VO = 0.2 VPP,
VS = ±5 V
f - Frequency - Hz
Noninverting Gain - dB
-4
-2
0
2
4
6
8
10
12
14
16
1
10 M 100 M 1 G
f - Frequency - Hz
G = -5, RF = 909 Ω
G =-12, RF = 1 kΩ
VO = 2 VPP,
RL = 100 Ω,
VS = ±5 V
Inverting Gain - dB
0
2
4
6
8
10
12
14
16
1 M 10 M 100 M 1 G
f - Frequency - Hz
Noninverting Gain - dB
G = 5, RF = 806 Ω
G = 2, RF = 1.15 kΩ
VO = 4 VPP,
RL = 100 Ω,
VS = ±5 V
0
100
200
300
400
500
600
700
800
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
SR - Slew Rate - V/
V
O
- Output Voltage -V
PP
sµ
Gain = 1
RL = 100 Ω
RF = 1.5 kΩ
VS = ±5 V
Fall
Rise
0
100
200
300
400
500
600
700
800
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
SR - Slew Rate - V/
V
O
- Output Voltage -V
PP
sµ
Gain = 1
RL = 1 kΩ
RF = 1.5 kΩ
VS = ±5 V
Fall
Rise
0
100
200
300
400
500
600
700
800
0 1 2 3 4 5 6
SR - Slew Rate - V/
V
O
- Output Voltage -V
PP
sµ
Gain = 2
RL = 1 kΩ
RF = 1 kΩ
VS = ±5 V
Fall
Rise
0
100
200
300
400
500
600
700
800
0 1 2 3 4 5 6
SR - Slew Rate - V/
V
O
- Output Voltage -V
PP
sµ
Gain = 2
RL = 100 Ω
RF = 1 kΩ
VS = ±5 V
Fall
Rise
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS ( ±5 V)
NONINVERTING SMALL SIGNAL INVERTING SMALL SIGNAL
FREQUENCY RESPONSE FREQUENCY RESPONSE 0.1 dB FLATNESS
Figure 30. Figure 31. Figure 32.
THS3110, THS3111
NONINVERTING LARGE SIGNAL INVERTING LARGE SIGNAL vs
SLEW RATE
FREQUENCY RESPONSE FREQUENCY RESPONSE OUTPUT VOLTAGE STEP
#IMPLIED #IMPLIED. #IMPLIED #IMPLIED. Figure 33.
SLEW RATE SLEW RATE SLEW RATE
vs vs vs
OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP
Figure 34. #IMPLIED #IMPLIED. #IMPLIED #IMPLIED.
13
www.ti.com
-100
-95
-90
-85
-80
-75
-70
-65
0 1 2 3 4 5 6 7
Harmonic Distortion - dBc
VO - Output Voltage Swing - V
PP
HD2
Gain = 2,
RF = 1.15 kΩ
RL = 100 Ω,
f= 1 MHz
VS = ±5 V
HD3
-90
-80
-70
-60
-50
-40
-30
1 M 10 M 100 M
f - Frequency - Hz
2nd Harmonic Destortion - dBc
VO = 2 VPP,
RL = 100 Ω,
VS = ±5 V
100 k
-100
G = -2, RF = 1 kΩ
RL = 1 kΩ,
G = 5, RF = 681 Ω
G = 2, RF = 681 Ω
-90
-80
-70
-60
-50
-40
-30
1 M 10 M 100 M
f - Frequency - Hz
2nd Harmonic Destortion - dBc
VO = 2 VPP,
RL = 100 Ω,
VS = ±5 V
100 k
-100
G = -2, RF = 1 kΩ
RL = 1 kΩ,
G = 5,
RF = 681 Ω
G = 2,
RF = 681 Ω
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0 10 20 30 40 50 60 70 80
t - Time - ns
- Output Voltage - VV
O
Gain = 2
RL = 100 Ω
R
F
= 1.15 kΩ
VS = ±5 V
Input
Output
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
3
0 10 20 30 40 50 60 70 80
t - Time - ns
- Output Voltage - VV
O
Output
Input
Gain = -5,
RL = 100 Ω,
RF = 909 Ω,
VS = ±5 V
-90
-80
-70
-60
-50
-40
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Harmonic Distortion - dBc
VO - Output Voltage Swing - V
PP
HD2
Gain = 2,
RF = 1 kΩ
RL = 100 Ω,
f= 8 MHz
VS = ±5 V
HD3
-5
-4
-3
-2
-1
0
1
2
3
4
5
0.2 0.4 0.6 0.8 1
-1.25
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
1.25
t - Time - µs
- Input Voltage - VV
I
Gain = 4,
RL = 100 Ω,
RF = 909 Ω,
VS = ±5 V
- Output Voltage - VV
O
0
0
10
20
30
40
50
60
70
100 k 1 M 10 M 100 M
VS = ±5 V
Rejection Ratio - dB
f - Frequency - Hz
PSRR-
CMRR
PSRR+
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS ( ±5 V) (continued)
2nd HARMONIC DISTORTION 3rd HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY FREQUENCY OUTPUT VOLTAGE SWING
Figure 35. Figure 36. Figure 37.
HARMONIC DISTORTION
vs NONINVERTING SMALL SIGNAL INVERTING LARGE SIGNAL
OUTPUT VOLTAGE SWING TRANSIENT RESPONSE TRANSIENT RESPONSE
14
Figure 38. Figure 39. Figure 40.
REJECTION RATIO
vs
OVERDRIVE RECOVERY TIME FREQUENCY
Figure 41. Figure 42.
www.ti.com
_
+
THS3110
R
F
1 kΩ
49.9 Ω
0.1 µF 6.8 µF
-V
S
-15 V
R
G
50 Ω Source
+
V
I
0.1 µF 6.8 µF
+
+V
S
15 V
49.9 Ω
50 Ω LOAD
1 kΩ
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
APPLICATION INFORMATION
MAXIMUM SLEW RATE FOR REPETITIVE
SIGNALS
The THS3110 and THS3111 are recommended for
high slew rate pulsed applications where the internal
nodes of the amplifier have time to stabilize between
pulses. It is recommended to have at least 20-ns
delay between pulses.
The THS3110 and THS3111 are not recommended
for applications with repetitive signals (sine, square,
sawtooth, or other) that exceed 900 V/ µ s. Using the
part in these applications results in excessive current
draw from the power supply and possible device
damage.
For applications with high slew rate, repetitive signals,
the THS3091 and THS3095 (single), or THS3092 and
THS3096 (dual) are recommended.
WIDEBAND, NONINVERTING OPERATION
The THS3110 and THS3111 are unity gain stable
100-MHz current-feedback operational amplifiers, designed to operate from a ± 5-V to ± 15-V power supply.
Figure 43 shows the THS3111 in a noninverting gain
of 2-V/V configuration typically used to generate the
performance curves. Most of the curves were
characterized using signal sources with 50- Ω source
impedance, and with measurement equipment presenting a 50- Ω load impedance.
Current-feedback amplifiers are highly dependent on
the feedback resistor R
for maximum performance
F
and stability. Table 1 shows the optimal gain setting
resistors R
and R
F
at different gains to give maxi-
G
mum bandwidth with minimal peaking in the
frequency response. Higher bandwidths can be
achieved, at the expense of added peaking in the
frequency response, by using even lower values for
RF. Conversely, increasing R
decreases the
F
bandwidth, but stability is improved.
Table 1. Recommended Resistor Values for
Optimum Frequency Response
THS3110 and THS3111 RFand RGvalues for minimal peaking
GAIN (V/V) RG( Ω) RF( Ω)
1
2
5
10
-1
-2 ± 15 and ± 5 549 1.1 k
-5 ± 15 and ± 5 182 909
-10 ± 15 and ± 5 64.9 649
with RL= 100 Ω
SUPPLY VOLTAGE
(V)
± 15 -- 1.5 k
± 5 -- 1.5 k
± 15 1 k 1 k
± 5 1.15 k 1.15 k
± 15 200 806
± 5 200 806
± 15 66.5 604
± 5 66.5 604
± 15 1 k 1 k
± 5 1 k 1 k
Figure 43. Wideband, Noninverting Gain
Configuration
15
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_
+
THS3110
49.9 Ω
50 Ω Source
V
I
+V
S
R
F
1 kΩ
R
G
1 kΩ
+V
S
2
+V
S
2
_
+
THS3110
549 Ω
50 Ω Source
V
I
V
S
R
F
1.1 kΩ
+V
S
2
+V
S
2
56.2 Ω
R
G
R
T
R
T
49.9 Ω
49.9 Ω
50 Ω LOAD
50 Ω LOAD
_
+
THS3110
R
G
549 Ω
0.1 µF 6.8 µF
-V
S
-15 V
50 Ω Source
+
V
I
0.1 µF 6.8 µF
+
+V
S
15 V
R
F
1.1 kΩ
R
M
56.2 Ω
49.9 Ω
50 Ω LOAD
+
-
75 Ω
75 Ω
75 Ω
75 Ω
75 Ω
n Lines
V
O(1)
V
O(n)
75-Ω Transmission Line
V
I
1 kΩ
-15 V
15 V
1 kΩ
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
WIDEBAND, INVERTING OPERATION
Figure 44 shows the THS3111 in a typical inverting
gain configuration where the input and output impedances and signal gain from Figure 43 are retained
in an inverting circuit configuration.
Figure 44. Wideband, Inverting Gain
Configuration
SINGLE SUPPLY OPERATION
The THS3110 and THS3111 have the capability to
operate from a single supply voltage ranging from
10 V to 30 V. When operating from a single power
supply, biasing the input and output at mid-supply
allows for the maximum output voltage swing. The
circuits shown in Figure 45 shows inverting and
noninverting amplifiers configured for single supply
operations.
16
Figure 45. DC-Coupled, Single-Supply Operation
Video Distribution
The wide bandwidth, high slew rate, and high output
drive current of the THS3110 and THS3111 matches
the demands for video distribution for delivering video
signals down multiple cables. To ensure high signal
quality with minimal degradation of performance, a
0.1-dB gain flatness should be at least 7x the
passband frequency to minimize group delay variations from the amplifier. A high slew rate minimizes
distortion of the video signal, and supports
component video and RGB video signals that require
fast transition times and fast settling times for high
signal quality.
Figure 46. Video Distribution Amplifier
Application
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0
10
20
30
40
50
60
10 100
C
L
- Capacitive Load - pF
Recommended R Ω
Gain = 5,
RL = 100 Ω,
VS = ±15 V
ISO
-
_
+
V
S
-V
S
49.9 Ω
806 Ω
5.11 Ω
1 µF
200 Ω
V
S
100 Ω LOAD
R
ISO
_
+
V
S
-V
S
49.9 Ω
5.11 Ω
1 µF
200 Ω
V
S
27 pF
806 Ω
R
F
R
G
750 Ω
100 Ω LOAD
R
IN
_
+
V
S
-V
S
49.9 Ω
806 Ω
Ferrite Bead
1 µF
200 Ω
V
S
100 Ω LOAD
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
Driving Capacitive Loads
Applications, such as FET drivers and line drivers can
be highly capacitive and cause stability problems for
high-speed amplifiers.
Figure 47 through Figure 53 show recommended
methods for driving capacitive loads. The basic idea
is to use a resistor or ferrite chip to isolate the phase
shift at high frequency caused by the capacitive load
from the amplifier’s feedback path. See Figure 47 for
recommended resistor values versus capacitive load.
Figure 47. Recommended R
vs Capacitive Load
ISO
Placing a small series resistor, R
, between the
ISO
amplifier’s output and the capacitive load, as shown
in Figure 48 , is an easy way of isolating the load
capacitance.
Using a ferrite chip in place of R
, as shown in
ISO
Figure 49 , is another approach of isolating the output
of the amplifier. The ferrite's impedance characteristic
versus frequency is useful to maintain the low frequency load independence of the amplifier while
isolating the phase shift caused by the capacitance at
high frequency. Use a ferrite with similar impedance
to R
, 20 Ω - 50 Ω, at 100 MHz and low impedance
ISO
at dc.
Figure 50 shows another method used to maintain
the low frequency load independence of the amplifier
while isolating the phase shift caused by the capacitance at high frequency. At low frequency, feedback
is mainly from the load side of R
. At high fre-
ISO
quency, the feedback is mainly via the 27-pF capacitor. The resistor R
in series with the negative input
IN
is used to stabilize the amplifier and should be equal
to the recommended value of R
Replacing R
with a ferrite of similar impedance at
IN
F
at unity gain.
about 100 MHz as shown in Figure 51 gives similar
results with reduced dc offset and low frequency
noise. (See the ADDITIONAL REFERENCE MA-
TERIAL section for expanding the usability of cur-
rent-feedback amplifiers.)
Figure 48.
Figure 49.
Figure 50.
17
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_
+
V
S
-V
S
49.9 Ω
5.11 Ω
1 µF
200 Ω
V
S
27 pF
806 Ω
R
F
R
G
FB
100 Ω LOAD
F
IN
_
+
V
S
-V
S
_
+
V
S
-V
S
-V
S
V
S
301 Ω
301 Ω
66.5 Ω
5.11 Ω
5.11 Ω
_
+
V
S
-V
S
806 Ω
5.11 Ω
200 Ω
V
S
_
+
V
S
-V
S
806 Ω
5.11 Ω
200 Ω
24.9 Ω
24.9 Ω
1 nF
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
Figure 51.
Figure 52 is shown using two amplifiers in parallel to
double the output drive current to larger capacitive
loads. This technique is used when more output
current is needed to charge and discharge the load
faster like when driving large FET transistors.
Figure 52.
Figure 53 shows a push-pull FET driver circuit typical
of ultrsound applications with isolation resistors to
isolate the gate capacitance from the amplifier.
18
Figure 53. PowerFET Drive Circuit
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY AND SETTING
THRESHOLD LEVELS WITH THE
REFERENCE PIN
The THS3110 features a power-down pin (PD) which
lowers the quiescent current from 4.8 mA down to
270 µA, ideal for reducing system power.
The power-down pin of the amplifier defaults to the
negative supply voltage in the absence of an applied
voltage, putting the amplifier in the power-on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the positive rail. The threshold voltages for
power-on and power-down are relative to the supply
rails and are given in the specification tables. Below
the Enable Threshold Voltage, the device is on.
Above the Disable Threshold Voltage, the device is
off. Behavior in between these threshold voltages is
not specified.
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
Figure 54 shows the total system output impedance
which includes the amplifier output impedance in
parallel with the feedback plus gain resistors, which
cumulate to 1870 Ω . Figure 43 shows this circuit
configuration for reference.
www.ti.com
0
200
400
600
800
1000
1200
1400
1600
1800
2000
100 k 1 M 10 M 100 M 1 G
f - Frequency - Hz
Powerdown Output Impedance - Ω
Gain = 2
RF = 1 kΩ
VS = ±15 V and ±5 V
Figure 54. Power-down Output Impedance vs
As with most current feedback amplifiers, the internal
architecture places some limitations on the system
when in power-down mode. Most notably is the fact
that the amplifier actually turns ON if there is a ± 0.7 V
or greater difference between the two input nodes
(V+ and V-) of the amplifier. If this difference exceeds
± 0.7 V, the output of the amplifier creates an output
voltage equal to approximately
[(V+ - V-) -0.7 V] × Gain. This also implies that if a
voltage is applied to the output while in power-down
mode, the V- node voltage is equal to
V
O(applied)
× R
and a large applied voltage at the output, the amplifier may actually turn ON due to the aforementioned
behavior.
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach either 10% or 90% of the final
output voltage. The time delays are in the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
POWER-DOWN REFERENCE PIN
OPERATION
In addition to the power-down pin, the THS3110 also
features a reference pin (REF) which allows the user
to control the enable or disable power-down voltage
levels applied to the PD pin. In most split-supply
applications, the reference pin is connected to
ground. In either case, the user needs to be aware of
voltage level thresholds that apply to the power-down
pin. The usable range at the REF pin is from V
(V
- 4 V)
S+
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
Achieving optimum performance with high frequency
amplifier, like the THS3110 and THS3111, requires
careful attention to board layout parasitic and external
component types.
Recommendations that optimize performance include:
• Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
Frequency
/(R
+ RG). For low gain configurations
G
F
to
S-
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
• Minimize the distance (< 0.25”) from the power
supply pins to high frequency 0.1- µF and 100-pF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors.
Larger (6.8 µF or more) tantalum decoupling
capacitors, effective at lower frequency, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PC board.
• Careful selection and placement of external
components preserve the high frequency performance of the THS3110 and THS3111. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a
tighter overall layout. Again, keep their leads and
PC board trace length as short as possible.
Never use wirebound type resistors in a high
frequency application. Since the output pin and
inverting input pins are the most sensitive to
parasitic capacitance, always position the
feedback and series output resistors, if any, as
close as possible to the inverting input pins and
output pins. Other network components, such as
input termination resistors, should be placed
close to the gain-setting resistors. Even with a
low parasitic capacitance shunting the external
resistors, excessively high resistor values can
create significant time constants that can degrade
performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF
in shunt with the resistor. For resistor values >
2.0 k Ω, this parasitic capacitance can add a pole
and/or a zero that can effect circuit operation.
Keep resistor values as low as possible, consistent with load driving considerations.
19
www.ti.com
DIE
Side View (a)
DIE
End View (b)
Thermal
Pad
Bottom View (c)
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
• Connections to other wideband devices on the almost impossible to achieve a smooth, stable
board may be made with short direct traces or frequency response. Best results are obtained by
through onboard transmission lines. For short soldering the THS3110 / THS3111 parts directly
connections, consider the trace and the input to onto the board.
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and determine if isolation
resistors on the outputs are necessary. Low
parasitic capacitive loads (< 4 pF) may not need
an R
since the THS3110 and THS3111 are
S
nominally compensated to operate with a 2-pF
parasitic load. Higher parasitic capacitive loads
without an RS are allowed as the signal gain
increases (increasing the unloaded phase margin). If a long trace is required, and the 6-dB
signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched
impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50- Ω environment is not necessary
onboard, and in fact, a higher impedance environment improves distortion as shown in the
distortion versus load plots. With a characteristic
board trace impedance based on board material
and trace dimensions, a matching series resistor
into the trace from the output of the THS3110 /
THS3111 is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and
the input impedance of the destination device:
this total effective impedance should be set to
match the trace impedance. If the 6-dB attenuation of a doubly terminated transmission line is
unacceptable, a long trace can be
series-terminated at the source end only. Treat
the trace as a capacitive load in this case. This
does not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of
the destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
• Socketing a high speed part like the THS3110
and THS3111 is not recommended. The additional lead length and pin-to-pin capacitance
introduced by the socket can create an extremely
troublesome parasitic network which can make it
PowerPAD ™ DESIGN CONSIDERATIONS
The THS3110 and THS3111 are available in a
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
leadframe upon which the die is mounted [see
Figure 55 (a) and Figure 55 (b)]. This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package [see Figure 55 (c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal performance can be achieved by providing a good
thermal path away from the thermal pad. Note that
devices such as the THS311x have no electrical
connection between the PowerPAD and the die.
The PowerPAD package allows for both assembly
and thermal management in one manufacturing operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
Figure 55. Views of Thermal Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
20
www.ti.com
0.060
0.040
0.075 0.025
0.205
0.010
vias
Pin 1
Top V iew
0.017
0.035
0.094
0.030
0.013
Figure 56. DGN PowerPAD PCB Etch and Via
Pattern
PowerPAD ™ LAYOUT CONSIDERATIONS
1. PCB with a top side etch pattern as shown in
Figure 56 . There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad.
These holes should be 10 mils in diameter. Keep
them small so that solder wicking through the
holes is not a problem during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. This helps dissipate the heat generated by
the THS3110 / THS3111 IC. These additional
vias may be larger than the 10-mil diameter vias
directly under the thermal pad. They can be
larger because they are not in the thermal pad
area to be soldered so that wicking is not a
problem.
4. Connect all holes to the internal ground plane.
Note that the PowerPAD is electrically isolated
from the silicon and all leads. Connecting the
PowerPAD to any potential voltage such as V
is acceptable as there is no electrical connection
to the silicon.
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This makes the soldering of
vias that have plane connections easier. In this
application, however, low thermal resistance is
desired for the most efficient heat transfer. Therefore, the holes under the THS3110 / THS3111
PowerPAD package should make their connection to the internal ground plane with a complete
connection around the entire circumference of the
plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area
with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This prevents solder from
being pulled away from the thermal pad area
during the reflow process.
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that
is properly installed.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The THS3110 and THS3111 incorporates automatic
thermal shutoff protection. This protection circuitry
shuts down the amplifier if the junction temperature
exceeds approximately 160 ° C. When the junction
temperature reduces to approximately 140 ° C, the
amplifier turns on again. But, for maximum performance and reliability, the designer must take care to
ensure that the design does not exeed a junction
temperature of 125 ° C. Between 125 ° C and 150 ° C,
damage does not occur, but the performance of the
amplifier begins to degrade and long term reliability
suffers. The thermal characteristics of the device are
dictated by the package and the PC board. Maximum
,
S-
power dissipation for a given package can be calculated using the following formula.
21
www.ti.com
P
Dmax
T
max
T
A
JA
where:
P
Dmax
is the maximum power dissipation in the amplifier (W).
T
max
is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θ
JC
+ θ
CA
θJC is the thermal coeffiecient from the silicon junctions to
the case (°C/W).
θCA is the thermal coeffiecient from the case to ambient
air (°C/W).
4
3.5
3
2.5
2
1.5
1
0.5
0
−40 −20 0 20 40 60 80 100
− Maximum Power Dissipation − W
P
D
TA − Free-Air Temperature − °C
Results are With No Air Flow and PCB Size = 3”x 3”
θJA = 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN)
θJA = 95°C/W for 8-Pin SOIC High−K Test PCB (D)
θJA = 158°C/W for 8-Pin MSOP w/PowerPad w/o Solder
θJA = 58.4°C/W
θJA = 95°C/W
θJA = 158°C/W
ΤJ = 125°C
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
For systems where heat dissipation is more critical,
the THS3110 and THS3111 are offered in an 8-pin
MSOP with PowerPAD package offering even better
thermal performance. The thermal coefficient for the
PowerPAD packages are substantially improved over
the traditional SOIC. Maximum power dissipation
levels are depicted in the graph for the available
packages. The data for the PowerPAD packages
assume a board layout that follows the PowerPAD
layout guidelines referenced above and detailed in
the PowerPAD application note (literature number
SLMA002). The following graph also illustrates the
effect of not soldering the PowerPAD to a PCB. The
thermal impedance increases substantially which may
cause serious heat and performance issues. Be sure
to always solder the PowerPAD to the PCB for
optimum performance.
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power dissipation, but also dynamic power dissipation. Often
times, this is difficult to quantify because the signal
pattern is inconsistent, but an estimate of the RMS
power dissipation can provide visibility into a possible
problem.
DESIGN TOOLS
Evaluation Fixtures, Spice Models, and
Application Support
Texas Instruments is committed to providing its customers with the highest quality of applications support. To support this goal an evaluation board has
been developed for the THS3110 and THS3111
operational amplifier. The board is easy to use,
allowing for straightforward evaluation of the device.
The evaluation board can be ordered through the
Texas Instruments web site, www.ti.com, or through
your local Texas Instruments sales representative.
Computer simulation of circuit performance using
SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF-amplifier circuits where
parasitic capacitance and inductance can have a
major effect on circuit performance. A SPICE model
for the THS3111 is available through the Texas
Instruments web site (www.ti.com). The PIC is also
available for design assistance and detailed product
information. These models do a good job of predicting small-signal ac and transient performance
under a wide variety of operating conditions. They are
not intended to model the distortion characteristics of
the amplifier, nor do they attempt to distinguish
between the package types in their small-signal ac
performance. Detailed information about what is and
is not modeled is contained in the model file itself.
Figure 57. Maximum Power Distribution vs
22
Ambient Temperature
www.ti.com
TP2GND
J2
+
C2
VS−
J7
C4
C6
C1
J1
+
FB1
C5
C3
FB2
VS−
VS+
VS+
R4
J4
Vin+
R8A
2
3
6
7
4
1
J8
Vs+
R2
Z2
J7
R1
J6
Vout
Vs−
R3
J5
Vin
−
_
+
PD
8
R8B
R5 Z1
TP1
R6
0
R7BR7A
REF
1
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
NOTE: The Edge number for the THS3111 is
6445587.
Figure 58. THS3110 EVM Circuit Configuration
Figure 59. THS3110 EVM Board Layout (Top
Layer)
Figure 60. THS3110 EVM Board Layout (Bottom
Layer)
23
www.ti.com
THS3110, THS3111
SLOS422A – SEPTEMBER 2003 – REVISED NOVEMBER 2003
Table 2. Bill of Materials
THS3110DGN and THS3111DGN EVM
ITEM DESCRIPTION SMD SIZE
1 BeadD, Ferrite, 3 A, 80 Ω 1206 FB1, FB2 2 (Steward) HI1206N800R-00
2 D C1, C2 2 (AVX) TAJD685K035R
3 Open 0805 R5, Z1 2
4 Cap. 0.1 µF, Ceramic, X7R, 50 V 0805 C3, C4 2 (AVX) 08055C104KAT2A
5 Cap. 100 pF, Ceramic, NPO, 100 V 0805 C5, C6 2 (AVX) 08051A101JAT2A
6 Resistor, 0 Ω , 1/8 W, 1% 0805 R6
7 Resistor, 750 Ω , 1/8 W, 1% 0805 R3, R4 2 (Phycomp) 9C08052A7500FKHFT
8 Open 1206 R7A, Z2 2
9 Resistor, 49.9 Ω , 1/4 W, 1% 1206 R2, R8A 2 (Phycomp) 9C12063A49R9FKRFT
10 Resistor, 53.6 Ω , 1/4 W, 1% 1206 R1 1 (Phycomp) 9C12063A53R6FKRFT
11 Open 2512 R7B, R8B 2
12 Header, 0.1" CTRS, 0.025" SQ pins 3 Pos. JP1
13 Shunts JP1
14 J1, J2, J3 3 (SPC) 813
15 Test point, red J7
16 Test point, black TP2 1 (Keystone) 5001
17 Connector, SMA PCB jack J4, J5, J6 3 (Amphenol) 901-144-8RFX
18 Standoff, 4-40 hex, 0.625" length 4 (Keystone) 1808
19 Screw, Phillips, 4-40, 0.250" 4 SHR-0440-016-SN
20 IC, THS3110 U1 1 (TI) THS3110DGN
21 Board, printed-circuit (THS3110) 1 (TI) EDGE # 6445586
22 IC, THS3111 U1 1 (TI) THS3111DGN
23 Board, printed-circuit (THS3111) 1 (TI) EDGE # 6445587
Cap. 6.8 µF, Tanatalum,
35 V, 10%
Jack, banana receptance, 0.25" dia.
hole
(1) The manufacturer's part numbers were used for test purposes only.
(2) Applies to the THS3110DGN EVM only.
REFERENCE PCB MANUFACTURER'S
DESIGNATOR QTY PART NUMBER
(2)
(2)
(2)
(2)
(2)
, J8
, TP1 3 (Keystone) 5000
1 (Phycomp) 9C08052A0R00JLHFT
1 (Sullins) PZC36SAAN
1 (Sullins) SSC02SYAN
(1)
ADDITIONAL REFERENCE MATERIAL
• PowerPAD Made Easy, application brief (SLMA004)
• PowerPAD Thermally Enhanced Package, technical brief (SLMA002)
• Voltage Feedback vs Current Feedback Amplifiers, (SLVA051)
• Current Feedback Analysis and Compensation (SLOA021)
• Current Feedback Amplifiers: Review, Stability, and Application (SBOA081)
• Effect of Parasitic Capacitance in Op Amp Circuits (SLOA013)
• Expanding the Usability of Current-Feedback Amplifiers, by Randy Stephens, 3Q 2003 Analog Applications
Journal www.ti.com/sc/analogapps).
24
THERMAL PAD MECHANICAL DATA
www.ti.com
DGN (S-PDSO-G8)
THERMAL INFORMATION
This PowerPAD™ package incorporates an exposed thermal pad that is designed to be attached directly to an
external heatsink. When the thermal pad is soldered directly to the printed circuit board (PCB), the PCB can be
used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a
ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from
the integrated circuit (IC).
For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities,
refer to Technical Brief, PowerPAD Thermally Enhanced Package, Texas Ins truments Literature No. SLMA002
and Application Brief, PowerPAD Made Easy, Texas Instruments Literature N o . SLMA004. Both documents are
available at www.ti.com.
The exposed thermal pad dimensions for this package are shown in the following illustration.
8
5
Exposed Thermal Pad
1,73
MAX
NOTE: All linear dimensions are in millimeters
Exposed Thermal Pad Dimensions
1
1,78
MAX
Top View
4
PPTD041
PowerPAD is a trademark of Texas Instruments
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