TEXAS INSTRUMENTS THS1230 Technical data

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THS1230

3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH POWER DOWN

SLAS291A – OCTOBER 2000 – REVISED NOVEMBER 2000

features

12-Bit Resolution, 30 MSPS Analog-to-Digital Converter

Configurable Input Functions: – Single-Ended – Single-Ended With Offset – Differential

3.3-V Supply Operation

Internal Voltage Reference

Out-of-Range Indicator

Power-Down Mode

IF Undersampling

applications

Set Top Box (STB)

Camcorders

Digital Cameras

Copiers

Communications

Test Instruments

IF and Baseband Digitization

description

DW OR PW PACKAGE

(TOP VIEW)

AGND

CON1 CON0

EXTREF

AIN+ AIN–

AGND

AV REFT

REFB

OVRNG

D11

D10

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

CLK AV

OE D0 D1 D2 D3 D4 DV

DGND D5 D6 D7 D8

The THS1230 is a CMOS, low power, 12-bit, 30 MSPS analog-to-digital converter (ADC) that operates with a

3.3-V supply . The THS1230 gives circuit developers complete flexibility . The analog input to the THS1230 can be either single-ended, single-ended with offset, or differential. The THS1230 provides a wide selection of voltage references to match the user’s design requirements. For more design flexibility, the internal reference can be bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the application. The out-of-range output is used to monitor any out-of-range condition in the THS1230’s input range.

The speed, resolution, and single-supply operation of the THS1230 are suited for applications in set top box (STB), video, multimedia, high-speed acquisition, and communications. The speed and resolution ideally suit charge-couple device (CCD) input systems such as digital copiers, digital cameras, and camcorders. The wide input voltage range between V

REFB

and V

allows the THS1230 to be designed into multiple systems.

REFT

The THS1230C is characterized for operation from 0°C to 70°C. The THS1230I is characterized for operation from –40°C to 85°C.

AVAILABLE OPTIONS

0°C to 70°C THS1230CPW THS1230CDW

–40°C to 85°C THS1230IPW THS1230IDW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

28-TSSOP (PW) 28-SOIC (DW)

PACKAGED DEVICES

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1230

3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH POWER DOWN

SLAS291A – OCTOBER 2000 – REVISED NOVEMBER 2000

functional block diagram

CLK

AIN+

AIN–

CON0 CON1

Sample and Hold

Configuration

Control

Circuit

Internal

Reference

Circuit

Timing Circuitry

12-Bit ADC

EXTREF

REFT

REFB

3-State Output

Buffers

DGNDAGND

OVRNG

D[11:0]

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

Terminal Functions

TERMINAL

NAME NO.

AGND 1, 7 I Analog ground AV

AIN+ 5 I Positive analog input AIN– 6 I Negative analog input CLK 28 I ADC conversion clock CON1 2 I Configuration Input 1 CON0 3 I Configuration Input 0 DGND 19 I Digital ground DV

D11 12 O ADC data bit 11 D10 13 O ADC data bit 10 D9 14 O ADC data bit 9 D8 15 O ADC data bit 8 D7 16 O ADC data bit 7 D6 17 O ADC data bit 6 D5 18 O ADC data bit 5 D4 21 O ADC data bit 4 D3 22 O ADC data bit 3 D2 23 O ADC data bit 2 D1 24 O ADC data bit 1 D0 25 O ADC data bit 0 EXTREF 4 I Reference select input, high = external, low = internal OVRNG 11 O Out of range indicator OE 26 I Output enable, high = disable, low = enable REFT 9 I/O Upper ADC reference voltage REFB 10 I/O Lower ADC reference voltage

8, 27 I Analog supply

20 I Digital supply

THS1230

WITH POWER DOWN

SLAS291A – OCTOBER 2000 – REVISED NOVEMBER 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1230

3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH POWER DOWN

SLAS291A – OCTOBER 2000 – REVISED NOVEMBER 2000

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range: AVDD to AGND, DVDD to DGND –0.3 to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AGND to DGND –0.3 to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference voltage input range, REFT, REFB to AGND –0.3 to AV

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range, AIN+, AIN– to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock input voltage range, CLK to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range, digital input to DGND –0.3 to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital output voltage range, digital output to DGND –0.3 to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating junction temperature range, T Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STG

–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

electrical characteristics over recommended operating conditions (AVDD = DVDD = 3.3 V,

= 30 MHz/50% duty cycle, MODE = 1, 1-V input span, internal reference, T

min

to T

max

) ( unless

otherwise noted)

sampling rate and resolution

PARAMETER MIN NOM MAX UNIT

Sample frequency 5

Resolution 12 Bits

†

30 MSPS

analog inputs (all supplies = 3.3 V)

PARAMETER MIN TYP MAX UNIT

Positive analog input, AIN+ 0 AV Negative analog input, AIN– 0 AV

MODE1 –1 V

Analog input voltage difference for zero scale ADC out, (AIN+) – (AIN–)

Analog input voltage difference for full scale ADC out, (AIN+) – (AIN–)

Switched input capacitance, C Aperture delay time, t Aperture uncertainty (jitter) 2 ps DC leakage current (input = ±FS) 10 µA

†

The clock frequency may be extended to 5 MHz without degradation in specified performance.

d(ap)

MODE2 –2 V MODE3 0 V MODE1 1 V MODE2 2 V MODE3 1 V

DD DD

6 pF 2 ns

V V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VIHHigh level input voltage

VILLow level input voltage

THS1230

3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH POWER DOWN

SLAS291A – OCTOBER 2000 – REVISED NOVEMBER 2000

electrical characteristics over recommended operating conditions (AVDD = DVDD = 3.3 V,

= 30 MHz/50% duty cycle, MODE = 1, 1-V input span, internal reference, T

otherwise noted) (continued)

digital inputs and outputs (all supplies = 3.3 V)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Digital Inputs

High level input current 1 µA

Low level input current –1 µA

Input capacitance 5 pF

Digital Outputs

High level output voltage I

Low level output voltage I

High impedance output current ±1 µA

tr/t

Rise/fall time CL = 10 pF 5.5 ns

All other inputs 0.8 × DV CLK 0.8 × AV All other inputs 0.2 × DV CLK 0.2 × AV

= 50 µA DVDD–0.4 V

load

= –50 µA 0.4 V

load

DD DD

min

to T

max

DD DD

) (unless

power supply (CLK = 30 MHz)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

(analog)

(digital)

I(standby)

(PU)

D(STBY)

PSRR Power supply rejection ratio ±0.1 %FS

Supply voltage (all supplies) 3 3.3 3.6 V Supply current active – total 48 66 mA Supply current active – analog 35 mA Supply current active – digital 13 mA Standby supply current CLK = 0 MHz 10 µA Power-up time for references from standby 100 µs Power dissipation CLK = 30 MHz 168 220 mW Standby power dissipation CLK = 0 MHz 36 µW

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1230

3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH POWER DOWN

SLAS291A – OCTOBER 2000 – REVISED NOVEMBER 2000

electrical characteristics over recommended operating conditions (AVDD = DVDD = 3.3 V,

= 30 MHz/50% duty cycle, MODE = 1, 1-V input span, internal reference, T

otherwise noted) (continued)

min

to T

max

) (unless

THS1230

1.5 V

BAND

GAP

Figure 1. Reference Generation

REFT, REFB reference voltages (all supplies = 3.3 V)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Internal Reference

REFT

REFB

REF

External Reference

Internal or External Reference

Upper reference voltage 2.15 V Lower reference voltage 1.15 V Differential reference voltage, V Differential reference voltage, V

Externally applied V Externally applied V Externally applied (V External mode V

decoupling capacitor value 0.1 µF

REFT

decoupling capacitor value 0.1 µF

REFB

Decoupling capacitor V

REFT REFB

REFT–VREFB

to V

REFT

REFT–VREFB REFT–VREFB

reference voltage range 2 2.5 V reference voltage range 1.05 1.3 V

) reference voltage range 0.75 1.05 V

impedance 9 kΩ

REFB

to V

REFT

REFB

accuracy –5% 5%

REFT

REFB

0.95 1 1.05 V

10 µF

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1230

3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH POWER DOWN

SLAS291A – OCTOBER 2000 – REVISED NOVEMBER 2000

electrical characteristics over recommended operating conditions (AVDD = DVDD = 3.3 V,

= 30 MHz/50% duty cycle, MODE = 1, 1-V input span, internal reference, T

otherwise noted) (continued)

dc accuracy (linearity)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Number of missing codes All modes 0 codes DNL Differential nonlinearity All modes ±0.4 ±1 LSB INL Integral nonlinearity All modes –2.5 ±1.2 2 LSB

Offset error All modes 0.5 1.2 %FSR

Gain error All modes 0.5 3.5 %FSR

dynamic performance (all supplies = 3.3 V)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

fi = 3.58 MHz 10.9

ENOB Effective number of bits

THD Total harmonic distortion

SNR Signal-to-noise ratio

SINAD Signal-to-noise + distortion

SFDR Spurious free dynamic range

Analog input bandwidth 180 MHz

Differential phase, DP 0.12 degree G

Differential gain 0.01%

(diff)

timing (all supplies = 3.3 V)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

CLK

d(O)

d(PZ)

d(EN)

†

The clock frequency may be extended to 5 MHz without degradation in specified performance.

Clock frequency

Clock duty cycle 45% 50% 55%

Output delay time 19 ns

Delay time, output disable to Hi-Z output 3.2 ns

Delay time, output enable to output valid 16 19 ns

Latency 5 cycles

†

fi = 10 MHz fi = 15 MHz 10.8 fi = 3.58 MHz –76 fi = 10 MHz fi = 15 MHz –72.5 fi = 3.58 MHz 68 fi = 10 MHz fi = 15 MHz 67.7 fi = 3.58 MHz 67.4 fi = 10 MHz fi = 15 MHz 66.6 fi = 3.58 MHz 78.1 fi = 10 MHz fi = 15 MHz 74.6

to T

min

10.6 10.9

–74 –65

66 68

65.6 67.4

67 76.4

5 30 MHz

max

) (unless

Bits

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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