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THS1209
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TEXAS INSTRUMENTS THS1209 Technical data

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THS1209
12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
features
Simultaneous Sampling of 2 Single-Ended Signals or 1 Differential Signal
Signal-to-Noise Ratio: 68 dB at fI = 2 MHz
Differential Nonlinearity Error: ±1 LSB
Integral Nonlinearity Error: ±1.5 LSB
Auto-Scan Mode for 2 Inputs
3-V or 5-V Digital Interface Compatible
Low Power: 218 mW Max at 5 V
Power Down: 1 mW Max
5-V Analog Single Supply Operation
Internal Voltage References . . . 50 PPM/°C and ±5% Accuracy
Glueless DSP Interface
Parallel µC/DSP Interface
applications
Radar Applications
Communications
Control Applications
High-Speed DSP Front-End
Automotive Applications
description
D0 D1 D2 D3 D4 D5
BV
DD
BGND
D6 D7 D8 D9
RA0/D10
RA1/D11
CONV_CLK
SYNC
DA PACKAGE
(TOP VIEW)
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
NC RESET AINP AINM AGND REFOUT REFP REFM AGND AV
DD
CS0 CS1 WR
(R/W) RD DV
DD
DGND
The THS1209 is a CMOS, low-power , 12-bit, 8 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers allow for programming the ADC into the desired mode. The THS1209 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application.
The THS1209C is characterized for operation from 0°C to 70°C, and the THS1209I is characterized for operation from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICE
T
A
0°C to 70°C THS1209CDA
–40°C to 85°C THS1209IDA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TSSOP
(DA)
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
THS1209 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
functional block diagram
REFP
REFM
REFIN
AINP
AINM
CONV_CLK
CS0 CS1
RD
WR (R/W)
RESET
S/H
Control
S/H
Logic
and
Single-Ended
and/or
Differential
MUX
Control
Register
+ –
REFP
12-Bit
Pipeline
ADC
AV
3.5 V
1.5 V
DD
REFM
12
DV
DD
1.225 V REF
Buffers
2.5 V
REFOUT
BV
DD
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10/RA0 D11/RA1
BGND
SYNC
AGND DGND
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I/O
DESCRIPTION
THS1209
12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
Terminal Functions
TERMINAL
NAME NO.
AINP 30 I Analog input, single-ended or positive input of differential channel A AINM 29 I Analog input, single-ended or negative input of differential channel A AV
DD
AGND 24 I Analog ground BV
DD
BGND 8 I Digital ground for buffer CONV_CLK 15 I Digital input. This input is the conversion clock input CS0 22 I Chip select input (active low) CS1 21 I Chip select input (active high) SYNC 16 O Synchronization output. This signal indicates in a multi-channel operation that data of channel A is
DGND 17 I Digital ground. Ground reference for digital circuitry. DV
DD
D0 – D9 1–6, 9–12 I/O/Z Digital input, output; D0 = LSB RA0/D10 13 I/O/Z Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This
RA1/D11 14 I/O/Z Digital input, output (D1 1 = MSB). The data line D11 is also used as an address line (RA1) for the control
NC 32 O Not connected REFIN 28 I Common-mode reference input for the analog input channels. It is recommended that this pin be
REFP 26 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference
REFM 25 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference
RESET 31 I Hardware reset of the THS1209. Sets the control register to default values. REFOUT 27 O Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The reference
†
RD
WR (R/W)
†
The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.
†
23 I Analog supply voltage
7 I Digital supply voltage for buffer
brought to the digital output and can therefore be used for synchronization.
18 I Digital supply voltage
is required for writing to control register 0 and control register 1. See Table 8.
register. This is required for writing to control register 0 and control register 1. See Table 8.
connected to the reference output REFOUT.
voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 9.
voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 9.
output requires a capacitor of 10 µF to AGND for filtering and stability .
19 I The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input,
20 I This input is programmable. It functions as a read-write input (R/W) and can also be configured as a
active low as a data read select from the processor. See timing section.
write-only input (WR
input is used as a read input from the processor. See timing section.
the RD
), which is active low and used as data write select from the processor. In this case,
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
THS1209
High-level input voltage, V
Low-level input voltage, V
Operating free-air temperature, T
°C
12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range: DGND to DVDD –0.3 V to 8.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BGND to BVDD –0.3 V to 8.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGND to AV
–0.3 V to 8.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
Analog input voltage range AGND – 0.3 V to AVDD + 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage –0.3 + AGND to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range –0.3 V to BVDD/DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: THS1209C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THS1209I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
–85°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
power supply
MIN NOM MAX UNIT
Supply voltage
AV DV BV
DD
DD
DD
4.75 5 5.25
4.75 5 5.25 3 5.25
V
analog and reference inputs
MIN NOM MAX UNIT
Analog input voltage in single-ended configuration V Common-mode input voltage VCM in differential configuration 1 2.5 4 V External reference voltage,V External reference voltage, V Input voltage difference, REFP – REFM 2 V
(optional) 3.5 AVDD–1.2 V
REFP
(optional) 1.4 1.5 V
REFM
REFM
V
REFP
digital inputs
MIN NOM MAX UNIT
p
p
Input CONV_CLK frequency DVDD = 4.75 V to 5.25 V 0.1 8 MHz CONV_CLK pulse duration, clock high, t
CONV_CLK pulse duration, clock low, t
p
IH
IL
w(CONV_CLKH)
w(CONV_CLKL)
p
A
BVDD = 3.3 V 2 V BVDD = 5.25 V 2.8 V BVDD = 3.3 V 0.8 V BVDD = 5.25 V 0.8 V
DVDD = 4.75 V to 5.25 V 62 62 5000 ns DVDD = 4.75 V to 5.25 V 62 62 5000 ns
THS1209CDA 0 70 THS1209IDA –40 85
V
°
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
electrical characteristics over recommended operating conditions, AVDD = DVDD = 5 V, BV
digital specifications
= 3.3 V (unless otherwise noted)
DD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Digital inputs
I I C
Digital outputs
V V I C C
High-level input current DVDD = digital inputs –50 50 µA
IH
Low-level input current Digital input = 0 V –50 50 µA
IL
Input capacitance 5 pF
i
High-level output voltage I
OH
Low-level output voltage I
OL
High-impedance-state output current CS1 = DGND, CS0 = DV
OZ
Output capacitance 5 pF
O
Load capacitance at databus D0 – D11 30 pF
L
= –50 µA, BVDD = 3.3 V, 5 V BVDD–0.5 V
OH
= 50 µA, BVDD = 3.3 V, 5 V 0.4 V
OL
DD
–10 10 µA
THS1209
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
THS1209
Offset error
12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
electrical characteristics over recommended operating conditions, AVDD = DVDD = 5 V, BV
= 3.3 V, fs = 8 MSPS, V
DD
dc specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 12 Bits
Accuracy
Integral nonlinearity, INL ±1.5 LSB Differential nonlinearity , DNL ±1 LSB
Gain error –20 20 LSB
Analog input
Input capacitance 15 pF Input leakage current V
Internal voltage reference
Accuracy, V Accuracy, V Temperature coefficient 50 PPM/°C Reference noise 100 µV Accuracy, REFOUT 2.475 2.5 2.525 V
Power supply
I
DDA
I
DDD
I
DDB
Analog supply current AVDD = DVDD = 5 V, BVDD = 3.3 V 38 40 mA Digital supply voltage AVDD = DVDD = 5 V, BVDD = 3.3 V 0.5 1 mA Buffer supply voltage AVDD = DVDD = 5 V, BVDD = 3.3 V 1.5 4 mA Power dissipation AVDD = DVDD = 5 V, BVDD = 3.3 V 188 218 mW Power dissipation in power down with con-
version clock inactive
REFP REFM
= internal (unless otherwise noted)
REF
After calibration in single-ended mode 20 LSB After calibration in differential mode –20 20 LSB
= V
AIN
AVDD = DVDD = 5 V, BVDD = 3.3 V 0.25 mW
REFM
to V
REFP
±10 µA
3.3 3.5 3.7 V
1.4 1.5 1.6 V
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SINAD
Signal-to-noise ratio
distortion
SNR
Signal-to-noise ratio
THD
T otal harmonic distortion
Effective number of bits
SFDR
Spurious free dynamic range
THS1209
12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
electrical characteristics over recommended operating conditions, V f
= 2 MHz at –1dBFS (unless otherwise noted)
I
ac specifications, AVDD = DVDD = 5 V, BVDD = 3.3 V, CL < 30 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
+
ENOB (SNR)
p
Analog Input
Full-power bandwidth with a source impedance of 150 Ω in differential configuration.
Full-power bandwidth with a source impedance of 150 Ω in single-ended configuration.
Small-signal bandwidth with a source impedance of 150 Ω in differential configuration.
Small-signal bandwidth with a source impedance of 150 Ω in single-ended configuration.
Differential mode 63 65 dB Single-ended mode 62 64 dB Differential mode 64 69 dB Single-ended mode 64 68 dB Differential mode –70 –67 dB Single-ended mode –68 –64 dB Differential mode 10.17 10.5 Bits Single-ended mode 10 10.3 Bits Differential mode 67 71 dB Single-ended mode 65 69 dB
Full scale sinewave, –3 dB 98 MHz
Full scale sinewave, –3 dB 54 MHz
100 mVpp sinewave, –3 dB 98 MHz
100 mVpp sinewave, –3 dB 54 MHz
= internal, fs = 8 MSPS,
REF
timing specifications, AV
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(pipe)
t
su(CONV_CLKL–READL)
t
su(READH–CONV_CLKL)
t
dCONV_CLKL–SYNCL)
t
d(CONV_CLKL–SYNCH)
Latency 5 Setup time, CONV_CLK low before CS valid 10 ns
Setup time, CS invalid to CONV_CLK low 20 ns Delay time, CONV_CLK low to SYNC low 10 ns Delay time, CONV_CLK low SYNC high 10 ns
= DVDD = 5 V, BV
DD
= 3.3 V, V
DD
= Internal, CL < 30 pF
REF
CONV
CLK
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
THS1209 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
detailed description
reference voltage
The THS1209 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V and VREFM is set to 1.5 V . An external reference can also be used through two reference input pins, REFP and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.
analog inputs
The THS1209 consists of two analog inputs, which are sampled simultaneously . These inputs can be selected individually and configured as single-ended or differential inputs. The desired analog input channel can be programmed.
converter
The THS1209 uses a 12-bit pipelined multistaged architecture which achieves a high sample rate with low power consumption. The THS1209 distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while the second through the eighth stages operate on the seven preceding samples.
conversion
An external clock signal with a duty cycle of 50% has to be applied to the clock input (CONV_CLK). A new conversion is started with every falling edge of the applied clock signal. The conversion values are available at the output with a latency of 5 clock cycles.
sampling rate
The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1 shows the maximum conversion rate for different combinations.
Table 1. Maximum Conversion Rate
CHANNEL CONFIGURATION NUMBER OF CHANNELS
1 single-ended channel 1 8 MSPS 2 single-ended channels 2 4 MSPS 1 differential channel 1 8 MSPS 2 differential channels 2 4 MSPS 1 single-ended and 1 differential channel 2 4 MSPS
MAXIMUM CONVERSION
RATE PER CHANNEL
The maximum conversion rate in the continuous conversion mode per channel, fc, is given by:
8 MSPS
fc
+
# channels
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
conversion mode
During conversion, the ADC operates with a free running external clock signal applied to the input CONV_CLK. With every falling edge of the CONV_CLK signal a new converted value is available to the databus with the corresponding read signal. The THS1209 offers up to two analog inputs to be selected. It is important to provide the channel information to the system, this means to know which channel is available to the databus. T o maintain this channel integrity, the THS1209 an output signal SYNC, which is always active low if data of channel 1 is applied to the databus.
Figure 3 shows the timing of the conversion when one analog input channel is selected. The maximum throughput rate is 8 MSPS in this mode. The signal SYNC is disabled for the selection of one analog input since this information is not required for one analog input. There is a certain timing relationship required for the read signal with respect to the conversion clock. This can be seen in Figure 2 and T able 2. A more detailed description of the timing is given in the section timing and signal description of the THS1209.
Sample N
Channel 1
Sample N+1
Channel 1
Sample N+2
Channel 1
Sample N+3
Channel 1
Sample N+4
Channel 1
Sample N+5
Channel 1
Sample N+6
Channel 1
Sample N+7
Channel 1
Sample N+8
Channel 1
THS1209
AIN
t
d(A)
t
w(CONV_CLKH)
t
w(CONV_CLKL)
CONV_CLK
t
c
t
su(CONV_CLKL–READL)
†
READ
Data N–4
Channel 1
†
READ is the logical combination from CSO
Figure 1. Conversion Timing in 1-Channel Operation
Data N–3
Channel 1
, CS1, and RD
t
d(pipe)
Data N–2
Channel 1
t
su(READH_CONV–CLKL)
Data N–1
Channel 1
Data N
Channel 1
Data N+1
Channel 1
Data N+2
Channel 1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
THS1209 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
Figure 3 shows the conversion timing when two analog input channels are selected. The maximum throughput rate per channel is 4 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted data is available to the data bus. The SYNC signal is always active low if data of channel 1 is available to the data bus. There is a certain timing relationship required for the read signal with respect to the conversion clock. This can be seen in Figure 2 and T able 2. A more detailed description of the timing is given in the section timing and signal description of the THS1209.
AIN
t
w(CONV_CLKH)
CONV_CLK
†
READ
SYNC
Sample N
Channel 1, 2
t
d(A)
t
c
t
su(CONV_CLKL–READL)
Sample N+1 Channel 1, 2
t
t
w(CONV_CLKL)
d(pipe)
Sample N+2 Channel 1, 2
t
su(READH–CONV_CLKL)
t
d(CONV_CLKL–SYNCL)
Sample N+3 Channel 1, 2
Sample N+4 Channel 1, 2
t
d(CONV_CLKL–SYNCH)
Data N–2
Channel 1
†
READ is the logical combination from CSO
Figure 2. Conversion Timing in 2 Channel Operation
Data N–2
Channel 2
, CS1, and RD
Data N–1
Channel 1
Data N–1
Channel 2
Data N
Channel 1
Data N
Channel 2
Data N+1 Channel 1
10
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12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
digital output data format
The digital output data format of the THS1209 can be in either binary format or in twos complement format. The following tables list the digital outputs for the analog input voltages.
Table 2. Binary Output Format for Single-Ended Configuration
SINGLE-ENDED, BINARY OUTPUT
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
AIN = V
REFP
AIN = (V AIN = V
REFP
REFM
+ V
)/2 800h
REFM
Table 3. Twos Complement Output Format for Single-Ended Configuration
SINGLE-ENDED, TWOS COMPLEMENT
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
AIN = V
REFP
AIN = (V AIN = V
REFP
REFM
+ V
)/2 000h
REFM
FFFh
000h
7FFh
800h
THS1209
Table 4. Binary Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
Vin = AINP – AINM
V
= V
REF
Vin = V
REF
Vin = 0 800h Vin = –V
REF
REFP
– V
REFM
FFFh
000h
Table 5. Twos Complement Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
Vin = AINP – AINM
V
= V
REF
Vin = V
REF
Vin = 0 000h Vin = –V
REF
REFP
– V
REFM
7FFh
800h
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11
THS1209 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
ADC control register
The THS1209 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the desired mode. The bit definitions of both control registers are shown in Table 7.
Table 6. Bit Definitions of Control Register CR0 and CR1
BIT BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CR0 TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD RES VREF CR1 RBACK OFFSET BIN/2’s R/W RES RES RES RES RES RESET
writing to control register 0 and control register 1
The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control register and writing the register value to the ADC. The addressing is performed with the upper data bits D10 and D1 1, which function in this case as address lines RA0 and RA1. During this write process, the data bits D0 to D9 contain the desired control register value. Table 8 shows the addressing of each control register.
Table 7. Control Register Addressing
D0 – D9 D10/RA0 D11/RA1 Addressed Control Register
Desired register value 0 0 Control register 0 Desired register value 1 0 Control register 1 Desired register value 0 1 Reserved for future Desired register value 1 1 Reserved for future
12
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12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
initialization of the THS1209
The initialization of the THS1209 should be done according to the configuration flow shown in Figure 3.
Start
THS1209
SLAS288 – JULY 2000
Use Default
Values?
Yes
Write 0x401 to
THS1209
(Set Reset Bit in CR1)
Clear RESET By Writing 0x400 to
CR1
No
Write 0x401 to
THS1209
(Set Reset Bit in
CR1)
Clear RESET By
Writing 0x400 to
CR1
Write the User
Configuration to
CR0
Write the User
Configuration to
CR1 (Must Exclude
RESET)
Continue
Figure 3. THS1209 Configuration Flow
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13
THS1209 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
ADC control registers
control register 0 (see Table 8)
– – BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
– – TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD RES VREF
Table 8. Control Register 0 Bit Functions
RESET
BITS
VALUE
0 0 VREF V ref select:
1 0 RES Reserved 2 0 PD Power down.
3, 4 0,0 CHSEL0,
5,6 1,0 DIFF0, DIFF1 Number of differential channels
7 0 SCAN Autoscan enable
8,9 0,0 TEST0,
NAME FUNCTION
Bit 0 = 0 → The internal reference is selected. Bit 0 = 1 → The external reference voltage is selected.
Bit 2 = 0 → The ADC is active. Bit 2 = 1 → Power down
The reading and writing to and from the digital outputs is possible during power down.
CHSEL1
TEST1
Channel select Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 8.
Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 8.
Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 8. Test input enable
Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This feedback allows the check of all hardware connections and the ADC operation.
Refer to Table 8 for selection of the three different test voltages.
14
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12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
analog input channel selection
The analog input channels of the THS1209 can be selected via bits 3 to 7 of control register 0. One single channel (single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the selection between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more than one input channel is selected. Table 10 shows the possible selections.
Table 9. Analog Input Channel Configurations
THS1209
BIT 7ASBIT 6
DF1
0 0 0 0 0 Analog input AINP (single ended) 0 0 0 0 1 Analog input AINM (single ended) 0 0 0 1 0 Reserved 0 0 0 1 1 Reserved 0 0 1 0 0 Differential channel (AINP–AINM) 0 0 1 0 1 Reserved 1 0 0 0 1 Autoscan two single ended channels: AINP, AINM, AINP, … 1 0 0 1 0 Reserved 1 0 0 1 1 Reserved 1 1 0 0 1 Reserved 1 0 1 0 1 Reserved 1 0 1 1 0 Reserved 0 0 1 1 0 Reserved 0 0 1 1 1 Reserved 1 0 0 0 0 Reserved 1 0 1 0 0 Reserved 1 0 1 1 1 Reserved 1 1 0 0 0 Reserved 1 1 0 1 0 Reserved 1 1 0 1 1 Reserved 1 1 1 0 0 Reserved 1 1 1 0 1 Reserved 1 1 1 1 0 Reserved 1 1 1 1 1 Reserved
BIT 5
DF0
BIT 4
CHS1
BIT 3
CHS0
DESCRIPTION OF THE SELECTED INPUTS
test mode
The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown in Table 11.
Table 10. Test Mode
BIT 9
TEST1
BIT 8
TEST0
0 0 Normal mode 0 1 V 1 0 ((V 1 1 V
OUTPUT RESULT
REFP )+(V
REFM
REFP
REFM
))/2
Three different options can be selected. This feature allows support testing of hardware connections between the ADC and the processor.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
THS1209 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
analog input channel selection (continued)
control register 1 (see Table 8)
– – BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
– – RBACK OFFSET BIN/2s R/W RES RES RES RES RES RESET
Table 11. Control Register 1 Bit Functions
RESET
BITS
VALUE
0 0 RESET Reset
1 0 RES Always write 0
2, 3 0,0 RES Always write 0
4 1 RES Always write 0 5 1 RES Always write 0 6 0 R/W R/W, RD/WR selection
7 0 BIN/2s Complement select
8 0 OFFSET Offset cancellation mode
9 0 RBACK Debug mode
NAME FUNCTION
Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values. To bring the device out of reset, a 0 has to be written into this bit.
Bit 6 of control register 1 controls the function of the inputs RD to 1, WR
becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write with R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD WR
becomes a write input.
If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of control register 1 is set to 1, the output value of the ADC is in binary format. Refer to T able 20 through Table 23.
Bit 8 = 0 → normal conversion mode Bit 8 = 1 → offset calibration mode
If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a con­version. The conversion result is stored in an offset register and subtracted from all conversions in order to reduce the offset error.
Bit 9 = 0 → normal conversion mode Bit 9 = 1 → enable debug mode
When bit 9 of control register 1 is set to 1, debug mode is enabled. In this mode, the contents of control register 0 and control register 1 can be read back. The first read after bit 9 is set to 1 contains the value of control register 0. The second read after bit 9 is set to 1 contains the value of control register 1. To bring the device back into normal conversion mode, this bit has to be set back to 0 by writing again to control register 1.
and WR. When bit 6 in control register 1 is set
becomes a read input and the input
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
timing and signal description of the THS1209
The reading from the THS1209 and writing to the THS1209 is performed by using the chip select inputs (CS0, CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W). This is desired in cases where the connected processor consists of a combined read/write output signal (R/W
). The two chip select inputs can be used to interface easily to a processor.
THS1209
Reading from the THS1209 takes place by an internal RD
signal, which is generated from the logical
int
combination of the external signals CS0, CS1 and RD (see Figure 4). This signal is then used to strobe the words out and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid will make RD
active while the write input (WR) is inactive. The first of those external signals going to its inactive state
int
will then deactivate RD Writing to the THS1209 takes place by an internal WR
again.
int
signal, which is generated from the logical combination
int
of the external signals CS0, CS1 and WR. This signal is then used to strobe the control words into the control registers 0 and 1. The last external signal (either CS0, CS1 or WR) to become valid will make WR the read input (RD WR
again.
int
) is inactive. The first of those external signals going to its inactive state will then deactivate
CS0 CS1
RD
WR
Data Bits
RD
WR
int
int
Control/Data
Registers
active while
int
Figure 4. Logical Combination of CS0, CS1, RD, and WR
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
17
THS1209 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
timing and signal description of the THS1209 (continued)
read timing (using R/W, CS0-controlled)
Figure 5 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The reading of the data should be done with a certain timing relative to the conversion clock CONV_CLK, as illustrated in Figure 5.
t
t
su(CONV_CLKL–CSOL)
su(CSOH–CONV_CLKL)
CONV_CLK
CS0
CS1
R/W
RD
D(0–11)
10%
90%
10%
t
su(R/W
Figure 5. Read Timing Diagram Using R/W (CS0-controlled)
read timing parameter (CS0-controlled)
PARAMETER MIN TYP MAX UNIT
t
su(CONV_CLKL_CSOL)
t
su(CSOH–CONV_CLKL)
t
su(R/W)
t
a
t
h
t
h(R/W)
t
w(CS)
†
CS = CSO
Setup time, CONV_CLK low before CS valid 10 ns Setup time, CS invalid to CONV_CLK low 20 ns Setup time, R/W high to last CS valid 0 ns Access time, last CS valid to data valid 0 10 ns Hold time, first CS invalid to data invalid 0 5 ns Hold time, first external CS invalid to R/W change 5 ns Pulse duration, CS active 10 ns
10%
t
w(CS)
10%
)
t
a
90%
t
h(R/W)
90%
90%
t
h
90%
†
18
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12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
timing and signal description of the THS1209 (continued)
write timing (using R/W, CS0-controlled)
Figure 12 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The writing to the THS1209 can be performed irrespective of the conversion clock signal CONV_CLK.
THS1209
CS0
CS1
R/W
RD
D(0–11)
10%
10%
t
su(R/W
Figure 6. Write Timing Diagram Using R/W (CS0-controlled)
write timing parameter (CSO-controlled)
PARAMETER MIN TYP MAX UNIT
t
su(R/W
t
su
t
h
t
h(R/W)
t
w(CS)
Setup time, R/W stable to last CS valid 0 ns
)
Setup time, data valid to first CS invalid 5 ns Hold time, first CS invalid to data invalid 2 ns Hold time, first CS invalid to R/W change 5 ns Pulse duration, CS active 10 ns
t
w(CS)
10%
)
90%
t
h(R/W)
t
su
90%
10%
t
h
90%
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
19
THS1209 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
analog input configuration and reference voltage
The THS1209 features two analog input channels. These can be configured for either single-ended or differential operation. Figure 7 shows a simplified model, where a single-ended configuration for channel AINP is selected. The reference voltages for the ADC itself are V voltage). The analog input voltage range goes from V minimum voltage, and V reference source provides the voltage V
defines the maximum voltage, which can be applied to the ADC. The internal
REFP
of 1.5 V and the voltage V
REFM
voltage swing of 2 V can be expressed by:
REFM
REFP
and V
to V
(either internal or external reference
REFM
. This means that V
REFP
of 3.5 V. The resulting analog input
REFP
REFM
defines the
V
REFM
v
AINPvV
REFP
AINP
V
REFP
12-Bit
ADC
V
REFM
(1)
Figure 7. Single-Ended Input Stage
A differential operation is desired for many applications due to a better signal-to-noise ratio. Figure 8 shows a simplified model for the analog inputs AINM and AINP, which are configured for differential operation. The differential operation mode provides in terms of performance benefits over the single-ended mode and is therefore recommended for best performance. The THS1209 offers 1 differential analog input and in the single-ended mode 2 analog inputs. If the analog input architecture id differential, common-mode noise and common-mode voltages can be rejected. Additional details for both modes are given below.
V
AINP
AINM
+
V
ADC
Σ
–
REFP
12-Bit
ADC
V
REFM
Figure 8. Differential Input Stage
In comparison to the single-ended configuration it can be seen that the voltage, V input of the ADC, is the difference between the input AINP and AINM. The voltage V follows:
V
ADC
+
ABS(AINP–AINM
)
An advantage to single-ended operation is that the common-mode voltage
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
, which is applied at the
ADC
can be calculated as
ADC
(2)
12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
analog input configuration and reference voltage (continued)
THS1209
SLAS288 – JULY 2000
VCM+
can be rejected in the differential configuration, if the following condition for the analog input voltages is true:
AGNDvAINM, AINPvAV 1VvVCMv
AINM)AINP
2
DD
4V
single-ended mode of operation
The THS1209 can be configured for single-ended operation using dc or ac coupling. In every case, the input of the THS1209 should be driven from an operational amplifier that does not degrade the ADC performance. Because the THS1209 operates from a 5-V single supply, it is necessary to level-shift ground-based bipolar signals to comply with its input requirements. This can be achieved with dc- and ac-coupling.
(3)
(4) (5)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
THS1209 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
dc coupling
An operational amplifier can be configured to shift the signal level according to the analog input voltage range of the THS1209. The analog input voltage range of the THS1209 goes from 1.5 V to 3.5 V. An op-amp can be used as shown in Figure 9.
Figure 9 shows an example where the analog input signal in the range from –1 V up to 1 V is shifted by an operational amplifier to the analog input range of the THS1209 (1.5 V to 3.5 V). The operational amplifier is configured as an inverting amplifier with a gain of –1. The required dc voltage of 1.25 V at the noninverting input is derived from the 2.5-V output reference REFOUT of the THS1209 by using a resistor divider. Therefore, the op-amp output voltage is centered at 2.5 V. The 10 µF tantalum capacitor is required for bypassing REFOUT. REFIN of the THS1209 must be connected directly to REFOUT in single-ended mode. The use of ratio matched, thin-film resistor networks minimizes gain and offset errors.
1 V 0 V
–1 V
R
1
1.25 V
_ +
5 V
R
1
R
S
C
3.5 V
2.5 V
1.5 V
R
2
THS1209
AINP REFIN
REFOUT
+
10 µF
R
2
Figure 9. Level-Shift for DC-Coupled Input
differential mode of operation
For the differential mode of operation, a conversion from single-ended to differential is required. A conversion to differential signals can be achieved by using an RF-transformer, which provides a center tap. Best performance is achieved in differential mode.
Mini Circuits
49.9 Ω
T4–1
200 Ω
10 µF
R
C
R
C
+
Figure 10. Transformer Coupled Input
THS1209
AINP
AINM
REFOUT
22
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THS1209
12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
80
75
70
65
60
55
50
45
THD – Total Harmonic Distortion – dB
40
0123456789
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –1 dBFS
fs – Sampling Frequency – MHz
Figure 11
SIGNAL-TO-NOISE AND DISTORTION
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
70
65
60
55
50
AVDD = 5 V, DVDD = BVDD = 3 V,
45
SINAD – Signal-to-Noise and Distortion – dB
40
fIN = 500 kHz, AIN = –1 dBFS
0123456789
fs – Sampling Frequency – MHz
Figure 12
SPURIOUS FREE DYNAMIC RANGE
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
90 85 80 75 70 65 60 55 50 45
SFDR – Spurious Free Dynamic Range – dB
40
0123456789
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –1 dBFS
fs – Sampling Frequency – MHz
Figure 13
SIGNAL-TO-NOISE
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
70
65
60
55
50
SNR – Signal-to-Noise – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
45
40
fIN = 500 kHz, AIN = –1 dBFS
0123456789
fs – Sampling Frequency – MHz
Figure 14
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23
THS1209 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
85
80
75
70
65
60
55
50
AVDD = 5 V, DVDD = BVDD = 3 V,
45
THD – Total Harmonic Distortion – dB
40
fIN = 500 kHz, AIN = –1 dBFS
0123456789
fs – Sampling Frequency – MHz
Figure 15
SIGNAL-TO-NOISE AND DISTORTION
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
80
75
70
65
60
55
50
AVDD = 5 V, DVDD = BVDD = 3 V,
45
SINAD – Signal-to-Noise and Distortion – dB
40
fIN = 500 kHz, AIN = –1 dBFS
0123456789
fs – Sampling Frequency – MHz
Figure 16
SPURIOUS FREE DYNAMIC RANGE
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
100
95 90 85 80 75 70 65 60 55
AVDD = 5 V, DVDD = BVDD = 3 V,
50
SFDR – Spurious Free Dynamic Range – dB
45 40
fIN = 500 kHz, AIN = –1 dBFS
0123456789
fs – Sampling Frequency – MHz
Figure 17
SIGNAL-TO-NOISE
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
80
75
70
65
60
55
50
SNR – Signal-to-Noise – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
45
40
fIN = 500 kHz, AIN = –1 dBFS
0123456789
fs – Sampling Frequency – MHz
Figure 18
24
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THS1209
12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY (SINGLE-ENDED)
80
75
70
65
60
55
50
THD – Total Harmonic Distortion – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
45
40
fs = 8 MSPS, AIN = –1 dBFS
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
fi – Input Frequency – MHz
Figure 19
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY (SINGLE-ENDED)
80
AVDD = 5 V, DVDD = BVDD = 3 V,
75
70
65
60
55
50
45
SINAD – Signal-to-Noise and Distortion – dB
40
fs = 8 MSPS, AIN = –1 dBFS
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
fi – Input Frequency – MHz
Figure 20
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY (SINGLE-ENDED)
100
AVDD = 5 V, DVDD = BVDD = 3 V,
95 90 85 80 75 70 65 60 55 50
SFDR – Spurious Free Dynamic Range – dB
45 40
fs = 8 MSPS, AIN = –1 dBFS
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
fi – Input Frequency – MHz
Figure 21
SIGNAL-TO-NOISE
vs
INPUT FREQUENCY (SINGLE-ENDED)
80
AVDD = 5 V, DVDD = BVDD = 3 V,
75
70
65
60
55
50
SNR – Signal-to-Noise – dB
45
40
fs = 8 MSPS, AIN = –1 dBFS
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
fi – Input Frequency – MHz
Figure 22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
25
THS1209 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY (DIFFERENTIAL)
80
75
70
65
60
55
50
THD – Total Harmonic Distortion – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
45
40
fs = 8 MSPS, AIN = –1 dBFS
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
fi – Input Frequency – MHz
Figure 23
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY (DIFFERENTIAL)
100
95 90 85 80 75 70 65 60 55 50
SFDR – Spurious Free Dynamic Range – dB
45 40
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = –1 dBFS
fi – Input Frequency – MHz
Figure 25
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY (DIFFERENTIAL)
80
AVDD = 5 V, DVDD = BVDD = 3 V,
75
70
65
60
55
50
45
SINAD – Signal-to-Noise and Distortion – dB
40
fs = 8 MSPS, AIN = –1 dBFS
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
fi – Input Frequency – MHz
Figure 24
SIGNAL-TO-NOISE
vs
INPUT FREQUENCY (DIFFERENTIAL)
80
AVDD = 5 V, DVDD = BVDD = 3 V,
75
70
65
60
55
50
SNR – Signal-to-Noise – dB
45
40
fs = 8 MSPS, AIN = –1 dBFS
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
fi – Input Frequency – MHz
Figure 26
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1209
12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
12
AVDD = 5 V, DVDD = BVDD = 3 V,
fin = 500 kHz, AIN = –1 dBFS
11
10
9
8
7
ENOB – Effective Number of Bits – Bits
6
0123456789
fs – Sampling Frequency – MHz
Figure 27
EFFECTIVE NUMBER OF BITS
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
12
11
10
9
8
AVDD = 5 V, DVDD = BVDD = 3 V,
7
ENOB – Effective Number of Bits – Bits
6
fin = 500 kHz, AIN = –1 dBFS
0123456789
fs – Sampling Frequency – MHz
Figure 28
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY (SINGLE-ENDED)
12
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = –1 dBFS
11
10
9
8
7
ENOB – Effective Number of Bits – Bits
6
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
fi – Input Frequency – MHz
Figure 29
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY (DIFFERENTIAL)
12
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = –1 dBFS
11
10
9
8
7
ENOB – Effective Number of Bits – Bits
6
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
fi – Input Frequency – MHz
Figure 30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
27
THS1209 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
vs
1.0 AVDD = 5 V
0.8 DVDD = BVDD = 3 V
0.6
fs = 8 MSPS
0.4
0.2
–0.0 –0.2 –0.4 –0.6 –0.8
–1
DNL – Differential Nonlinearity – LSB
0 500 1000 1500 2000 2500 3000 3500 4000
ADC CODE
ADC Code
Figure 31
INTEGRAL NONLINEARITY
vs
ADC CODE
1.0
0.8
0.6
0.4
0.2
–0.0 –0.2 –0.4 –0.6 –0.8
INL – Integral Nonlinearity – LSB
AVDD = 5 V DVDD = BVDD = 3 V fs = 8 MSPS
–1
0 500 1000 1500 2000 2500 3000 3500 4000
ADC Code
Figure 32
28
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THS1209
12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
TYPICAL CHARACTERISTICS
FAST FOURIER TRANSFORM (4096 POINTS)
(SINGLE-ENDED)
vs
0 –20 –40 –60 –80
–100
Magnitude – dB
–120 –140
0 1000000 2000000 3000000 4000000
FREQUENCY
AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = –1 dBFS fin = 1.25 MHz
f – Frequency – Hz
Figure 33
0 –20 –40 –60 –80
Magnitude – dB
–100 –120 –140
0 1000000 2000000 3000000 4000000
FAST FOURIER TRANSFORM (4096 POINTS)
(DIFFERENTIAL)
vs
FREQUENCY
AVDD = 5 V, DVDD = BVDD = 3 V, fs = 8 MSPS, AIN = –1 dBFS fin = 1.25 MHz
f – Frequency – Hz
Figure 34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
29
THS1209 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
definitions of specifications and terminology
integral nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two points.
differential nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
zero offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the deviation of the actual transition from that point.
gain error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.
signal-to-noise ratio + distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels.
effective number of bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
(
SINAD*1.76
N
+
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.
total harmonic distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels.
spurious free dynamic range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
6.02
)
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1209
12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS288 – JULY 2000
MECHANICAL DATA
DA (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
38 PINS SHOWN
0,65
38
1
1,20 MAX
0,30 0,19
20
19
A
0,15 0,05
0,13
6,20 NOM
M
8,40 7,80
0,15 NOM
Gage Plane
0,25
0°–8°
0,75 0,50
Seating Plane
0,10
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. Falls within JEDEC MO-153
28
9,80
9,60
30
11,10
32
11,10
10,9010,90
38
12,60
12,40
4040066/D 11/98
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
31
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