TEXAS INSTRUMENTS THS1209 Technical data

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THS1209

12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS288 – JULY 2000

features

Simultaneous Sampling of 2 Single-Ended Signals or 1 Differential Signal

Signal-to-Noise Ratio: 68 dB at fI = 2 MHz

Differential Nonlinearity Error: ±1 LSB

Integral Nonlinearity Error: ±1.5 LSB

Auto-Scan Mode for 2 Inputs

3-V or 5-V Digital Interface Compatible

Low Power: 218 mW Max at 5 V

Power Down: 1 mW Max

5-V Analog Single Supply Operation

Internal Voltage References . . . 50 PPM/°C and ±5% Accuracy

Glueless DSP Interface

Parallel µC/DSP Interface

applications

Radar Applications

Communications

Control Applications

High-Speed DSP Front-End

Automotive Applications

description

D0 D1 D2 D3 D4 D5

BGND

D6 D7 D8 D9

RA0/D10

RA1/D11

CONV_CLK

SYNC

DA PACKAGE

(TOP VIEW)

NC RESET AINP AINM AGND REFOUT REFP REFM AGND AV

CS0 CS1 WR

(R/W) RD DV

DGND

The THS1209 is a CMOS, low-power , 12-bit, 8 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers allow for programming the ADC into the desired mode. The THS1209 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application.

The THS1209C is characterized for operation from 0°C to 70°C, and the THS1209I is characterized for operation from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGED DEVICE

0°C to 70°C THS1209CDA

–40°C to 85°C THS1209IDA

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TSSOP

(DA)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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THS1209 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

SLAS288 – JULY 2000

functional block diagram

REFP

REFM

REFIN

AINP

AINM

CONV_CLK

CS0 CS1

WR (R/W)

RESET

S/H

Control

S/H

Logic

and

Single-Ended

and/or

Differential

MUX

Control

+ –

REFP

12-Bit

Pipeline

ADC

3.5 V

1.5 V

REFM

1.225 V REF

Buffers

2.5 V

REFOUT

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10/RA0 D11/RA1

BGND

SYNC

AGND DGND

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I/O

DESCRIPTION

THS1209

12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS288 – JULY 2000

Terminal Functions

TERMINAL

NAME NO.

AINP 30 I Analog input, single-ended or positive input of differential channel A AINM 29 I Analog input, single-ended or negative input of differential channel A AV

AGND 24 I Analog ground BV

BGND 8 I Digital ground for buffer CONV_CLK 15 I Digital input. This input is the conversion clock input CS0 22 I Chip select input (active low) CS1 21 I Chip select input (active high) SYNC 16 O Synchronization output. This signal indicates in a multi-channel operation that data of channel A is

DGND 17 I Digital ground. Ground reference for digital circuitry. DV

D0 – D9 1–6, 9–12 I/O/Z Digital input, output; D0 = LSB RA0/D10 13 I/O/Z Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This

RA1/D11 14 I/O/Z Digital input, output (D1 1 = MSB). The data line D11 is also used as an address line (RA1) for the control

NC 32 O Not connected REFIN 28 I Common-mode reference input for the analog input channels. It is recommended that this pin be

REFP 26 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference

REFM 25 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference

RESET 31 I Hardware reset of the THS1209. Sets the control register to default values. REFOUT 27 O Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The reference

†

WR (R/W)

†

The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.

†

23 I Analog supply voltage

7 I Digital supply voltage for buffer

brought to the digital output and can therefore be used for synchronization.

18 I Digital supply voltage

is required for writing to control register 0 and control register 1. See Table 8.

connected to the reference output REFOUT.

voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 9.

output requires a capacitor of 10 µF to AGND for filtering and stability .

19 I The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input,

20 I This input is programmable. It functions as a read-write input (R/W) and can also be configured as a

active low as a data read select from the processor. See timing section.

write-only input (WR

input is used as a read input from the processor. See timing section.

the RD

), which is active low and used as data write select from the processor. In this case,

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THS1209

High-level input voltage, V

Low-level input voltage, V

Operating free-air temperature, T

°C

12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

SLAS288 – JULY 2000

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range: DGND to DVDD –0.3 V to 8.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BGND to BVDD –0.3 V to 8.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AGND to AV

–0.3 V to 8.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range AGND – 0.3 V to AVDD + 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage –0.3 + AGND to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range –0.3 V to BVDD/DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range: THS1209C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

THS1209I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–85°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

power supply

MIN NOM MAX UNIT

Supply voltage

AV DV BV

4.75 5 5.25

4.75 5 5.25 3 5.25

analog and reference inputs

MIN NOM MAX UNIT

Analog input voltage in single-ended configuration V Common-mode input voltage VCM in differential configuration 1 2.5 4 V External reference voltage,V External reference voltage, V Input voltage difference, REFP – REFM 2 V

(optional) 3.5 AVDD–1.2 V

REFP

(optional) 1.4 1.5 V

REFM

REFP

digital inputs

MIN NOM MAX UNIT

Input CONV_CLK frequency DVDD = 4.75 V to 5.25 V 0.1 8 MHz CONV_CLK pulse duration, clock high, t

CONV_CLK pulse duration, clock low, t

w(CONV_CLKH)

w(CONV_CLKL)

BVDD = 3.3 V 2 V BVDD = 5.25 V 2.8 V BVDD = 3.3 V 0.8 V BVDD = 5.25 V 0.8 V

DVDD = 4.75 V to 5.25 V 62 62 5000 ns DVDD = 4.75 V to 5.25 V 62 62 5000 ns

THS1209CDA 0 70 THS1209IDA –40 85

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12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS288 – JULY 2000

electrical characteristics over recommended operating conditions, AVDD = DVDD = 5 V, BV

digital specifications

= 3.3 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Digital inputs

I I C

Digital outputs

V V I C C

High-level input current DVDD = digital inputs –50 50 µA

Low-level input current Digital input = 0 V –50 50 µA

Input capacitance 5 pF

High-level output voltage I

Low-level output voltage I

High-impedance-state output current CS1 = DGND, CS0 = DV

Output capacitance 5 pF

Load capacitance at databus D0 – D11 30 pF

= –50 µA, BVDD = 3.3 V, 5 V BVDD–0.5 V

= 50 µA, BVDD = 3.3 V, 5 V 0.4 V

–10 10 µA

THS1209

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1209

Offset error

12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

SLAS288 – JULY 2000

electrical characteristics over recommended operating conditions, AVDD = DVDD = 5 V, BV

= 3.3 V, fs = 8 MSPS, V

dc specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 12 Bits

Accuracy

Integral nonlinearity, INL ±1.5 LSB Differential nonlinearity , DNL ±1 LSB

Gain error –20 20 LSB

Analog input

Input capacitance 15 pF Input leakage current V

Internal voltage reference

Accuracy, V Accuracy, V Temperature coefficient 50 PPM/°C Reference noise 100 µV Accuracy, REFOUT 2.475 2.5 2.525 V

Power supply

DDA

DDD

DDB

Analog supply current AVDD = DVDD = 5 V, BVDD = 3.3 V 38 40 mA Digital supply voltage AVDD = DVDD = 5 V, BVDD = 3.3 V 0.5 1 mA Buffer supply voltage AVDD = DVDD = 5 V, BVDD = 3.3 V 1.5 4 mA Power dissipation AVDD = DVDD = 5 V, BVDD = 3.3 V 188 218 mW Power dissipation in power down with con-

version clock inactive

REFP REFM

= internal (unless otherwise noted)

REF

After calibration in single-ended mode 20 LSB After calibration in differential mode –20 20 LSB

= V

AIN

AVDD = DVDD = 5 V, BVDD = 3.3 V 0.25 mW

REFM

to V

REFP

±10 µA

3.3 3.5 3.7 V

1.4 1.5 1.6 V

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SINAD

Signal-to-noise ratio

distortion

SNR

Signal-to-noise ratio

THD

T otal harmonic distortion

Effective number of bits

SFDR

Spurious free dynamic range

THS1209

12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS288 – JULY 2000

electrical characteristics over recommended operating conditions, V f

= 2 MHz at –1dBFS (unless otherwise noted)

ac specifications, AVDD = DVDD = 5 V, BVDD = 3.3 V, CL < 30 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ENOB (SNR)

Analog Input

Full-power bandwidth with a source impedance of 150 Ω in differential configuration.

Full-power bandwidth with a source impedance of 150 Ω in single-ended configuration.

Small-signal bandwidth with a source impedance of 150 Ω in differential configuration.

Small-signal bandwidth with a source impedance of 150 Ω in single-ended configuration.

Differential mode 63 65 dB Single-ended mode 62 64 dB Differential mode 64 69 dB Single-ended mode 64 68 dB Differential mode –70 –67 dB Single-ended mode –68 –64 dB Differential mode 10.17 10.5 Bits Single-ended mode 10 10.3 Bits Differential mode 67 71 dB Single-ended mode 65 69 dB

Full scale sinewave, –3 dB 98 MHz

Full scale sinewave, –3 dB 54 MHz

100 mVpp sinewave, –3 dB 98 MHz

100 mVpp sinewave, –3 dB 54 MHz

= internal, fs = 8 MSPS,

REF

timing specifications, AV

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

d(pipe)

su(CONV_CLKL–READL)

su(READH–CONV_CLKL)

dCONV_CLKL–SYNCL)

d(CONV_CLKL–SYNCH)

Latency 5 Setup time, CONV_CLK low before CS valid 10 ns

Setup time, CS invalid to CONV_CLK low 20 ns Delay time, CONV_CLK low to SYNC low 10 ns Delay time, CONV_CLK low SYNC high 10 ns

= DVDD = 5 V, BV

= 3.3 V, V

= Internal, CL < 30 pF

REF

CONV

CLK

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THS1209 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

SLAS288 – JULY 2000

detailed description

reference voltage

The THS1209 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V and VREFM is set to 1.5 V . An external reference can also be used through two reference input pins, REFP and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.

analog inputs

The THS1209 consists of two analog inputs, which are sampled simultaneously . These inputs can be selected individually and configured as single-ended or differential inputs. The desired analog input channel can be programmed.

converter

The THS1209 uses a 12-bit pipelined multistaged architecture which achieves a high sample rate with low power consumption. The THS1209 distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while the second through the eighth stages operate on the seven preceding samples.

conversion

An external clock signal with a duty cycle of 50% has to be applied to the clock input (CONV_CLK). A new conversion is started with every falling edge of the applied clock signal. The conversion values are available at the output with a latency of 5 clock cycles.

sampling rate

The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1 shows the maximum conversion rate for different combinations.

Table 1. Maximum Conversion Rate

CHANNEL CONFIGURATION NUMBER OF CHANNELS

1 single-ended channel 1 8 MSPS 2 single-ended channels 2 4 MSPS 1 differential channel 1 8 MSPS 2 differential channels 2 4 MSPS 1 single-ended and 1 differential channel 2 4 MSPS

MAXIMUM CONVERSION

RATE PER CHANNEL

The maximum conversion rate in the continuous conversion mode per channel, fc, is given by:

8 MSPS

# channels

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12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS288 – JULY 2000

conversion mode

During conversion, the ADC operates with a free running external clock signal applied to the input CONV_CLK. With every falling edge of the CONV_CLK signal a new converted value is available to the databus with the corresponding read signal. The THS1209 offers up to two analog inputs to be selected. It is important to provide the channel information to the system, this means to know which channel is available to the databus. T o maintain this channel integrity, the THS1209 an output signal SYNC, which is always active low if data of channel 1 is applied to the databus.

Figure 3 shows the timing of the conversion when one analog input channel is selected. The maximum throughput rate is 8 MSPS in this mode. The signal SYNC is disabled for the selection of one analog input since this information is not required for one analog input. There is a certain timing relationship required for the read signal with respect to the conversion clock. This can be seen in Figure 2 and T able 2. A more detailed description of the timing is given in the section timing and signal description of the THS1209.

Sample N

Channel 1

Sample N+1

Channel 1

Sample N+2

Channel 1

Sample N+3

Channel 1

Sample N+4

Channel 1

Sample N+5

Channel 1

Sample N+6

Channel 1

Sample N+7

Channel 1

Sample N+8

Channel 1

THS1209

AIN

d(A)

w(CONV_CLKH)

w(CONV_CLKL)

CONV_CLK

su(CONV_CLKL–READL)

†

READ

Data N–4

Channel 1

†

READ is the logical combination from CSO

Figure 1. Conversion Timing in 1-Channel Operation

Data N–3

Channel 1

, CS1, and RD

d(pipe)

Data N–2

Channel 1

su(READH_CONV–CLKL)

Data N–1

Channel 1

Data N

Channel 1

Data N+1

Channel 1

Data N+2

Channel 1

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THS1209 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

SLAS288 – JULY 2000

Figure 3 shows the conversion timing when two analog input channels are selected. The maximum throughput rate per channel is 4 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted data is available to the data bus. The SYNC signal is always active low if data of channel 1 is available to the data bus. There is a certain timing relationship required for the read signal with respect to the conversion clock. This can be seen in Figure 2 and T able 2. A more detailed description of the timing is given in the section timing and signal description of the THS1209.

AIN

w(CONV_CLKH)

CONV_CLK

†

READ

SYNC

Sample N

Channel 1, 2

d(A)

su(CONV_CLKL–READL)

Sample N+1 Channel 1, 2

w(CONV_CLKL)

d(pipe)

Sample N+2 Channel 1, 2

su(READH–CONV_CLKL)

d(CONV_CLKL–SYNCL)

Sample N+3 Channel 1, 2

Sample N+4 Channel 1, 2

d(CONV_CLKL–SYNCH)

Data N–2

Channel 1

†

READ is the logical combination from CSO

Figure 2. Conversion Timing in 2 Channel Operation

Data N–2

Channel 2

, CS1, and RD

Data N–1

Channel 1

Data N–1

Channel 2

Data N

Channel 1

Data N

Channel 2

Data N+1 Channel 1

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