Texas Instruments THS1050EVM, THS1050IPHP, THS1050CPHP Datasheet
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278 – APRIL 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
features
D
50 MSPS Maximum Sample Rate
D
10-Bit Resolution
D
No Missing Codes
D
On-Chip Sample and Hold
D
73 dB Spurious Free Dynamic Range at
fin = 15.5 MHz
D
5 V Analog and Digital Supply
D
3 V and 5 V CMOS Compatible Digital
Output
D
9.7 Bit ENOB at fIN = 31 MHz
D
60 dB SNR at fIN = 31 MHz
D
82 MHz Bandwidth
D
Internal or External Reference
D
Buffered 900 Ω Differential Analog Input
applications
D
Wireless Local Loop
D
Wireless Internet Access
D
Cable Modem Receivers
D
Medical Ultrasound
D
Magnetic Resonant Imaging
description
The THS1050 is a high speed low noise 10-bit
CMOS pipelined analog-to-digital converter. A
differential sample and hold minimizes even order
harmonics and allows for a high degree of
common mode rejection at the analog input. A
buffered analog input enables operation with a
constant analog input impedance, and prevents
transient voltage spikes from feeding backward to
the analog input source. Full temperature DNL
performance allows for industrial application with
the assurance of no missing codes. The typical
integral nonlinearity (INL) for the THS1050 is less
than one LSB. The superior INL curve of the THS1050 results in SFDR performance that is exceptional for a
10-bit analog-to-digital converter. The THS1050 can operate with either internal or external references. Internal
reference usage selection is accomplished simply by externally connecting reference output terminals to
reference input terminals.
AVAILABLE OPTIONS
PACKAGE
T
A
48-TQFP
(PHP)
–40°C to 85°C THS1050I
0°C to 70°C THS1050C
Copyright 2000, Texas Instruments Incorporated
14 15
NC
NC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
AV
SS
AV
DD
V
IN+
V
IN–
AV
DD
V
REFOUT–
V
REFIN
–
V
REFIN
+
V
REFOUT
+
V
BG
AV
SS
AV
DD
17 18 19 20
47 46 45 44 4348 42
V
AV
CLK+
40 39 3841
21
22 23 24
37
13
CLK–
48 PHP PACKAGE
(TOP VIEW)
CM
DD
DVDDDVSSDVSSDVDDDVSSDV
DD
DRV
SS
DRV
DD
AVSSAVSSAVDDAV
SS
DRVSSAVSSDRV
SS
AV
DD
DRVDDDRV
DD
DV
SS
AV
SS
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278 – APRIL 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Digital Error Correction
S/H
Stage 1 Stage 10
Reference
3.0 V
2.0 V
AV
DD/2
Timing
V
IN–
V
REFOUT+
V
CM
CLK+
DV
SS
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
AVDDDV
DD
D/A
Σ
A/D
Σ
D/AA/D A/D
V
REFOUT–
V
REFIN+
V
REFIN–
CLK–
1
1
1
Buffer
DRV
DD
AV
SS
DRV
SS
Stages 2 – 9
V
IN+
900 Ω
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
AV
DD
2, 5, 12 43,
45, 47
I Analog power supply
AV
SS
1, 11, 13, 41,
42, 44, 46
I Analog ground return for internal analog circuitry
CLK+ 15 I Clock input
CLK– 16 I Complementary clock input
D9–D0 25–34 O Digital data output bits; LSB= D0, MSB = D9 (2s complement output format)
DRV
DD
24, 37, 38 I Digital output driver supply
DRV
SS
23, 39, 40 I Digital output driver ground return
DV
DD
17, 20, 22 I Positive digital supply
DV
SS
18, 19, 21 I Digital ground return
V
BG
10 O Band gap reference. Bypass to ground with a 1 µF and a 0.01 µF chip capacitor.
V
CM
48 O Common mode voltage output. Bypass to ground with a 0.1 µF and a 0.01 µF chip device capacitor.
V
IN+
3 I Analog signal input
V
IN–
4 I Complementary analog signal input
V
REFIN–
7 I External reference input low
V
REFIN+
8 I External reference input high
V
REFOUT+
9 O Internal reference output. Compensate with a 1 µF and a 0.01 µF chip capacitor.
V
REFOUT–
6 O Internal reference output. Compensate with a 1 µF and a 0.01 µF chip capacitor.
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278 – APRIL 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
The THS1050 uses a differential pipeline architecture and assures no missing codes over the full operating
temperature range. The device uses a 1 bit per stage architecture in order to achieve the highest possible
bandwidth. The differential analog inputs are terminated with a 900-Ω resistor . The inputs are then fed to a unity
gain buffer followed by the S/H (sample and hold) stage. This S/H stage is a switched capacitor operational
amplifier based circuit, see Figure 3. The pipeline is a typical 1 bit per stage pipeline as shown in the functional
block diagram. The digital output of the 10 stages and the last 1 bit flash are sent to a digital correction logic
block which then outputs the final 10 bits.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range: AVDD –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DV
DD
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRVDD –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage between AVSS and DVSS –0.3 V to 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage between DRVDD and DVDD –0.5 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage between AVDD and DVDD –0.5 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital data output –0.3 V to DV
DD
+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLK peak input current 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak total input current (all inputs) –30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: THS1050C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THS1050I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
PARAMETER MIN NOM MAX UNIT
Sample rate 1 50 MSPS
Analog supply voltage, AV
DD
4.75 5 5.25 V
Digital supply voltage, DV
DD
4.75 5 5.25 V
Digital output driver supply voltage, DRV
DD
3 3.3 5.25 V
CLK + high level input voltage, V
IH
4 5 5.5 V
CLK + low-level input voltage, V
IL
0 1 V
CLK – high-level input voltage, V
IH
4 5 5.5 V
CLK – low-level input voltage, V
IL
0 1 V
CLK pulse-width high, t
p(H)
9 10 ns
CLK pulse-width low, t
p(L)
9 10 ns
Operating free-air temperature range, T
A
THS1050C 0 70 °C
Operating free-air temperature range, T
A
THS1050I –40 85 °C
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278 – APRIL 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
AV
DD
= DVDD = 5 V, DRVDD = 3.3 V, internal references, CLK = 50 MHz (unless otherwise noted)
†
dc accuracy
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
DNL Differential nonlinearity ±0.3 ±0.6 LSB
No missing codes Assured
INL Integral nonlinearity ±0.9 ±2.5 LSB
E
O
Offset error 14 29 mV
E
G
Gain error –7 –10 %FSR
†
All typical values are at TA = 25°C.
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I(AV
DD)
Analog supply current V(VIN) = V(VCM) 100 145 mA
I(DV
DD)
Digital supply current V(VIN) = V(VCM) 2 5 mA
I(DRV
DD)
Output driver supply current V(VIN) = V(VCM) 2 6 mA
P
D
Power dissipation V(VIN) = V(VCM) 0.5 W
†
All typical values are at TA = 25°C.
reference
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
REFOUT–
Negative reference output voltage 1.95 2 2.05 V
V
REFOUT+
Positive reference output voltage 2.95 3 3.05 V
V
REFIN–
External reference supplied 2 V
V
REFIN+
External reference supplied 3 V
V(VCM) Common mode output voltage AVDD/2 V
I(VCM) Common mode output current 10 µA
†
All typical values are at TA = 25°C.
analog input
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RIDifferential input resistance 900 Ω
CIDifferential input capacitance 4 pF
VIAnalog input common mode range VCM ±0.05 V
VIDDifferential input voltage range 2
V p-p
BW Analog input bandwidth (large signal) –3 dB 82 MHz
†
All typical values are at TA = 25°C.
digital outputs
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
High-level output voltage IOH = –50 µA 0.8DRV
DD
V
V
OL
Low-level output voltage IOL = 50 µA 0.2DRV
DDVDD
C
L
Output load capacitance 15 pF
†
All typical values are at TA = 25°C.
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278 – APRIL 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ac specifications over recommended operating free-air temperature range, AVDD = DVDD = 5 V,
DRV
DD
= 3.3 V, internal references, CLK = 50 MHz, analog input at – 2 dBFS (unless otherwise
noted)
†
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fIN = 2.2 MHz 61
SNR Signal-to-noise ratio
fIN =15.5 MHz
58 61
dBFS
fIN =31 MHz 60.5
fIN = 2.2 MHz 60.5
SINAD Signal-to-noise and distortion
fIN =15.5 MHz
56 60.8
dBFS
fIN =31 MHz 60.2
ENOB Effective number of bits fIN =15.5 MHz 9.3 9.8 bits
THD Total harmonic distortion fIN =15.5 MHz –72 –63
SFDR Spurious-free dynamic range fIN =15.5 MHz 65 73
dBc
fIN = 2.2 MHz –83
2
n
d
Harmonic Distortion
fIN =15.5 MHz
–89 –65
dBc
fIN = 31 MHz –77
fIN = 2.2 MHz –68
3
r
d
Harmonic Distortion
fIN =15.5 MHz
–73 –65
dBc
fIN = 31 MHz –80
Two tone SFDR
F1 = 14.9 MHz, F2 = 15.6 MHz,
Analog inputs at – 8 dBFS each
72 dBc
†
All typical values are at TA = 25°C.
operating characteristics over recommended operating conditions, AVDD = DVDD = 5 V,
DRV
DD
= 3.3 V
†
switching specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Aperture delay, t
d(A)
120 ps
Aperture jitter 1 ps RMS
Output delay t
d(O)
After falling edge of CLK+ 13 ns
Pipeline delay t
d(PIPE)
6.5
CLK
Cycle
†
All typical values are at TA = 25°C.
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278 – APRIL 2000
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
definitions of specifications
analog bandwidth
The analog input frequency at which the spectral power of the fundamental frequency of a large input signal
is reduced by 3 dB.
aperture delay
The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is
sampled.
aperture uncertainity (jitter)
The sample-to-sample variation in aperture delay
differential nonlinearity
The average deviation of any output code from the ideal width of 1 LSB.
clock pulse width/duty cycle
Pulse width high is the minimum amount of time that the clock pulse should be left in logic 1 state to achieve
rated performance; pulse width low is the minimum time clock pulse should be left in low state. At a given clock
rate, these specs define acceptable clock duty cycles.
offset error
The difference between the analog input voltage at which the analog-to-digital converter output changes from
negative full scale, to one LSB above negative full scale, and the ideal voltage at which this transition should
occur.
gain error
The maximum error in LSBs between a digitized ideal full scale low frequency offset corrected triangle wave
analog input, from the ideal digitized full scale triangle wave, divided by the full scale range, in this case 1024.
harmonic distortion
The ratio of the power of the fundamental to a given harmonic component reported in dBc.
integral nonlinearity
The deviation of the transfer function from an end-point adjusted reference line measured in fractions of 1 LSB.
Also the integral of the DNL curve.
output delay
The delay between the 50% point of the falling edge of the clock and signal and the time when all output data
bits are within valid logic levels (not including pipeline delay).
signal-to-noise-and distortion (SINAD)
When tested with a single tone, the ratio of the signal power to the sum of the power of all other spectral
components, excluding dc, referenced to full scale.
signal-to-noise ratio (SNR)
When tested with a single tone, the ratio of the signal power to the sum of the power of all other power spectral
components, excluding dc and the first 9 harmonics, referenced to full scale.
effective number of bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the effective number of bits, using the following formula,
ENOB
+
(
SINAD*1.76
)
6.02
spurious-free dynamic range (SFDR)
The ratio of the signal power to the power of the worst spur, excluding dc. The worst spurious component may
or may not be a harmonic. The ratio is reported in dBc (that is, degrades as signal levels are lowered).
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