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THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUARY 2002
10-Bit, 40-MSPS ANALOG-TO-DIGITAL CONVERTER
WITH PGA AND CLAMP
FEATURES
Analog Supply 3 V
D
D Digital Supply 3 V
D Configurable Input Functions:
– Single-Ended
– Single-Ended With Analog Clamp
– Single-Ended With Programmable Digital
Clamp
– Differential
D Built-In Programmable Gain Amplifier (PGA)
D Differential Nonlinearity: ±0.45 LSB
D Signal-to-Noise: 60 dB Typ at 4.8 MHz
D Spurious Free Dynamic Range: 72 dB
D Adjustable Internal Voltage Reference
D Unsigned Binary/2s Complement Output
D Out-of-Range Indicator
D Power-Down Mode
APPLICATIONS
Video/CCD Imaging
D
D Communications
D Set-Top-Box
D Medical
DESCRIPTION
The THS1041 is a CMOS, low power, 10-bit, 40 MSPS
analog-to-digital converter (ADC) that operates from a
single 3-V supply . The THS1041 has been designed to
give circuit developers flexibility . The analog input to the
THS1041 can be either single-ended or differential.
This device has a built-in clamp amplifier whose clamp
input level can be driven from an external dc source or
from an internal high-precision 10-bit digital clamp level
programmable via an internal CLAMP register. A 3-bit
PGA is included to maintain SNR for small signals. The
THS1041 provides a wide selection of voltage
references to match the user’s design requirements.
For more design flexibility , the internal reference can be
bypassed to use an external reference to suit the dc
accuracy and temperature drift requirements of the
application. The out-of-range output indicates any
out-of-range condition in THS1041’s input signal. The
format of the digital output can be coded in either
unsigned binary or 2s complement.
The speed, resolution, and single-supply operation of
the THS1041 are suited to applications in set-top-box
(STB), video, multimedia, imaging, high-speed
acquisition, and communications. The built-in clamp
function allows dc restoration of a video signal and is
suitable for video applications. The speed and
resolution ideally suit charge-couple device (CCD) input
systems such as color scanners, digital copiers, digital
cameras, and camcorders. A wide input voltage range
allows the THS1041 to be applied in both imaging and
communications systems.
The THS1041C is characterized for operation from 0°C
to 70°C, while the THS1041I is characterized for
operation from –40°C to 85°C.
28-PIN TSSOP/SOIC PACKAGE
AGND
DV
DGND
DD
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
OVR
(TOP VIEW)
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
AV
DD
AIN+
VREF
AIN–
REFB
MODE
REFT
CLAMPOUT
CLAMPIN
CLAMP
REFSENSE
WR
OE
CLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright 2002, Texas Instruments Incorporated
1
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
T
A
0°C to 70°C THS1041CPW THS1041CDW
–40°C to 85°C THS1041IPW THS1041IDW
functional block diagram
CLAMPIN
Clamp
Logic
AVAILABLE OPTIONS
28-TSSOP (PW) 28-SOIC (DW)
Clamp
Logic
PACKAGED DEVICES
10 Bit
DAC
Clamp
Logic
Digital
Interface
WR
CLAMPOUT
CLAMP
AIN+
AIN–
MODE
AV
DD
AGND
Mode
Detection
VREF
NOTE: A1 – Internal bandgap reference
A2 – Internal ADC reference generator
A2
SHPGA
10 Bit
ADC
ADC
Reference
Resistor
REFB REFT
VREF
3-State
Output
Buffers
Timing
Circuit
A1
0.5 V
REFSENSE
+
–
I/O (0–9)
OVR
OE
DV
DD
DGND
CLK
2
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SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
THS1041
Terminal Functions
TERMINAL
NAME NO.
AGND 1 I Analog ground
AIN+ 27 I Positive analog input
AIN– 25 I Negative analog input
AV
DD
CLAMP 19 I High to enable clamp mode, low to disable clamp mode
CLAMPIN 20 I Connect to an external analog clamp reference input.
CLAMPOUT 21 O
CLK 15 I Clock input
DGND 14 I Digital ground
DV
DD
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
MODE 23 I Operating mode select (AGND, AVDD/2, AVDD)
OE 16 I High to high-impedance state the data bus, low to enable the data bus
OVR 13 O Out-of-range indicator
REFB 24 I/O Bottom ADC reference voltage
REFSENSE 18 I VREF mode control
REFT 22 I/O Top ADC reference voltage
VREF 26 I/O Internal or external reference
WR 17 I Write strobe
I/O
28 I Analog supply
The CLAMPOUT pin can provide a dc restoration or a bias source function (see AC reference generation
section). If neither function is required then the clamp can be disabled to save power (see power management
section).
2 I Digital supply
3
4
5
6
7
8
9
10
11
12
Digital I/O bit 0 (LSB)
Digital I/O bit 1
Digital I/O bit 2
Digital I/O bit 3
Digital I/O bit 4
I/O
Digital I/O bit 5
Digital I/O bit 6
Digital I/O bit 7
Digital I/O bit 8
Digital I/O bit 9 (MSB)
DESCRIPTION
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3
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range: AV
to AGND, DVDD to DGND –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
†
AGND to DGND –0.3 V to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AV
to DV
DD
DD
MODE input voltage range, MODE to AGND –0.3 V to AV
Reference voltage input range, REFT, REFB, to AGND –0.3 V to AV
Analog input voltage range, AIN to AGND –0.3 V to AV
Reference input voltage range, VREF to AGND –0.3 V to AV
Reference output voltage range, VREF to AGND –0.3 V to AV
Clock input voltage range, CLK to AGND –0.3 V to AV
Digital input voltage range, digital input to DGND –0.3 V to DV
Digital output voltage range, digital output to DGND –0.3 V to DV
Operating junction temperature range, T
Storage temperature range, T
stg
J
–4 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
0°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, AVDD, DV
High-level digital input, V
Low-level digital input, V
Minimum digital output load resistance, R
Maximum digital output load capacitance, C
Clock frequency, f
Clock duty cycle 45% 50% 55%
p
Operating free-air temperature
clk
DD
IH
IL
L
L
p
THS1041C 0 25 70
THS1041I –40 25 85
3 3 3.6 V
DV
DD
DGND DGND V
100 kΩ
5 40 MHz
DV
DD
10 pF
°
°C
V
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V,
= 40 MSPS/50% duty cycle, MODE = AVDD (internal reference), differential input range = 1 Vpp
f
s
and 2 Vpp, PGA = 1X, T
dc accuracy
Resolution 10 Bits
INL Integral nonlinearity (see definitions) ±0.75 ±1.5 LSB
DNL Differential nonlinearity (see definitions) ±0.3 ±1 LSB
Zero error (see definitions) 0.7 1.5 %FSR
Full-scale error (see definitions) 2.2 3 %FSR
Missing code No missing code assured
4
A
= T
to T
min
PARAMETER MIN TYP MAX UNIT
(unless otherwise noted)
max
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SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
THS1041
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V,
= 40 MSPS/50% duty cycle, MODE = AVDD (internal reference), differential input range = 1 Vpp
f
s
and 2 Vpp, PGA = 1X, T
power supply
AV
DD
DV
DD
I
CC
P
D
P
D(STBY)
NOTES: 1. Actual values will vary slightly depending on application clamp load, VREF load, etc.
analog inputs
Differential analog input voltage, V
Reference input voltage, V
Clamp input voltage, V
REFT, REFB external ADC reference voltages inputs (MODE = AGND)
Supply voltage
Operating supply current All circuits active, See Note 1 34 42 mA
Power dissipation All circuits active 103 125 mW
Standby power 75 µW
Power up time for all references from standby, t
Wake-up time, t
2. Wake-up time is from the power-down state to accurate ADC samples being taken and is specified for MODE = AGND with external
reference sources applied to the device at the time of release of power-down and an applied 40-MHz clock. Circuits that need to
power up are the bandgap, bias generator, ADC, and SHPGA.
I(VREF)
I(CLAMPIN)
Reference input voltage, REFT–REFB 0.5
Reference common mode voltage, (REFT + REFB)/2 AVDD = 3 1.5 V
Input resistance between REFT and REFB 1.9 kΩ
= T
A
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(WU)
I(AIN)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
to T
min
= AIN+ – AIN– –1 1 V
(unless otherwise noted) (continued)
max
(PU)
See Note 2 45 µs
3 3 3.6
3 3 3.6
770 µs
MIN NOM MAX UNIT
0.5 1 V
0.1 AVDD–0.1 V
1
V
V
REFT, REFB internal ADC reference voltages outputs (MODE = AVDD or AVDD/2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference voltage top, REFT
Refence voltage bottom, REFB
VREF = 0.5 V
VREF = 1 V
VREF = 0.5 V
VREF = 1 V
AVDD = 3 V
AVDD = 3 V
1.75
1.25
VREF (on-chip voltage reference generator)
PARAMETER MIN TYP MAX UNIT
Internal 0.5-V reference voltage (REFSENSE = VREF) 0.45 0.5 0.55 V
Internal 1-V reference voltage (REFSENSE = AGND) 0.95 1 1.05 V
External reference voltage (REFSENSE = AVDD) 0.5 1 V
Reference input resistance (REFSENSE = AVDD, MODE = AVDD/2 or AVDD) 14 kΩ
2
1
V
V
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5
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V,
= 40 MSPS/50% duty cycle, MODE = AVDD (internal reference), differential input range = 1 Vpp
f
s
and 2 Vpp, PGA = 1X, T
dynamic performance (ADC and PGA)
ENOB Effective number of bits
SFDR Spurious free dynamic range
THD T otal harmonic distortion
SNR Signal-to-noise ratio
SINAD Signal-to-noise and distortion
BW Full power bandwidth (–3 dB) 900 MHz
PGA
Gain range (linear scale) 0.5 4 V/V
Gain step size (linear scale) 0.5 V/V
Gain error (deviation from ideal, all gain settings) –3% 3%
Number of control bits 3 Bits
= T
A
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
to T
min
PARAMETER MIN TYP MAX UNIT
(unless otherwise noted) (continued)
max
f = 4.8 MHz, –0.5 dBFS 8.8 9.6
f = 20 MHz, –0.5 dBFS
f = 4.8 MHz, –0.5 dBFS 60.5 72
f = 20 MHz, –0.5 dBFS
f = 4.8 MHz, –0.5 dBFS –72.5 –61.3
f = 20 MHz, –0.5 dBFS
f = 4.8 MHz, –0.5 dBFS 55.7 60
f = 20 MHz, –0.5 dBFS
f = 4.8 MHz, –0.5 dBFS 55.6 59.7
f = 20 MHz, –0.5 dBFS
9.5
70
–71.6
57
59.6
Bits
dB
dB
dB
dB
clamp amplifier and clamp DAC
PARAMETER MIN TYP MAX UNIT
Resolution 10 Bits
DAC output range REFB REFT V
DAC differential nonlinearity –1 1 LSB
DAC integral nonlinearity ±1 LSB
Clamping analog output voltage range 0.1 AVDD–0.1 V
Clamping analog output voltage error –40 40 mV
NOTE: The CLAMPOUT pin must see a load capacitance of at least 10 nF to ensure stability of the on-chip clamp buffer. When using the clamp
for dc restoration, the signal coupling capacitor should be at least 10 nF. When using the clamp buffer as a dc biasing reference,
CLAMPOUT should be decoupled to analog ground through at least a 10-nF capacitor.
6
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SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
THS1041
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V,
= 40 MSPS/50% duty cycle, MODE = AVDD (internal reference), differential input range = 1 Vpp
f
s
and 2 Vpp, PGA = 1X, T
digital specifications
Digital Inputs
V
IH
V
IL
I
IH
I
IL
C
i
Digital Outputs
V
OH
V
OL
Clock Input
t
c
t
w(CKH)
t
w(CKL)
t
d(o)
t
d(AP)
High-level input voltage
Low-level input voltage
High-level input current 1 µA
Low-level input current
Input capacitance 5 pF
High-level output voltage I
Low-level output voltage I
High impedance output current ±1 µA
Rise/fall time C
Clock cycle 25 200 ns
Pulse duration, clock high 11.25 110 ns
Pulse duration, clock low 11.25 110 ns
Clock duty cycle 45% 50% 55%
Clock to data valid, delay time 9.5 16 ns
Pipeline latency 4 Cycles
Aperture delay time 0.1 ns
Aperture uncertainty (jitter) 1 ps
A
= T
to T
min
PARAMETER MIN NOM MAX UNIT
(unless otherwise noted) (continued)
max
Clock input 0.8 × AV
All other inputs
Clock input 0.2 × AV
All other inputs
= 50 µA DVDD–0.4 V
load
= 50 µA 0.4 V
load
= 15 pF 3.5 ns
load
0.8 × DV
DD
DD
0.2 × DV
DD
DD
|–1|
V
V
µA
timing
t
d(DZ)
t
d(DEN)
t
d(OEW)
t
d(WOE)
t
w(WP)
t
su
t
h
PARAMETER MIN TYP MAX UNIT
Output disable to Hi-Z output, delay time 0 10 ns
Output enable to output valid, delay time 0 10 ns
Output disable to write enable, delay time 12 ns
Write disable to output enable, delay time 12 ns
Write pulse duration 15 ns
Input data setup time 5 ns
Input data hold time 5 ns
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7
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
PARAMETER MEASUREMENT INFORMATION
OE
See Note A
t
d(OEW)
t
w(WP)
WE
t
d(DZ)
I/O
Hi-Z Hi-Z
NOTE A: All timing measurements are based on 50% of edge transition.
Figure 1. Write Timing Diagram
Analog
Input
t
w(CKH)
Sample 1
t
c
Sample 2
t
Sample 3
Sample 4
w(CKL)
t
su
Input OutputOutput
Sample 5
t
d(WOE)
t
h
t
d(DEN)
Sample 6
Sample 7
Input Clock
Digital
Output
OE
See
Note A
t
d(DEN)
Pipeline Latency
NOTE A: All timing measurements are based on 50% of edge transition.
Figure 2. Digital Output Timing Diagram
t
d(o)
(I/O Pad Delay or
Propagation Delay)
Sample 1
t
d(DZ)
Sample 2
8
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SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
THS1041
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
vs
1.0
AVDD = 3 V
DVDD = 3 V
0.5
fs = 40 MSPS
V
= 1 V
ref
0.0
–0.5
–1.0
0 128 256 384 512 640 768 896 1024
DNL – Differential Nonlinearity – LSB
INTEGRAL NONLINEARITY
1.0
INPUT CODE
Input Code
Figure 3
vs
INPUT CODE
INL – Integral Nonlinearity – LSB
0.5
0.0
–0.5
–1.0
AVDD = 3 V
DVDD = 3 V
fs = 40 MSPS
V
= 1 V
ref
0 128 256 384 512 640 768 896 1024
Input Code
Figure 4
INTEGRAL NONLINEARITY
vs
1.0
0.5
0.0
–0.5
AVDD = 3 V
DVDD = 3 V
fs = 40 MSPS
V
= 0.5 V
ref
INPUT CODE
INL – Integral Nonlinearity – LSB
–1.0
0 128 256 384 512 640 768 896 1024
Input Code
Figure 5
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9
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
–80
Differential Input = 1 V
–75
–70
–6 dB
–65
–60
–55
–50
THD – Total Harmonic Distortion – dB
–45
–40
0 102030 405060708090100
–20 dB
See Note
fi – Input Frequency – MHz
–0.5 dB
Figure 6
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
61
59
57
Diff Input = 2 V
SE Input = 2 V
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
–80
–75
–70
–6 dB
See Note
0 102030405060708090100
THD – Total Harmonic Distortion – dB
–65
–60
–55
–50
–45
–40
–0.5 dB
–20 dB
fi – Input Frequency – MHz
Differential Input = 2 V
Figure 7
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
85
80
75
70
Diff Input = 2 V
Diff Input = 1 V
55
SE Input = 1 V
Diff Input = 1 V
53
51
SNR – Signal-to-Noise Ratio – dB
49
See Note
47
0 1020304050 60708090100
fi – Input Frequency – MHz
Figure 8
NOTE: AVDD = DVDD = 3 V, CLK = 40 MSPS, PGA = 1, 20-pF capacitors AIN+ to AGND and AIN– to AGND,
10
Input series resistor = 25 Ω,
2-V Input: Ext Ref, REFT = 2 V, REFB = 1 V
1-V Input: Ext Ref, REFT = 1.75 V, REFB = 1.25 V
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65
60
55
50
45
SE Input = 2 V
40
SFDR – Spurious Free Dynamic Range – dB
See Note
35
0102030405060708090100
fi – Input Frequency – MHz
SE Input = 1 V
Figure 9
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
THS1041
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE PLUS DISTORTION
vs
INPUT FREQUENCY
SINAD – Signal-to-Noise Plus Distortion – dB
65
Diff Input = 2 V
60
Diff Input = 1 V
55
50
45
SE Input = 1 V
40
See Note
35
0102030405060708090
fi – Input Frequency – MHz
SE Input = 2 V
100
–85
–80
–75
–70
–65
–60
–55
–50
–45
THD – Total Harmonic Distortion – dB
–40
–35
Figure 10
NOTE: AVDD = DVDD = 3 V, CLK = 40 MSPS, PGA = 1, 20-pF capacitors AIN+ to AGND and AIN– to AGND,
Input series resistor = 25 Ω,
2-V Input: Ext Ref, REFT = 2 V, REFB = 1 V
1-V Input: Ext Ref, REFT = 1.75 V, REFB = 1.25 V
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
Diff Input = 2 V
See Note
Diff Input = 1 V
SE Input = 1 V
SE Input = 2 V
0102030405060708090100
fi – Input Frequency – MHz
Figure 11
TOTAL HARMONIC DISTORTION
vs
SAMPLE RATE
–75
–70
–65
–60
–55
–50
THD – Total Harmonic Distortion – dB
–45
–40
0 5 10 20 25 30 35 40 45 50
15
Sample Rate – MSPS
Diff Input = 2 V
fi = 20 MHz, –0.5 dB
Figure 12
SIGNAL-TO-NOISE RATIO
vs
SAMPLE RATE
75
70
65
60
55
50
SNR – Signal-to-Noise Ratio – dB
45
40
0 5 10 20 25 30 35 40 45 50
15
Sample Rate – MSPS
Diff Input = 2 V
fi = 20 MHz, –0.5 dB
Figure 13
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11
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
TYPICAL CHARACTERISTICS
Spurious Free Dynamic Range – dB
75
73
71
69
67
65
63
61
59
57
3 3.1
75
73
71
SPURIOUS FREE DYNAMIC RANGE
vs
SUPPLY VOLTAGE
Diff Input = 2 V,
fi = 10 MHz, –0.5 dBFS
Sample Rate = 40 MSPS
VDD – Supply Voltage – V
Figure 14
SIGNAL-TO-NOISE RATIO
vs
SUPPLY VOLTAGE
Diff Input = 2 V,
fi = 10 MHz, –0.5 dBFS
Sample Rate = 40 MSPS
TOTAL HARMONIC DISTORTION
vs
SUPPLY VOLTAGE
–75
–73
–71
–69
–67
–65
–63
–61
THD – Total Harmonic Distortion – dB
–59
–57
3.63.2 3.3 3.4 3.5
3 3.1 3.63.2 3.3 3.4 3.5
VDD – Supply Voltage – V
Diff Input = 2 V,
fi = 10 MHz, –0.5 dBFS
Sample Rate = 40 MSPS
Figure 15
SIGNAL-TO-NOISE PLUS DISTORTION
vs
SUPPLY VOLTAGE
75
Diff Input = 2 V,
fi = 10 MHz, –0.5 dBFS
73
Sample Rate = 40 MSPS
71
12
69
67
65
63
61
SNR – Signal-to-Noise Ratio – dB
59
57
3 3.1 3.63.2 3.3 3.4 3.5
VDD – Supply Voltage – V
Figure 16
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69
67
65
63
61
59
SNRD – Signal-to-Noise Plus Distortion – dB
57
3 3.5 3.6
3.1 3.2 3.3 3.4
VDD – Supply Voltage – V
Figure 17
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
THS1041
TYPICAL CHARACTERISTICS
FFT
0
fi = 10 MHz at –0.5 dBFS,
CLK = 40 MSPS
–20
Input = 2 V Differential
–40
–60
–80
Amplitude – dB
–100
–120
–140
0510
Frequency – MHz
Figure 18
15 20
REFERENCE VOLTAGE ERROR
vs
FREE-AIR TEMPERATURE
0.2
0.1
0
–0.1
–0.2
Reference Voltage Error – %
–0.3
–0.4
–40 –20 0 20 40 60 80
TA – Free-Air Temperature – °C
V
= 0.5 V
ref
V
= 1 V
ref
Figure 19
NOTE: See wake-up time in definitions at the end of this data sheet.
ADC CODES
vs
WAKE-UP SETTLING TIME
125
MODE = AGND,
120
115
110
105
ADC Codes
100
95
90
–105 203550658095110
Wake-Up Settling Time – µs
Clock = 40 MHz,
Ext. REF = 1 V and 2 V,
AVDD = 3 V
See Note
Figure 20
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13
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
TYPICAL CHARACTERISTICS
POWER-UP TIME FOR INTERNAL
REFERENCE VOLTAGE FROM STANDBY
2.4
2
1.6
V
= 1 V, Reft = 10 µF,
ref
Refb = 10 µF, AVDD = 3 V
V
reft
110
AVDD = 3 V,
V
= 1 V
ref
POWER DISSIPATION
vs
SAMPLE RATE
Int. Ref
TA = 25°C
1.2
0.8
Reft, Refb Reference Voltage – V
0.4
0
0
90
180
270
360
Powerup Time – µs
V
refb
450
540
630
Figure 21
720
810
900
990
1080
1170
90
– Power Dissipation – mW
D
P
70
4 8 12 16 20 24 28 32 36 40 44
fs – Sample Rate – MSPS
Figure 22
Ext. Ref
TA = 25°C
EFFECTIVE NUMBER OF BITS
vs
FREE-AIR TEMPERATURE
4
2
0
–2
INPUT BANDWIDTH
AVDD = 3 V
DVDD = 3 V
fs = 40 MSPS
See Note
9.75
9.70
9.65
9.60
9.55
Amplitude – dB
–4
–6
–8
10 100 300 500 700 900 1100
fi – Input Frequency – MHz
Figure 23
NOTE: No series resistors and no bypass capacitors at AIN+ and AIN– inputs
14
www.ti.com
9.50
Effective Number of Bits
9.45
Diff Input = 2 V,
9.40
9.35
–40 –30 –20 –10010203040506070 80
TA – Free-Air Temperature – °C
fi = 4.4 MHz, –0.5 dBFS
Sample Rate = 40 MSPS
Figure 24
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
PRINCIPLES OF OPERATION
functional overview
Refer to functional block diagram. A single-ended, sample rate clock is required at pin CLK for device operation.
Analog inputs AIN+ and AIN– are sampled on each rising edge of CLK in a switched capacitor sample and hold
unit, the output of which feeds a programmable gain amplifier (PGA) to the ADC core, where analog-to-digital
conversion is performed against the ADC reference voltages REFT and REFB.
Internal or external ADC reference voltage configurations are selected by connecting the MODE pin
appropriately . When MODE = AGND, the user must provide external sources at pins REFB and REFT. When
MODE = AV
REFT and REFB pins using the voltage at pin VREF as its input. The user can choose to drive VREF from the
internal bandgap reference, or they can disable A1 and provide their own reference voltage at pin VREF.
On the fourth rising CLK edge following the edge that sampled AIN+ and AIN–, the conversion result is output
via data pins I/O0 to I/O9. The output buffers can be disabled by pulling pin OE
device configuration data on the data pins, which are then latched into the internal control registers by strobing
the WR pin high then low. The internal registers control the data output format (unsigned or twos complement),
the PGA gain, device powerdown, and the clamp functions.
or MODE = AVDD/2, an internal ADC references generator (A2) is enabled, which drives the
DD
high, allowing the user to place
THS1041
The THS1041 offers a clamp circuit suitable for dc restoration of ac-coupled signals. The clamp voltage level
can be set using an external reference applied to the CLAMPIN pin, or it can be set to a reference level provided
by an on-chip 10-bit DAC. The CLAMPOUT pin must be connected externally to AIN+ or AIN– in applications
requiring the clamp function.
The following sections explain further:
D How signals flow from AIN+ and AIN– to the ADC core, and how the reference voltages at REFT and REFB
set the ADC input range and hence the input range at AIN+ and AIN–
D How to set the ADC references REFT and REFB using external sources or the internal ADC reference buffer
(A2) to match the device input range to the input signal
D How to set the output of the internal bandgap reference (A1) if required
D How to use the clamp and device control registers
signal processing chain (sample and hold, PGA, ADC)
Figure 25 shows the signal flow through the sample and hold unit and the PGA to the ADC core.
REFT
AIN+
AIN–
X1
X–1
VP+
Sample
and
Hold
PGA
VQ+
ADC
Core
VP–
VQ–
REFB
Figure 25. Analog Input Signal Flow
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15
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
PRINCIPLES OF OPERATION
sample-and-hold
Differential input signal sources can be connected directly to the AIN+ and AIN– pins using either dc- or
ac-coupling.
For single-ended sources, the signal can be dc- or ac-coupled to one of AIN+ or AIN–, and a suitable reference
voltage (usually the midscale voltage, see operating configuration examples) must be applied to the other pin.
Note that connecting the signal to AIN– results in it being inverted during sampling.
The sample and hold differential output voltage VP = VP+ – VP– is given by
VP = (AIN+) – (AIN–)
A clamp is available for dc restoration of ac-coupled single-ended inputs (see clamp operation).
programmable gain amplifier
VP is amplified by the PGA and fed to the ADC as a voltage VQ = VQ+ – VQ– where
VQ = Gain × VP = Gain × [(AIN+) – (AIN–)]
analog-to-digital converter
VQ is digitized by the ADC, using the voltages at pins REFT and REFB to set the ADC zero-scale (code 0) and
full-scale (code 1023) input voltages.
VQ (ZS) = – (REFT – REFB)
VQ (FS) = (REFT – REFB)
Any inputs at AIN+ and AIN– that give VQ voltages less than VQ(ZS) or greater than VQ(FS) lie outside the
ADC’s conversion range and attempts to convert such voltages are signalled by driving pin OVR high when the
conversion result is output. VQ voltages less than VQ(ZS) digitize to give ADC output code 0, and VQ voltages
greater than VQ(FS) give ADC output code 1023.
complete system and system input range
Combining the above equations to find the input voltages [(AIN+) – (AIN–)] that correspond to the limits of the
ADC’s valid input range gives:
(1)
(2)
(3)
(4)
(REFB * REFT)
Gain
For both single-ended and differential inputs, the ADC can thus handle signals with a peak-to-peak input range
[(AIN+) – (AIN–)] of:
[(AIN+) – (AIN–)]
The next sections describe the options available to the user for setting the REFT and REFB voltages to obtain
the desired input range and performance in their THS1041 applications.
16
[(
v
pk–pk input range + 2
AIN)
)*(
AIN*
(REFT* REFB)
)]
v
(REFT * REFB)
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Gain
Gain
(5)
(6)
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
PRINCIPLES OF OPERATION
ADC reference generation
The THS1041 ADC references REFT and REFB can be driven from external (off-chip) sources or from the
internal A2 reference buffer. The voltage at the MODE pin determines the ADC references source.
Connecting MODE to AGND enables external ADC references mode. In this mode the internal buffer A2 is
powered down and the user must provide the REFT and REFB voltages by connecting external sources directly
to these pins. This mode is useful where several THS1041 devices must share common references for best
matching of their ADC input ranges, or when the application requires better accuracy and temperature stability
than the on-chip reference source can provide.
THS1041
Connecting MODE to AV
or AVDD/2 enables internal ADC references mode. In this mode the buffer A2 is
DD
powered up and drives the REFT and REFB pins. External reference sources should not be connected in this
mode. Using internal ADC references mode when possible helps to reduce the component count and hence
the system cost.
When MODE is connected to A V
, a buffered AVDD/2 voltage is also available at the CLAMPOUT pin. This
DD
voltage can be used as a dc bias level for any ac-coupling networks connecting the input signal sources to the
AIN+ and AIN– pins.
MODE PIN REFERENCE SELECTION CLAMPOUT PIN FUNCTION
AGND External Clamp
AVDD/2 Internal Clamp
AV
DD
Internal AVDD/2 for AIN± bias
external reference mode (MODE = AGND)
AIN+
AIN–
VREF
REFT
REFB
X1
X–1
Sample
and
Hold
Internal
Reference
Buffer
PGA
ADC
Core
Figure 26. ADC Reference Generation, MODE = AGND
Connecting pin MODE to AGND powers-down the internal references buffer A2 and disconnects its outputs
from the REFT and REFB pins. The user must connect REFT and REFB to external sources to provide the ADC
reference voltages required to match the THS1041 input range to their application requirements. The
common-mode reference voltage must be AV
(REFT ) REFB)
2
+
AV
DD
2
/2 for correct THS1041 operation:
DD
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(7)
17
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
PRINCIPLES OF OPERATION
internal reference mode (MODE = AV
AIN+
AIN–
VREF
AGND
DD
X1
X–1
Reference
or AVDD/2)
Sample
and
Hold
Internal
Buffer
PGA
AVDD + VREF
2
ADC
Core
AVDD – VREF
2
Figure 27. ADC Reference Generation, MODE = AVDD/2
Connecting MODE to A V
or A VDD/2 enables the internal ADC references buffer A2. The outputs of A2 are
DD
connected to the REFT and REFB pins and its inputs are connected to pins VREF and AGND. The resulting
voltages at REFT and REFB are:
REFT +
REFB +
ǒ
AVDD) VREF
2
ǒ
AVDD* VREF
2
Ǔ
Ǔ
(8)
(9)
Depending on the connection of the REFSENSE pin, the voltage on VREF may be driven by an off-chip source
or by the internal bandgap reference (A1) (see onboard reference generator configuration) to match the
THS1041 input range to their application requirements.
When MODE = AV
the CLAMPOUT pin provides a buffered, stabilized AVDD/2 output voltage that can be
DD
used as a bias reference for ac coupling networks connecting the signal sources to the AIN+ or AIN– inputs.
This removes the need for the user to provide a stabilized external bias reference.
18
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SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
THS1041
PRINCIPLES OF OPERATION
internal reference mode (MODE = AV
+FS
AIN+
–FS
+FS
AIN–
–FS
0.1 µF
0.1 µF
Figure 28. Internal Reference Mode, 1-V Reference Span
+FS
VM
–FS
or AVDD/2) (continued)
DD
AIN+
AIN–
REFT
0.1 µF10 µF
REFB
AIN+
MODE
REFSENSE
VREF
CLAMPOUT
MODE
AVDD or
AV
DD
2
AV
DD
2
V
MID
V
CLAMP
or AV
1 V (Output)
if MODE = AV
if MODE =
DD
DD
AV
DD
2
DC SOURCE = VM
VM
0.1 µF
0.1 µF
+
_
0.1 µF10 µF
AIN–
REFT
REFB
VREF
REFSENSE
0.5 V (Output)
Figure 29. Internal Reference Mode, 0.5-V Reference Span, Single-Ended Input
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19
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
PRINCIPLES OF OPERATION
onboard reference generator configuration
The internal bandgap reference A1 can provide a supply-voltage-independent and temperature-independent
voltage on pin VREF.
External connections to REFSENSE control A1’s output to the VREF pin as shown in Table 1.
Table 1. Effect of REFSENSE Connection on VREF Value
REFSENSE CONNECTION A1 OUTPUT TO VREF REFER TO:
VREF pin 0.5 V Figure 30
AGND 1 V Figure 31
External divider junction (1 + Ra/Rb)/2 V Figure 32
AV
DD
REFSENSE = AVDD powers the internal bandgap reference A1 down, saving power when A1 is not required.
If MODE is connected to A V
REFT +
AV
2
DD
)
VREF
or A VDD/2, then the voltage at VREF determines the ADC reference voltages:
DD
2
Open circuit Figure 33
(10)
REFB +
AV
2
DD
*
VREF
REFT–REFB + VREF
VBG
Figure 30. 0.5-V VREF Using the Internal Bandgap Reference A1
(11)
2
(12)
ADC
References
Buffer A2
MODE =
AV
DD
or AV
+
+
_
_
2
DD
VREF = 0.5 V
0.1 µF 1 µF
REFSENSE
AGND
20
www.ti.com
PRINCIPLES OF OPERATION
onboard reference generator configuration (continued)
ADC
References
Buffer A2
MODE =
AV
DD
or AV
DD
VBG
+
+
_
_
2
10 kΩ
10 kΩ
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
VREF = 1 V
0.1 µF 1 µF
REFSENSE
AGND
Figure 31. 1-V VREF Using the Internal Bandgap Reference A1
ADC
References
Buffer A2
MODE =
AV
DD
or AV
DD
VREF = (1 + Ra/Rb)/2
Ra
REFSENSE
Rb
AGND
0.1 µF 1 µF
VBG
+
+
_
_
2
Figure 32. External Divider Mode
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21
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
PRINCIPLES OF OPERATION
onboard reference generator configuration (continued)
ADC
References
Buffer A2
MODE =
AV
+
VBG
+
_
_
DD
2
or AV
DD
VREF = External
REFSENSE
AV
DD
AGND
Figure 33. Drive VREF Mode
operating configuration examples
Figure 34 shows a configuration using the internal ADC references for digitizing a single-ended signal with span
0 V to 2 V . T ying REFSENSE to ground gives 1 V at pin VREF . T ying MODE to AV
REFB voltages via the internal reference generator for a 2-V
ADC input range and the CLAMPOUT pin also
p-p
provides the midscale 1-V bias for the AIN– input. Using the clamp to drive AIN– rather than connecting AIN–
directly to VREF helps to prevent kickback from the AIN– pin corrupting VREF . AIN– can be connected to VREF ,
provided that VREF is well-decoupled to analog ground. Internal PGA gain setting is 1.
2 V
1 V
0 V
10 µF
0.1 µF
20 Ω
20 pF
20 Ω
20 pF
1 µF
AVDD/2
AIN+
MODE
CLAMP
AIN–
CLAMPOUT
CLAMPIN
VREF = 1 V
REFT
AV
/2 then sets the REFT and
DD
DD
22
10 µF
0.1 µF
0.1 µF
REFB
REFSENSE
Figure 34. Operating Configuration: 2-V Single-Ended Input, Internal ADC References
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SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
PRINCIPLES OF OPERATION
operating configuration examples (continued)
Figure 35 shows a configuration using the internal ADC references for digitizing a dc-coupled differential input
with 1.5-V
reference output at VREF to 0.75 V . Tying MODE to A V
reference generator for a 1.5-V
If a transformer is used to generate the differential ADC input from a single-ended signal, then the CLAMPOUT
pin provides a suitable bias voltage for the secondary windings center tap when MODE = AV
span and 1.5-V common-mode voltage. External resistors are used to set the internal bandgap
p-p
1.875 V
1.5 V
1.125 V
1.875 V
1.5 V
1.125 V
ADC input range.
p-p
20 Ω
20 Ω
20 pF
20 pF
then sets the REFT and REFB voltages via the internal
DD
.
DD
AV
DD
AIN+
AIN–
VREF = 0.75 V
MODE
5 kΩ
THS1041
0.1 µF
10 µF
0.1 µF
REFT
0.1 µF
REFB
REFSENSE
10 µF
10 kΩ
Figure 35. Operating Configuration: 1.5-V Differential Input, Internal ADC References
Figure 36 shows a configuration using the internal ADC references and an external VREF source for digitizing
a dc coupled single-ended input with span 0.5 V to 2 V . A 1.25-V external source provides the bias voltage for
the AIN– pin and also, via a buffered potential divider; the 0.75 VREF voltage required to set the input range
to 1.5 V
MODE is tied to AVDD to set internal ADC references configuration.
p-p
AV
1.25 V
0.5 V
1.25
Source
10 µF
2 V
10 kΩ
(0.75 V)
15 kΩ
20 Ω
20 Ω
AIN+
20 pF
20 pF
_
+
AIN–
VREF
MODE
REFT
REFB
REFSENSE
DD
0.1 µF
AV
0.1 µF
10 µF
0.1 µF
DD
Figure 36. Operating Configuration: 1.5-V Single-Ended Input, External VREF Source
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23
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
PRINCIPLES OF OPERATION
operating configuration examples (continued)
Figure 37 shows a configuration using external ADC references for digitizing a differential input with span 0.8 V .
T o maximize the signal swing at the ADC core, the PGA gain is set to 2.5 to give a 2-V
MODE is tied to ground to disable the internal reference buffer . The external ADC reference sources must set
REFT 1 V higher than REFB to set the ADC input span to 2 V
sources must be centered near A V
/2 for best ADC operation. REFSENSE is shown tied to A VDD to disable
DD
, and the voltages provided by the external
p-p
the internal bandgap refence (A1), though other components in the system may use the VREF output if desired.
External ADC references are best suited to applications which require the tighter reference voltage tolerance
and temperature coefficient than the internal bandgap reference (A1) can provide, or where the references are
to be shared among several THS1041 ADCs for best matching of their ADC channels.
output from the PGA.
p-p
Figure 37. Operating Configuration: 0.8-V Differential Input and External ADC References
clamp operation
1.7 V
1.5 V
1.3 V
1.7 V
1.5 V
1.3 V
2 V
10 µF
1 V
C
V
IN
IN
20 Ω
20 Ω
10 µF
10 µF
CLAMPIN
CLAMP
CLAMPOUT
R
IN
AIN+
20 pF
20 pF
0.1 µF
SW1
AIN+
AIN–
REFT
REFB
MODE
REFSENSE
+
V
(Clamp)
_
AV
DD
10-Bit
DAC
Control Register (Bit CLINT)
S/H
Figure 38. Schematic of Clamp Circuitry
The THS1041 provides a clamp function for restoring a dc reference level to the signal at AIN+ or AIN– which
has been lost through ac-coupling from the signal source to this pin.
Figure 38 and Figure 39 show an example of using the clamp to restore the black level of a composite video
input ac-coupled to AIN+. While the clamp pin is held high, the clamp amplifier forces the voltage at AIN+ to equal
the clamp reference voltage, setting the dc voltage at AIN+ for the video black level.
After power up, the clamp reference voltage is the voltage on the CLAMPIN pin. This reference can instead be
taken from the internal CLAMP DAC by suitably programming the THS1041 clamp and control registers.
Clamp acquisition and clamp droop design calculations are discussed later.
24
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SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
PRINCIPLES OF OPERATION
clamp operation (continued)
Black
Line Sync
Video at AIN
CLAMP
Figure 39. Example Waveforms for Line-Clamping to a Video Input Black Level
clamp DAC output voltage range and limits
When using the internal clamp DAC, the user must ensure that the desired dc clamp level at AIN+/– lies within
the voltage range V
V
REFB
to V
. Specifically:
REFT
VDAC + V
REFB
REFB
to V
) (V
. This is because the clamp DAC voltage is constrained to lie within this range
REFT
REFT
* V
) (0.006) 0.988 (DAC code)ń1024)
REFB
Level
THS1041
(13)
DAC codes can range from 0 to 1023. Figure 40 graphically shows the clamp DAC output voltage versus the
DAC code.
VDAC
V
REFT
V
V
REFB
+ 0.006(V
REFB
0 1023
REFT–VREFB
V
+ 0.987(V
REFB
)
REFT–VREFB
)
DAC Code
Figure 40. Clamp DAC Output Voltage Versus DAC Register Code Value
If the desired dc level at AIN+/– does not lie within the voltage range V
REFT
to V
, then either the CLAMPIN
REFB
pin can be used instead to provide a suitable reference voltage, or it may be possible to redesign the application
to move the AIN+/– input range into the CLAMP DAC voltage range.
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25
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
PRINCIPLES OF OPERATION
power management
In power-sensitive applications (such as battery-powered systems) where the THS1041 ADC is not required
to convert continuously, power can be saved between conversion intervals by placing the THS1041 into
power-down mode. This is achieved by setting bit 3 (PWDN) of the control register to 1. In power-down mode,
the device typically consumes less than 0.1 mW. Power-down mode is exited by resetting control register bit
3 to 0. On power up, typical wake-up and power-up times apply. See power supply section.
In systems where the ADC must run continuously , but where the clamp is not required, the supply current can
be reduced by approximately 1.2 mA by setting the control register bit 6 (CLDIS) to 1, which disables the clamp
circuit. Similarly, when REFSENSE is tied to AV
reduced by approximately 1.2 mA.
output format and digital I/O
While the OE pin is held low, ADC conversion results are output at pins I/O0 (LSB) to I/O9 (MSB). The ADC input
over-range indicator is output at pin OVR. OVR is also disabled when OE
The default ADC output data format is unsigned binary (output codes 0 to 1023). The output format can be
switched to 2s complement (output codes –512 to 511) by setting control register bit 5 (TWOC) to 1.
, the reference generator is disabled and supply current
DD
is held high.
writing to the internal registers through the digital I/O bus
Pulling pin OE
high disables the I/O and OVR pin output drivers, placing the driver outputs in a high impedance
state. This allows control register data to be loaded into the THS1041 by presenting it on the I/O0 to I/O9 pins
and pulsing the WR pin high then low to latch the data into the chosen control or DAC register.
Figure 41 shows an example register write cycle where the clamp DAC code is set to 10F (hex) by writing to
clamp registers 1 and 2 (see the register map in Table 2). Pins I/O0 to I/O7 are driven to the clamp DAC code
lower byte (0F hex), and pins I/08 and I/O9 are both driven to 0 to select clamp register 1 as the data destination.
The clamp low-byte data is then loaded into this register by pulsing WR high. The top 2 bits of the DAC word
are then loaded by driving 01(hex) on pins I/O0 to I/O7 and by driving pin I/O8 to 1 and pin I/O9 to 0 to select
clamp register 2 as the data destination. WR is pulsed a second time to latch this second control word into clamp
register 2. Interface timing parameters are given in Figures 1 and 2.
OE
WR
I/O (0–9)
Output Input 00F Input 101 Output
Load 0F Into
REGISTER 0
Load 01 Into
REGISTER 1
Figure 41. Example Register Write Cycle to Clamp DAC Register
26
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ADDRESS
DEF
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
PRINCIPLES OF OPERATION
digital control registers
The THS1041 contains two clamp registers and a control register for user programming of THS1041 operation.
Binary data can be written into these registers by using pins I/O0 to I/O9 and the WR and OE
previous section). In input mode, the two I/O bus MSBs are address bits, 00 addressing clamp register 1, 01
clamp register 2, and 10 the control register.
Table 2. Register Map
pins (see the
THS1041
ADDRESS
I/O[9:8]
00 Clamp register 1 00 RW DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]
01 Clamp register 2 00 RW DAC[9] DAC[8]
10 Control register 01 RW CLDIS TWOC CLINT PDWN PGA[2] PGA[1] PGA[0]
†
11
†
Do not write to register 11
DESCRIPTION
Reserved
†
DEF
(HEX)
RW
B7 B6 B5 B4 B3 B2 B1 B0
BIT
Table 3. Register Contents
REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION
PGA gain:
000 = 0.5
001 = 1.0 (default value)
010 = 1.5
011 = 2.0
100 = 2.5
101 = 3.0
110 = 3.5
111 = 4.0
Power down
0 = THS1041 powered up
1 = THS1041 powered down
Clamp voltage internal/external
0 = external analog clamp voltage from CLAMPIN pin
1 = from onboard DAC (see clamp register)
Output format
0 = unsigned binary
1 = twos complement
CLAMPOUT pin disable (for power saving)
0 = Enable
1 = Disable
Clamp DAC voltage
(DAC[0] = LSB.)
DAC[9:0] = 00h: Clamp voltage = REFB
DAC[9:0] = 3Fh: Clamp voltage = REFT
Clamp DAC voltage
(DAC[9] = MSB)
Control register
I/O[9:8] = 10
Clamp register 1
I/O[9:8] = 00
Clamp register 2
I/O[9:8] = 01
2:0 PGA[2:0] 001
3 PDWN 0
4 CLINT 0
5 TWOC 0
6 CLDIS 0
7 Unused
7:0 DAC[7:0] 0
7:2 Unused
1:0 DAC[9:8] 0
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27
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
APPLICATION INFORMATION
driving the THS1041 analog inputs
driving the clock input
Obtaining good performance from the THS1041 requires care when driving the clock input.
Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should
ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as
possible in which to operate.
The CLK pin should also be driven from a low jitter source for best dynamic performance. T o maintain low jitter
at the CLK input, any clock buffers external to the THS1041 should have fast rising edges. Use a fast logic family
such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other
logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter.
As the CLK input threshold is nominally around A V
/2, any clock buffers need to have an appropriate supply
DD
voltage to drive above and below this level.
driving the sample and hold inputs
driving the AIN+ and AIN– pins
Figure 42 shows an equivalent circuit for the THS1041 AIN+ and AIN– pins. The load presented to the system
at the AIN pins comprises the switched input sampling capacitor, C
Sample
, and various stray capacitances, C
and C2.
AV
DD
AIN
AGND
C1
8 pF
CLK
C2
1.2 pF
CLK
+
_
VCM = AIN+/AIN– Common Mode Voltage
1.2 pF
C
Sample
Figure 42. Equivalent Circuit for Analog Input Pins AIN+ and AIN–
The input current pulses required to charge C
Sample
and C2 can be time averaged and the switched capacitor
circuit modelled as an equivalent resistor:
1
R
+
IN2
where CS is the sum of C
1
CS f
Sample
resistance for high impedance sources.
28
(14)
CLK
and C2. This model can be used to approximate the input loading versus source
www.ti.com
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
THS1041
APPLICATION INFORMATION
AV
DD
AIN
AGND
C1
8 pF
I
IN
R2 = 1/CS f
CLK
+
VCM = AIN+/AIN– Common Mode Voltage
_
Figure 43. Equivalent Circuit for the AIN Switched Capacitor Input
AIN input damping
The charging current pulses into AIN+ and AIN– can make the signal sources jump or ring, especially if the
sources are slightly inductive at high frequencies. Inserting a small series resistor of 20 Ω or less and a small
capacitor to ground of 20 pF or less in the input path can damp source ringing (see Figure 44). The resistor and
capacitor values can be made larger than 20 Ω and 20 pF if reduced input bandwidth and a slight gain error (due
to potential division between the external resistors and the AIN equivalent resistors) are acceptable.
Note that the capacitors should be soldered to a clean analog ground with a common ground point to prevent
any voltage drops in the ground plane appearing as a differential voltage at the ADC inputs.
V
R< 20 Ω
S
AIN
C < 20 pF
Figure 44. Damping Source Ringing Using a Small Resistor and Capacitor
driving the VREF pin
Figure 45 shows the equivalent load on the VREF pin when driving the ADC internal references buffer via this
pin (MODE = AVDD/2 or AVDD and REFSENSE = AVDD).
AV
DD
R
VREF
AGND
IN
10 kΩ
MODE = AV
DD
REFSENSE = AVDD,
MODE = AVDD/2 or AV
+
(AVDD + VREF) /4
_
DD
Figure 45. Equivalent Circuit of VREF
The nominal input current I
3V
+
REF
4 R
I
REF
is given by:
REF
* AV
IN
DD
(15)
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29
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
APPLICATION INFORMATION
driving the VREF pin (continued)
Note that the maximum current may be up to 30% higher. The user should ensure that VREF is driven from a
low noise, low drift source, well decoupled to analog ground and capable of driving the maximum I
driving REFT and REFB (external ADC references, MODE = AGND)
AV
DD
REF
.
REFT
AGND
AV
DD
REFB
AGND
Figure 46. Equivalent Circuit of REFT and REFB Inputs
designing the dc clamp
Figure 38 shows the basic operation of the clamp circuit with the analog input AIN+ coupled via an RC circuit.
AIN– must be connected to a dc source whose voltage level keeps the THS1041 differential input within the ADC
input range. The clamp voltage output level may be established by an analog voltage on the CLAMPIN pin or
by programming the on-chip clamp DAC.
(Note that it is possible to reverse the AIN+ and AIN– connections if signal inversion is also required. The
following section assumes that the signal is coupled to AIN+ and that AIN– is connected to a suitable dc bias
level).
initial clamp acquisition time
Acquisition time is the time required to reach the target clamp voltage at AIN+ when the clamp switch SW1 is
closed for the first time. The acquisition time is given by
2 kΩ
To ADC Core
To ADC Core
V
T
where VC is the difference between the dc level of the input VIN and the target clamp output voltage, V
V
is the difference between the ideal VC and the actual VC obtained during the acquisition time. The maximum
E
tolerable error depends on the application requirements.
For example, consider clamping an incoming video signal that has a black level near 0.3 V to a black level of
1.3 V at the THS1041 AIN+ input. The voltage V
1.3 – 0.3 = 1 V. If a 10 mV or less clamp voltage error V
resistance R
reach this error is:
T
ACQ
30
+ CIN RlN ln
ACQ
is 20 Ω and the coupling capacitor CIN is 1 µF, then the total clamp pulse duration required to
IN
= 1 µF × 20 Ω × ln(1/0.01) = 92 µs (approximate)
C
ǒ
Ǔ
V
E
required across the input coupling capacitor is thus
C
www.ti.com
gives acceptable system operation, the source
E
(16)
Clamp
.
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
APPLICATION INFORMATION
initial clamp acquisition time (continued)
Initial acquisition can be performed in two ways:
D Pulsing the CLAMP pin as in normal operation. Provided that clamp droop (see below) is negligible, initial
acquisition is complete when the total clamped (CLAMP = high) time equals T
D Pulling the CLAMP pin high for the required acquisition time before starting normal operation. This method
is faster, though possibly less convenient for the user to implement.
clamp droop
The charging currents drawn by the sample-and-hold switched capacitor input can charge or discharge C
causing the dc voltage at AIN+ to drift towards the dc bias voltage at AIN– during the time between clamp pulses.
This effect is called clamp droop.
ACQ
.
THS1041
IN
,
Voltage droop is a function of the AIN+ and AIN– input currents to the THS1041, I
intervals, t
Worst case droop between clamping intervals occurs for maximum input bias current. Maximum input current
is I
INFS
For example, at 40 MSPS I
RIN2—see driving the sample and hold reference inputs to calculate R
by ±30% because of processing variations and voltage dependencies. Designs should allow for this variation.
If the time t
clamp pulses is
If this droop is greater than can be tolerated in the application, then increase C
reduce the voltage change between clamp pulses.
If a high leakage capacitor is used for coupling the input source to the AIN pin then the droop may be significantly
worse than calculated above. Avoid using electrolytic and tantalum coupling capacitors as these have higher
leakage currents than nonpolarized capacitor types. Electrolytic and tantalum capacitors also tend to have
higher parasitic inductance, which can cause problems at high input frequencies.
:
D
I
V
DROOP
, which occurs when the input level is at its maximum or minimum.
between clamping intervals is 63.5 µs and CIN is 1 µF , then the maximum clamp level droop between
d
V
DROOP
(max) + 20 mAń1 mF 63.5 ms + 1.25 mV (approximate, ignoring30% tolerance)
IN
[
ǒ
Ǔ t
C
IN
INFS
+ 0.62 LSB at PGA gain + 1, 2 V ADC references
(approximate)
d
is approximately 20 µA for a 2-V input range at AIN (assuming 2 V appear across
). Note that I
IN2
, and the time between clamp
IN
may vary from this
INFS
to slow the droop and hence
IN
(17)
(18)
steady-state clamp voltage error
During the clamp pulse (CLAMP = high), the dc voltage on AIN is refreshed from the clamp voltage. Provided
that droop is not excessive, clamping fully reverses the effect of droop. However , using very short clamp pulses
with long intervals between pulses (t
voltage at AIN and V
Figure 47 shows the approximate voltage waveform at AIN resulting from a a large clamp droop during t
clamp voltage reacquisition during the clamp pulse time, t
(Clamp)
.
) can result in a steady-state voltage difference, V
d
.
c
www.ti.com
, between the dc
COS
and
d
31
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
APPLICATION INFORMATION
steady-state clamp voltage error (continued)
V
(Clamp)
V
AIN
V
COS
V
DROOP
= ∆V
AIN
VM
t
c
t
d
Figure 47. Approximate Waveforms at AIN During Droop and Clamping
The voltage change at AIN during acquisition has been approximated as a linear charging ramp by assuming
that almost all of V
approximation when V
appears across RIN, giving a charging current V
COS
is large enough to be of concern). The voltage change at AIN during clamp
COS
COS/RIN
(this is a reasonable
acquisition is then:
DV
AIN
V
+
RIN C
COS
t
d
IN
The peak-to-peak voltage variation at AIN must equal the clamp droop voltage at steady state. Equating the
droop voltage to the clamp acquisition voltage change gives:
V
COS
RIN IIN t
+
t
c
d
Thus for low offset voltage, keep RIN low, design for low droop and ensure that the ratio td/tc is not unreasonably
large.
reference decoupling
VREF pin
When the on-chip reference generator is enabled, the VREF pin should be decoupled to the circuit board’s
analog ground plane close to the THS1041 AGND pin via a 1-µF capacitor and a 0.1-µF ceramic capacitor.
(19)
(20)
REFT and REFB pins
In any mode of operation, the REFT and REFB pins should be decoupled as shown in Figure 48. Use short
board traces between the THS1041 and the capacitors to minimize parasitic inductance.
0.1 µF
REFT
THS1041
REFB
0.1 µF
10 µF
0.1 µF
Figure 48. Recommended Decoupling for the ADC Reference Pins REFT and REFB
32
www.ti.com
APPLICATION INFORMATION
CLAMPOUT decoupling (when used as dc bias source)
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
When using CLAMPOUT as a dc biasing reference (e.g., MODE = AV
decoupled to the circuit board’s analog ground plane close to the THS1041 AGND pin via a 1-µF capacitor and
a 0.1-µF ceramic capacitor.
supply decoupling
The analog (AV
decoupled for best performance. Each supply needs at least a 10-µF electrolytic or tantalum capacitor (as a
charge reservoir) and a 100-nF ceramic type capacitor placed as close as possible to the respective pins (to
suppress spikes and supply noise).
digital output loading and circuit board layout
The THS1041 outputs are capable of driving rail-to-rail with up to 10 pF of load per pin at 40-MHz clock frequency
and 3-V digital supply . Minimizing the load on the outputs improves THS1041 signal-to-noise performance by
reducing the switching noise coupling from the THS1041 output buffers to the internal analog circuits. The
output load capacitance can be minimized by buffering the THS1041 digital outputs with a low input capacitance
buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks
between the THS1041 and this buffer. Inserting small resistors in the range 100 Ω to 300 Ω between the
THS1041 I/O outputs and their loads can help minimize the output-related noise in noise-critical applications.
Noise levels at the output buffers, which may affect the analog circuits within THS1041, increase with the digital
supply voltage. Where possible, consider using the lowest DV
Use good layout practices when designing the application PCB to ensure that any off-chip return currents from
the THS1041 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any
sensitive analog circuits. The THS1041 should be soldered directly to the PCB for best performance. Socketing
the device degrades performance by adding parasitic socket inductance and capacitance to all pins.
, AGND) and digital (DVDD, DGND) power supplies to the THS1041 should be separately
DD
that the application can tolerate.
DD
), the CLAMPOUT pin should be
DD
user tips for obtaining best performance from the THS1041
D Choose differential input mode for best distortion performance.
D Choose a 2-V ADC input span for best noise performance.
D Choose a 1-V ADC input span for best distortion performance.
D Drive the clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short
PCB traces.
D Use a small RC filter (typically 20 Ω and 20 pF) between the signal source(s) the AIN+ (and AIN–) input(s)
when the systems bandwidth requirements allow this.
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33
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
APPLICATION INFORMATION
definitions
D Integral nonlinearity (INL)—Integral nonlinearity refers to the deviation of each individual code from a line
drawn from zero to full scale. The point used as zero occurs 1/2 LSB before the first code transition. The
full-scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from
the center of each particular code to the true straight line between these two endpoints.
D Differential nonlinearity (DNL)—An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL
is the deviation from this ideal value. Therefore this measure indicates how uniform the transfer function
step sizes are. The ideal step size is defined here as the step size for the device under test (i.e., (last
transition level – first transition level) ÷ (2
and offset error. A minimum DNL better than –1 LSB ensures no missing codes.
D Zero-error—Zero-error is defined as the difference in analog input voltage—between the ideal voltage and
the actual voltage—that switches the ADC output from code 0 to code 1. The ideal voltage level is
determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The voltage
corresponding to 1 LSB is found from the difference of top and bottom references divided by the number
of ADC output levels (1024).
n
– 2)). Using this definition for DNL separates the effects of gain
D Full-scale error—Full-scale error is defined as the difference in analog input voltage—between the ideal
voltage and the actual voltage—that will switch the ADC output from code 1022 to code 1023. The ideal
voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference level.
The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (1024).
D Wake-up time—W ake-up time is from the power-down state to accurate ADC samples being taken and is
specified for MODE = AGND with external reference sources applied to the device at the time of release
of power-down, and an applied 40-MHz clock. Circuits that need to power up are the bandgap, bias
generator, SHPGA, and ADC.
D Power-up time—Power-up time is from the power-down state to accurate ADC samples being taken and
is specified for MODE = AV
include VREF reference generation (A1), bias generator, ADC, the SHPGA, and the on-chip ADC reference
generator (A2).
/2 or AVDD and an applied 40-MHz clock. Circuits that need to power up
DD
D Aperture delay—The delay between the 50% point of the rising edge of the clock and the instant at which
the analog input is sampled.
D Aperture uncertainty (Jitter)—The sample-to-sample variation in aperture delay.
34
www.ti.com
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
THS1041
MECHANICAL DATA
DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE
16 PINS SHOWN
0.050 (1,27)
16
1
0.020 (0,51)
0.014 (0,35)
9
0.299 (7,59)
0.293 (7,45)
8
A
0.010 (0,25)
0.419 (10,65)
0.400 (10,15)
M
0.010 (0,25) NOM
0°–ā8°
Gage Plane
0.010 (0,25)
0.050 (1,27)
0.016 (0,40)
0.104 (2,65) MAX
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
0.012 (0,30)
0.004 (0,10)
DIM
A MAX
A MIN
PINS **
16
0.410
(10,41)
0.400
(10,16)
Seating Plane
0.004 (0,10)
20
0.510
(12,95)
0.500
(12,70)
0.610
(15,49)
0.600
(15,24)
24
28
0.710
(18,03)
0.700
(17,78)
4040000/C 07/96
www.ti.com
35
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
MECHANICAL DATA
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE
14 PINS SHOWN
0,65
1,20 MAX
14
0,30
0,19
8
4,50
4,30
PINS **
7
Seating Plane
0,15
0,05
8
1
A
DIM
14
0,10
6,60
6,20
M
0,10
0,15 NOM
2016
0°–ā8°
Gage Plane
24
0,25
0,75
0,50
28
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
36
3,10
2,90
5,10
4,90
www.ti.com
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
4040064/F 01/97
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