TEXAS INSTRUMENTS THS1041 Technical data
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THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUARY 2002
10-Bit, 40-MSPS ANALOG-TO-DIGITAL CONVERTER
WITH PGA AND CLAMP
FEATURES
Analog Supply 3 V
D
D Digital Supply 3 V
D Configurable Input Functions:
– Single-Ended
– Single-Ended With Analog Clamp
– Single-Ended With Programmable Digital
Clamp
– Differential
D Built-In Programmable Gain Amplifier (PGA)
D Differential Nonlinearity: ±0.45 LSB
D Signal-to-Noise: 60 dB Typ at 4.8 MHz
D Spurious Free Dynamic Range: 72 dB
D Adjustable Internal Voltage Reference
D Unsigned Binary/2s Complement Output
D Out-of-Range Indicator
D Power-Down Mode
APPLICATIONS
Video/CCD Imaging
D
D Communications
D Set-Top-Box
D Medical
DESCRIPTION
The THS1041 is a CMOS, low power, 10-bit, 40 MSPS
analog-to-digital converter (ADC) that operates from a
single 3-V supply . The THS1041 has been designed to
give circuit developers flexibility . The analog input to the
THS1041 can be either single-ended or differential.
This device has a built-in clamp amplifier whose clamp
input level can be driven from an external dc source or
from an internal high-precision 10-bit digital clamp level
programmable via an internal CLAMP register. A 3-bit
PGA is included to maintain SNR for small signals. The
THS1041 provides a wide selection of voltage
references to match the user’s design requirements.
For more design flexibility , the internal reference can be
bypassed to use an external reference to suit the dc
accuracy and temperature drift requirements of the
application. The out-of-range output indicates any
out-of-range condition in THS1041’s input signal. The
format of the digital output can be coded in either
unsigned binary or 2s complement.
The speed, resolution, and single-supply operation of
the THS1041 are suited to applications in set-top-box
(STB), video, multimedia, imaging, high-speed
acquisition, and communications. The built-in clamp
function allows dc restoration of a video signal and is
suitable for video applications. The speed and
resolution ideally suit charge-couple device (CCD) input
systems such as color scanners, digital copiers, digital
cameras, and camcorders. A wide input voltage range
allows the THS1041 to be applied in both imaging and
communications systems.
The THS1041C is characterized for operation from 0°C
to 70°C, while the THS1041I is characterized for
operation from –40°C to 85°C.
28-PIN TSSOP/SOIC PACKAGE
AGND
DV
DGND
DD
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
OVR
(TOP VIEW)
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
AV
DD
AIN+
VREF
AIN–
REFB
MODE
REFT
CLAMPOUT
CLAMPIN
CLAMP
REFSENSE
WR
OE
CLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright 2002, Texas Instruments Incorporated
1
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
T
A
0°C to 70°C THS1041CPW THS1041CDW
–40°C to 85°C THS1041IPW THS1041IDW
functional block diagram
CLAMPIN
Clamp
Logic
AVAILABLE OPTIONS
28-TSSOP (PW) 28-SOIC (DW)
Clamp
Logic
PACKAGED DEVICES
10 Bit
DAC
Clamp
Logic
Digital
Interface
WR
CLAMPOUT
CLAMP
AIN+
AIN–
MODE
AV
DD
AGND
Mode
Detection
VREF
NOTE: A1 – Internal bandgap reference
A2 – Internal ADC reference generator
A2
SHPGA
10 Bit
ADC
ADC
Reference
Resistor
REFB REFT
VREF
3-State
Output
Buffers
Timing
Circuit
A1
0.5 V
REFSENSE
+
–
I/O (0–9)
OVR
OE
DV
DD
DGND
CLK
2
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SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
THS1041
Terminal Functions
TERMINAL
NAME NO.
AGND 1 I Analog ground
AIN+ 27 I Positive analog input
AIN– 25 I Negative analog input
AV
DD
CLAMP 19 I High to enable clamp mode, low to disable clamp mode
CLAMPIN 20 I Connect to an external analog clamp reference input.
CLAMPOUT 21 O
CLK 15 I Clock input
DGND 14 I Digital ground
DV
DD
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
MODE 23 I Operating mode select (AGND, AVDD/2, AVDD)
OE 16 I High to high-impedance state the data bus, low to enable the data bus
OVR 13 O Out-of-range indicator
REFB 24 I/O Bottom ADC reference voltage
REFSENSE 18 I VREF mode control
REFT 22 I/O Top ADC reference voltage
VREF 26 I/O Internal or external reference
WR 17 I Write strobe
I/O
28 I Analog supply
The CLAMPOUT pin can provide a dc restoration or a bias source function (see AC reference generation
section). If neither function is required then the clamp can be disabled to save power (see power management
section).
2 I Digital supply
3
4
5
6
7
8
9
10
11
12
Digital I/O bit 0 (LSB)
Digital I/O bit 1
Digital I/O bit 2
Digital I/O bit 3
Digital I/O bit 4
I/O
Digital I/O bit 5
Digital I/O bit 6
Digital I/O bit 7
Digital I/O bit 8
Digital I/O bit 9 (MSB)
DESCRIPTION
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3
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range: AV
to AGND, DVDD to DGND –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
†
AGND to DGND –0.3 V to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AV
to DV
DD
DD
MODE input voltage range, MODE to AGND –0.3 V to AV
Reference voltage input range, REFT, REFB, to AGND –0.3 V to AV
Analog input voltage range, AIN to AGND –0.3 V to AV
Reference input voltage range, VREF to AGND –0.3 V to AV
Reference output voltage range, VREF to AGND –0.3 V to AV
Clock input voltage range, CLK to AGND –0.3 V to AV
Digital input voltage range, digital input to DGND –0.3 V to DV
Digital output voltage range, digital output to DGND –0.3 V to DV
Operating junction temperature range, T
Storage temperature range, T
stg
J
–4 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
0°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, AVDD, DV
High-level digital input, V
Low-level digital input, V
Minimum digital output load resistance, R
Maximum digital output load capacitance, C
Clock frequency, f
Clock duty cycle 45% 50% 55%
p
Operating free-air temperature
clk
DD
IH
IL
L
L
p
THS1041C 0 25 70
THS1041I –40 25 85
3 3 3.6 V
DV
DD
DGND DGND V
100 kΩ
5 40 MHz
DV
DD
10 pF
°
°C
V
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V,
= 40 MSPS/50% duty cycle, MODE = AVDD (internal reference), differential input range = 1 Vpp
f
s
and 2 Vpp, PGA = 1X, T
dc accuracy
Resolution 10 Bits
INL Integral nonlinearity (see definitions) ±0.75 ±1.5 LSB
DNL Differential nonlinearity (see definitions) ±0.3 ±1 LSB
Zero error (see definitions) 0.7 1.5 %FSR
Full-scale error (see definitions) 2.2 3 %FSR
Missing code No missing code assured
4
A
= T
to T
min
PARAMETER MIN TYP MAX UNIT
(unless otherwise noted)
max
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SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
THS1041
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V,
= 40 MSPS/50% duty cycle, MODE = AVDD (internal reference), differential input range = 1 Vpp
f
s
and 2 Vpp, PGA = 1X, T
power supply
AV
DD
DV
DD
I
CC
P
D
P
D(STBY)
NOTES: 1. Actual values will vary slightly depending on application clamp load, VREF load, etc.
analog inputs
Differential analog input voltage, V
Reference input voltage, V
Clamp input voltage, V
REFT, REFB external ADC reference voltages inputs (MODE = AGND)
Supply voltage
Operating supply current All circuits active, See Note 1 34 42 mA
Power dissipation All circuits active 103 125 mW
Standby power 75 µW
Power up time for all references from standby, t
Wake-up time, t
2. Wake-up time is from the power-down state to accurate ADC samples being taken and is specified for MODE = AGND with external
reference sources applied to the device at the time of release of power-down and an applied 40-MHz clock. Circuits that need to
power up are the bandgap, bias generator, ADC, and SHPGA.
I(VREF)
I(CLAMPIN)
Reference input voltage, REFT–REFB 0.5
Reference common mode voltage, (REFT + REFB)/2 AVDD = 3 1.5 V
Input resistance between REFT and REFB 1.9 kΩ
= T
A
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(WU)
I(AIN)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
to T
min
= AIN+ – AIN– –1 1 V
(unless otherwise noted) (continued)
max
(PU)
See Note 2 45 µs
3 3 3.6
3 3 3.6
770 µs
MIN NOM MAX UNIT
0.5 1 V
0.1 AVDD–0.1 V
1
V
V
REFT, REFB internal ADC reference voltages outputs (MODE = AVDD or AVDD/2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference voltage top, REFT
Refence voltage bottom, REFB
VREF = 0.5 V
VREF = 1 V
VREF = 0.5 V
VREF = 1 V
AVDD = 3 V
AVDD = 3 V
1.75
1.25
VREF (on-chip voltage reference generator)
PARAMETER MIN TYP MAX UNIT
Internal 0.5-V reference voltage (REFSENSE = VREF) 0.45 0.5 0.55 V
Internal 1-V reference voltage (REFSENSE = AGND) 0.95 1 1.05 V
External reference voltage (REFSENSE = AVDD) 0.5 1 V
Reference input resistance (REFSENSE = AVDD, MODE = AVDD/2 or AVDD) 14 kΩ
2
1
V
V
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5
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V,
= 40 MSPS/50% duty cycle, MODE = AVDD (internal reference), differential input range = 1 Vpp
f
s
and 2 Vpp, PGA = 1X, T
dynamic performance (ADC and PGA)
ENOB Effective number of bits
SFDR Spurious free dynamic range
THD T otal harmonic distortion
SNR Signal-to-noise ratio
SINAD Signal-to-noise and distortion
BW Full power bandwidth (–3 dB) 900 MHz
PGA
Gain range (linear scale) 0.5 4 V/V
Gain step size (linear scale) 0.5 V/V
Gain error (deviation from ideal, all gain settings) –3% 3%
Number of control bits 3 Bits
= T
A
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
to T
min
PARAMETER MIN TYP MAX UNIT
(unless otherwise noted) (continued)
max
f = 4.8 MHz, –0.5 dBFS 8.8 9.6
f = 20 MHz, –0.5 dBFS
f = 4.8 MHz, –0.5 dBFS 60.5 72
f = 20 MHz, –0.5 dBFS
f = 4.8 MHz, –0.5 dBFS –72.5 –61.3
f = 20 MHz, –0.5 dBFS
f = 4.8 MHz, –0.5 dBFS 55.7 60
f = 20 MHz, –0.5 dBFS
f = 4.8 MHz, –0.5 dBFS 55.6 59.7
f = 20 MHz, –0.5 dBFS
9.5
70
–71.6
57
59.6
Bits
dB
dB
dB
dB
clamp amplifier and clamp DAC
PARAMETER MIN TYP MAX UNIT
Resolution 10 Bits
DAC output range REFB REFT V
DAC differential nonlinearity –1 1 LSB
DAC integral nonlinearity ±1 LSB
Clamping analog output voltage range 0.1 AVDD–0.1 V
Clamping analog output voltage error –40 40 mV
NOTE: The CLAMPOUT pin must see a load capacitance of at least 10 nF to ensure stability of the on-chip clamp buffer. When using the clamp
for dc restoration, the signal coupling capacitor should be at least 10 nF. When using the clamp buffer as a dc biasing reference,
CLAMPOUT should be decoupled to analog ground through at least a 10-nF capacitor.
6
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SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
THS1041
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V,
= 40 MSPS/50% duty cycle, MODE = AVDD (internal reference), differential input range = 1 Vpp
f
s
and 2 Vpp, PGA = 1X, T
digital specifications
Digital Inputs
V
IH
V
IL
I
IH
I
IL
C
i
Digital Outputs
V
OH
V
OL
Clock Input
t
c
t
w(CKH)
t
w(CKL)
t
d(o)
t
d(AP)
High-level input voltage
Low-level input voltage
High-level input current 1 µA
Low-level input current
Input capacitance 5 pF
High-level output voltage I
Low-level output voltage I
High impedance output current ±1 µA
Rise/fall time C
Clock cycle 25 200 ns
Pulse duration, clock high 11.25 110 ns
Pulse duration, clock low 11.25 110 ns
Clock duty cycle 45% 50% 55%
Clock to data valid, delay time 9.5 16 ns
Pipeline latency 4 Cycles
Aperture delay time 0.1 ns
Aperture uncertainty (jitter) 1 ps
A
= T
to T
min
PARAMETER MIN NOM MAX UNIT
(unless otherwise noted) (continued)
max
Clock input 0.8 × AV
All other inputs
Clock input 0.2 × AV
All other inputs
= 50 µA DVDD–0.4 V
load
= 50 µA 0.4 V
load
= 15 pF 3.5 ns
load
0.8 × DV
DD
DD
0.2 × DV
DD
DD
|–1|
V
V
µA
timing
t
d(DZ)
t
d(DEN)
t
d(OEW)
t
d(WOE)
t
w(WP)
t
su
t
h
PARAMETER MIN TYP MAX UNIT
Output disable to Hi-Z output, delay time 0 10 ns
Output enable to output valid, delay time 0 10 ns
Output disable to write enable, delay time 12 ns
Write disable to output enable, delay time 12 ns
Write pulse duration 15 ns
Input data setup time 5 ns
Input data hold time 5 ns
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7
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
PARAMETER MEASUREMENT INFORMATION
OE
See Note A
t
d(OEW)
t
w(WP)
WE
t
d(DZ)
I/O
Hi-Z Hi-Z
NOTE A: All timing measurements are based on 50% of edge transition.
Figure 1. Write Timing Diagram
Analog
Input
t
w(CKH)
Sample 1
t
c
Sample 2
t
Sample 3
Sample 4
w(CKL)
t
su
Input OutputOutput
Sample 5
t
d(WOE)
t
h
t
d(DEN)
Sample 6
Sample 7
Input Clock
Digital
Output
OE
See
Note A
t
d(DEN)
Pipeline Latency
NOTE A: All timing measurements are based on 50% of edge transition.
Figure 2. Digital Output Timing Diagram
t
d(o)
(I/O Pad Delay or
Propagation Delay)
Sample 1
t
d(DZ)
Sample 2
8
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SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
THS1041
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
vs
1.0
AVDD = 3 V
DVDD = 3 V
0.5
fs = 40 MSPS
V
= 1 V
ref
0.0
–0.5
–1.0
0 128 256 384 512 640 768 896 1024
DNL – Differential Nonlinearity – LSB
INTEGRAL NONLINEARITY
1.0
INPUT CODE
Input Code
Figure 3
vs
INPUT CODE
INL – Integral Nonlinearity – LSB
0.5
0.0
–0.5
–1.0
AVDD = 3 V
DVDD = 3 V
fs = 40 MSPS
V
= 1 V
ref
0 128 256 384 512 640 768 896 1024
Input Code
Figure 4
INTEGRAL NONLINEARITY
vs
1.0
0.5
0.0
–0.5
AVDD = 3 V
DVDD = 3 V
fs = 40 MSPS
V
= 0.5 V
ref
INPUT CODE
INL – Integral Nonlinearity – LSB
–1.0
0 128 256 384 512 640 768 896 1024
Input Code
Figure 5
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9
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
–80
Differential Input = 1 V
–75
–70
–6 dB
–65
–60
–55
–50
THD – Total Harmonic Distortion – dB
–45
–40
0 102030 405060708090100
–20 dB
See Note
fi – Input Frequency – MHz
–0.5 dB
Figure 6
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
61
59
57
Diff Input = 2 V
SE Input = 2 V
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
–80
–75
–70
–6 dB
See Note
0 102030405060708090100
THD – Total Harmonic Distortion – dB
–65
–60
–55
–50
–45
–40
–0.5 dB
–20 dB
fi – Input Frequency – MHz
Differential Input = 2 V
Figure 7
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
85
80
75
70
Diff Input = 2 V
Diff Input = 1 V
55
SE Input = 1 V
Diff Input = 1 V
53
51
SNR – Signal-to-Noise Ratio – dB
49
See Note
47
0 1020304050 60708090100
fi – Input Frequency – MHz
Figure 8
NOTE: AVDD = DVDD = 3 V, CLK = 40 MSPS, PGA = 1, 20-pF capacitors AIN+ to AGND and AIN– to AGND,
10
Input series resistor = 25 Ω,
2-V Input: Ext Ref, REFT = 2 V, REFB = 1 V
1-V Input: Ext Ref, REFT = 1.75 V, REFB = 1.25 V
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65
60
55
50
45
SE Input = 2 V
40
SFDR – Spurious Free Dynamic Range – dB
See Note
35
0102030405060708090100
fi – Input Frequency – MHz
SE Input = 1 V
Figure 9
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
THS1041
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE PLUS DISTORTION
vs
INPUT FREQUENCY
SINAD – Signal-to-Noise Plus Distortion – dB
65
Diff Input = 2 V
60
Diff Input = 1 V
55
50
45
SE Input = 1 V
40
See Note
35
0102030405060708090
fi – Input Frequency – MHz
SE Input = 2 V
100
–85
–80
–75
–70
–65
–60
–55
–50
–45
THD – Total Harmonic Distortion – dB
–40
–35
Figure 10
NOTE: AVDD = DVDD = 3 V, CLK = 40 MSPS, PGA = 1, 20-pF capacitors AIN+ to AGND and AIN– to AGND,
Input series resistor = 25 Ω,
2-V Input: Ext Ref, REFT = 2 V, REFB = 1 V
1-V Input: Ext Ref, REFT = 1.75 V, REFB = 1.25 V
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
Diff Input = 2 V
See Note
Diff Input = 1 V
SE Input = 1 V
SE Input = 2 V
0102030405060708090100
fi – Input Frequency – MHz
Figure 11
TOTAL HARMONIC DISTORTION
vs
SAMPLE RATE
–75
–70
–65
–60
–55
–50
THD – Total Harmonic Distortion – dB
–45
–40
0 5 10 20 25 30 35 40 45 50
15
Sample Rate – MSPS
Diff Input = 2 V
fi = 20 MHz, –0.5 dB
Figure 12
SIGNAL-TO-NOISE RATIO
vs
SAMPLE RATE
75
70
65
60
55
50
SNR – Signal-to-Noise Ratio – dB
45
40
0 5 10 20 25 30 35 40 45 50
15
Sample Rate – MSPS
Diff Input = 2 V
fi = 20 MHz, –0.5 dB
Figure 13
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11
THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUAR Y 2002
TYPICAL CHARACTERISTICS
Spurious Free Dynamic Range – dB
75
73
71
69
67
65
63
61
59
57
3 3.1
75
73
71
SPURIOUS FREE DYNAMIC RANGE
vs
SUPPLY VOLTAGE
Diff Input = 2 V,
fi = 10 MHz, –0.5 dBFS
Sample Rate = 40 MSPS
VDD – Supply Voltage – V
Figure 14
SIGNAL-TO-NOISE RATIO
vs
SUPPLY VOLTAGE
Diff Input = 2 V,
fi = 10 MHz, –0.5 dBFS
Sample Rate = 40 MSPS
TOTAL HARMONIC DISTORTION
vs
SUPPLY VOLTAGE
–75
–73
–71
–69
–67
–65
–63
–61
THD – Total Harmonic Distortion – dB
–59
–57
3.63.2 3.3 3.4 3.5
3 3.1 3.63.2 3.3 3.4 3.5
VDD – Supply Voltage – V
Diff Input = 2 V,
fi = 10 MHz, –0.5 dBFS
Sample Rate = 40 MSPS
Figure 15
SIGNAL-TO-NOISE PLUS DISTORTION
vs
SUPPLY VOLTAGE
75
Diff Input = 2 V,
fi = 10 MHz, –0.5 dBFS
73
Sample Rate = 40 MSPS
71
12
69
67
65
63
61
SNR – Signal-to-Noise Ratio – dB
59
57
3 3.1 3.63.2 3.3 3.4 3.5
VDD – Supply Voltage – V
Figure 16
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69
67
65
63
61
59
SNRD – Signal-to-Noise Plus Distortion – dB
57
3 3.5 3.6
3.1 3.2 3.3 3.4
VDD – Supply Voltage – V
Figure 17
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