查询THS1040IDWR供应商
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
FEATURES
Analog Supply 3 V
D
D Digital Supply 3 V
D Configurable Input Functions:
− Single Ended
− Differential
D Differential Nonlinearity: ±0.45 LSB
D Signal-to-Noise: 60 dB Typ f
at 4.8 MHz
(IN)
D Spurious Free Dynamic Range: 72 dB
D Adjustable Internal Voltage Reference
D On-Chip Voltage Reference Generator
D Unsigned Binary Data Output
D Out-of-Range Indicator
D Power-Down Mode
APPLICATIONS
Video/CCD Imaging
D
D Communications
D Set-Top Box
D Medical
DESCRIPTION
The THS1040 is a CMOS, low power, 10-bit, 40-MSPS
analog-to-digital converter (ADC) that operates from a
single 3-V supply. The THS1040 has been designed to
give circuit developers flexibility . The analog input to the
THS1040 can be either single-ended or differential. The
THS1040 provides a wide selection of voltage
references to match the user’s design requirements.
For more design flexibility, the internal reference can be
bypassed to use an external reference to suit the dc
accuracy and temperature drift requirements of the
application. The out-of-range output indicates any
out-of-range condition in THS1040’s input signal.
The speed, resolution, and single-supply operation of
the THS1040 are suited to applications in set-top-box
(STB), video, multimedia, imaging, high-speed
acquisition, and communications. The speed and
resolution ideally suit charge-couple device (CCD) input
systems such as color scanners, digital copiers, digital
cameras, and camcorders. A wide input voltage range
allows the THS1040 to be applied in both imaging and
communications systems.
The THS1040C is characterized for operation from 0°C
to 70°C, while the THS1040I is characterized for
operation from −40°C to 85°C.
28-PIN TSSOP/SOIC PACKAGE
AGND
DV
DGND
DD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
OVR
(TOP VIEW)
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
AV
DD
AIN+
VREF
AIN−
REFB
MODE
REFT
BIASREF
TEST
AGND
REFSENSE
STBY
OE
CLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
! " #$% !" &$'(#! )!%*
)$#" # "&%##!" &% +% %" %,!" "$%"
"!)!) -!!.* )$# &#%""/ )%" %#%""!(. #($)%
%"/ !(( &!!%%"*
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Copyright 2001 − 2004, Texas Instruments Incorporated
1
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRODUCT
THS1040C
THS1040I −40°C to 85°C TJ1040
THS1040C
THS1040I −40°C to 85°C TJ1040
†
For the most current specification and package information, refer to the TI web site at www.ti.com.
PACKAGE
LEAD
TSSOP−28 PW
SOP−28 DW
functional block diagram
PACKAGE
DESGIGNATOR
AVAILABLE OPTIONS
SPECIFIED
TEMPERATURE
†
RANGE
0°C to 70°C TH1040
0°C to 70°C TH1040
PACKAGE
MARKINGS
ORDERING
NUMBER
THS1040CPW Tube, 50
THS1040CPWR Tube and Reel, 2000
THS1040IPW Tube, 50
THS1040IPWR Tube and Reel, 2000
THS1040CDW Tube, 20
THS1040CDWR Tube and Reel, 1000
THS1040IDW Tube, 20
THS1040IDWR Tube and Reel, 1000
TRANSPORT MEDIA,
QUANTITY
BIASREF
AIN+
AIN−
MODE
AV
DD
AGND
NOTE: A1 − Internal bandgap reference
A2 − Internal ADC reference generator
Mode
Detection
VREF
A2
SHA
10-Bit
ADC
ADC
Reference
Resistor
REFB REFT
VREF
3-State
Output
Buffers
Timing
Circuit
Digital
Control
A1
0.5 V
REFSENSE
STBY
D (0−9)
OVR
OE
DV
DD
DGND
CLK
+
−
2
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I/O
DESCRIPTION
Terminal Functions
TERMINAL
NAME NO.
AGND 1, 19 I Analog ground
AIN+ 27 I Positive analog input
AIN− 25 I Negative analog input
AV
DD
BIASREF 21 O
CLK 15 I Clock input
DGND 14 I Digital ground
DV
DD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
MODE 23 I Operating mode select (AGND, AVDD/2, or AVDD)
OE 16 I High to 3-state the data bus, low to enable the data bus
OVR 13 O Out-of-range indicator
REFB 24 I/O Bottom ADC reference voltage
REFSENSE 18 I VREF mode control
REFT 22 I/O Top ADC reference voltage
STBY 17 I Drive high to power-down the THS1040
TEST 20 I Production test pin. Tie to DVDD or DGND
VREF 26 I/O Internal or external reference
28 I Analog supply
When the MODE pin is at A VDD, a buffered A VDD/2 is present at this pin that can be used by external input
biasing circuits. The output is high impedance when MODE is AGND or A VDD/2.
2 I Digital supply
3
4
5
6
7
8
9
10
11
12
Digital data bit 0 (LSB)
Digital data bit 1
Digital data bit 2
Digital data bit 3
Digital data bit 4
O
Digital data bit 5
Digital data bit 6
Digital data bit 7
Digital data bit 8
Digital data bit 9 (MSB)
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
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3
Operating free-air temperature, T
C
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range: AV
to AGND, DVDD to DGND −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
†
AGND to DGND −0.3 V to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AV
to DV
DD
DD
MODE input voltage range, MODE to AGND −0.3 V to AV
Reference voltage input range, REFT, REFB, to AGND −0.3 V to AV
Analog input voltage range, AIN to AGND −0.3 V to AV
Reference input voltage range, VREF to AGND −0.3 V to AV
Reference output voltage range, VREF to AGND −0.3 V to AV
Clock input voltage range, CLK to AGND −0.3 V to AV
Digital input voltage range, digital input to DGND −0.3 V to DV
Digital output voltage range, digital output to DGND −0.3 V to DV
Operating junction temperature range, T
Storage temperature range, T
stg
J
−4 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
0°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−65 °C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , a nd
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
over operating free-air temperature range TA, (unless otherwise noted)
PARAMETER CONDITION MIN NOM MAX UNIT
Power Supply
Supply voltage AVDD, DV
Analog and Reference Inputs
VREF input voltage V
REFT input voltage V
REFB input voltage V
Reference input voltage V
Reference common mode voltage (V
Analog input voltage differential (see Note 1) V
Analog input capacitance, C
Clock input (see Note 2) 0 AV
Digital Outputs
Maximum digital output load resistance R
Maximum digital output load capacitance C
Digital Inputs
High-level input voltage, V
Low-level input voltage, V
Clock frequency (see Note 3) t
Clock pulse duration t
NOTE 1: V
NOTE 2: The clock pin is referenced to AVSS and powered by AVDD.
NOTE 3: Clock frequency can be extended to this range without degradation of performance.
is AIN+ − AIN− range, based on V
I(AIN)
voltage is recommended to be A VDD/2.
I
IH
IL
A
I(VREF)
I(REFT)
I(REFB)
I(REFT) − VI(REFB)
I(AIN)
L
L
c
w(CKL), tw(CKH)
I(REFT) − VI(REFB)
DD
I(REFT) + VI(REFB)
REFSENSE = AV
MODE = AGND 1.75 2 V
MODE = AGND 1 1.25 V
MODE = AGND 0.5 1 V
)/2 MODE = AGND (AVDD/2) − 0.05 (AVDD/2) + 0.05 V
REFSENSE = AGND −1 1 V
REFSENSE = VREF −0.5 0.5 V
f
= 5 MHz to 40 MHz 25 200 nS
(CLK)
f
= 40 MHz 11.25 12.5 13.75 nS
(CLK)
THS1040C 0 70
THS1040I −40 85
= 1 V. Varies proportional to the V
DD
3 3 3.6 V
0.5 1 V
10 pF
DD
100 kΩ
10 pF
2.4 DV
DGND 0.8 V
I(REFT) − VI(REFB)
value. Input common mode
DD
V
V
°
4
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SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
electrical characteristics
over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 40 MSPS/50% duty cycle, MODE = AVDD (internal reference),
differential input range = 1 VPP and 2 VPP, TA = T
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AV
DD
DV
DD
I
CC
P
D
P
D(STBY)
t
(WU)
Supply voltage
Operating supply current See Note 4 33 40 mA
Power dissipation See Note 4 100 120 mW
Standby power 75 µW
Power up time for all references from standby, t
Wake-up time See Note 5 45 µs
REFT, REFB internal ADC reference voltages outputs (MODE = AVDD or AVDD/2) (See Note 6)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference voltage top, REFT
Reference voltage bottom, REFB
Input resistance between REFT and REFB 1.4 1.9 2.5 kΩ
to T
min
VREF = 0.5 V
VREF = 1 V
VREF = 0.5 V
VREF = 1 V
(unless otherwise noted)
max
(PU)
10 µF bypass 770 µs
AVDD = 3 V
AVDD = 3 V
3 3.6
3 3.6
1.75
2
1.25
1
V
V
V
VREF (on-chip voltage reference generator)
PARAMETER MIN TYP MAX UNIT
Internal 0.5-V reference voltage (REFSENSE = VREF) 0.45 0.5 0.55 V
Internal 1-V reference voltage (REFSENSE = AGND) 0.95 1 1.05 V
Reference input resistance (REFSENSE = AVDD, MODE = AVDD/2 or AVDD) 7 14 21 kΩ
dc accuracy
PARAMETER MIN TYP MAX UNIT
Resolution 10 Bits
INL Integral nonlinearity (see definitions) −1.5 ± 0.75 1.5 LSB
DNL Differential nonlinearity (see definitions) −0.9 ± 0.45 0.9 LSB
Zero error (see definitions) −1.5 0.7 1.5 %FSR
Full-scale error (see definitions) −3 2.2 3 %FSR
Missing code No missing code assured
NOTE 4: Apply a −1 dBFS 10-KHz triangle wave at AIN+ and AIN− with an internal bandgap reference and ADC reference enabled, and BIASREF
NOTE 5: Wake-up time is from the power-down state to accurate ADC samples being taken and is specified for MODE = AGND with external
NOTE 6: External reference values are listed in the Recommended Operating Conditions Table.
enabled at AVDD/2. Any additional load at BIASREF or VREF may require additional current.
reference sources applied to the device at the time of release of power-down, and an applied 40-MHz clock. Circuits that need to power
up are the bandgap, bias generator, ADC, and SHA.
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5
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
electrical characteristics
over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 40 MSPS/50% duty cycle, MODE = AVDD (internal reference),
differential input range = 1 VPP and 2 VPP, TA = T
dynamic performance (ADC)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ENOB Effective number of bits
SFDR Spurious free dynamic range
THD Total harmonic distortion
SNR Signal-to-noise ratio
SINAD Signal-to-noise and distortion
BW Full power bandwidth (−3 dB) 900 MHz
digital specifications
PARAMETER MIN NOM MAX UNIT
Digital Inputs
V
IH
V
IL
I
IH
I
IL
C
i
Digital Outputs
V
OH
V
OL
Clock Input
t
c
t
w(CKH)
t
w(CKL)
t
d(o)
t
d(AP)
High-level input voltage
Low-level input voltage
High-level input current 1 µA
Low-level input current |−1| µA
Input capacitance 5 pF
High-level output voltage I
Low-level output voltage I
High-impedance output current ±1 µA
Rise/fall time C
Clock cycle time 25 200 ns
Pulse duration, clock high 11.25 110 ns
Pulse duration, clock low 11.25 110 ns
Clock duty cycle 45% 50% 55%
Clock to data valid, delay time 9.5 16 ns
Pipeline latency 4 Cycles
Aperture delay time 0.1 ns
Aperture uncertainty (jitter) 1 ps
min
to T
(unless otherwise noted) (continued)
max
f = 4.8 MHz, −0.5 dBFS 8.8 9.6
f = 20 MHz, −0.5 dBFS
f = 4.8 MHz, −0.5 dBFS 60.5 72
f = 20 MHz, −0.5 dBFS
f = 4.8 MHz, −0.5 dBFS −72.5 −61.3
f = 20 MHz, −0.5 dBFS
f = 4.8 MHz, −0.5 dBFS 55.7 60
f = 20 MHz, −0.5 dBFS
f = 4.8 MHz, −0.5 dBFS 55.6 59.7
f = 20 MHz, −0.5 dBFS
Clock input 0.8 × AV
All other inputs
Clock input 0.2 × AV
All other inputs
= 50 µA DVDD−0.4 V
load
= −50 µA 0.4 V
load
= 15 pF 3.5 ns
load
0.8 × DV
DD
DD
9.5
70
−71.6
57
59.6
0.2 × DV
DD
DD
Bits
dB
dB
dB
dB
V
V
timing
t
d(DZ)
t
d(DEN)
V
O(BIASREF)
6
PARAMETER MIN TYP MAX UNIT
Output disable to Hi-Z output, delay time 0 10 ns
Output enable to output valid, delay time 0 10 ns
Output voltage MODE = AV
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DD
(AVDD/2) − 0.1 (AVDD/2) + 0. 1 V
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
Analog
Input
t
w(CKH)
Input Clock
Digital
Output
OE
Sample 1
Note A
See
t
c
t
d(DEN)
Sample 2
t
Sample 3
Sample 4
w(CKL)
Pipeline Latency
NOTE A: All timing measurements are based on 50% of edge transition.
Figure 1. Digital Output Timing Diagram
Sample 5
Sample 6
t
d(o)
(I/O Pad Delay or
Propagation Delay)
Sample 1
t
d(DZ)
Sample 7
Sample 2
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7
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
1.0
AVDD = 3 V
DVDD = 3 V
0.5
fs = 40 MSPS
V
= 1 V
ref
0.0
−0.5
−1.0
0 128 256 384 512 640 768 896 1024
DNL − Differential Nonlinearity − LSB
1.0
DIFFERENTIAL NONLINEARITY
vs
INPUT CODE
Input Code
Figure 2
INTEGRAL NONLINEARITY
vs
INPUT CODE
0.5
0.0
−0.5
−1.0
INL − Integral Nonlinearity − LSB
−0.5
AVDD = 3 V
DVDD = 3 V
fs = 40 MSPS
V
= 1 V
ref
0 128 256 384 512 640 768 896 1024
1.0
AVDD = 3 V
0.5
0.0
DVDD = 3 V
fs = 40 MSPS
V
ref
Input Code
Figure 3
INTEGRAL NONLINEARITY
vs
INPUT CODE
= 0.5 V
−1.0
INL − Integral Nonlinearity − LSB
0 128 256 384 512 640 768 896 1024
Input Code
Figure 4
8
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SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
−80
1-V FS Differential Input Range
−75
−70
−65
−60
−55
−50
THD − Total Harmonic Distortion − dB
−45
−40
0 10 20 30 40 50 60 70 80 90 100110 120
−6 dBFS
See Note
fi − Input Frequency − MHz
−0.5 dBFS
−20 dBFS
Figure 5
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
61
59
57
Diff Input = 2 V
SE Input = 2 V
Diff Input = 1 V
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
−85
−80
−75
−70
−65
−60
−55
−50
THD − Total Harmonic Distortion − dB
−45
−40
−0.5 dBFS
See Note
0 102030405060708090100110120
2-V FS Differential Input Range
−6 dBFS
−20 dBFS
fi − Input Frequency − MHz
Figure 6
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
82
72
Diff Input = 2 V
Diff Input = 1 V
55
53
SE Input = 1 V
51
SNR − Signal-to-Noise Ratio − dB
49
See Note
47
0 102030405060708090100110120
fi − Input Frequency − MHz
Figure 7
NOTE: AVDD = DVDD = 3 V, fS = 40 MSPS, 20-pF capacitors AIN+ to AGND and AIN− to AGND,
Input series resistor = 25 Ω,
2-V Input: Ext Ref, REFT = 2 V, REFB = 1 V, −0.5 dBFS
1-V Input: Ext Ref, REFT = 1.75 V, REFB = 1.25 V, −0.5 dBFS
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62
52
42
SFDR − Spurious Free Dynamic Range − dB
32
0 10 20 30 40 50 60 70 80 90 100 110 120
SE Input = 1 V
See Note
fi − Input Frequency − MHz
Figure 8
SE Input = 2 V
9
TOTAL HARMONIC DISTORTION
SIGNAL-TO-NOISE RATIO
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE PLUS DISTORTION
vs
INPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
Diff Input = 2 V
57
52
47
42
37
SINAD − Signal-to-Noise Plus Distortion − dB
32
SE Input = 1 V
SE Input = 2 V
See Note
0102030405060708090100110120
fi − Input Frequency − MHz
Diff Input = 1 V
−82
−72
−62
−52
−42
THD − Total Harmonic Distortion − dB
−32
Diff Input = 2 V
SE Input = 1 V
See Note
0 10 20 30 40 50 60 70 80 90 100 110 120
fi − Input Frequency − MHz
Figure 9
NOTE: AVDD = DVDD = 3 V, fS = 40 MSPS, 20-pF capacitors AIN+ to AGND and AIN− to AGND,
Input series resistor = 25 Ω,
2-V Input: Ext Ref, REFT = 2 V, REFB = 1 V, −0.5 dBFS
1-V Input: Ext Ref, REFT = 1.75 V, REFB = 1.25 V, −0.5 dBFS
vs
SAMPLE RATE
Diff Input = 1 V
SE Input = 2 V
Figure 10
vs
SAMPLE RATE
−75
−70
−65
−60
−55
−50
THD − Total Harmonic Distortion − dB
−45
−40
0 5 10152025303540455055
Diff Input = 2 V
fi = 20 MHz, −0.5 dBFS
Sample Rate − MSPS
Figure 11
75
70
65
60
55
50
SNR − Signal-To-Noise Ratio − dB
45
40
0 5 10 15 20 25 30 35 40 45 50 55
Sample Rate − MSPS
Diff Input = 2 V
fi = 20 MHz, −0.5 dBFS
Figure 12
10
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INPUT BANDWIDTH
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
SAMPLE RATE
AVDD = 3 V,
V
= 1 V
ref
110
Int. Ref
TA = 25°C
Ext. Ref
90
− Power Dissipation − mW
D
P
70
4 8 12 16 20 24 28 32 36 40 44
fs − Sample Rate − MSPS
TA = 25°C
Figure 13
TOTAL CURRENT
vs
CLOCK FREQUENCY
AVDD = 3 V
36
V
= 1 V
ref
34
Int. Ref
32
30
− Total Current − mA
DD
I
28
26
24
0 5 10 15 20 25 30 35 40 45
TA = 25°C
Ext. Ref
TA = 25°C
f
− Clock Frequency − MHz
clk
Figure 14
4
AVDD = 3 V
DVDD = 3 V
fs = 40 MSPS
2
0
−2
Amplitude − dB
−4
−6
See Note
−8
10 100 300 500 700 900 1100
fi − Input Frequency − MHz
Figure 15
NOTE: No series resistors and no bypass capacitors at AIN+ and AIN− inputs.
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11
ADC CODES
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
2.4
2
1.6
1.2
0.8
Reft, Refb Reference Voltage − V
0.4
0
POWER-UP TIME FOR INTERNAL
REFERENCE VOLTAGE FROM STANDBY
V
= 1 V, Reft = 10 µF,
ref
Refb = 10 µF, AVDD = 3 V
V
reft
V
refb
0
90
180
270
360
450
540
630
720
810
900
990
Power-Up Time − µs
Figure 16
1080
1170
vs
WAKE-UP SETTLING TIME
125
MODE = AGND,
120
115
110
105
ADC Codes
100
95
90
−10 5 20 35 50 65 80 95 110
Wake-Up Settling Time − µs
fS = 40 MSPS,
Ext. REF = 1 V and 2 V,
AVDD = 3 V
See Note
Figure 17
12
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SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
20
fi= 10 MHz, −0.5 dBFS
0
−20
−40
−60
−80
Amplitude − dB
−100
−120
−140
Amplitude − dB
−100
−120
−140
fS = 40 MSPS,
Diff Input = 2 V
0
20
fi = 4.5 MHz, −0.5 dBFS
0
fS = 40 MSPS,
−20
Diff Inpt = 2 V
−40
−60
−80
0
FFT
5
f − Frequency − MHz
10 15 20
Figure 18
FFT
5
f − Frequency − MHz
10 15 20
Figure 19
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13
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
functional overview
See the functional block diagram. A single-ended, sample rate clock is required at pin CLK for device operation.
Analog inputs AIN+ and AIN− are sampled on each rising edge of CLK in a switched capacitor sample and hold
unit, the output of which feeds the ADC core, where analog-to-digital conversion is performed against the ADC
reference voltages REFT and REFB.
Internal or external ADC reference voltage configurations are selected by connecting the MODE pin
appropriately. When MODE = AGND, the user must provide external sources at pins REFB and REFT. When
MODE = AV
and REFB pins using the voltage at pin VREF as its input. The user can choose to drive VREF from the internal
bandgap reference, or disable A1 and provide their own reference voltage at pin VREF.
On the fourth rising CLK edge following the edge that sampled AIN+ and AIN−, the conversion result is output
via data pins D0 to D9. The output buffers can be disabled by pulling pin OE
The following sections explain further:
D How signals flow from AIN+ and AIN− to the ADC core, and how the reference voltages at REFT and REFB
set the ADC input range and hence the input range at AIN+ and AIN−.
or MODE = A VDD/2, an internal ADC references generator (A2) is enabled which drives the REFT
DD
high.
D How to set the ADC references REFT and REFB using external sources or the internal reference buffer (A2)
to match the device input range to the input signal.
D How to set the output of the internal bandgap reference (A1) if required.
signal processing chain (sample and hold, ADC)
Figure 20 shows the signal flow through the sample and hold unit to the ADC core.
REFT
VQ+
AIN+
AIN−
Sample
X1
X−1
and
Hold
VQ−
REFB
Figure 20. Analog Input Signal Flow
ADC
Core
14
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(1)
(2)
(3)
(4)
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SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
sample-and-hold
Differential input signal sources can be connected directly to the AIN+ and AIN− pins using either dc- or
ac-coupling.
For single-ended sources, the signal can be dc- or ac-coupled to one of AIN+ or AIN−, and a suitable reference
voltage (usually the midscale voltage, see operating configuration examples) must be applied to the other pin.
Note that connecting the signal to AIN− results in it being inverted during sampling.
The sample and hold differential output voltage VQ = (VQ+) − (VQ−) is given by:
VQ = (AIN+) − (AIN−)
analog-to-digital converter
VQ is digitized by the ADC, using the voltages at pins REFT and REFB to set the ADC zero-scale (code 0) and
full-scale (code 1023) input voltages.
VQ(ZS) +*(REFT* REFB)
VQ(FS) + (REFT * REFB)
Any inputs at AIN+ and AIN− that give VQ voltages less than VQ(ZS) or greater than VQ(FS) lie outside the
ADC’s conversion range and attempts to convert such voltages are signalled by driving pin OVR high when the
conversion result is output. VQ voltages less than VQ(ZS) digitize to give ADC output code 0 and VQ voltages
greater than VQ(FS) give ADC output code 1023.
complete system and system input range
Combining the above equations to find the input voltages [(AIN+) − (AIN−)] that correspond to the limits of the
ADC’s valid input range gives:
(REFB * REFT) v[(AIN)
For both single-ended and differential inputs, the ADC can thus handle signals with a peak-to-peak input range
[(AIN+) − (AIN−)] of:
[(AIN+) − (AIN−)] pk-pk input range = 2 x (REFT − REFB)
The REFT and REFB voltage difference and the gain sets the device input range. The next sections describe
in detail the various methods available for setting voltages REFT and REFB to obtain the desired input span
and device performance.
)*(
AIN*)]v (REFT* REFB)
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15
(6)
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
ADC reference generation
The THS1040 ADC references REFT and REFB can be driven from external (off-chip) sources or from the
internal (on-chip) reference buffer A2. The voltage at the MODE pin determines the ADC references source.
Connecting MODE to AGND enables external ADC references mode. In this mode the internal buffer A2 is
powered down and the user must provide the REFT and REFB voltages by connecting external sources directly
to these pins. This mode is useful where several THS1040 devices must share common references for best
matching of their ADC input ranges, or when the application requires better accuracy and temperature stability
than the on-chip reference source can provide.
Connecting MODE to AV
or AVDD/2 enables internal ADC references mode. In this mode the buffer A2 is
DD
powered up and drives the REFT and REFB pins. External reference sources should not be connected in this
mode. Using internal ADC references mode when possible helps to reduce the component count and hence
the system cost.
When MODE is connected to AV
, a buffered AVDD/2 voltage is available at the BIASREF pin. This voltage
DD
can be used as a dc bias level for any ac-coupling networks connecting the input signal sources to the AIN+
and AIN− pins.
MODE PIN REFERENCE SELECTION BIASREF PIN FUNCTION
AGND External High impedance
AVDD/2 Internal High impedance
AV
DD
Internal AVDD/2 for AIN± bias
external reference mode (MODE = AGND)
AIN+
AIN−
VREF
REFT
REFB
X1
X−1
Sample
and
Hold
Internal
Reference
Buffer
ADC
Core
Figure 21. ADC Reference Generation, MODE = AGND
Connecting pin MODE to AGND powers down the internal references buffer A2 and disconnects its outputs from
the REFT and REFB pins. The user must connect REFT and REFB to external sources to provide the ADC
reference voltages required to match the THS1040 input range to their application requirements. The
common-mode reference voltage must be AV
(REFT ) REFB)
2
16
+
AV
DD
2
/2 for correct THS1040 operation:
DD
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AVDD + VREF
(7)
(8)
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
internal reference mode (MODE = AV
AIN+
AIN−
VREF
AGND
X1
X−1
or AVDD/2)
DD
Sample
and
Hold
Internal
Reference
Buffer
2
ADC
Core
AVDD − VREF
2
Figure 22. ADC Reference Generation, MODE = AVDD/2
Connecting MODE to AV
or AVDD/2 enables the internal ADC references buffer A2. The outputs of A2 are
DD
connected to the REFT and REFB pins and its inputs are connected to pins VREF and AGND. The resulting
voltages at REFT and REFB are:
REFT +
REFB +
ǒ
AVDD) VREF
2
ǒ
AVDD* VREF
2
Ǔ
Ǔ
Depending on the connection of the REFSENSE pin, the voltage on VREF may be driven by an off-chip source
or by the internal bandgap reference A1 (see onboard reference generator) to match the THS1040 input range
to their application requirements.
When MODE = AV
the BIASREF pin provides a buffered, stabilized AVDD/2 output voltage that can be used
DD
as a bias reference for ac coupling networks connecting the signal sources to the AIN+ or AIN− inputs. This
removes the need for the user to provide a stabilized external bias reference.
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17
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
internal reference mode (MODE = AV
+FS
AIN+
−FS
+FS
AIN−
−FS
0.1 µF
0.1 µF
Figure 23. Internal Reference Mode, 1-V Reference Span
+FS
VM
−FS
or AVDD/2) (continued)
DD
AIN+
AIN−
REFT
0.1 µF10 µF
REFB
AIN+
MODE
REFSENSE
VREF
BIASREF
MODE
AVDD or
AV
AV
DD
2
1 V (Output)
V
if MODE = AV
MID
High-Impedance if MODE =
DD
or AV
2
DD
DD
AV
DD
2
DC SOURCE = VM
VM
0.1 µF
0.1 µF
+
_
0.1 µF10 µF
AIN−
REFT
REFB
VREF
REFSENSE
0.5 V (Output)
Figure 24. Internal Reference Mode, 0.5-V Reference Span, Single-Ended Input
18
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(9)
(10)
(11)
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
onboard reference generator configuration
The internal bandgap reference A1 can provide a supply-voltage-independent and temperature-independent
voltage on pin VREF.
External connections to REFSENSE control A1’s output to the VREF pin as shown in Table 1.
Table 1. Effect of REFSENSE Connection on VREF Value
REFSENSE CONNECTION A1 OUTPUT TO VREF SEE:
VREF pin 0.5 V Figure 25
AGND 1 V Figure 26
External divider junction (1 + Ra/Rb)/2 V Figure 27
AV
DD
REFSENSE = AVDD powers the internal bandgap reference A1 down, saving power when A1 is not required.
If MODE is connected to AV
REFT +
AV
2
DD
)
VREF
or A VDD/2, then the voltage at VREF determines the ADC reference voltages:
DD
2
Open circuit Figure 28
REFB +
AV
2
DD
*
VREF
REFT–REFB + VREF
VBG
Figure 25. 0.5-V VREF Using the Internal Bandgap Reference A1
2
ADC
References
Buffer A2
MODE =
AV
DD
or AV
+
+
_
_
2
DD
VREF = 0.5 V
0.1 µF 1 µF
REFSENSE
AGND
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19
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
onboard reference generator configuration (continued)
ADC
References
Buffer A2
MODE =
AV
DD
or AV
DD
VBG
+
+
_
_
2
10 kΩ
10 kΩ
VREF = 1 V
0.1 µF 1 µF
REFSENSE
AGND
Figure 26. 1-V VREF Using the Internal Bandgap Reference A1
ADC
References
Buffer A2
MODE =
AV
DD
or AV
DD
VREF = (1 + Ra/Rb)/2
Ra
REFSENSE
Rb
AGND
0.1 µF 1 µF
VBG
+
+
_
_
2
Figure 27. External Divider Mode
20
www.ti.com
PRINCIPLES OF OPERATION
onboard reference generator configuration (continued)
ADC
References
Buffer A2
MODE =
AV
+
VBG
+
_
_
2
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
DD
or AV
DD
VREF = External
REFSENSE
AV
DD
AGND
Figure 28. Drive VREF Mode
operating configuration examples
Figure 29 shows a configuration using the internal ADC references for digitizing a single-ended signal with span
0 V to 2 V. Tying REFSENSE to ground gives 1 V at pin VREF. T ying MODE to AV
REFB voltages via the internal reference generator for a 2-V
ADC input range. The VREF pin provides the
p-p
1-V mid-scale bias voltage required at AIN−. VREF should be well decoupled to AGND to prevent
sample-and-hold switching at AIN− from corrupting the VREF voltage.
2 V
1 V
0 V
10 µF
0.1 µF
10 µF
0.1 µF
20 Ω
20 pF
20 Ω
20 pF
0.1 µF
AIN+
MODE
AIN−
VREF = 1 V
REFT
REFSENSE
REFB
AVDD/2
/2 then sets the REFT and
DD
Figure 29. Operating Configuration: 2-V Single-Ended Input, Internal ADC References
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21
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
operating configuration examples (continued)
Figure 30 shows a configuration using the internal ADC references for digitizing a dc-coupled differential input
with 1.5-V
reference output at VREF to 0.75 V. Tying MODE to AV
reference generator for a 1.5-V
If a transformer is used to generate the differential ADC input from a single-ended signal, then the BIASREF
pin provides a suitable bias voltage for the secondary windings center tap when MODE = AV
span and 1.5-V common-mode voltage. External resistors are used to set the internal bandgap
p-p
1.875 V
1.5 V
1.125 V
1.875 V
1.5 V
1.125 V
ADC input range.
p-p
20 Ω
20 Ω
20 pF
20 pF
then sets the REFT and REFB voltages via the internal
DD
DD
AV
DD
AIN+
AIN−
VREF = 0.75 V
MODE
5 kΩ
.
0.1 µF
10 µF
0.1 µF
REFT
0.1 µF
REFB
REFSENSE
10 µF
10 kΩ
Figure 30. Operating Configuration: 1.5-V Differential Input, Internal ADC References
Figure 31 shows a configuration using the internal ADC references and an external VREF source for digitizing
a dc-coupled single-ended input with span 0.5 V to 2 V. A 1.25-V external source provides the bias voltage for
the AIN− pin and also, via a buffered potential divider, the 0.75 VREF voltage required to set the input range
to 1.5 V
MODE is tied to AVDD to set internal ADC references configuration.
p-p
AV
1.25 V
0.5 V
1.25
Source
10 µF
2 V
10 kΩ
(0.75 V)
15 kΩ
20 Ω
20 Ω
20 pF
20 pF
_
+
AIN+
AIN−
VREF
MODE
REFT
REFB
REFSENSE
DD
0.1 µF
AV
0.1 µF
10 µF
0.1 µF
DD
22
Figure 31. Operating Configuration: 1.5-V Single-Ended Input, External VREF Source
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SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
power management
In power-sensitive applications (such as battery-powered systems) where the THS1040 is not required to
convert continuously, power can be saved between conversion intervals by placing the THS1040 into
power-down mode. This is achieved by pulling the STBY pin high. In power-down mode, the device typically
consumes less than 0.1 mW of power.
If the internal VREF generator (A1) is not required, it can be powered down by tying pin REFSENSE to AV
saving approximately 1.2 mA of supply current.
If the BIASREF function is not required when using internal references then tying MODE to AV
BIASREF buffer down, saving approximately 1.2 mA.
/2 powers the
DD
digital I/O
While the OE pin is held low, ADC conversion results are output at pins D0 (LSB) to D9 (MSB). The ADC input
over-range indicator is output at pin OVR. OVR is also disabled when OE
The only ADC output data format supported is unsigned binary (output codes 0 to 1023). Twos complement
output (output codes −512 to 511) can be obtained by using an external inverter to invert the D9 output.
is held high.
DD
,
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23
(12)
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
APPLICATION INFORMATION
driving the THS1040 analog inputs
driving the clock input
Obtaining good performance from the THS1040 requires care when driving the clock input.
Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should
ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as
possible in which to operate.
The CLK pin should also be driven from a low jitter source for best dynamic performance. To maintain low jitter
at the CLK input, any clock buffers external to the THS1040 should have fast rising edges. Use a fast logic family
such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other
logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter.
As the CLK input threshold is nominally around AV
/2, any clock buffers need to have an appropriate supply
DD
voltage to drive above and below this level.
driving the sample and hold inputs
driving the AIN+ and AIN− pins
Figure 32 shows an equivalent circuit for the THS1040 AIN+ and AIN− pins. The load presented to the system
at the AIN pins comprises the switched input sampling capacitor, C
Sample
, and various stray capacitances, C
and C2.
AV
DD
AIN
AGND
C1
8 pF
CLK
C2
1.2 pF
CLK
+
_
VCM = AIN+/AIN− Common Mode Voltage
1.2 pF
C
Sample
Figure 32. Equivalent Circuit for Analog Input Pins AIN+ and AIN−
The input current pulses required to charge C
Sample
and C2 can be time averaged and the switched capacitor
circuit modelled as an equivalent resistor:
1
R
+
IN2
where CS is the sum of C
1
CS f
Sample
resistance for high impedance sources.
24
CLK
and C2. This model can be used to approximate the input loading versus source
www.ti.com
(13)
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
APPLICATION INFORMATION
AV
DD
AIN
AGND
C1
8 pF
R2 = 1/CS f
I
IN
CLK
+
VCM = AIN+/AIN− Common Mode Voltage
_
Figure 33. Equivalent Circuit for the AIN Switched Capacitor Input
AIN input damping
The charging current pulses into AIN+ and AIN− can make the signal sources jump or ring, especially if the
sources are slightly inductive at high frequencies. Inserting a small series resistor of 20 Ω or less and a small
capacitor to ground of 20 pF or less in the input path can damp source ringing (see Figure 34). The resistor and
capacitor values can be made larger than 20 Ω and 20 pF if reduced input bandwidth and a slight gain error (due
to potential division between the external resistors and the AIN equivalent resistors) are acceptable.
Note that the capacitors should be soldered to a clean analog ground with a common ground point to prevent
any voltage drops in the ground plane appearing as a differential voltage at the ADC inputs.
V
S
R < 20 Ω
AIN
C < 20 pF
Figure 34. Damping Source Ringing Using a Small Resistor and Capacitor
driving the VREF pin
Figure 35 shows the equivalent load on the VREF pin when driving the ADC internal references buffer via this
pin (MODE = AVDD/2 or AVDD and REFSENSE = AVDD).
AV
DD
R
VREF
AGND
IN
10 kΩ
MODE = AV
DD
REFSENSE = AVDD,
MODE = AVDD/2 or AV
+
(AVDD + VREF) /4
_
DD
Figure 35. Equivalent Circuit of VREF
The nominal input current I
3V
+
REF
4 R
I
REF
is given by:
REF
* AV
IN
DD
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25
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
APPLICATION INFORMATION
driving the VREF pin (continued)
Note that the maximum current may be up to 30% higher. The user should ensure that VREF is driven from a
low noise, low drift source, well decoupled to analog ground and capable of driving the maximum I
driving REFT and REFB (external ADC references, MODE = AGND)
AV
DD
REF
.
REFT
REFB
AV
AGND
DD
AGND
2 kΩ
To ADC Core
To ADC Core
Figure 36. Equivalent Circuit of REFT and REFB Inputs
reference decoupling
VREF pin
When the on-chip reference generator is enabled, the VREF pin should be decoupled to the circuit board’s
analog ground plane close to the THS1040 AGND pin via a 1-µF capacitor and a 0.1-µF ceramic capacitor.
REFT and REFB pins
In any mode of operation, the REFT and REFB pins should be decoupled as shown in Figure 37. Use short
board traces between the THS1040 and the capacitors to minimize parasitic inductance.
0.1 µF
REFT
THS1040
REFB
0.1 µF
10 µF
0.1 µF
Figure 37. Recommended Decoupling for the ADC Reference Pins REFT and REFB
BIASREF pin
When using the on-chip BIASREF source, the BIASREF pin should be decoupled to the circuit board’s analog
ground plane close to the THS1040 AGND pin via a 1-µF capacitor and a 0.1-µF ceramic capacitor.
26
www.ti.com
supply decoupling
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
APPLICATION INFORMATION
The analog (AV
decoupled for best performance. Each supply needs at least a 10-µF electrolytic or tantalum capacitor (as a
charge reservoir) and a 100-nF ceramic type capacitor placed as close as possible to the respective pins (to
suppress spikes and supply noise).
digital output loading and circuit board layout
The THS1040 outputs are capable of driving rail-to-rail with up to 10 pF of load per pin at 40-MHz clock frequency
and 3-V digital supply. Minimizing the load on the outputs improves THS1040 signal-to-noise performance by
reducing the switching noise coupling from the THS1040 output buffers to the internal analog circuits. The
output load capacitance can be minimized by buffering the THS1040 digital outputs with a low input capacitance
buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks
between the THS1040 and this buffer. Inserting small resistors in the range 100 Ω to 300 Ω between the
THS1040 I/O outputs and their loads can help minimize the output-related noise in noise-critical applications.
Noise levels at the output buffers, which may affect the analog circuits within THS1040, increase with the digital
supply voltage. Where possible, consider using the lowest DV
Use good layout practices when designing the application PCB to ensure that any off-chip return currents from
the THS1040 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any
sensitive analog circuits. The THS1040 should be soldered directly to the PCB for best performance. Socketing
the device degrades performance by adding parasitic socket inductance and capacitance to all pins.
user tips for obtaining best performance from the THS1040
, AGND) and digital (DVDD, DGND) power supplies to the THS1040 must be separately
DD
that the application can tolerate.
DD
D Choose differential input mode for best distortion performance.
D Choose a 2-V ADC input span for best noise performance.
D Choose a 1-V ADC input span for best distortion performance.
D Drive the clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short
PCB traces.
D Use a small RC filter (typically 20 Ω and 20 pF) between the signal source(s) the AIN+ (and AIN−) input(s)
when the systems bandwidth requirements allow this.
www.ti.com
27
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
APPLICATION INFORMATION
definitions
D Integral nonlinearity (INL)—Integral nonlinearity refers to the deviation of each individual code from a line
drawn from zero to full scale. The point used as zero occurs 1/2 LSB before the first code transition. The
full-scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from
the center of each particular code to the true straight line between these two endpoints.
D Differential nonlinearity (DNL)—An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL
is the deviation from this ideal value. Therefore this measure indicates how uniform the transfer function
step sizes are. The ideal step size is defined here as the step size for the device under test (i.e., (last
transition level – first transition level) ÷ (2
and offset error. A minimum DNL better than –1 LSB ensures no missing codes.
D Zero-error—Zero-error is defined as the difference in analog input voltage—between the ideal voltage and
the actual voltage—that switches the ADC output from code 0 to code 1. The ideal voltage level is
determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The voltage
corresponding to 1 LSB is found from the difference of top and bottom references divided by the number
of ADC output levels (1024).
n
– 2)). Using this definition for DNL separates the effects of gain
D Full-scale error—Full-scale error is defined as the difference in analog input voltage—between the ideal
voltage and the actual voltage—that switches the ADC output from code 1022 to code 1023. The ideal
voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference level.
The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (1024).
D Wake-up time—Wake-up time is from the power-down state to accurate ADC samples being taken and is
specified for MODE = AGND with external reference sources applied to the device at the time of release
of power-down, and an applied 40-MHz clock. Circuits that need to power up are the bandgap, bias
generator, ADC, and SHA.
D Power-up time—Power-up time is from the power-down state to accurate ADC samples being taken and
is specified for MODE = AV
include VREF reference generation (A1), bias generator, ADC, the SHA, and the on-chip ADC reference
generator (A2).
/2 or AVDD and an applied 40-MHz clock. Circuits that need to power up
DD
D Aperture delay—The delay between the 50% point of the rising edge of the clock and the instant at which
the analog input is sampled.
D Aperture uncertainty (Jitter)—The sample-to-sample variation in aperture delay.
28
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
THS1040CDW ACTIVE SOIC DW 28 20 Pb-Free
THS1040CDWR ACTIVE SOIC DW 28 1000 Pb-Free
THS1040CPW ACTIVE TSSOP PW 28 50 None CU NIPDAU Level-2-220C-1 YEAR
THS1040CPWR ACTIVE TSSOP PW 28 2000 None CU NIPDAU Level-2-220C-1 YEAR
THS1040IDW ACTIVE SOIC DW 28 20 Pb-Free
THS1040IDWR ACTIVE SOIC DW 28 1000 Pb-Free
THS1040IPW ACTIVE TSSOP PW 28 50 None CU NIPDAU Level-2-220C-1 YEAR
THS1040IPWR ACTIVE TSSOP PW 28 2000 None CU NIPDAU Level-2-220C-1 YEAR
THS1040IPWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
(3)
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
1,20 MAX
14
0,30
0,19
8
4,50
4,30
PINS **
7
Seating Plane
0,15
0,05
8
1
A
DIM
14
0,10
6,60
6,20
M
0,10
0,15 NOM
0°–8°
2016
Gage Plane
24
0,25
0,75
0,50
28
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
4040064/F 01/97
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