TEXAS INSTRUMENTS THS1040 Technical data
查询THS1040IDWR供应商
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
FEATURES
Analog Supply 3 V
D
D Digital Supply 3 V
D Configurable Input Functions:
− Single Ended
− Differential
D Differential Nonlinearity: ±0.45 LSB
D Signal-to-Noise: 60 dB Typ f
at 4.8 MHz
(IN)
D Spurious Free Dynamic Range: 72 dB
D Adjustable Internal Voltage Reference
D On-Chip Voltage Reference Generator
D Unsigned Binary Data Output
D Out-of-Range Indicator
D Power-Down Mode
APPLICATIONS
Video/CCD Imaging
D
D Communications
D Set-Top Box
D Medical
DESCRIPTION
The THS1040 is a CMOS, low power, 10-bit, 40-MSPS
analog-to-digital converter (ADC) that operates from a
single 3-V supply. The THS1040 has been designed to
give circuit developers flexibility . The analog input to the
THS1040 can be either single-ended or differential. The
THS1040 provides a wide selection of voltage
references to match the user’s design requirements.
For more design flexibility, the internal reference can be
bypassed to use an external reference to suit the dc
accuracy and temperature drift requirements of the
application. The out-of-range output indicates any
out-of-range condition in THS1040’s input signal.
The speed, resolution, and single-supply operation of
the THS1040 are suited to applications in set-top-box
(STB), video, multimedia, imaging, high-speed
acquisition, and communications. The speed and
resolution ideally suit charge-couple device (CCD) input
systems such as color scanners, digital copiers, digital
cameras, and camcorders. A wide input voltage range
allows the THS1040 to be applied in both imaging and
communications systems.
The THS1040C is characterized for operation from 0°C
to 70°C, while the THS1040I is characterized for
operation from −40°C to 85°C.
28-PIN TSSOP/SOIC PACKAGE
AGND
DV
DGND
DD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
OVR
(TOP VIEW)
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
AV
DD
AIN+
VREF
AIN−
REFB
MODE
REFT
BIASREF
TEST
AGND
REFSENSE
STBY
OE
CLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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)$#" # "&%##!" &% +% %" %,!" "$%"
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Copyright 2001 − 2004, Texas Instruments Incorporated
1
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRODUCT
THS1040C
THS1040I −40°C to 85°C TJ1040
THS1040C
THS1040I −40°C to 85°C TJ1040
†
For the most current specification and package information, refer to the TI web site at www.ti.com.
PACKAGE
LEAD
TSSOP−28 PW
SOP−28 DW
functional block diagram
PACKAGE
DESGIGNATOR
AVAILABLE OPTIONS
SPECIFIED
TEMPERATURE
†
RANGE
0°C to 70°C TH1040
0°C to 70°C TH1040
PACKAGE
MARKINGS
ORDERING
NUMBER
THS1040CPW Tube, 50
THS1040CPWR Tube and Reel, 2000
THS1040IPW Tube, 50
THS1040IPWR Tube and Reel, 2000
THS1040CDW Tube, 20
THS1040CDWR Tube and Reel, 1000
THS1040IDW Tube, 20
THS1040IDWR Tube and Reel, 1000
TRANSPORT MEDIA,
QUANTITY
BIASREF
AIN+
AIN−
MODE
AV
DD
AGND
NOTE: A1 − Internal bandgap reference
A2 − Internal ADC reference generator
Mode
Detection
VREF
A2
SHA
10-Bit
ADC
ADC
Reference
Resistor
REFB REFT
VREF
3-State
Output
Buffers
Timing
Circuit
Digital
Control
A1
0.5 V
REFSENSE
STBY
D (0−9)
OVR
OE
DV
DD
DGND
CLK
+
−
2
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I/O
DESCRIPTION
Terminal Functions
TERMINAL
NAME NO.
AGND 1, 19 I Analog ground
AIN+ 27 I Positive analog input
AIN− 25 I Negative analog input
AV
DD
BIASREF 21 O
CLK 15 I Clock input
DGND 14 I Digital ground
DV
DD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
MODE 23 I Operating mode select (AGND, AVDD/2, or AVDD)
OE 16 I High to 3-state the data bus, low to enable the data bus
OVR 13 O Out-of-range indicator
REFB 24 I/O Bottom ADC reference voltage
REFSENSE 18 I VREF mode control
REFT 22 I/O Top ADC reference voltage
STBY 17 I Drive high to power-down the THS1040
TEST 20 I Production test pin. Tie to DVDD or DGND
VREF 26 I/O Internal or external reference
28 I Analog supply
When the MODE pin is at A VDD, a buffered A VDD/2 is present at this pin that can be used by external input
biasing circuits. The output is high impedance when MODE is AGND or A VDD/2.
2 I Digital supply
3
4
5
6
7
8
9
10
11
12
Digital data bit 0 (LSB)
Digital data bit 1
Digital data bit 2
Digital data bit 3
Digital data bit 4
O
Digital data bit 5
Digital data bit 6
Digital data bit 7
Digital data bit 8
Digital data bit 9 (MSB)
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
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3
Operating free-air temperature, T
C
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range: AV
to AGND, DVDD to DGND −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
†
AGND to DGND −0.3 V to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AV
to DV
DD
DD
MODE input voltage range, MODE to AGND −0.3 V to AV
Reference voltage input range, REFT, REFB, to AGND −0.3 V to AV
Analog input voltage range, AIN to AGND −0.3 V to AV
Reference input voltage range, VREF to AGND −0.3 V to AV
Reference output voltage range, VREF to AGND −0.3 V to AV
Clock input voltage range, CLK to AGND −0.3 V to AV
Digital input voltage range, digital input to DGND −0.3 V to DV
Digital output voltage range, digital output to DGND −0.3 V to DV
Operating junction temperature range, T
Storage temperature range, T
stg
J
−4 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
0°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−65 °C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , a nd
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
over operating free-air temperature range TA, (unless otherwise noted)
PARAMETER CONDITION MIN NOM MAX UNIT
Power Supply
Supply voltage AVDD, DV
Analog and Reference Inputs
VREF input voltage V
REFT input voltage V
REFB input voltage V
Reference input voltage V
Reference common mode voltage (V
Analog input voltage differential (see Note 1) V
Analog input capacitance, C
Clock input (see Note 2) 0 AV
Digital Outputs
Maximum digital output load resistance R
Maximum digital output load capacitance C
Digital Inputs
High-level input voltage, V
Low-level input voltage, V
Clock frequency (see Note 3) t
Clock pulse duration t
NOTE 1: V
NOTE 2: The clock pin is referenced to AVSS and powered by AVDD.
NOTE 3: Clock frequency can be extended to this range without degradation of performance.
is AIN+ − AIN− range, based on V
I(AIN)
voltage is recommended to be A VDD/2.
I
IH
IL
A
I(VREF)
I(REFT)
I(REFB)
I(REFT) − VI(REFB)
I(AIN)
L
L
c
w(CKL), tw(CKH)
I(REFT) − VI(REFB)
DD
I(REFT) + VI(REFB)
REFSENSE = AV
MODE = AGND 1.75 2 V
MODE = AGND 1 1.25 V
MODE = AGND 0.5 1 V
)/2 MODE = AGND (AVDD/2) − 0.05 (AVDD/2) + 0.05 V
REFSENSE = AGND −1 1 V
REFSENSE = VREF −0.5 0.5 V
f
= 5 MHz to 40 MHz 25 200 nS
(CLK)
f
= 40 MHz 11.25 12.5 13.75 nS
(CLK)
THS1040C 0 70
THS1040I −40 85
= 1 V. Varies proportional to the V
DD
3 3 3.6 V
0.5 1 V
10 pF
DD
100 kΩ
10 pF
2.4 DV
DGND 0.8 V
I(REFT) − VI(REFB)
value. Input common mode
DD
V
V
°
4
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SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
electrical characteristics
over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 40 MSPS/50% duty cycle, MODE = AVDD (internal reference),
differential input range = 1 VPP and 2 VPP, TA = T
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AV
DD
DV
DD
I
CC
P
D
P
D(STBY)
t
(WU)
Supply voltage
Operating supply current See Note 4 33 40 mA
Power dissipation See Note 4 100 120 mW
Standby power 75 µW
Power up time for all references from standby, t
Wake-up time See Note 5 45 µs
REFT, REFB internal ADC reference voltages outputs (MODE = AVDD or AVDD/2) (See Note 6)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference voltage top, REFT
Reference voltage bottom, REFB
Input resistance between REFT and REFB 1.4 1.9 2.5 kΩ
to T
min
VREF = 0.5 V
VREF = 1 V
VREF = 0.5 V
VREF = 1 V
(unless otherwise noted)
max
(PU)
10 µF bypass 770 µs
AVDD = 3 V
AVDD = 3 V
3 3.6
3 3.6
1.75
2
1.25
1
V
V
V
VREF (on-chip voltage reference generator)
PARAMETER MIN TYP MAX UNIT
Internal 0.5-V reference voltage (REFSENSE = VREF) 0.45 0.5 0.55 V
Internal 1-V reference voltage (REFSENSE = AGND) 0.95 1 1.05 V
Reference input resistance (REFSENSE = AVDD, MODE = AVDD/2 or AVDD) 7 14 21 kΩ
dc accuracy
PARAMETER MIN TYP MAX UNIT
Resolution 10 Bits
INL Integral nonlinearity (see definitions) −1.5 ± 0.75 1.5 LSB
DNL Differential nonlinearity (see definitions) −0.9 ± 0.45 0.9 LSB
Zero error (see definitions) −1.5 0.7 1.5 %FSR
Full-scale error (see definitions) −3 2.2 3 %FSR
Missing code No missing code assured
NOTE 4: Apply a −1 dBFS 10-KHz triangle wave at AIN+ and AIN− with an internal bandgap reference and ADC reference enabled, and BIASREF
NOTE 5: Wake-up time is from the power-down state to accurate ADC samples being taken and is specified for MODE = AGND with external
NOTE 6: External reference values are listed in the Recommended Operating Conditions Table.
enabled at AVDD/2. Any additional load at BIASREF or VREF may require additional current.
reference sources applied to the device at the time of release of power-down, and an applied 40-MHz clock. Circuits that need to power
up are the bandgap, bias generator, ADC, and SHA.
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5
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
electrical characteristics
over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 40 MSPS/50% duty cycle, MODE = AVDD (internal reference),
differential input range = 1 VPP and 2 VPP, TA = T
dynamic performance (ADC)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ENOB Effective number of bits
SFDR Spurious free dynamic range
THD Total harmonic distortion
SNR Signal-to-noise ratio
SINAD Signal-to-noise and distortion
BW Full power bandwidth (−3 dB) 900 MHz
digital specifications
PARAMETER MIN NOM MAX UNIT
Digital Inputs
V
IH
V
IL
I
IH
I
IL
C
i
Digital Outputs
V
OH
V
OL
Clock Input
t
c
t
w(CKH)
t
w(CKL)
t
d(o)
t
d(AP)
High-level input voltage
Low-level input voltage
High-level input current 1 µA
Low-level input current |−1| µA
Input capacitance 5 pF
High-level output voltage I
Low-level output voltage I
High-impedance output current ±1 µA
Rise/fall time C
Clock cycle time 25 200 ns
Pulse duration, clock high 11.25 110 ns
Pulse duration, clock low 11.25 110 ns
Clock duty cycle 45% 50% 55%
Clock to data valid, delay time 9.5 16 ns
Pipeline latency 4 Cycles
Aperture delay time 0.1 ns
Aperture uncertainty (jitter) 1 ps
min
to T
(unless otherwise noted) (continued)
max
f = 4.8 MHz, −0.5 dBFS 8.8 9.6
f = 20 MHz, −0.5 dBFS
f = 4.8 MHz, −0.5 dBFS 60.5 72
f = 20 MHz, −0.5 dBFS
f = 4.8 MHz, −0.5 dBFS −72.5 −61.3
f = 20 MHz, −0.5 dBFS
f = 4.8 MHz, −0.5 dBFS 55.7 60
f = 20 MHz, −0.5 dBFS
f = 4.8 MHz, −0.5 dBFS 55.6 59.7
f = 20 MHz, −0.5 dBFS
Clock input 0.8 × AV
All other inputs
Clock input 0.2 × AV
All other inputs
= 50 µA DVDD−0.4 V
load
= −50 µA 0.4 V
load
= 15 pF 3.5 ns
load
0.8 × DV
DD
DD
9.5
70
−71.6
57
59.6
0.2 × DV
DD
DD
Bits
dB
dB
dB
dB
V
V
timing
t
d(DZ)
t
d(DEN)
V
O(BIASREF)
6
PARAMETER MIN TYP MAX UNIT
Output disable to Hi-Z output, delay time 0 10 ns
Output enable to output valid, delay time 0 10 ns
Output voltage MODE = AV
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DD
(AVDD/2) − 0.1 (AVDD/2) + 0. 1 V
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
Analog
Input
t
w(CKH)
Input Clock
Digital
Output
OE
Sample 1
Note A
See
t
c
t
d(DEN)
Sample 2
t
Sample 3
Sample 4
w(CKL)
Pipeline Latency
NOTE A: All timing measurements are based on 50% of edge transition.
Figure 1. Digital Output Timing Diagram
Sample 5
Sample 6
t
d(o)
(I/O Pad Delay or
Propagation Delay)
Sample 1
t
d(DZ)
Sample 7
Sample 2
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7
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
1.0
AVDD = 3 V
DVDD = 3 V
0.5
fs = 40 MSPS
V
= 1 V
ref
0.0
−0.5
−1.0
0 128 256 384 512 640 768 896 1024
DNL − Differential Nonlinearity − LSB
1.0
DIFFERENTIAL NONLINEARITY
vs
INPUT CODE
Input Code
Figure 2
INTEGRAL NONLINEARITY
vs
INPUT CODE
0.5
0.0
−0.5
−1.0
INL − Integral Nonlinearity − LSB
−0.5
AVDD = 3 V
DVDD = 3 V
fs = 40 MSPS
V
= 1 V
ref
0 128 256 384 512 640 768 896 1024
1.0
AVDD = 3 V
0.5
0.0
DVDD = 3 V
fs = 40 MSPS
V
ref
Input Code
Figure 3
INTEGRAL NONLINEARITY
vs
INPUT CODE
= 0.5 V
−1.0
INL − Integral Nonlinearity − LSB
0 128 256 384 512 640 768 896 1024
Input Code
Figure 4
8
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SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
−80
1-V FS Differential Input Range
−75
−70
−65
−60
−55
−50
THD − Total Harmonic Distortion − dB
−45
−40
0 10 20 30 40 50 60 70 80 90 100110 120
−6 dBFS
See Note
fi − Input Frequency − MHz
−0.5 dBFS
−20 dBFS
Figure 5
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
61
59
57
Diff Input = 2 V
SE Input = 2 V
Diff Input = 1 V
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
−85
−80
−75
−70
−65
−60
−55
−50
THD − Total Harmonic Distortion − dB
−45
−40
−0.5 dBFS
See Note
0 102030405060708090100110120
2-V FS Differential Input Range
−6 dBFS
−20 dBFS
fi − Input Frequency − MHz
Figure 6
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
82
72
Diff Input = 2 V
Diff Input = 1 V
55
53
SE Input = 1 V
51
SNR − Signal-to-Noise Ratio − dB
49
See Note
47
0 102030405060708090100110120
fi − Input Frequency − MHz
Figure 7
NOTE: AVDD = DVDD = 3 V, fS = 40 MSPS, 20-pF capacitors AIN+ to AGND and AIN− to AGND,
Input series resistor = 25 Ω,
2-V Input: Ext Ref, REFT = 2 V, REFB = 1 V, −0.5 dBFS
1-V Input: Ext Ref, REFT = 1.75 V, REFB = 1.25 V, −0.5 dBFS
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62
52
42
SFDR − Spurious Free Dynamic Range − dB
32
0 10 20 30 40 50 60 70 80 90 100 110 120
SE Input = 1 V
See Note
fi − Input Frequency − MHz
Figure 8
SE Input = 2 V
9
TOTAL HARMONIC DISTORTION
SIGNAL-TO-NOISE RATIO
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE PLUS DISTORTION
vs
INPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
Diff Input = 2 V
57
52
47
42
37
SINAD − Signal-to-Noise Plus Distortion − dB
32
SE Input = 1 V
SE Input = 2 V
See Note
0102030405060708090100110120
fi − Input Frequency − MHz
Diff Input = 1 V
−82
−72
−62
−52
−42
THD − Total Harmonic Distortion − dB
−32
Diff Input = 2 V
SE Input = 1 V
See Note
0 10 20 30 40 50 60 70 80 90 100 110 120
fi − Input Frequency − MHz
Figure 9
NOTE: AVDD = DVDD = 3 V, fS = 40 MSPS, 20-pF capacitors AIN+ to AGND and AIN− to AGND,
Input series resistor = 25 Ω,
2-V Input: Ext Ref, REFT = 2 V, REFB = 1 V, −0.5 dBFS
1-V Input: Ext Ref, REFT = 1.75 V, REFB = 1.25 V, −0.5 dBFS
vs
SAMPLE RATE
Diff Input = 1 V
SE Input = 2 V
Figure 10
vs
SAMPLE RATE
−75
−70
−65
−60
−55
−50
THD − Total Harmonic Distortion − dB
−45
−40
0 5 10152025303540455055
Diff Input = 2 V
fi = 20 MHz, −0.5 dBFS
Sample Rate − MSPS
Figure 11
75
70
65
60
55
50
SNR − Signal-To-Noise Ratio − dB
45
40
0 5 10 15 20 25 30 35 40 45 50 55
Sample Rate − MSPS
Diff Input = 2 V
fi = 20 MHz, −0.5 dBFS
Figure 12
10
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