TEXAS INSTRUMENTS THS0842 Technical data

查询THS0842EVM供应商

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User’s Guide

September 2000 AAP Data Conversion

SLAU043C

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Copyright  2000, Texas Instruments Incorporated

About This Manual

How to Use This Manual

Preface

Read This First

This document presents a description of the THS0842 evaluation module.

How to Use This Manual

This document contains the following chapters:

- Chapter 1 – Overview

- Chapter 2 – Circuit Functionality

- Chapter 3 – Layout, Decoupling, and Grounding Considerations

- Chapter 4 – PC Board and Bill of Materials

- Appendix A – Schematics

Read This First

iii

iv

Running Title—Attribute Reference

Contents

1 Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Purpose 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 EVM Basic Function 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Power Requirements 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.1 Voltage Limits 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 THS0842 EVM Operational Procedure 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Circuit Functionality 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Circuit Function 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Analog Inputs 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Single-Ended Transformer Coupled Interface 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Differential Interface 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Digital Inputs 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 Internal Clock 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 External Clock 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Analog Output 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Digital Output 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 References 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Power 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Layout, Decoupling, and Grounding Considerations 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 PC Board and Bill of Materials 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Printed-Circuit Board 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Bill of Materials 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A Schematics A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter Title—Attribute Reference

v

Running Title—Attribute Reference

Figures

1–1 Block Diagram 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 Printed-Circuit Board (Top) 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 Printed-Circuit Board Layer 1 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 Printed-Circuit Board Layer 2 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 Printed-Circuit Board Layer 3 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 Printed-Circuit Board Layer 4 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Printed-Circuit Board Layer 5 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 Printed-Circuit Board Layer 6 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–8 Printed-Circuit Board (Bottom) 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

T ables

1–1 Jumper List Table 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2 Default Jumper Positions 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 Daughtercard Connector J2 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Daughtercard Connector J5 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Minimum/Maximum Reference Input Levels 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

Chapter 1

Overview

This chapter gives a general overview of the THS0842 evaluation module
(EVM), and describes some of the factors that must be considered in using the
module.

T opic Page

1.1 Purpose 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 EVM Basic Function 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Power Requirements 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 THS0842 EVM Operational Procedure 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . .

Overview

1-1

Purpose

T

T

1.1 Purpose

The THS0842 evaluation module (EVM) provides a platform for evaluating the
THS0842 analog-to-digital converter (ADC) under various signal, reference,
and supply conditions. The system block diagram is shown below. This illustra­tion provides a general indication of the features and functions available. It
should be read in combination with the circuit schematic supplied.

Figure 1–1.Block Diagram

AIN+

AIN–

1:1

Xfmr

A

IN

1:1

Xfmr

A

IN

IIN+

IIN–
CML

QIN+

QIN–

THS0842

DA7
DA0

COUT

COUT

I

THS5651A

Buffer

8

J2 – I OUT

OU

AIN–

AIN+

Clock

80 MHz

Osc

Optional
External

Reference

CLK
REFT

REFB

DB7
DB0

8

Buffer

THS5651A

J5 – Q OUT

I

OU

1-2

1.2 EVM Basic Function

Analog inputs to the ADC are provided via six external SMB connectors. Two
pairs of SMB connectors provide true differential inputs, or two individual SMB
connectors provide single-ended transformer-coupled signals to the inputs of
the device.

The EVM provides an external SMB connection for input of the ADC clock. A
crystal oscillator is provided on the board to perform this function and can be
used when required. Refer to the section on clocking for correct provisioning.

Digital output from the EVM is via two 25-pin connectors. The digital lines from
the ADC are buffered before going to the connectors. More information on
these connectors can be found in the ADC output section.

Analog output from the EVM is via two SMB connectors (J1 and J3). A pair of
THS5651 10-bit DACS are used to recreate the analog signal from the ADC’s
digital data. More information on this can be found in the ADC analog output
section.

Power connections to the EVM are via a pair of screw-down connectors.
Separate input connectors are provided for the analog and digital supplies.

EVM Basic Function

1.3 Power Requirements

The EVM is powered directly through independent 3.3-V analog and digital
supplies.

1.3.1 Voltage Limits

Exceeding the 3.3-V maximum can damage EVM components. Under voltage
may cause improper operation of some or all of the EVM components.

Overview

1-3

THS0842 EVM Operational Procedure

1.4 THS0842 EVM Operational Procedure

The THS0842 EVM provides a flexible means of evaluating the THS0842 in
a number of modes of operation. A basic setup procedure that can be used as
a board confidence check follows:

1) Verify all jumper settings against the schematic jumper list in Table 1–1:

Table 1–1.Jumper List Table

Jumper Function Installed Removed Default

W1 Reserved for future use Required Do not use Installed
W2 Reserved for future use Required Do not use Installed
W3 Oscillator power down Power down Active Installed
W4 Reference select Internal External Installed
W5 THS0842 standby Active Power down Installed
W6 Select clock source Onboard Offboard Removed
W7 Digital bus output enable 3-state bus Active Removed
W8 Single/dual bus mode Dual mode Single mode Installed
W9 External REFB source 1–2 onboard 2–3 offboard 1–2
W10 External REFB feed External Internal Removed
W1 1 External REFT feed External Internal Removed
W12 Q+ Input select 1–2 differential 2–3 single-ended 2–3
W13 Q– Input select 1–2 differential 2–3 single-ended 2–3
W14 I+ Input select 1–2 differential 2–3 single-ended 2–3
W15 I– Input select 1–2 differential 2–3 single-ended 2–3
W16 External REFT source 1–2 onboard 2–3 offboard 1–2

Table 1–2.Default Jumper Positions

EVM Jumper Table (connection)

THS0842 W1, W2, W3, W4, W5, W7, W9 (1–2), W12 (2–3), W13 (2–3), W14(2–3), W15 (2–3), W16(1–2)

1) Set both dc power supplies to read 3.3 V at the output terminals. Connect
GND of the first power supply to the AGND(J6–2) terminal on the EVM,
and GND of the other power supply to the DGND(J7–2) terminal on the
EVM. Then connect the first power supply’s 3.3-V output to the A VDD pow­er (J6–1) terminal of the EVM, and the other power supply’s 3.3-V output
to the DVDD(J7–1) terminal of the EVM.

1-4

2) Switch power supplies on.

3) Set function generator number one to output a square wave at a frequency
of 80 MHz, 0-V offset, and an amplitude of 3.3 V on the 50-Ω output.

4) Use a 50-Ω coaxial cable with BNC/SMB connectors to connect generator
number 1 to J4 (clock input).

THS0842 EVM Operational Procedure

5) Set function generator number 2 to output a sine wave at a frequency of
1 MHz, 0-V offset, and an amplitude of 0.8 Vp-p on the 50-Ω output.

6) Use a 50-Ω coaxial cable with BNC/SMB connectors to connect generator
number 2 to J8 (Q input). Use a T-splitter to connect the test signal to chan­nel 1 of the oscilloscope.

7) Use a 50-Ω coaxial cable with BNC/SMB connectors to connect the se­cond channel of the oscilloscope to J3 (Q-output). The two sine waves
should have the same period (their amplitudes may differ).

8) Repeat Step 5 with the SMB connected to J11 (I-input).

9) Repeat Step 6, except connect to J1 (I-output).

Overview

1-5

1-6

Chapter 2

Circuit Functionality

This chapter describes the digital interface-master clock, ADC data, and
power supply.

Topic Page

2.1 Circuit Function 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Analog Inputs 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Digital Inputs 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Analog Output 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Digital Output 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 References 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Power 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Circuit Functionality

2-1

Circuit Function

2.1 Circuit Function

The following sections describe the function of individual circuits. Refer to the
relevant data sheet for device operating characteristics.

2.2 Analog Inputs

The ADC has either transformer-coupled single-ended or differential-analog
inputs. These are provided on the EVM via SMB connectors J8 and J11 for
single-ended inputs, or J9/J10 and J12/J13 for differential inputs, and can be
configured in two ways, as discussed in Sections 2.2.1 and 2.2.2.

2.2.1 Single-Ended Transformer Coupled Interface

Connectors J8 (Q) and J1 1 (I) are single-ended inputs that use a 1:1 transform­er to provide differential analog inputs to the I+/I– and Q+/Q– inputs of U11
(THS0842). The signal input is nominally 0.89 Vpp.

W12, W13, W14, and W15 should be strapped across pins 2 and 3. The inputs
have 50-Ω terminators.

2.2.2 Differential Interface

Connectors J9 (Q+), J10 (Q–), J12 (I–), and J13 (I+) are used to connect ac­coupled differential signals directly to U1 1 (THS0842). The signal input is nom­inally a 0.44 Vpp.

W12, W13, W14, and W15 should be strapped across pins 1 and 2.

2.3 Digital Inputs

The THS0842 EVM utilizes jumpers for all digital inputs, with the exception of
the external clock. There are no connectors for setting the digital inputs. Refer
to the jumper table (T able 1–1 ) for a description of the jumpers and their func­tion.

2.3.1 Internal Clock

The EVM provides flexibility as to the source of the ADC’s conversion clock.
This clock can come from an external signal generator, as described in Section

2.3.2, or by enabling onboard 80-MHz oscillator X1. Removing the shorting bar
from W3 will enable oscillator X1. Adding a shorting bar to jumper pins W6 will
direct clock oscillations from oscillator X1 to buffer amplifier U10A and to the
rest of the circuit. The EVM is shipped with external clock selected, W6 open,
and W3 shorted.

2-2

Note:

R49 must be removed to avoid loading the output of X1.

2.3.2 External Clock

2.4 Analog Output

2.5 Digital Output

Circuit Function

SMB Connector J4 can be used to input a clock signal to the board from an
external source. The input source should be a 50-Ω L VTTL square wave signal
with an amplitude of 3.3 V referenced to digital ground. This is the default setup
for the EVM.

The ADC digital data is buffered and sent to a pair of THS5651A DACs. The
5651 DACs latch the THS0842 data on COUT (Q-DAC) or /COUT (I-DAC). An
analog signal is generated on J1 for the I-output and J3 for the Q-output. The
DAC outputs can only be used when the THS0842 EVM is set up for dual-bus
mode (W8 installed, SELB low). For further information on the THS5651A,
please refer to the product folder on TI’s website:

http://www.ti.com/sc/docs/products/analog/ths5651a.html

.

The digital-output codes of the ADC are made available on two 26-pin headers
along with COUT and COUT

. J2 provides access to the data from the I-input
and J5 provides access to the data from the Q-input. The output is 3.3 V TTL­compatible.

Table 2–1.Daughtercard Connector J2

J2 Pin Name Function J2 Pin Name Function

1 DA0 I
3 DA1 I
5 DA2 I
7 DA3 I
9 DA4 I
11 DA5 I
13 DA6 I
15 DA7 I
17 RSVD NC 18 DGND Ground
19 RSVD NC 20 DGND Ground
21 COUT COUT clock 22 DGND Ground
23 COUT COUT clock 24 DGND Ground
25 80 MHz 80-MHz clock 26 DGND Ground

0 2 DGND Ground

OUT

1 4 DGND Ground

OUT

2 6 DGND Ground

OUT

3 8 DGND Ground

OUT

4 10 DGND Ground

OUT

5 12 DGND Ground

OUT

6 14 DGND Ground

OUT

7 16 DGND Ground

OUT

Circuit Functionality

2-3

Circuit Function

Table 2–2.Daughtercard Connector J5

J2 Pin Name Function J2 Pin Name Function

2.6 References

1 DB0 Q
3 DB1 Q
5 DB2 Q
7 DB3 Q
9 DB4 Q
11 DB5 Q
13 DB6 Q
15 DB7 Q
17 RSVD NC 18 DGND Ground
19 RSVD NC 20 DGND Ground
21 COUT COUT clock 22 DGND Ground
23 COUT COUT clock 24 DGND Ground
25 80 MHz 80-MHz clock 26 DGND Ground

0 2 DGND Ground

OUT

1 4 DGND Ground

OUT

2 6 DGND Ground

OUT

3 8 DGND Ground

OUT

4 10 DGND Ground

OUT

5 12 DGND Ground

OUT

6 14 DGND Ground

OUT

7 16 DGND Ground

OUT

The EVM can use either the THS0842 internal reference, a tunable external
reference generated on the EVM board, or a customer-provided external
reference.

The THS0842’s input range is determined by the voltages on its V
V

pins. Since the part has an internal-voltage reference generator, it must

REFT

REFB

and

be powered down (W4 removed) before applying an external voltage to the
REFT and REFB pins. It is advantageous to have a wider analog input range,
especially at higher sampling rates. This can be achieved by using external

= 3.3 V , the full-scale range can be

voltage references. For example, at AV

DD

extended from 1 Vpp (internal reference) to 1.3 Vpp (external reference), as

not

shown in Table 3–3. These voltages should

be derived from a power­supply source via a voltage divider. Use instead a bandgap-derived voltage
reference to derive both references via an operational-amplifier circuit. Refer
to the schematic of the THS0842 evaluation module for an example circuit.

The full-scale ADC input range and its dc position can be adjusted when using
external references. The full-scale ADC range is always equal to V

REFT

–
VREFB. The maximum full-scale range is dependent on AVDD, as shown in
the THS0842 data sheet specifications section. Aside from the constraint on
their difference, there are limitations on the useful range of V

REFT

and V

REFB

individually, depending on the value of AVDD. Table 3–3 summarizes these
limits for three cases.

2-4

Table 2–3.Minimum/Maximum Reference Input Levels

Circuit Function

AV

DD

3.0 V 0.8 V 1.2 V 1.8 V 2.2 V 1.0 V

3.3 V 0.8 V 1.2 V 2.1 V 2.5 V 1.3 V

3.6 V 0.8 V 1.2 V 2.4 V 2.8 V 1.6 V

V

REFB(min)

V

REFB(max)

V

REFT(min)

V

REFT(max)

[V

REFT–VREFB]max

2.7 Power

Power is supplied to the EVM via screw-down connectors. For best perfor­mance use a separate low-noise analog power supply connected to J6–1
(+3.3 V) and J6–2 (GND). Use a separate low-noise digital power supply
connected to J7–1 (+3.3 V) and J7–2 (GND). The positive side is marked by
a + on the EVM’s silkscreen placed next to the connectors themselves.

Circuit Functionality

2-5

2-6

Chapter 3

Layout, Decoupling, and Grounding

Considerations

Proper grounding and layout of the PCB is essential to achieve the stated
performance. It is advised to use separate analog and digital ground planes
that are spliced underneath the device. The THS0842 has digital and analog
terminals on opposite sides of the package to make this easier. Since there is
no internal connection between analog and digital grounds, they have to be
joined on the PCB. This should be done at one point in close proximity to the
THS0842.

Separate analog and digital power-supply terminals are provided on the
device (A V
kept separate. Lowering the voltage on this supply to 3 V instead of the nominal

3.3 V improves performance due to the lower switching noise caused by the
output buffers.

/DVDD). The supply to the digital-output drivers (DRVDD) is also

DD

Because of the high sampling rate and switched-capacitor architecture, the
THS0842 generates transients on the supply and reference lines. Proper
decoupling of these lines is essential. Decoupling as shown in the schematic
of the THS0842 EVM is recommended.

Layout, Decoupling, and Grounding Considerations

3-1

3-2

Chapter 4

PC Board and Bill of Materials

This chapter presents the PC board design and a listing of the parts required
to build this evaluation module

Topic Page

4.1 Printed-Circuit Board 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Bill of Materials 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PC Board and Bill of Materials

4-1

Printed-Circuit Board

4.1 Printed-Circuit Board

This section presents the printed-circuit board for the THS0842 EVM.

Figure 4–1.Printed-Circuit Board (Top)

4-2

Figure 4–2.Printed-Circuit Board Layer 1

Printed-Circuit Board

PC Board and Bill of Materials

4-3

Printed-Circuit Board

Figure 4–3.Printed-Circuit Board Layer 2

4-4

Figure 4–4.Printed-Circuit Board Layer 3

Printed-Circuit Board

PC Board and Bill of Materials

4-5

Printed-Circuit Board

Figure 4–5.Printed-Circuit Board Layer 4

4-6

Figure 4–6.Printed-Circuit Board Layer 5

Printed-Circuit Board

PC Board and Bill of Materials

4-7

Printed-Circuit Board

Figure 4–7.Printed-Circuit Board Layer 6

4-8

Figure 4–8.Printed-Circuit Board (Bottom)

Printed-Circuit Board

PC Board and Bill of Materials

4-9

Bill of Materials

4.2 Bill of Materials

Part Type Designator Footprint Description Manufacturer Part Number

10 µF C4, C8, C12,

C14, C16, C18,
C21, C23, C29,
C44, C48, C49,
C52, C54, C59,
C60, C61, C62,
C86, C88, C90

0.1 µF C2, C3, C5,
C10, C11, C17,
C65, C71

0.1 µF C6, C13, C15,
C19, C24, C34,
C37, C38, C40,
C42, C45, C46,
C47, C50, C53,
C63, C67, C68,
C69, C72, C73,
C75, C76, C77,
C78, C80, C82,
C84, C85, C87,
C89, C91

4.7 µF C43, C51 3216 Low profile tantalum

470 pF C7, C12, C20,

C22, C26, C33,
C35, C36, C39,
C41, C64, C66,
C70, C74, C79

1.0 µF C25, C28, C31,
C32

0.01 µF C1, C9, C27,
C30, C55, C56,
C57, C58, C81,
C83

GREEN LED D1, D2 LED–1206 LED with LENS Lumex 67–1357–1
SMA JACK J3 SMA_JACK PCB mount SMA jack Johnson

KRMZ2 J6, J7 2term_screw_con 2 Terminal screw

SMA J1, J4, J8, J9,

J10, J11, J12,
J13

26PIN_IDC J2, J5 13×2×0.1 26 Pin header TSW–113–07–L–D

4.7 µH L1, L3 DO1608C DO1608C-Series –

1.0 µH L2 DO1608C DO1608C-Series –

20 R4, R5, R6, R8,

R9, R11, R12,
R13, R14, R15,
R17, R18, R19,
R20, R21, R24,
R25, R26, R27,
R28, R48

49.9 R39, R40, R41,
R42, R49, R57,
R58, R61, R62,
R63, R64

3528 Low profile tantalum

capacitor

1206 Multilayer ceramic –

variable footprint

805 Multilayer ceramic Mouser 77–VJ08Y50V104K

capacitor

805 Multilayer ceramic Mouser 77–VJ08A100V471J

805 Multilayer ceramic Digikey PCC1807CT–ND

805 Multilayer ceramic Mouser 77–VJ08Y50V103K

connector

SMA_JACK PCB mount SMA jack Johnson

Coil Craft

Coil Craft

1206 Mouser 263–20

1206 1/4W 1210 Chip

resistor

Digikey PCS1156CT–ND

Mouser 77–VJ12U50V104M

Digikey PCS1475CT–ND

142–0701–206

Components

506–5UL V02

142–0701–206

Components

Mouser 290–49.9

4-10

Bill of Materials

Part Type Part NumberManufacturerDescriptionFootprintDesignator

750 R36 1206 1/4W 1206 Chip

0 Ω R16, R23, R35,

2.49K 1% R38 1206 1/4W 1206 Chip

1.0 K R22, R44, R56,

2K POT R29, R30 BOURNS Digikey 3214W–202ECT–ND
33 Ω R1, R3, R10 2NBS16 Bourns 2NBS Series 4816P–1–330
2K R2, R7 1206 1/4W 1206 Chip

10K R31, R32, R33,

1.0K R44 1206 1/4W 1206 Chip

T1–1T–KK81 T1, T2, T3, T4 MC_KK81 RF transformer

TSW–101–07–LS TP1, TP2, TP3,

REF–
REF+

74LVC827A U1, U2, U4, U5,

SN74HC04D U8 14–SOP(D) Hex inverter TI SN74HC04D
SN74LVC08A U10 14–SOP(D) Quad NAND gate TI SN74LVC08AD
TL1431CD U14 8–SOP(D) Precision

TLV2772 U13 8–SOP(D) Dual op amp in 8 pin

THS0842 U11 48–TQFP(PFB) THS0842 TI THS0842IPFB
THS56X1 U3, U6 28–SOIC(DW) 2.7–5.5V, 10 bit,

TSW–102–07–LS W1, W2, W3,

3POS_JUMPER W9, W12, W13,

XTAL X1 4PIN_XTL_DC Crystal oscillator

R37, R51, R52

R59

R34, R43, R45,
R46, R47, R50,
R53, R54, R55,
R60,

TP4, TP5, TP6,
TP7, TP9,
TP10, TP11,
TP12, TP14,
TP15, TP16,
TP17

TP8
TP13

U7, U9, U12

W4, W5, W6,
W7, W8, W9,
W10, W11

W14, W15,
W16

1206 1/4W 1206 Chip

1206 1/4W 1206 Chip

1206 1/4W 1206 Chip

test_point2 T urret terminal test

test_point2 T urret terminal test

24 SOP (DW) 10-Bit bus interface FF

2pos_jump 2 Position jumper _

3pos_jump 3 Position jumper _

resistor 1%

resistor

resistor

resistor

resistor

resistor

resistor

MINI-circuits
T1–1T–KK81

point

point

3SO

programmable
reference

SOP package

125 MHz,
communications DAC

0.1” spacing

0.1” spacing

80 MHz

Mouser 290–750

Mouser 263–0

Mouser 263–2.49K

Mouser 263–1K

Mouser 263–2.00K

Mouser 263–10K

Mouser 263–1K

Samtec TSW–101–07–LS

Samtec TSW–101–07–LS

TI SN74LVC827ADW

TI TL1431QD

TI TLV2772ID

TI THS5651IDW

Samtec TSW–102–07–L–S

TSW–103–07–L–S

Digikey SG–8002DC–

SCC–80.00 MHz

PC Board and Bill of Materials

4-1 1

4-12

Schematics

This Appendix contains the THS0842 EVM schematics.

Appendix A

Schematics

A-1

A-2





C41

C40

470pF

0.1uF

OE11OE213A12A23A34A45A56A67A78A89A910A10

U7

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA[0..9]

DA7

DA8

11

DA9

74LVC827A

OE11OE213A12A23A34A45A56A67A78A89A910A10

U9

11

OE11OE213A12A23A34A45A56A67A78A89A910A10

U12

74LVC827A

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

11

DB9

DB[0..9]

74LVC827A

T3

J8

Qin

R57

49.9

T1-1T-KK81

DRV3

DRV3 DV3

C22

C77

C33

C85

AV3 AV3

470pF

0.1uF

470pF

0.1uF

C26

C24

C36

470pF

0.1uF

470pF

U11

27

13

45

DRVdd1DRVdd

AVdd

AVdd

AVdd

41

37

DVdd

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DA8

DA9

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

20

R4 20

R8 20

R9 20

R12 20

R1320R14 20

R6 20

R5 20

23

22

D0A

Q-35Q+

34

38

R15

R17 20

R20 20

R21 20

NC14NC

STBY

W5

11

44

R18 20

10

D0B

SELB

R19 20

OE

48

W7

R11 20

15

D7A16D6A17D5A18D4A19D3A20D2A21D1A

I-39I+

CLK

42

47

20

R25 20

R2620R27 20

R28

R24 20

3

D7B4D6B5D5B6D4B7D3B8D2B9D1B

BG

31

29

NC2NC

REFT

25

REFB

30

26

C_OUT

C_OUT

PWDN_REF

33

32

W4

CML

28

43

DVss

AVss40AVss36AVss

24

DRVss12DRVss

Vss

46

THS0842

C27

.01uF

R58

W14

49.9

W15

I-





I+





AV3

C37

0.1uF

R47

REFB

C81

C28

10k

.01uF

1.0uF

R50

10k

R53

10k

C39

470pF

C38

0.1uF

W8

R54

10k

DV3

80M

I-

I+

Q-

Q+

D

C

REFT

C84

0.1uF

C25

C31

C83

1.0uF

1.0uF

.01uF

T4

T1-1T-KK81

J11

Iin

B

C58

.01uF

J13





I

nstalled

I

for

THS0842

nstalled

for

THS0842

DACA[0..9]

U3

14

NC111NC212NC313NC4

IOUT122IOUT2

21

DACA0

DACA1

DACA2

DACA3

DACA4

DACA5

DACA6

DACA7

DACA8

D010D19D28D37D46D55D64D73D82D9

EXTLO16EXTIO17BIASJ

DACA9

1

18

C2

0.1uF

R2

28

2K

CLK

AV3

15

SLEEP

24

AVDD

C65

25

MODE

COMP119COMP2

0.1uF

DACB[0..9]

C5

0.1uF

DV3

26

DVDD27DGND

DACB0

DACB1

DACB2

DACB3

DACB4

DACB5

DACB6

DACB7

DACB8

DACB9

25

CLK

15

SLEEP

MODE

14

D010D19D28D37D46D55D64D73D82D9

NC111NC212NC313NC4

1

28

U6

THS56X1

AGND

20

23

C3

0.1uF

IOUT122IOUT2

21

EXTLO16EXTIO17BIASJ

18

C10

0.1uF

R7

2K

AV3

AVDD

24

C71

19

0.1uF

C1

0.01uF

R40

49.9

T1

T1-1T-KK81

R39

COUTB

R42

49.9

T2

T1-1T-KK81

R41

C9

0.01uF

I out

J1

D

C

Q out

J3

B





+

+

AV3

AV3

TP5

D2

+

C14

+

C42

10uF

C43

0.1uF

4.7uF

R22

1.0K

DV3

DV3

DRV3

TP10

TP6

C88

10uF

R60

10K

TP8

D1

R44

1.0K

C23

10uF

+

C48

10uF

+

0.1uF

C78

C87

0.1uF

L2

1.0uH

4.7uF

C51

+

0.1uF

C15

TP13

TP11

R30

REF+

2K POT

W16

AV3



R59

R35



1.0K

750

R36

0

REF-

W9

1K

R56

C91

0.1uF

+

10uF

C90

U14

TL1431CD

R37

C49

+

0

10uF

R38

2.49K

R55

10uF

C86

10K





R29

L1

9 $QDORJ

4.7uH

1

C4

+

C45

C54

+

C44

+

C21

+

C89

10uF

10uF

C76

10uF

C46

10uF

J6

0.1uF

0.1uF

0.1uF

0.1uF

2

L3

9 'LJLWDO

4.7uH

1

C18

C52

C16

C8

C29

10uF

+

10uF

+

10uF

+

10uF

+

10uF

+

C80

C82

C68

C72

C53

J7

0.1uF

0.1uF

0.1uF

0.1uF

2

DV3

DV3

.1uF

VCC

GNDOUT

OE

X1

W6

W3

R46

10k

U10A

1

J4

80M

R48

20

3

2

R49

49.9

CLOCK IN

SN74LVC08A

U8C

U10B

4

5 6

6

SN74LVC08A9U10C

5

SN74X04

U8D

9 8

D

C

B