Texas Instruments TC255PA, TC255P Datasheet

TC255P

336- × 244-PIXEL CCD IMAGE SENSOR

SOCS057 – JUNE 1996

2-1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• Medium-Resolution, Solid-State Image

Sensor for Low-Cost B/W TV Applications

• 324(H) x 243(V) Active Elements in Image

Sensing Area

• 10-µm Square Pixels

• Fast Clear Capability

• Electronic Shutter Function From

1/60–1/50000 s

• Low Dark Current

• Electron-Hole Recombination Antiblooming

• Dynamic Range...66 dB Typical

• High Sensitivity

• High Blue Response

• 8-Pin Dual-In-Line Plastic Package

• 4-mm Image-Area Diagonal

• Solid-State Reliability With No Image

Burn-In, Residual Imaging, Image Distortion, Image Lag, or Microphonics

• High Photoresponse Uniformity

description

The TC255P is a frame-transfer charge-coupled device (CCD) designed for use in B/W NTSC TV and specialpurpose applications where low cost and small size are desired.

The image-sensing area of the TC255P is configured in 243 lines with 336 elements in each line. Twelve elements are provided in each line for dark reference. The blooming-protection feature of the sensor is based on recombining excess charge with charge of opposite polarity in the substrate. This antiblooming is activated by supplying clocking pulses to the antiblooming gate, which is an integral part of each image-sensing element.

The sensor can be operated in a noninterlace mode as a 324(H) by 243(V) sensor with low dark current. The device can also be operated in an interlace mode, electronically displacing the image-sensing elements during the charge integration in alternate fields, and effectively increasing the vertical resolution and minimizing aliasing.

One important aspect of this image sensor is its high-speed image-transfer capability . This capability allows for an electronic-shutter function comparable to interline-transfer and frame-interline-transfer sensors without the loss of sensitivity and resolution inherent in those technologies.

The charge is converted to signal voltage with a 12-µV per electron conversion factor by a high-performance charge-detection structure with built-in automatic reset and a voltage-reference generator. The signal is buffered by a low-noise two-stage source-follower amplifier to provide high output-drive capability.

The TC255P uses TI-proprietary virtual-phase technology , which provides devices with high blue response, low dark signal, high photoresponse uniformity, and single-phase clocking. The TC255P is characterized for operation from –10°C to 45°C.

This MOS device contains limited built-in gate protection. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to SUB. Under no circumstances should pin voltages exceed absolute maximum ratings. Avoid shorting OUTn to ADB during operation to prevent damage to the amplifier. The device can also be damaged if the output terminals are reverse-biased and an excessive current is

allowed to flow. Specific guidelines for handling devices of this type are contained in the publication

Guidelines for Handling

Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies

available from Texas Instruments.

DUAL-IN-LINE PACKAGE

(TOP VIEW)

IAG2

ADB

SUB

OUT

ABG

IAG1

SAG

SRG

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TC255P 336- × 244-PIXEL CCD IMAGE SENSOR

SOCS057 – JUNE 1996

2-2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Amplifier

OUT

ADB

IAG2

SAG

IAG1

ABG

Storage Area

Blooming Protection

Image Area With

Dark-Reference Elements

SUB

2 Dummy Elements

Serial Register

SRG

Clear Line

Clearing Drain

TC255P

336- × 244-PIXEL CCD IMAGE SENSOR

SOCS057 – JUNE 1996

2-3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

sensor topology diagram

Effective-Imaging Area

324 Active Pixels

243 Lines

1 Dark Line

1 Clear Line

244 Lines

336 Pixels

212 1324Dummy Pixels

Optical

Black (OPB)

Dummy Pixel

Buffer Column

Active Pixels

Storage Area

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

ABG 8 I Antiblooming gate ADB 2 I Supply voltage for amplifier-drain bias SUB 3 Substrate IAG1 7 I Image-area gate 1 IAG2 1 I Image-area gate 2 OUT 4 O Output SAG 6 I Storage-area gate SRG 5 I Serial-register gate

TC255P 336- × 244-PIXEL CCD IMAGE SENSOR

SOCS057 – JUNE 1996

2-4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

The TC255P consists of five basic functional blocks: 1) the image-sensing area, 2) the image-clear line, 3) the image-storage area, 4) the serial register, and 5) the charge-detection node and output amplifier.

image-sensing area

Cross sections with potential-well diagrams and top views of image-sensing and storage-area elements are shown in Figure 1 and Figure 2. As light enters the silicon in the image-sensing area, free electrons are generated and collected in the potential wells of the sensing elements. During this time, the antiblooming gate is activated by the application of a burst of pulses every horizontal-blanking interval. This prevents blooming caused by the spilling of charge from overexposed elements into neighboring elements. To generate the dark reference that is necessary in subsequent video-processing circuits for restoration of the video-black level, there are 12 columns of elements on the left edge of the image-sensing area shielded from light. There is also one column of elements on the right side of the image-sensing area and one line between the image-sensing area and the image-clear line.

ABG

IAG

10 µm

Clocked Barrier

Virtual Barrier Antiblooming Gate

Virtual Well

Clocked Well

Light

Antiblooming

Clocking Levels

Accumulated Charge

10 µm

Figure 1. Charge-Accumulation Process

SAG

Channel Stops

Virtual Phase

Clocked Phase

Figure 2. Charge-Transfer Process

image-clear line

During start-up or electronic-shutter operations, it is necessary to clear the image area of charge without transferring it to the storage area. In such situations, the two image-area gates are clocked 244 times without clocking the storage-area gate. The charge in the image area is then cleared through the image-clear line.

TC255P

336- × 244-PIXEL CCD IMAGE SENSOR

SOCS057 – JUNE 1996

2-5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

image-storage area

After exposure, the image-area charge packets are transferred through the image-clear line to the storage area. The stored charge is then transferred line by line into the serial register for readout. Figure 3 illustrates the timing to (1) transfer the image to the storage area and (2) to transfer each line from the storage area to the serial register.

serial register

After each line is clocked into the serial register, it is read out pixel by pixel. Figure 3 illustrates the serial-register clock sequence.

SAG

SRG

IAG1

IAG2

SAG

Expanded Section of Parallel Transfer

1) 2) 3)

1) End of serial readout of line

2) Transfer of new line to serial register

3) Beginning of readout of new line

244 Clocks

244 Cycles

Composite

Blank

ABG

IAG1

IAG2

SAG

SRG

339 Cycles

SRG

t = 80 ns

244 Clocks

Electronic

Shutter

Operation

Integration Time

Figure 3. Timing Diagram

TC255P 336- × 244-PIXEL CCD IMAGE SENSOR

SOCS057 – JUNE 1996

2-6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

charge-detection node and output amplifier

The buffer amplifier converts charge into a video signal. Figure 4 shows the circuit diagram of the charge-detection node and output amplifier. As charge is transferred into the detection node, the potential of this node changes in proportion to the amount of signal received. This change is sensed by an MOS transistor and, after proper buffering, the signal is supplied to the output terminal of the image sensor . After the potential change is sensed, the node is reset to a reference voltage supplied by an on-chip reference generator. The reset is accomplished by a reset gate that is connected internally to the serial register. The detection node and buf fer amplifier are located a short distance from the edge of the storage area; therefore, two dummy cells are used to span this distance.

Reference Generator

SRG

Detection

Node

ADB

Figure 4. Buffer Amplifier and Charge-Detection Node

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