Burn-in, Residual Imaging, Image
Distortion, Image Lag, or Microphonics
description
The TC245 is a frame-transfer charge-coupled device (CCD) image sensor designed for use in single-chip B/W
NTSC TV applications. The device is intended to replace a 1/2-inch vidicon tube in applications requiring small
size, high reliability, and low cost.
20 SUB
19 IAG
18 ABG
17 SAG
16 SRG3
15 SRG2
14 SRG1
13 NC
12 TRG
11 IDB
The image-sensing area of the TC245 is configured into 242 lines with 786 elements in each line. Twenty-nine
elements are provided in each line for dark reference. The blooming-protection feature of the sensor is based
on recombining excess charge with charge of opposite polarity in the substrate. This antiblooming is activated
by supplying clocking pulses to the antiblooming gate, which is an integral part of each image-sensing element.
The sensor is designed to operate in an interlace mode, electronically displacing the image-sensing elements
in alternate fields by one-half of a vertical line during the charge integration period, effectively increasing the
vertical resolution and minimizing aliasing. The device can also be operated as a 755 (H) by 242 (V)
noninterlaced sensor with significant reduction in the dark signal.
A gated floating-diffusion detection structure with an automatic reset and voltage reference incorporated on-chip
converts charge to signal voltage. The signal is further processed by a low-noise, state-of-the-art correlated
clamp-sample-and-hold circuit. A low-noise, two-stage, source-follower amplifier buffers the output and
provides high output-drive capability . The image is read out through three outputs, each of which reads out every
third image column.
The TC245 is built using TI-proprietary virtual-phase technology, which provides devices with high blue
response, low dark signal, good uniformity , and single-phase clocking. The TC245 is characterized for operation
from –10°C to 45°C.
This MOS device contains limited built-in gate protection. During storage or handling, the device leads should be shorted together
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to SUB. Under no
circumstances should pin voltages exceed absolute maximum ratings. Avoid shorting OUTn to ADB during operation to prevent
allowed to flow. Specific guidelines for handling devices of this type are contained in the publication
Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies
damage to the amplifier. The device can also be damaged if the output terminals are reverse-biased and an excessive current is
Guidelines for Handling
available from Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1991, Texas Instruments Incorporated
2-1
TC245
786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
functional block diagram
2
IAG
ADB
3
4
Amplifiers
ABG
Top Drain
Image Area With
Blooming Protection
Dark Reference Elements
Storage Area
19
18
17
IAG
ABG
SAG
OUT3
OUT2
OUT1
11 Dummy
Elements
5
IDB
6
7
8
AMP GNDCDB
Multiplexer, Transfer
Gates, and Serial Registers
Clearing Drain
9
11
16
15
14
12
detailed description
The TC245 consists of four basic functional blocks: (1) the image-sensing area, (2) the image-storage area,
(3) the multiplexer block with serial registers and transfer gates, and (4) the low-noise signal-processing
amplifier block with charge-detection nodes. The location of each of these blocks is identified in the functional
block diagram.
SRG3
SRG2
SRG1
TRG
2-2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
sensor topology diagram
I/O
DESCRIPTION
TC245
786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
244755 + 1/2 + 1/2
1
1/2
Reverse TransferReverse Transfer
11
11
11.5
Dummy PixelsOPB
Effective Imaging Area
2 Lines
252
252
251 + 1/2 + 1/2
Terminal Functions
PIN
NAMENO.
†
ABG
†
ABG
ADB4ISupply voltage for amplifier drain bias
AMP GND8Amplifier ground
CDB9ISupply voltage for clearing drain bias
†
IAG
†
IAG
IDB11ISupply voltage for input diode bias
OUT17OOutput signal 1
OUT26OOutput signal 2
OUT35OOutput signal 3
All pins of the same name should be connected together externally.
3IAntiblooming gate
18IAntiblooming gate
2IImage-area gate
19IImage-area gate
1Substrate and clock return
10Substrate and clock return
20Substrate and clock return
1
29 + 1/2
10
10
9.5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-3
TC245
786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
image-sensing and storage areas
Figure 1 and Figure 2 show cross sections with potential well diagrams and top views of image-sensing and
storage-area elements. As light enters the silicon in the image-sensing area, free electrons are generated and
collected in the potential wells of the sensing elements. During this time, blooming protection is activated by
applying a burst of pulses to the antiblooming gate inputs every horizontal blanking interval. This prevents
blooming caused by the spilling of charge from overexposed elements into neighboring elements. After
integration is complete, the signal charge is transferred into the storage area.
There are 29 full columns and one half-column of elements at the right edge of the image-sensing area that are
shielded from incident light; these elements provide the dark reference used in subsequent video processing
circuits to restore the video black level. There are also one full column and one half-column of light-shielded
elements at the left edge of the image-sensing area and two lines of light-shielded elements between the
image-sensing and image-storage areas (the latter prevent charge leakage from the image-sensing area into
the image-storage area).
multiplexer with transfer gates and serial registers
The multiplexer and transfer gates transfer charge line by line from the storage-area columns into the
corresponding serial registers and prepare it for readout. Figure 3 illustrates the layout of the multiplexing gate
that vertically separates the pixels for input into the serial registers. Figure 4 shows the layout of the interface
region between the serial-register gates and the transfer gates. Multiplexing is activated during the horizontal
blanking interval by applying appropriate pulses to the transfer gates and serial registers; the required pulse
timing is shown in Figure 5. A drain is also included to provide the capability to clear the image-sensing and
storage areas of unwanted charge. Such charge can accumulate in the imager during the start-up of operation
or under special circumstances when nonstandard TV operation is desired.
correlated clamp-sample-and-hold amplifier with charge-detection nodes
Figure 6 illustrates the correlated clamp-sample-and-hold amplifier circuit. Charge is converted into a video
signal by transferring the charge onto a floating diffusion structure in detection node1 that is connected to the
gate of MOS transistor Q1. The proportional charge-induced signal is then processed by the circuit shown in
Figure 6. This circuit consists of a low-pass filter formed by Q1 and C2, coupling capacitor C1, dummy detection
node 2, which restores the dc bias on the gate of Q3, sampling transistor Q5, holding capacitor C3, and output
buffer Q6. Transistors Q2, Q4, and Q7 are current sources for each corresponding stage of the amplifier. The
parameters of this high-performance signal-processing amplifier have been optimized to minimize noise and
maximize the video signal.
The signal processing begins with a reset of detection node 1 and restoration of the dc bias on the gate of Q3
through the clamping function of dummy detection node 2. After the clamping is completed, the new charge
packet is transferred onto detection node 1. The resulting signal is sampled by the sampling transistor Q5 and
is stored on the holding capacitor C3. This process is repeated periodically and is correlated to the charge
transfer in the registers. The correlation is achieved automatically since the same clock lines used in registers
φ-S2 and φ-S3 for charge transport serve for reset and sample. The multiple use of the clock lines significantly
reduces the number of signals required to operate the sensor. The amplifier also contains an internal voltage
reference generator that provides the reference bias for the reset and clamp transistors. The detection nodes
and the corresponding amplifiers are located some distance away from the edge of the storage area. Therefore,
eleven dummy elements are incorporated at the end of each serial register to span the distance. The location
of the dummy elements, which are considered to be part of the amplifiers, is shown in the functional block
diagram.
The spurious nonuniformity specification of the TC245 CCD grades –10, –20, –30, and –40 is based on several
sensor characteristics:
•Amplitude of the nonuniform pixel
•Polarity of the nonuniform pixel
–Black
–White
•Location of the nonuniformity (see Figure 7)
–Area A
–Element columns near horizontal center of the area
–Element rows near vertical center of the area
–Area B
–Up to the pixel or line border
–Up to area A
–Other
–Edge of the imager
–Up to area B
•Nonuniform pixel count
•Distance between nonuniform pixels
•Column amplitude
The CCD sensors are characterized in both an illuminated condition and a dark condition. In the dark condition,
the nonuniformity is specified in terms of absolute amplitude as shown in Figure 8. In the illuminated condition,
the nonuniformity is specified as a percentage of the total illumination as shown in Figure 9.
The grade specification for the TC245 is as follows (CCD video-output signal is 50 mV ±10 mV):
Pixel nonuniformity:
DARK CONDITIONILLUMINATED CONDITION
PART
TC245-20x > 3.5000000x > 500————
-
†
White and black nonuniform pixel pair
‡
The total spot count is the sum of all nonuniform white, black, and white/black pairs in the dark condition added to the number of nonuniform black
pixels in the illuminated condition. The sum of all nonuniform combinations will not exceed the total count.
PIXEL
(mV)
2.5 < x ≤ 3.52525255.0 < x ≤ 7.525
x > 3.5000000x > 7.500
3.5 < x ≤ 73737377.5 < x ≤ 1537
x > 7000000x > 1500
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the substrate terminal.
Capacitive loadOUT1, OUT2, OUT36pF
Operating free-air temperature, T
‡
The algebraic convention, in which the least-positive (most negative) value is designated minimum, is used in this data sheet for clock voltage
levels.
§
Adjustment is required for optimal performance.
I
clock
ABG
IAG, SAG3.58
SRG1, SRG2, SRG3, TRG4.77
ABG2
A
Intermediate level
Low level–11–9
High level1.522.5
Low level–11–9
High level246
Intermediate level
Low level–7.5–7–6.5
High level1.522.5
Low level–11–9
High level1.522.5
Low level–11–9
§
§
–5.7
–2.3
MHz
–1045°C
†
2-10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TC245
Noi
786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
electrical characteristics over recommended operating range of supply voltage, TA = –10°C to 45°C
PARAMETERMINTYP
Dynamic range (see Note 2)Antiblooming disabled (see Note 3)6070dB
Charge conversion factor3.844.2µV/e
Charge transfer efficiency (see Note 4)0.99990 0.999951
Signal response delay time, τ (see Note 5 and Figure 13)182022ns
Gamma (see Note 6)0.970.980.99
Output resistance700800Ω
se voltage
Noise equivalent signal30electrons
Rejection ratio at 4.77 MHzSRG1, SRG2, SRG3 (see Note 8)40dB
Supply current5mA
Input capacitance, C
†
All typical values are at TA = 25 °C
NOTES: 2. Dynamic range is –20 times the logarithm of the mean noise signal divided by the saturation output signal.
3. For this test, the antiblooming gate must be biased at the intermediate level.
4. Charge transfer efficiency is one minus the charge loss per transfer in the output register. The test is performed in the dark using
an electrical input signal.
5. Signal-response delay time is the time between the falling edge of the SRG clock pulse and the output signal valid state.
6. Gamma (γ) is the value of the exponent in the equation below for two points on the linear portion of the transfer function curve (this
value represents points near saturation):
7. ADB rejection ratio is –20 times the logarithm of the ac amplitude at the output divided by the ac amplitude at ADB.
8. SRGn rejection ratio is –20 times the logarithm of the ac amplitude at the output divided by the ac amplitude at SRGn.
9. ABG rejection ratio is –20 times the logarithm of the ac amplitude at the output divided by the ac amplitude at ABG.
i
1/f noise (5 kHz)0.1
Random noise (f = 100 kHz)0.08
optical characteristics, TA = 40°C, integration time = 16.67 ms (unless otherwise noted)
PARAMETERMINTYPMAXUNIT
ens
y
Saturation signal, V
Maximum usable signal, V
ooming overload ratio (see Note
Image-area well capacity80 x 10
Smear (see Note 14)See Note 150.0004
Dark currentInterlace offTA = 21°C0.027nA/cm
gnal (see Note
uniformity
umn uniformity
ShadingOutput signal = 100 mV15%
NOTES: 10. Sensitivity is measured at an integration time of 16.67 ms with a source temperature of 2856 K. A CM-500 filter is used.
11. VU is the output voltage that represents the threshold of operation of antiblooming. VU ≈ 1/2 saturation signal.
12. Saturation is the condition in which further increase in exposure does not lead to further increase in output signal.
13. Blooming overload ratio is the ratio of blooming exposure to saturation exposure.
14. Smear is a measure of the error induced by transferring charge through an illuminated pixel in shutterless operation. It is equivalent
to the ratio of the single-pixel transfer time during a fast dump to the exposure time using an illuminated section that is 1/10 of the
image- area vertical height with recommended clock frequencies.
15. Exposure time is 16.67 ms, the fast-dump clocking rate during vertical timing is 3.58 MHz, and the illuminated section is 1/10 of the
height of the image section.
16. Dark-signal level is measured from the dummy pixels.
(see Note 12) Antiblooming disabled, interlace off320mV
SN28835FS44 pin flatpackT iming generatorNTSC timing generator (CCD, S/H, processing)
SN28846DW20 pin small outlineSerial driverDriver for TRG, SRG1, SRG2, SRG3
TMS3473BDW20 pin small outlineParallel driverDriver for IAG, SAG, ABG
TL1593CNS16 pin small outline (EIAJ)Sample and holdThree-channel sample-and-hold IC
Figure 15. Typical Application Circuit Diagram
2-16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TC245
786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
MECHANICAL DAT A
The package for the TC245 consists of a ceramic base, a glass window, and a 20-lead frame. The glass window is
sealed to the package by an epoxy adhesive. The package leads are configured in a dual in-line organization and
fit into mounting holes with 1,78 mm (0.070 in) center-to-center spacings.
TC245 (20 pin)
Index
Mark
6,50 (0.256)
6,10 (0.240)
Optical
Center
Package
Center
Focus
Plane
7,60 (0.299)
7,20 (0.283)
Rotation ±90°
15,14 (0.596)
14,84(0.584)
13,87 (0.546)
13,67 (0.538)
18,30 (0.720)
MAX
15,64 (0.616)
15,44 (0.608)
1,78 (0.070)
0,76 (0.030)
3,38(0.133)
2,72 (0.107)
4,01 (0.158) MAX
1,91 (0.075)
1,65 (0.065)
0,51 (0.020)
0,41 (0.016)
5,50 (0.217)
3,90 (0.154)
1,70 (0.067)
1,10 (0.043)
15,54 (0.612)
14,94 (0.588)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. The center of the package and the center of image area not coincident.
B. The distance from the top of the glass to the image sensor surface is typically 1 mm (0.04 inch). The glass is 0.95 ±0.08 mm thick
and has an index of refraction of 1.53.
C. Each pin centerline is located within 0.18 mm of its true longitudinal position.
D. Maximum rotation of the sensor within the package is 1.5°.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0,33 (0.013)
0,17 (0.007)
7/94
2-17
SOCS019A – DECEMBER 1991
2-18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer . Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright 1995, Texas Instruments Incorporated
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