TEXAS INSTRUMENTS TC245 Technical data

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TC245
786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
High-Resolution, Solid-State Image Sensor
8-mm Image-Area Diagonal, Compatible
With 1/2” Vidicon Optics
755 (H) x 242 (V) Active Elements in
Image-Sensing Area
Advanced On-Chip Signal Processing
Low Dark Current
Electron-Hole Recombination Antiblooming
Dynamic Range . . . More Than 70 dB
High Sensitivity
SUB 1
IAG 2 ABG 3 ADB 4
OUT3 5 OUT2 6 OUT1 7
AMP GND 8
CDB 9 SUB 10
DUAL-IN-LINE PACKAGE
(TOP VIEW)
High Photoresponse Uniformity
High Blue Response
NC – No internal connection
Single-Phase Clocking
Solid-State Reliability With No Image
Burn-in, Residual Imaging, Image Distortion, Image Lag, or Microphonics
description
The TC245 is a frame-transfer charge-coupled device (CCD) image sensor designed for use in single-chip B/W NTSC TV applications. The device is intended to replace a 1/2-inch vidicon tube in applications requiring small size, high reliability, and low cost.
20 SUB 19 IAG 18 ABG 17 SAG 16 SRG3 15 SRG2 14 SRG1 13 NC 12 TRG 11 IDB
The image-sensing area of the TC245 is configured into 242 lines with 786 elements in each line. Twenty-nine elements are provided in each line for dark reference. The blooming-protection feature of the sensor is based on recombining excess charge with charge of opposite polarity in the substrate. This antiblooming is activated by supplying clocking pulses to the antiblooming gate, which is an integral part of each image-sensing element. The sensor is designed to operate in an interlace mode, electronically displacing the image-sensing elements in alternate fields by one-half of a vertical line during the charge integration period, effectively increasing the vertical resolution and minimizing aliasing. The device can also be operated as a 755 (H) by 242 (V) noninterlaced sensor with significant reduction in the dark signal.
A gated floating-diffusion detection structure with an automatic reset and voltage reference incorporated on-chip converts charge to signal voltage. The signal is further processed by a low-noise, state-of-the-art correlated clamp-sample-and-hold circuit. A low-noise, two-stage, source-follower amplifier buffers the output and provides high output-drive capability . The image is read out through three outputs, each of which reads out every third image column.
The TC245 is built using TI-proprietary virtual-phase technology, which provides devices with high blue response, low dark signal, good uniformity , and single-phase clocking. The TC245 is characterized for operation from –10°C to 45°C.
This MOS device contains limited built-in gate protection. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to SUB. Under no circumstances should pin voltages exceed absolute maximum ratings. Avoid shorting OUTn to ADB during operation to prevent
allowed to flow. Specific guidelines for handling devices of this type are contained in the publication
Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies
damage to the amplifier. The device can also be damaged if the output terminals are reverse-biased and an excessive current is
Guidelines for Handling
available from Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 1991, Texas Instruments Incorporated
2-1
TC245 786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
functional block diagram
2
IAG
ADB
3
4
Amplifiers
ABG
Top Drain
Image Area With
Blooming Protection
Dark Reference Elements
Storage Area
19
18
17
IAG
ABG
SAG
OUT3
OUT2
OUT1
11 Dummy
Elements
5
IDB
6
7
8
AMP GND CDB
Multiplexer, Transfer
Gates, and Serial Registers
Clearing Drain
9
11
16 15 14
12
detailed description
The TC245 consists of four basic functional blocks: (1) the image-sensing area, (2) the image-storage area, (3) the multiplexer block with serial registers and transfer gates, and (4) the low-noise signal-processing amplifier block with charge-detection nodes. The location of each of these blocks is identified in the functional block diagram.
SRG3 SRG2 SRG1
TRG
2-2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
sensor topology diagram
I/O
DESCRIPTION
TC245
786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
244 755 + 1/2 + 1/2
1
1/2
Reverse Transfer Reverse Transfer
11 11
11.5
Dummy Pixels OPB
Effective Imaging Area
2 Lines
252 252
251 + 1/2 + 1/2
Terminal Functions
PIN
NAME NO.
ABG
ABG
ADB 4 I Supply voltage for amplifier drain bias
AMP GND 8 Amplifier ground
CDB 9 I Supply voltage for clearing drain bias
IAG
IAG
IDB 11 I Supply voltage for input diode bias OUT1 7 O Output signal 1 OUT2 6 O Output signal 2 OUT3 5 O Output signal 3
SAG 17 I Storage-area gate SRG1 14 I Serial-register gate 1 SRG2 15 I Serial-register gate 2 SRG3 16 I Serial-register gate 3
SUB
SUB
SUB
TRG 12 I Transfer gate
All pins of the same name should be connected together externally.
3 I Antiblooming gate
18 I Antiblooming gate
2 I Image-area gate
19 I Image-area gate
1 Substrate and clock return 10 Substrate and clock return 20 Substrate and clock return
1
29 + 1/2
10 10
9.5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
2-3
TC245 786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
image-sensing and storage areas
Figure 1 and Figure 2 show cross sections with potential well diagrams and top views of image-sensing and storage-area elements. As light enters the silicon in the image-sensing area, free electrons are generated and collected in the potential wells of the sensing elements. During this time, blooming protection is activated by applying a burst of pulses to the antiblooming gate inputs every horizontal blanking interval. This prevents blooming caused by the spilling of charge from overexposed elements into neighboring elements. After integration is complete, the signal charge is transferred into the storage area.
There are 29 full columns and one half-column of elements at the right edge of the image-sensing area that are shielded from incident light; these elements provide the dark reference used in subsequent video processing circuits to restore the video black level. There are also one full column and one half-column of light-shielded elements at the left edge of the image-sensing area and two lines of light-shielded elements between the image-sensing and image-storage areas (the latter prevent charge leakage from the image-sensing area into the image-storage area).
multiplexer with transfer gates and serial registers
The multiplexer and transfer gates transfer charge line by line from the storage-area columns into the corresponding serial registers and prepare it for readout. Figure 3 illustrates the layout of the multiplexing gate that vertically separates the pixels for input into the serial registers. Figure 4 shows the layout of the interface region between the serial-register gates and the transfer gates. Multiplexing is activated during the horizontal blanking interval by applying appropriate pulses to the transfer gates and serial registers; the required pulse timing is shown in Figure 5. A drain is also included to provide the capability to clear the image-sensing and storage areas of unwanted charge. Such charge can accumulate in the imager during the start-up of operation or under special circumstances when nonstandard TV operation is desired.
correlated clamp-sample-and-hold amplifier with charge-detection nodes
Figure 6 illustrates the correlated clamp-sample-and-hold amplifier circuit. Charge is converted into a video signal by transferring the charge onto a floating diffusion structure in detection node1 that is connected to the gate of MOS transistor Q1. The proportional charge-induced signal is then processed by the circuit shown in Figure 6. This circuit consists of a low-pass filter formed by Q1 and C2, coupling capacitor C1, dummy detection node 2, which restores the dc bias on the gate of Q3, sampling transistor Q5, holding capacitor C3, and output buffer Q6. Transistors Q2, Q4, and Q7 are current sources for each corresponding stage of the amplifier. The parameters of this high-performance signal-processing amplifier have been optimized to minimize noise and maximize the video signal.
The signal processing begins with a reset of detection node 1 and restoration of the dc bias on the gate of Q3 through the clamping function of dummy detection node 2. After the clamping is completed, the new charge packet is transferred onto detection node 1. The resulting signal is sampled by the sampling transistor Q5 and is stored on the holding capacitor C3. This process is repeated periodically and is correlated to the charge transfer in the registers. The correlation is achieved automatically since the same clock lines used in registers φ-S2 and φ-S3 for charge transport serve for reset and sample. The multiple use of the clock lines significantly reduces the number of signals required to operate the sensor. The amplifier also contains an internal voltage reference generator that provides the reference bias for the reset and clamp transistors. The detection nodes and the corresponding amplifiers are located some distance away from the edge of the storage area. Therefore, eleven dummy elements are incorporated at the end of each serial register to span the distance. The location of the dummy elements, which are considered to be part of the amplifiers, is shown in the functional block diagram.
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TC245
786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
19.75 µm(V)
8.5 µm(H)
Clocked Barrier
Virtual Barrier Antiblooming Gate
Virtual Well
Clocked Well
Antiblooming
Clocking Levels
Accumulated Charge
Figure 1. Charge-Accumulation Process
φ-PS
Clocked Phase
Virtual Phase
φ-IAG
Light
φ-ABG
Channel Stops
Figure 2. Charge-Transfer Process
Channel Stops
Virtual Well
Clocked Well
Channel Stop
Multiplexing Gate
Clocked
Wells
Serial-Register Gate
Transfer Gate
Figure 3. Multiplexing-Gate Layout Figure 4. Interface-Region Layout
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
2-5
TC245 786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
Composite
Blanking
ABG
IAG
SAG
TRG
SRG 1
SRG2
SRG3
Blanking Interval
Expanded
Horizontal
Figure 5. Timing Diagram
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Reference Generator
Detection Node 1
CCD Register
Gate
Virtual
Gate
Clocked
TC245
786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
ADB
Reset Gate
and
Output
Diode
Detection
Node 2
SRG1
Q1
C1
Q2
SRG2 SRG3
C2
Q3
Q5
Q4
Figure 6. Correlated Clamp-Sample-and-Hold Amplifier Circuit Diagram
C3
Q7
Q6
V
O
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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TC245 786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
spurious nonuniformity specification
The spurious nonuniformity specification of the TC245 CCD grades –10, –20, –30, and –40 is based on several sensor characteristics:
Amplitude of the nonuniform pixel
Polarity of the nonuniform pixel
Black – White
Location of the nonuniformity (see Figure 7)
Area A
Element columns near horizontal center of the area – Element rows near vertical center of the area
Area B
Up to the pixel or line border – Up to area A
Other
Edge of the imager – Up to area B
Nonuniform pixel count
Distance between nonuniform pixels
Column amplitude
The CCD sensors are characterized in both an illuminated condition and a dark condition. In the dark condition, the nonuniformity is specified in terms of absolute amplitude as shown in Figure 8. In the illuminated condition, the nonuniformity is specified as a percentage of the total illumination as shown in Figure 9.
11
Lines
377
Pixels
233
Lines
20 Pixels
Figure 7. Sensor Area Map
18 Pixels
7
Lines
BA
2-8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
mV
DISTANCE
NUMBER
AMPLITUDE
AREA A
AREA B
COUNT‡
(mV)
TC245-30
12
10080A
TC245-40
15
PART
NUMBER
(mV)
AREAS
AREAS
TC245
786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
Amplitude
t
% of Total
Illumination
Figure 8. Pixel Nonuniformity, Figure 9. Pixel Nonuniformity,
Dark Condition Illuminated Condition
The grade specification for the TC245 is as follows (CCD video-output signal is 50 mV ±10 mV): Pixel nonuniformity:
DARK CONDITION ILLUMINATED CONDITION
PART
TC245-20 x > 3.5 0 0 0 0 0 0 x > 5 0 0
-
White and black nonuniform pixel pair
The total spot count is the sum of all nonuniform white, black, and white/black pairs in the dark condition added to the number of nonuniform black pixels in the illuminated condition. The sum of all nonuniform combinations will not exceed the total count.
PIXEL
(mV)
2.5 < x 3.5 2 5 2 5 2 5 5.0 < x 7.5 2 5 x > 3.5 0 0 0 0 0 0 x > 7.5 0 0
3.5 < x 7 3 7 3 7 3 7 7.5 < x 15 3 7 x > 7 0 0 0 0 0 0 x > 15 0 0
NONUNIFORM PIXEL TYPE WHITE BLACK W/B
, x
AREA AREA AREA
A B A B A B
% OF TOTAL
ILLUMINATION
TOTAL
DISTANCE
SEPARATION
X Y AREA
t
Column nonuniformity:
PART
NUMBER
TC245-20 x > 0.3 0 0 TC245-30 x > 0.5 0 0 TC245-40 x > 0.7 0 0
COLUMN
AMPLITUDE, x
WHITE BLACK
AREAS AREAS
A AND B
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A AND B
2-9
TC245
SRG1, SRG2, SRG3
V
SAG
TRG
qy
clock
786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range for ADB, CDB, IDB (see Note 1) 0 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range for ABG, IAG, SAG, SRG, TRG –15 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
–30°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
Storage temperature range –30°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the substrate terminal.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, ADB 11 12 13 V Substrate bias voltage 0 V
High level 1.5 2 2.5
IAG
Input voltage, V
Clock frequency, f
Capacitive load OUT1, OUT2, OUT3 6 pF Operating free-air temperature, T
The algebraic convention, in which the least-positive (most negative) value is designated minimum, is used in this data sheet for clock voltage levels.
§
Adjustment is required for optimal performance.
I
clock
ABG
IAG, SAG 3.58 SRG1, SRG2, SRG3, TRG 4.77 ABG 2
A
Intermediate level Low level –11 –9 High level 1.5 2 2.5 Low level –11 –9 High level 2 4 6 Intermediate level Low level –7.5 –7 –6.5 High level 1.5 2 2.5 Low level –11 –9 High level 1.5 2 2.5 Low level –11 –9
§
§
–5.7
–2.3
MHz
–10 45 °C
2-10
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TC245
Noi
786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
electrical characteristics over recommended operating range of supply voltage, TA = –10°C to 45°C
PARAMETER MIN TYP
Dynamic range (see Note 2) Antiblooming disabled (see Note 3) 60 70 dB Charge conversion factor 3.8 4 4.2 µV/e Charge transfer efficiency (see Note 4) 0.99990 0.99995 1 Signal response delay time, τ (see Note 5 and Figure 13) 18 20 22 ns Gamma (see Note 6) 0.97 0.98 0.99 Output resistance 700 800
se voltage
Noise equivalent signal 30 electrons
Rejection ratio at 4.77 MHz SRG1, SRG2, SRG3 (see Note 8) 40 dB
Supply current 5 mA
Input capacitance, C
All typical values are at TA = 25 °C
NOTES: 2. Dynamic range is –20 times the logarithm of the mean noise signal divided by the saturation output signal.
3. For this test, the antiblooming gate must be biased at the intermediate level.
4. Charge transfer efficiency is one minus the charge loss per transfer in the output register. The test is performed in the dark using an electrical input signal.
5. Signal-response delay time is the time between the falling edge of the SRG clock pulse and the output signal valid state.
6. Gamma (γ) is the value of the exponent in the equation below for two points on the linear portion of the transfer function curve (this value represents points near saturation):
7. ADB rejection ratio is –20 times the logarithm of the ac amplitude at the output divided by the ac amplitude at ADB.
8. SRGn rejection ratio is –20 times the logarithm of the ac amplitude at the output divided by the ac amplitude at SRGn.
9. ABG rejection ratio is –20 times the logarithm of the ac amplitude at the output divided by the ac amplitude at ABG.
i
1/f noise (5 kHz) 0.1 Random noise (f = 100 kHz) 0.08
ADB (see Note 7) 20
ABG (see Note 9) 20
IAG 6500 SRG1, SRG2, SRG3 68 ABG 2400 pF TRG 180 SAG 6800
Exposure (2)
ǒ
Exposure (1)
g
Ǔ
Output signal (2)
ǒ
+
Output signal (1)
Ǔ
MAX UNIT
µV/Hz
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2-11
TC245
S
itivit
Measured at V
U
V/l
Bl
13)
Dark si
16)
T
45°C
V
Pixel
Output si
±10 mV
V
Col
Output si
±10 mV
V
786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
optical characteristics, TA = 40°C, integration time = 16.67 ms (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
ens
y
Saturation signal, V Maximum usable signal, V
ooming overload ratio (see Note
Image-area well capacity 80 x 10 Smear (see Note 14) See Note 15 0.0004 Dark current Interlace off TA = 21°C 0.027 nA/cm
gnal (see Note
uniformity
umn uniformity
Shading Output signal = 100 mV 15%
NOTES: 10. Sensitivity is measured at an integration time of 16.67 ms with a source temperature of 2856 K. A CM-500 filter is used.
11. VU is the output voltage that represents the threshold of operation of antiblooming. VU 1/2 saturation signal.
12. Saturation is the condition in which further increase in exposure does not lead to further increase in output signal.
13. Blooming overload ratio is the ratio of blooming exposure to saturation exposure.
14. Smear is a measure of the error induced by transferring charge through an illuminated pixel in shutterless operation. It is equivalent to the ratio of the single-pixel transfer time during a fast dump to the exposure time using an illuminated section that is 1/10 of the image- area vertical height with recommended clock frequencies.
15. Exposure time is 16.67 ms, the fast-dump clocking rate during vertical timing is 3.58 MHz, and the illuminated section is 1/10 of the height of the image section.
16. Dark-signal level is measured from the dummy pixels.
(see Note 12) Antiblooming disabled, interlace off 320 mV
sat
use
No IR Filter With IR Filter
Antiblooming enabled, interlace on 180 mV
°
=
A
gnal = 50 mV
gnal = 50 mV
Measured at V (see Notes 10 and 11)
Interlace on 100 Interlace off 200
TC245-30 5.5 TC245-40 6 TC245-30 3.5 TC245-40 5 TC245-30 0.5 TC245-40 0.7
U
197
24
m
3
electrons
x
2
m
m
m
2-12
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
786- × 488-PIXEL CCD IMAGE SENSOR
PARAMETER MEASUREMENT INFORMATION
TC245
SOCS019A – DECEMBER 1991
V
O
V
sat (min)
V
use (max)
V
use (typ)
V
n
DR (dynamic range) Vn = noise floor voltage
V
sat (min)
V
use (max)
V
use (typ)
NOTES: A. V
= minimum saturation voltage
= maximum usable voltage
= typical user voltage (camera white clip)
use (typ)
B. A system trade-off is necessary to determine the system light sensitivity versus the signal/noise ratio. By lowering the V
the light sensitivity of the camera is increased; however, this sacrifices the signal/noise ratio of the camera.
Blooming Point With Antiblooming
Blooming Point With Antiblooming Disabled
Level Dependent
Upon Antiblooming
Gate High Level
DR
camera white clip voltage
+
is defined as the voltage determined to equal the camera white clip. This voltage must be less than V
V
n
Enabled
Dependent On
Well Capacity
Lux (light input)
use (max)
use (typ)
.
,
Figure 10. Typical V
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
sat
, V
Relationship
use
2-13
TC245 786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
PARAMETER MEASUREMENT INFORMATION
VIH min
Intermediate Level
VIL max
Slew rate between 10% and 90% = 70 to 120 V/µs, tr = 150 ns, tf = 90 ns.
100%
90%
10%
0%
t
r
Figure 11. Typical Clock Waveform for IAG, ABG and SAG
VIH min
VIL max
100%
90%
10%
0%
t
r
t
f
t
f
Slew rate between 10% and 90% = 300 V/µs, tr = tf = 15 ns.
Figure 12. Typical Clock Waveform for SRG and TRG
SRG
OUT
90%
100%
CCD Delay
Sample
and
Hold
– 9 V
τ
Figure 13. SRG and CCD Output Waveforms
1.5 V to 2.5 V
– 9 V to –11 V
0%
15 ns10 ns
2-14
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
CCD SPECTRAL RESPONSIVITY
1
TC245
786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
100 60
50 40 30
20
0.1
0.01
Responsivity – A/W
0.001
V
= 12 V, TA = 25°C
ADB
No IR Filter Light Power = 1.5 µW/cm Light Box: Canon SA702
400 500 600 1000 1100
300
Incident Wavelength – nm
700 800 900
Figure 14
10
5 3
2
Quantum Efficiency – %
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
2-15
TC245 786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
APPLICATION INFORMATION
IALVL
V
ABG+
V
SS
TMS3473B
1
IALVL
2
I/N
3 4 5 6 7 8
9
10
1 2 3 4 5 6 7 8
9
10
IAIN ABIN MIDSEL
SAIN PD GND V V
SEL0OUT GND PD SRG3IN SRG2IN SRG1IN TRGIN NC SEL1OUT
ABG+
SS
Parallel Driver
SN28846
SRG3OUT SRG2OUT
SRG1OUT
SS
Serial Driver
ABSR
ABLVL
IAOUT ABOUT SAOUT
V
TRGOUT
V
IASR
V
V
ABG–
SEL0
V
SEL1V
V
20
SS
19
22 k
ABLVL
V
ABG –
20 pF
47 k
TC245
20
SUB
19
IAG
18
ABG
17
SAG
16
SRG3
15
SRG2
14
SEG1
13
NC
12
TRG
11
IDB
V
CC
23
T
24
S1
25
S2
26
S3
27
PD
28
PS
29
GT
30
ABIN
31
PI
32
MODE
33
GND
AMP GND
Image Sensor
VCC
HGATE
CLK2M
SH1
X2
X1
SUB
IAG ABG ADB
OUT3 OUT2 OUT1
CDB SUB
VGATE
NTSC Timer
GT3/SH2
18 17
CC
16 15 14 13 12
CC
11
20
V
SS
19 18
NC
17
V
CC
16 15 14 13 12
CC
11
1 2 3 4 5 6 7 8 9 10
VD2
WHTA
SN28835
GT2
GT1/SH3
VD
VCR
ADB
VCCV
GP
HCR
4.7 µF
4.7 µF
SB
VDS
4.7 µF
+
+
GPS
E/L
4.7 µF
+
+
CC
SC(90)
CSYNC
1213141516171819202122
HIGH ABS1
ABS0
CBLK
CP1 CP2
BCP2 BCP1
FI
4443424140393837363534
SC BF
100
100
100
1
ANLG V
2
AIN1
3
CIN1
4
AIN2
5
CIN2
6
AIN3
7
CIN3
8
ANLG GND
11 10
V
CC
9 8 7 6 5 4 3 2 1
DC VOLTAGES
ADB V
CC
V
SS
V ABLVL IALVL V
ABG+
V
ABG–
TL1593
CC
DIG V
DGTL GND
Sample-and-Hold
S/H1 S/H2 S/H
OUT1 OUT2
OUT3
CC
3
12 V
5 V
–10 V
2 V
–2.5 V
–5 V
4 V
–6 V
16 15 14 13 12 OUT3 11 OUT2 10 OUT1
9
Oscillator
14.3-MHz
15 pF
SUPPORT CIRCUITS
DEVICE PACKAGE APPLICATION FUNCTION
SN28835FS 44 pin flatpack T iming generator NTSC timing generator (CCD, S/H, processing) SN28846DW 20 pin small outline Serial driver Driver for TRG, SRG1, SRG2, SRG3 TMS3473BDW 20 pin small outline Parallel driver Driver for IAG, SAG, ABG TL1593CNS 16 pin small outline (EIAJ) Sample and hold Three-channel sample-and-hold IC
Figure 15. Typical Application Circuit Diagram
2-16
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TC245
786- × 488-PIXEL CCD IMAGE SENSOR
SOCS019A – DECEMBER 1991
MECHANICAL DAT A
The package for the TC245 consists of a ceramic base, a glass window, and a 20-lead frame. The glass window is sealed to the package by an epoxy adhesive. The package leads are configured in a dual in-line organization and fit into mounting holes with 1,78 mm (0.070 in) center-to-center spacings.
TC245 (20 pin)
Index Mark
6,50 (0.256) 6,10 (0.240)
Optical
Center
Package
Center
Focus Plane
7,60 (0.299) 7,20 (0.283)
Rotation ±90°
15,14 (0.596)
14,84(0.584)
13,87 (0.546) 13,67 (0.538)
18,30 (0.720)
MAX
15,64 (0.616) 15,44 (0.608)
1,78 (0.070) 0,76 (0.030)
3,38(0.133)
2,72 (0.107)
4,01 (0.158) MAX
1,91 (0.075) 1,65 (0.065)
0,51 (0.020) 0,41 (0.016)
5,50 (0.217) 3,90 (0.154)
1,70 (0.067) 1,10 (0.043)
15,54 (0.612) 14,94 (0.588)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. The center of the package and the center of image area not coincident.
B. The distance from the top of the glass to the image sensor surface is typically 1 mm (0.04 inch). The glass is 0.95 ±0.08 mm thick
and has an index of refraction of 1.53. C. Each pin centerline is located within 0.18 mm of its true longitudinal position. D. Maximum rotation of the sensor within the package is 1.5°.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
0,33 (0.013) 0,17 (0.007)
7/94
2-17
SOCS019A – DECEMBER 1991
2-18
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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