TEXAS INSTRUMENTS TB5R3 Technical data

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AIAI

D1D1

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

AI AI

BI BI

GND

VCC DI DI DO E2 CO CI CI

SOIC PACKAGE

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TB5R3

SLLS643 – SEPTEMBER 2005

QUAD DIFFERENTIAL PECL RECEIVERS

FEATURES DESCRIPTION

• Functional Replacement for the Agere BRF1A

• Pin Equivalent to General Trade 26LS32

• High Input Impedance Approximately 8 k Ω

• <2.6-ns Maximum Propagation Delay

• TB5R3 Provides 50-mV Hysteresis (Typical)

• -1.1-V to 7.1-V Common-Mode Input Voltage

Range

• Single 5-V ± 10% Supply

• ESD Protection HBM > 3 kV and CDM > 2 kV

• Operating Temperature Range: -40 ° C to 85 ° C

• Available in Gull-Wing SOIC (JEDEC MS-013, The packaging for this differential line receiver is a

DW) and SOIC (D) Package

APPLICATIONS

• Digital Data or Clock Transmission Over Bal-

anced Lines

These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels.

The TB5R3 is a pin- and function-compatible replacement for the Agere systems BRF1A; it includes 3-kV HBM and 2-kV CDM ESD protection.

The power-down loading characteristics of the receiver input circuit are approximately 8 k Ω relative to the power supplies; hence they do not load the transmission line when the circuit is powered down.

16-pin gull wing SOIC (DW) or a 16 pin SOIC (D). The enable inputs of this device include internal

pull-up resistors of approximately 40 k Ω that are connected to V

to ensure a logical high level input

if the inputs are open circuited.

PIN ASSIGNMENTS

FUNCTIONAL BLOCK DIAGRAM

Enable Truth Table

E1 E2

0 0 Active 1 0 Active 0 1 Disabled 1 1 Active

OUTPUT

CONDITION

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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TB5R3

SLLS643 – SEPTEMBER 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PART NUMBER

TB5R3DW TB5R3 Gull-Wing SOIC NiPdAu Production

TB5R3LDW TB5R3L Gull-Wing SOIC SnPb Production

TB5R3D TB5R3 SOIC NiPdAu Production

TB5R3LD TB5R3L SOIC SnPb Production

(1) Add the R suffix for tape and reel carrier (i.e., TB5R3DR)

POWER DISSIPATION RATINGS

PACKAGE JUNCTION-TO-AMBIENT TOR

(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow. (2) In accordance with the low-K thermal metric definitions of EIA/JESD51-3. (3) In accordance with the high-K thermal metric definitions of EIA/JESD51-7.

(1)

CIRCUIT BOARD POWER RATING POWER RATING

MODEL TA≤ 25 ° C TA= 85 ° C

Low-K

High-K

Low-K

High-K

PART MARKING Package LEAD FINISH STATUS

THERMAL RESISTANCE, DERATING FAC-

WITH NO AIR FLOW TA≥ 25 ° C

(2)

(3)

(2)

(3)

831 mW 120.3 ° C/W 8.3 mW/ ° C 332 mW

1240 mW 80.8 ° C/W 12.4 mW/ ° C 494 mW

763 mW 131.1 ° C/W 7.6 mW/ ° C 305 mW

1190 mW 84.1 ° C/W 11.9 mW/ ° C 475 mW

(1)

THERMAL CHARACTERISTICS

PARAMETER PACKAGE VALUE UNIT

Junction-to-Board

Thermal Resistance

Junction-to-Case

Thermal Resistance

DW 53.7

D 47.5

DW 47.1

D 44.2

° C/W

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

Supply voltage, V Magnitude of differential bus (input) voltage, |V

ESD

Continuous power dissipation See Dissipation Rating Table Storage temperature, T

(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (3) Tested in accordance with JEDEC Standard 22, Test Method C101.

Human Body Model Charged-Device Model

stg

- VAI|, |V

(2)

All pins ± 3.5 kV

(3)

All pins ± 2 kV

- VBI|, |V

(1)

UNIT

0 V to 6 V

- VCI|, |V

- VDI| 8.4 V

-65 ° C to 150 ° C

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SLLS643 – SEPTEMBER 2005

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

Supply voltage, V

Bus pin input voltage, VAI, VAI, VBIVBI, VCI, or VCI, VDI, V Magnitude of differential input voltage, |V Low-level enable input voltage High-level enable input voltage Operating free-air temperature, T

(2)

, VIL(V

(2)

, VIH(V

- VAI|, |V

= 5.5 V) 0.8 V

= 5.5 V) 2 V

- VBI|, |V

- VCI|, |V

- VDI| 0.1 6 V

4.5 5 5.5 V

(1)

-1.2

-40 85 ° C

(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless

otherwise noted. (2) The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment.

DEVICE ELECTRICAL CHARACTERISTICS

over operating free-air temperature range unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Supply current

(1)

(1) Current is dc power draw as measured through GND pin and does not include power delivered to load.

Outputs disabled 50 mA Outputs enabled 48 mA

TB5R3

7.2 V

RECEIVER ELECTRICAL CHARACTERISTICS

over operating free-air temperature range unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V V V V

V V

I I

(1) This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original (2) The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment.

Output low voltage V

Output high voltage V

Enable input clamp voltage V

Positive-going differential input threshold voltage

TH+

Negative-going differential input threshold voltage

TH-

Differential input threshold voltage hysteresis, (V

HYST

OZL

Output off-state current, (High-Z) V

OZH

Output short circuit current V

Enable input low current V

(2)

, (V

- VxI) x = A, B, C, or D 100 mV

(2)

, (V

- VxI) x = A, B, C, or D mV

- V

TH+

) 50 mV

TH_

Enable input high current VIN= 2.7 V 20 µA

Enable input reverse current VIN= 5.5 V 100 µA Differential input low current V

Differential input high current VCC= 5.5V, VIN= 7.2 V 1 mA

Small-signal output resistance Ω

= 4.5 V, IOL= 8 mA 0.4 V

= 4.5 V, IOH= -400 µA 2.4 V

= 4.5 V, II= -5 mA -1

= 5.5 V

= 5.5 V mA

= 5.5 V, VIN= 0.4 V µA

= 5.5 V

= 5.5V, VIN= -1.2 V -2

VO= 0.4 V -20 VO= 2.4 V 20 µA

Output High 50 Output Low 25

Agere data sheet.

(1)

100

(1)

µA

(1)

400

(1)

400

(1)

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OUTPUT

3.7 V

2.7 V

3.2 V

VOL

1.5 V

THL

PHL

PLH

TLH

20%

80%

20%

80%

INPUT

See Note A See Note A

80% 80% 20% 20%

TB5R3

SLLS643 – SEPTEMBER 2005

SWITCHING CHARACTERISTICS

over operating free-air temperature range unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PLH

PHL

PLH

PHL

PHZ

PLZ

skew1

∆ t

-p

∆ t t

PZH

PZL

TLH

THL

Propagation delay time, low-to-high-level output 1.64 <2.6 Propagation delay time, high-to-low-level output 1.57 <2.6 Propagation delay time, low-to-high-level output 2.2 3.5 Propagation delay time, high-to-low-level output 2.1 3.5 Output disable time, high-level-to-high-impedance

(3)

output Output disable time, low-level-to-high-impedance

(3)

output

Pulse-width distortion, |t

skew1p

Part-to-part output waveform skew

Same part output waveform skew CL= 10 pF, See Figure 2 and Figure 4 0.3 ns

skew

Output enable time, high-impedance-to-high-level

(3)

output Output enable time, high-impedance-to-low-level

(3)

output

- t

PHL

PLH

Rise time (20%-80%) 1 ns Fall time (80%-20%) 1 ns

CL= 0 pF

CL= 50 pF, See Figure 2 and Figure 4

(1)

, See Figure 2 and Figure 4 ns

(2)

7.7 12 ns

CL= 5 pF, See Figure 3 and Figure 5

5.2 12 ns

CL= 10 pF, See Figure 2 and Figure 4 0.7 ns CL= 150 pF, See Figure 2 and Figure 4 4 ns CL= 10 pF, TA= 75 ° C, See Figure 2 and

Figure 4

0.8 1.4 ns

CL= 10 pF, See Figure 2 and Figure 4 1.5 ns

6.9 12 ns

CL= 10 pF, See Figure 3 and Figure 4

6.3 12 ns

CL= 10 pF, See Figure 2 and Figure 4

(1) The propagation delay values with a 0 pF load are based on design and simulation. (2) tr/tf: 3 ns (20% - 80%) (3) See Table 1.

A. tr/tf: 3 ns (20% - 80%)

Figure 1. Receiver Propagation Delay Times

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