Texas Instruments TAS5782M Datasheet

Supply Voltage (V)

Output Power (W)

5 10 15 20 24

0

20

40

60

80

10 20

D002

8 : Load Peak 6 : Load Peak 4 : Load Peak 6 : Load Continous 4 : Load Continous

System

PP

CH2

CH1

Control and

Status

Digital Audio

I2C

TAS5782M

Power Bridge

DAC

PCDSP

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Technical Documents

Tools & Software

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SLASEG8A –MARCH 2016–REVISED JULY 2017

TAS5782M 30 W Stereo Class-D Amplifier with 96-kHz Processing

TAS5782M

1 Features

1

• Flexible Audio I/O Configuration – Supports I2S, TDM, LJ, RJ Digital Input – Sample Rate Support – BD Amplifier Modulation – Supports 3-Wire Digital Audio Interface (No

MCLK required)

• High-Performance Closed-Loop Architecture (PVDD = 12 V, R

– Closed-Loop = reduced component count/

smaller solution size – Idle Channel Noise = 62 µVrms (A-Wtd) – THD+N = 0.2% (at 1 W, 1 kHz) – SNR = 103dB A-Wtd (Ref. to THD+N = 1%)

• Flexible Processing Features – 15 BiQuads / SmartEQ – 2 x 5 BiQuads for X-Over / EQ – 3-Band Advanced DRC + AGL – Dynamic EQ and SmartBass – Sound Field Spatializer (SFS) – 96-kHz Processor Sampling

• Communication Features – Software Mode Control via I2C Port – Two Address Select Pins – Up to 4 Devices

• Robustness and Reliability Features – Clock Error , DC, and Short-Circuit Protection – Overtemperature and Overcurrent Protection

SPACE

Simplified Block Diagram

= 8 Ω, SPK_GAIN = 20 dB)

SPK

2 Applications

• LCD, LED TV, and Multi-Purpose Monitors

• Sound Bars, Docking Stations, and PC Audio

• Wireless Subwoofers, Bluetooth Speakers, and Active Speakers

3 Description

The TAS5782M device is a high-performance, stereo closed-loop Class-D amplifier with integrated audio processor with up to 96-kHz architecture. To convert from digital to analog, the device uses a high performance DAC with Burr Brown™ audio technology. It requires only two power supplies: one DVDD for low-voltage circuitry and one PVDD for high-voltage circuitry. It is controlled by a software control port using standard I2C communication.

An optimal mix of thermal performance and device cost is provided in the 90 mΩ r MOSFETs. Additionally, a thermally enhanced 48-Pin TSSOP provides excellent operation in the elevated ambient temperatures found in modern consumer electronic devices.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

TAS5782M TSSOP (48) 12.50 mm × 6.10 mm (1) For all available packages, see the orderable addendum at

the end of the data sheet.

Power at 10% THD+N vs PVDD

DS(on)

(1)

of the output

(1)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

(1) Tested on TAS5782MEVM Board.

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

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4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (March 2017) to Revision A Page

• Added missing cross references to the Quick Reference Table .......................................................................................... 24

• Changed Changed the Volume Ramp Up/Down Step default value to 11 .......................................................................... 50

• Changed 5th bit of the I2C Slave Address table .................................................................................................................. 54

• Added DSP Book, Page, and Register Update section ....................................................................................................... 56

• Deleted Page 0 Registers 0x0A, 0x50, 0x51, 0x52, and 0x54............................................................................................. 80

• Changed the PLLE bit type of Register 4 from R to R/W..................................................................................................... 81

• Changed Bit configuration of Register 0x14......................................................................................................................... 88

• Changed PJDV bit in Register 21 from 5-4 to 5-0................................................................................................................ 89

• Changed Reset value of Register 0x3D to '00110000'......................................................................................................... 98

• Changed Bit configuration of Register 0x5D ...................................................................................................................... 112

• Deleted Page 1 Registers 0x05 and 0x08.......................................................................................................................... 116

2

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5 Device Comparison Table

DEVICE NAME MODULATION STYLE PROCESSING TYPE

TAS5782MDCA BD Modulation

TAS5754MDCA 1SPW (Ternary)

TAS5756MDCA BD Modulation TAS5766MDCA BD Modulation 50 MIPs, Fixed-Function (Uses single ROM image of process flow)

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

100 MIPs, Flexible Process flow (Uses mixture of RAM and ROM

components to create several process flows)

50 MIPs, HybridFlow (Uses mixture of RAM and ROM components to

create several process flows)

50 MIPs, HybridFlow (Uses mixture of RAM and ROM components to

create several process flows)

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3

1

5

4

3

2

6

10

9

8

7

12

11

36

32

33

34

35

31

27

28

29

30

25

26

PowerPAD

TM

SPK_OUTA-

PGND

SPK_OUTA+

PVDD

SPK_GAIN/FSW

BSTRPA+

SPK_INA-

DVDD_REG

CN

GND

CPVSS

CP

SPK_OUTB+

CPVDD

DVDD

LRCLK/FS

DGND

ADR0

SPK_MUTE

14

13

16

15

18

17

20

19

22

21

24

23

48

44

45

46

47

43

39

40

41

42

37

38

PVDD

SPK_OUTB-

PGND

BSTRPB-

BSTRPB+

PVDD

SPK_FAULT

SPK_INB-

PVDD

SPK_INB+

DAC_OUTB

PGND

SPK_INA+

DAC_OUTA

AGND

SCL

RESET

ADR1

GPIO0

GPIO2

BSTRPA-

SDA

SCLK

SDIN

PVDD

AGND

AVDD

GVDD_REG

MCLK

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

6 Pin Configuration and Functions

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48-Pin TSSOP with PowerPAD™

DCA Package

Top View

4

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Pin Functions

NAME NO.

ADR0 26 DI ADR1 20 DI

AGND

AVDD 14 P Figure 2 Power supply for internal analog circuitry BSTRPA– 1 P

BSTRPA+ 5 P

BSTRPB– 48 P

BSTRPB+ 44 P CN 34 P Figure 14 Negative pin for capacitor connection used in the line-driver charge pump

CP 32 P Figure 13 Positive pin for capacitor connection used in the line-driver charge pump CPVDD 31 P Figure 2 Power supply for charge pump circuitry CPVSS 35 P Figure 14 –3.3-V supply generated by charge pump for the DAC DAC_OUTA 13 AO DAC_OUTB 36 AO Single-ended output for Channel B of the DAC DGND 29 G — Ground reference for digital circuitry. Connect this pin to the system ground. DVDD 30 P Figure 2 Power supply for the internal digital circuitry

DVDD_REG 28 P Figure 15

GND 33 G — Ground pin for device. This pin should be connected to the system ground. GPIO0 18 GPIO2 21

GVDD_REG 8 P Figure 5

LRCK/FS 25 DI/O

MCLK 22 DI Master clock used for internal clock tree and sub-circuit and state machine clocking

PGND

PVDD

RESET 19 DI Figure 17 Device reset input. Pull down to reset, pull up to activate device. SCL 17 DI Figure 10 SCLK 23 DI/O Figure 11 Bit clock for the digital signal that is active on the input data line of the serial data port SDA 16 DI/O Figure 9 SDIN 24 D1 Figure 11 Data line to the serial data port SPK_INA– 11 AI SPK_INA+ 12 AI Positive pin for differential speaker amplifier input A SPK_INB– 38 AI Negative pin for differential speaker amplifier input B SPK_INB+ 37 AI Positive pin for differential speaker amplifier input B

TYPE

10 15

3

46

6

7 41 42 43

G — Ground reference for analog circuitry

DI/O General purpose input/output pins (GPIOx). Refer to GPIO registers for configuration.

G — Ground reference for power device circuitry. Connect this pin to the system ground.39

P Figure 1 Power supply for internal power circuitry

(1)

TERMINATION

INTERNAL

Figure 3

Figure 8

Figure 11

Figure 7

DESCRIPTION

Sets the LSB of the I2C address to 0 if pulled to GND, to 1 if pulled to DVDD Sets the second LSB of the I2C address to 0 if pulled to GND, to 1 if pulled to DVDD

(2)

Connection point for the SPK_OUTA– bootstrap capacitor which is used to create a power supply for the high-side gate drive for SPK_OUTA–

Connection point for the SPK_OUTA+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for SPK_OUTA+

Connection point for the SPK_OUTB– bootstrap capacitor which is used to create a power supply for the high-side gate drive for SPK_OUTB–

Connection point for the SPK_OUTB+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for SPK_OUTB+

Single-ended output for Channel A of the DAC

Voltage regulator derived from DVDD supply for use for internal digital circuitry. This pin is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry.

Voltage regulator derived from PVDD supply to generate the voltage required for the gate drive of output MOSFETs. This pin is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry.

Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ, and RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync boundary.

I2C serial control port clock

I2C serial control port data

Negative pin for differential speaker amplifier input A

TAS5782M

(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P =

Power, G = Ground (0 V)

(2) This pin should be connected to the system ground.

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5

PVDD

SPK_OUTxx

GVDD

PVDD

SPK_OUTxx

BSTRPxx

7 V ESD

PVDD

30 V ESD

DVDD

3.3 V ESD

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

Pin Functions (continued)

NAME NO.

SPK_FAULT 40 DO Figure 16 Fault pin which is pulled low when an overcurrent, overtemperature, or DC detect fault occurs SPK_GAIN/F

REQ SPK_OUTA– 2 AO SPK_OUTA+ 4 AO Positive pin for differential speaker amplifier output A SPK_OUTB– 47 AO Negative pin for differential speaker amplifier output B SPK_OUTB+ 45 AO Positive pin for differential speaker amplifier output B

SPK_MUTE 27 I Figure 12

PowerPAD — G —

TYPE

9 AI Figure 6 Sets the gain and switching frequency of the speaker amplifier, latched in upon start-up of the device.

(1)

TERMINATION

INTERNAL

Figure 4

DESCRIPTION

Negative pin for differential speaker amplifier output A

Speaker amplifier mute which must be pulled low (connected to DGND) to mute the device and pulled high (connected to DVDD) to unmute the device.

Provides both electrical and thermal connection from the device to the board. A matching ground pad must be provided on the PCB and the device connected to it through solder. For proper electrical operation, this ground pad must be connected to the system ground.

6.1 Internal Pin Configurations

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Figure 1. PVDD Pins Figure 2. AVDD, DVDD and CPVDD Pins

Figure 3. BSTRPxx Pins Figure 4. SPK_OUTxx Pins

6

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SDA

3.3 V ESD

DVDD

SCL

3.3 V ESD

DVDD

SPK_INxx

7 V ESD

Gain Switch

AVDD

CPVSS

DAC_OUTA

GVDD

7 V ESD

PVDD

10 Ÿ

GVDD

SPK_GAIN/FREQ

7 V ESD

10 NŸ

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Internal Pin Configurations (continued)

Figure 5. GVDD_REG Pin Figure 6. SPK_GAIN/FREQ Pin

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

Figure 7. SPK_INxx Pins Figure 8. DAC_OUTx Pins

Figure 9. SDA Pin Figure 10. SCL Pin

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7

DVDD

1.8 V ESD

DVDD_REG

28 V ESD

SPK_FAULT

100 Ÿ

CVPDD

3.3 V ESD

CP

CN

3.3 V ESD

CPVSS

3.3 V ESD

GND

DVDD

3.3 V ESD

MCLK

SCLK

SDIN

LRCK/FS

DVDD

3.3 V ESD

SPK_MUTE

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

Internal Pin Configurations (continued)

Figure 11. SCLK, MCLK, SDIN, and LRCK/FS Pins Figure 12. SPK_MUTE Pin

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8

Figure 13. CP Pin Figure 14. CN and CPVSS Pins

Figure 15. DVDD_REG Pin Figure 16. SPK_FAULT Pin

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RESET

3.3 V ESD

DVDD

TAS5782M

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SLASEG8A –MARCH 2016–REVISED JULY 2017

Internal Pin Configurations (continued)

Figure 17. RESET Pin

7 Specifications

7.1 Absolute Maximum Ratings

Free-air room temperature 25°C (unless otherwise noted)

DVDD, AVDD, CPVDD

PVDD PVDD supply –0.3 30 V V

I(AmpCtrl)

V

I(DigIn)

V

I(SPK_INxx)

V

I(SPK_OUTxx)

T

J

T

stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO2, LRCK/FS, MCLK, RESET, SCL, SCLK, SDA, SDIN, and

SPK_MUTE.

Low-voltage digital, analog, charge pump supply –0.3 3.9 V

Input voltage for SPK_GAIN/FREQ and SPK_FAULT pins –0.3 V DVDD referenced digital inputs

(2)

Analog input into speaker amplifier –0.3 6.3 V Voltage at speaker output pins –0.3 32 V Ambient operating temperature, T

A

Operating junction temperature, digital die –40 125 °C Operating junction temperature, power die –40 165 °C Storage temperature –40 125 °C

(1)

MIN MAX UNIT

+ 0.3 V

GVDD

–0.5 V

+ 0.5 V

DVDD

–25 85 °C

7.2 ESD Ratings

VALUE UNIT

V

(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 Charged-device model (CDM), per JEDEC specification JESD22-C101

(1) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.

Product Folder Links: TAS5782M

(1)

(2)

±2000

±500

V

9

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SLASEG8A –MARCH 2016–REVISED JULY 2017

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7.3 Recommended Operating Conditions

Free-air room temperature 25°C (unless otherwise noted)

MIN NOM MAX UNIT

V

(POWER)

R

SPK

V

IH(DigIn)

V

IL(DigIn)

L

OUT

Power supply inputs

Minimum speaker load

Input logic high for DVDD referenced digital inputs Input logic low for DVDD referenced digital inputs Minimum inductor value in LC filter under short-circuit

condition

(1) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO2, LRCK/FS, MCLK, RESET, SCL, SCLK, SDA, SDIN, and

SPK_MUTE.

(2) The best practice for driving the input pins of the TAS5782M device is to power the drive circuit or pullup resistor from the same supply

which provides the DVDD power supply.

(3) The best practice for driving the input pins of the TAS5782M device low is to pull them down, either actively or through pulldown

resistors to the system ground.

DVDD, AVDD, CPVDD 2.9 3.63 PVDD 4.5 26.4 BTL Mode 3 Ω PBTL Mode 2 Ω

(1)(2)

(1)(3)

0.9 × V V

DVDD DVDD

0 0.1 × V

V

DVDD DVDD

1 4.7 µH

V

V V

7.4 Thermal Information

TAS5782M

DCA (TSSOP)

THERMAL METRIC

(1)

JEDEC

STANDARD

2-LAYER PCB

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 41.8 27.6 19.4 °C/W Junction-to-case (top) thermal resistance 14.4 14.4 14.4 °C/W Junction-to-board thermal resistance 9.4 9.4 9.4 °C/W Junction-to-top characterization parameter 0.6 0.6 2 °C/W Junction-to-board characterization parameter 8.1 9.3 4.8 °C/W Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

48 PINS

JEDEC

STANDARD

4-LAYER PCB

UNIT

TAS5782MEVM

4-LAYER PCB

10

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7.5 Electrical Characteristics

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5782MEVM board and Audio Precision System 2722 with Analog Analyzer filter set to 40 kHz brickwall filter. The device output PWM frequency was set to 768 kHz unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL I/O

|IIH|1

|IIL|1

V

IH1

V

IL1

V

OH(DigOut)

V

OL(DigOut)

V

OL(SPK_FAULT)

GVDD_REG GVDD regulator voltage 7 V

I2C CONTROL PORT

C

L(I2C)

f

SCL(fast)

f

SCL(slow)

V

NH

MCLK AND PLL SPECIFICATIONS

D

MCLK

f

MCLK

f

PLL

SERIAL AUDIO PORT

t

DLY

D

SCLK

f

S

f

SCLK

f

SCLK

SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS)

A

V(SPK_AMP)

ΔA

V(SPK_AMP)

Input logic high current level for DVDD referenced digital input pins

(1)

V

IN(DigIn)

= V

DVDD

10 µA

Input logic low current level for DVDD referenced digital input pins

(1)

V

= 0 V –10 µA

IN(DigIn)

Input logic high threshold for DVDD referenced digital

(1)

inputs

70% V

DVDD

Input logic low threshold for DVDD referenced digital

(1)

inputs Output logic high voltage

(1)

level Output logic low voltage

(1)

level Output logic low voltage level

for SPK_FAULT

Allowable load capacitance for each I2C Line

IOH= 4 mA 80% V

IOH= –4 mA 22% V

With 100-kΩ pullup resistor 0.8 V

30% V

400 pF

DVDD

Support SCL frequency No wait states, fast mode 400 kHz Support SCL frequency No wait states, slow mode 100 kHz Noise margin at High level for

each connected device (including hysteresis)

0.2 × V

DD

V

Allowable MCLK duty cycle 40% 60% Supported MCLK frequencies Up to 50 MHz 128 512 f

PLL input frequency

Required LRCK/FS to SCLK rising edge delay

Clock divider uses fractional divide D > 0, P = 1

Clock divider uses integer divide D = 0, P = 1

6.7 20

1 20

5 ns

S

MHz

Allowable SCLK duty cycle 40% 60% Supported input sample rates 8 96 kHz Supported SCLK frequencies 32 64 f

S

SCLK frequency Either master mode or slave mode 24.576 MHz

SPK_GAIN/FREQ voltage < 3 V,

Speaker amplifier gain

see Adjustable Amplifier Gain and Switching

Frequency Selection

SPK_GAIN/FREQ voltage > 3.3 V, see Adjustable Amplifier Gain and Switching

20

dBV

26

Frequency Selection

Typical variation of speaker amplifier gain

±1 dBV

(2)

(1) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO2, LRCK/FS, MCLK,RESET, SCL, SCLK, SDA, SDIN, and

SPK_MUTE.

(2) A unit of fSindicates that the specification is the value listed in the table multiplied by the sample rate of the audio used in the

TAS5782M device.

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11

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Electrical Characteristics (continued)

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5782MEVM board and Audio Precision System 2722 with Analog Analyzer filter set to 40 kHz brickwall filter. The device output PWM frequency was set to 768 kHz unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Switching frequency depends on voltage

f

SPK_AMP

K

SVR

Switching frequency of the speaker amplifier

Power supply rejection ratio

Drain-to-source on resistance

r

DS(on)

OCE

OTE

THRES

of the individual output MOSFETs

SPK_OUTxx overcurrent error threshold

Overtemperature error threshold

Time required to clear

OCE

CLRTIME

overcurrent error after error condition is removed.

Time required to clear

OTE

OVE

UVE

CLRTIME

THRES(PVDD)

overtemperature error after error condition is removed.

PVDD overvoltage error threshold

PVDD undervoltage error threshold

SPEAKER AMPLIFIER (STEREO BTL)

|VOS| Amplifier offset voltage

I

CN(SPK)

P

O(SPK)

Idle channel noise

Output Power (Per Channel)

presented at SPK_GAIN/FREQ pin and the clocking arrangement, including the incoming sample rate, see Adjustable Amplifier Gain and

Switching Frequency Selection

Injected Noise = 50 Hz to 60 Hz, 200 mV = 26 dB, input audio signal = digital zero

V

= 24 V, I

PVDD

includes PVDD/PGND pins, leadframe, bondwires

= 500 mA, TJ= 25°C,

(SPK_OUT)

P-P

, Gain

and metallization layers. V

PVDD

= 24 V, I

= 500 mA, TJ= 25°C 90

(SPK_OUT)

Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 20 dB gain, V

= 12 V

PVDD

Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 26 dB gain, V

= 24 V

PVDD

V

= 12 V, SPK_GAIN = 20 dB, R

PVDD

Weighted V

= 15 V, SPK_GAIN = 20 dB, R

PVDD

Weighted V

= 19 V, SPK_GAIN = 26 dB, R

PVDD

Weighted V

= 24 V, SPK_GAIN = 26 dB, R

PVDD

Weighted V

= 12 V, SPK_GAIN = 20 dB, R

PVDD

THD+N = 0.1% V

= 12 V, SPK_GAIN = 20 dB, R

PVDD

THD+N = 0.1% V

= 15 V, SPK_GAIN = 26 dB, R

PVDD

THD+N = 0.1% V

= 15 V, SPK_GAIN = 26 dB, R

PVDD

THD+N = 0.1% V

= 19 V, SPK_GAIN = 26 dB, R

PVDD

THD+N = 0.1% V

= 19 V, SPK_GAIN = 26 dB, R

PVDD

THD+N = 0.1% V

= 24 V, SPK_GAIN = 26 dB, R

PVDD

THD+N = 0.1% V

= 24 V, SPK_GAIN = 26 dB, R

PVDD

THD+N = 0.1%

SPK

= 8 Ω, A-

= 4 Ω,

= 8 Ω,

= 4 Ω,

= 8 Ω,

= 4 Ω,

= 8 Ω,

= 4 Ω,

= 8 Ω,

176.4 768 kHz

60 dB

120

mΩ

7.5 A

165 °C

1.3 s

27 V

4.3 V

2

mV

5 15

49

59

µV

81

82

14

8

23

13

W

34

20

40

33

RMS

12

Product Folder Links: TAS5782M

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SLASEG8A –MARCH 2016–REVISED JULY 2017

Electrical Characteristics (continued)

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5782MEVM board and Audio Precision System 2722 with Analog Analyzer filter set to 40 kHz brickwall filter. The device output PWM frequency was set to 768 kHz unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

SNR

(referenced to 0 dBFS input signal)

Signal-to-noise ratio

THD+N

SPK

Total harmonic distortion and noise

Cross-talk (worst case

X-talk

SPK

between left-to-right and right-to-left coupling)

SPEAKER AMPLIFIER (MONO PBTL)

|VOS| Amplifier offset voltage

I

CN

Idle channel noise

= 12 V, SPK_GAIN = 20 dB, R

PVDD

Weighted, –120 dBFS Input V

= 15 V, SPK_GAIN = 26 dB, R

PVDD

Weighted, –120 dBFS Input V

= 19 V, SPK_GAIN = 26 dB, R

PVDD

Weighted, –120 dBFS Input V

= 24 V, SPK_GAIN = 26 dB, R

PVDD

Weighted, –120 dBFS Input V

= 12 V, SPK_GAIN = 20 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 12 V, SPK_GAIN = 20 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 15 V, SPK_GAIN = 26 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 15 V, SPK_GAIN = 26 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 19 V, SPK_GAIN = 26 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 19 V, SPK_GAIN = 26 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 24 V, SPK_GAIN = 26 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 24 V, SPK_GAIN = 26 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 12 V, SPK_GAIN = 20 dB, R

PVDD

Input Signal 250 mVrms, 1-kHz Sine, across f(S)

V

= 15 V, SPK_GAIN = 26 dBV, R

PVDD

Input Signal 250 mVrms, 1-kHz Sine, across f(S)

V

= 19 V, SPK_GAIN = 26 dBV, R

PVDD

Input Signal 250 mVrms, 1-kHz Sine, across f(S)

V

= 24 V, SPK_GAIN = 26 dBV, R

PVDD

Input Signal 250 mVrms, 1-kHz Sine, across f(S)

Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 20 dB gain, V

= 12 V

PVDD

Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 26 dB gain, V

= 24 V

PVDD

V

= 12 V, SPK_GAIN = 20 dB, R

PVDD

Weighted V

= 15 V, SPK_GAIN = 20 dB, RSPK = 8 Ω,

PVDD

A-Weighted V

= 19 V, SPK_GAIN = 26 dB, RSPK = 8 Ω,

PVDD

A-Weighted V

= 24 V, SPK_GAIN = 26 dB, R

PVDD

Weighted

SPK

= 8 Ω, A-

= 4 Ω,

= 8 Ω,

= 4 Ω,

= 8 Ω,

= 4 Ω,

= 8 Ω,

= 4 Ω,

= 8 Ω,

= 8 Ω, A-

103

102

103

105

0.021%

0.022%

0.02%

0.037%

0021%

0.028%

0.027%

0.038%

–90

–102

–93

0.7

48

49

83

82

dB

mV

4

µV

RMS

Product Folder Links: TAS5782M

13

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

www.ti.com

Electrical Characteristics (continued)

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5782MEVM board and Audio Precision System 2722 with Analog Analyzer filter set to 40 kHz brickwall filter. The device output PWM frequency was set to 768 kHz unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

P

O

SNR

THD+N

Output power (per channel)

Signal-to-noise ratio (referenced to 0 dBFS input signal)

Total harmonic distortion and noise

= 12 V, SPK_GAIN = 20 dB, R

PVDD

THD+N = 0.1%, Unless otherwise noted V

= 12 V, SPK_GAIN = 20 dB, R

PVDD

THD+N = 0.1%, Unless otherwise noted V

= 12 V, SPK_GAIN = 20 dB, R

PVDD

THD+N = 0.1% V

= 15 V, SPK_GAIN = 26 dB, R

PVDD

THD+N = 0.1%, Unless otherwise noted V

= 15 V, SPK_GAIN = 26 dB, R

PVDD

THD+N = 0.1%, Unless otherwise noted V

= 15 V, SPK_GAIN = 26 dB, R

PVDD

THD+N = 0.1% V

= 19 V, SPK_GAIN = 26 dB, R

PVDD

THD+N = 0.1%, Unless otherwise noted V

= 19 V, SPK_GAIN = 26 dB, R

PVDD

THD+N = 0.1%, Unless otherwise noted V

= 19 V, SPK_GAIN = 26 dB, R

PVDD

THD+N = 0.1% V

= 24 V, SPK_GAIN = 26 dB, R

PVDD

THD+N = 0.1%, Unless otherwise noted V

= 24 V, SPK_GAIN = 26 dB, R

PVDD

THD+N = 0.1%, Unless otherwise noted V

= 24 V, SPK_GAIN = 26 dB, R

PVDD

THD+N = 0.1% V

= 12 V, SPK_GAIN = 20 dB, R

PVDD

Weighted, –120 dBFS Input V

= 15 V, SPK_GAIN = 26 dB, R

PVDD

Weighted, –120 dBFS Input V

= 19 V, SPK_GAIN = 26 dB, R

PVDD

Weighted, –120 dBFS Input V

= 24 V, SPK_GAIN = 26 dB, R

PVDD

Weighted, –120 dBFS Input V

= 12 V, SPK_GAIN = 20 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 12 V, SPK_GAIN = 20 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 12 V, SPK_GAIN = 20 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 15 V, SPK_GAIN = 26 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 15 V, SPK_GAIN = 26 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 15 V, SPK_GAIN = 26 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 19 V, SPK_GAIN = 26 dB, R

PVDD

PO= 1 W, f = 1kHz V, R

= 4 Ω, PO= 1 W, f = 1kHz 0.012%

SPK

V

= 19 V, SPK_GAIN = 26 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 24 V, SPK_GAIN = 26 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 24 V, SPK_GAIN = 26 dB, R

PVDD

PO= 1 W, f = 1kHz V

= 24 V, SPK_GAIN = 26 dB, R

PVDD

PO= 1 W, f = 1kHz

SPK

= 2 Ω,

= 4 Ω,

= 8 Ω,

= 2 Ω,

= 4 Ω,

= 8 Ω,

= 2 Ω,

= 4 Ω,

= 8 Ω,

= 2 Ω,

= 4 Ω,

= 8 Ω,

= 8 Ω, A-

= 2 Ω,

= 4 Ω,

= 8 Ω,

= 2 Ω,

= 4 Ω,

= 8 Ω,

= 2 Ω,

= 8 Ω,

= 2 Ω,

= 4 Ω,

= 8 Ω,

30

16

9

44

22

13

W

50

36

20

40

61

34

105

104

dB

105

107

0.014%

0.011%

0.014%

0.015%

0.013%

0.015%

0.018%

0.020%

0.028%

0.02%

0.027%

14

Product Folder Links: TAS5782M

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7.6 Power Dissipation Characteristics

Free-air room temperature 25°C (unless otherwise noted)

V

PVDD

(V)

SPK_GAIN

7.4 20

(dBV)

(1)(2)(3)

f

SPK_AMP

(kHz)

384

768

STATE OF

OPERATION

Mute

Standby

Powerdown

Mute

Standby

Powerdown

Idle

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

R

SPK

(Ω)

I

PVDD

(mA)

(4)

4 21.30 59.70 0.355 6 21.33 59.68 0.355 8 21.30 59.70 0.355 4 21.33 58.82 0.352 6 21.34 58.81 0.352 8 21.36 58.81 0.352 4 2.08 12.41 0.056 6 2.11 12.41 0.057 8 2.17 12.41 0.057 4 2.03 0.730 0.017 6 2.04 0.740 0.018 8 2.06 0.740 0.018 4 27.48 59.7 0.400 6 27.49 59.73 0.401 8 24.46 59.72 0.378 4 27.50 58.8 0.398 6 27.51 58.8 0.398 8 27.52 58.81 0.398 4 2.04 12.41 0.056 6 2.08 12.41 0.056 8 2.11 12.41 0.057 4 2.06 0.73 0.018 6 2.07 0.74 0.018 8 2.08 0.74 0.018

I

DVDD

(mA)

(5)

P

DISS

(W)

(1) Mute: B0-P0-R3-D0,D4 = 1 (2) Standby: B0-P0-R2-D4 = 1 (3) Power down: B0-P0-R2-D0 = 1 (4) I

(5) I

refers to all current that flows through the PVDD supply for the DUT. Any other current sinks not directly related to the DUT current

PVDD

draw were removed.

refers to all current that flows through the DVDD (3.3-V) supply for the DUT. Any other current sinks not directly related to the

DVDD

DUT current draw were removed.

Product Folder Links: TAS5782M

15

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

Power Dissipation Characteristics (continued)

Free-air room temperature 25°C (unless otherwise noted)

V

PVDD

(V)

SPK_GAIN

11.1 20

(dBV)

(1)(2)(3)

f

SPK_AMP

(kHz)

384

768

STATE OF

OPERATION

Idle

Mute

Standby

Powerdown

Idle

Mute

Standby

Powerdown

R

SPK

(Ω)

I

PVDD

(mA)

(4)

I

DVDD

(mA)

(5)

4 24.33 59.74 0.467 6 24.32 59.74 0.467 8 24.36 59.70 0.467 4 24.36 58.81 0.464 6 24.32 58.82 0.464 8 24.37 58.84 0.465 4 3.58 12.40 0.081 6 3.57 12.41 0.081 8 3.58 12.42 0.081 4 3.52 0.74 0.042 6 3.52 0.74 0.042 8 3.54 0.74 0.042 4 30.70 59.70 0.538 6 30.65 59.72 0.537 8 30.67 59.71 0.537 4 3.072 58.80 0.528 6 30.69 58.81 0.535 8 30.69 58.81 0.535 4 3.54 12.40 0.080 6 3.54 12.41 0.080 8 3.58 12.42 0.081 4 3.53 0.74 0.042 6 3.53 0.74 0.042 8 3.55 0.74 0.042

www.ti.com

P

DISS

(W)

16

Product Folder Links: TAS5782M

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Power Dissipation Characteristics (continued)

Free-air room temperature 25°C (unless otherwise noted)

V

PVDD

(V)

SPK_GAIN

12 20

(dBV)

(1)(2)(3)

f

SPK_AMP

(kHz)

384

768

STATE OF

OPERATION

Idle

Mute

Standby

Powerdown

Idle

Mute

Standby

Powerdown

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

R

SPK

(Ω)

I

PVDD

(mA)

(4)

4 25.07 59.72 0.498 6 25.08 59.73 0.498 8 25.10 59.71 0.498 4 25.12 58.84 0.496 6 25.08 58.82 0.495 8 25.11 58.82 0.495 4 3.92 12.40 0.088 6 3.93 12.41 0.088 8 3.94 12.41 0.088 4 3.87 0.75 0.049 6 3.85 0.74 0.049 8 3.87 0.75 0.049 4 31.31 59.72 0.573 6 31.29 59.71 0.573 8 31.31 59.74 0.573 4 31.31 58.80 0.570 6 31.33 58.81 0.570 8 31.32 58.81 0.570 4 3.88 12.40 0.087 6 3.90 12.41 0.088 8 3.91 12.41 0.088 4 3.89 0.75 0.049 6 3.91 0.74 0.049 8 3.88 0.75 0.049

I

DVDD

(mA)

(5)

P

DISS

(W)

Product Folder Links: TAS5782M

17

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

Power Dissipation Characteristics (continued)

Free-air room temperature 25°C (unless otherwise noted)

V

PVDD

(V)

SPK_GAIN

15 26

(dBV)

(1)(2)(3)

f

SPK_AMP

(kHz)

384

768

STATE OF

OPERATION

Idle

Mute

Standby

Powerdown

Idle

Mute

Standby

Powerdown

R

SPK

(Ω)

I

PVDD

(mA)

(4)

I

DVDD

(mA)

(5)

4 27.94 59.73 0.616 6 27.91 59.75 0.616 8 27.75 59.69 0.613 4 27.98 58.84 0.614 6 27.94 58.87 0.613 8 27.88 58.85 0.612 4 5.09 12.41 0.117 6 5.12 12.41 0.118 8 5.19 12.41 0.119 4 5.02 0.74 0.078 6 5.06 0.74 0.078 8 5.14 0.74 0.080 4 33.05 59.7 0.693 6 33.03 59.72 0.693 8 33.08 59.68 0.693 4 33.03 58.81 0.690 6 33.04 58.81 0.690 8 33.05 58.80 0.690 4 5.07 12.41 0.117 6 5.09 12.41 0.117 8 5.14 12.41 0.118 4 5.02 0.74 0.078 6 5.04 0.74 0.078 8 5.09 0.74 0.079

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P

DISS

(W)

18

Product Folder Links: TAS5782M

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Power Dissipation Characteristics (continued)

Free-air room temperature 25°C (unless otherwise noted)

V

PVDD

(V)

SPK_GAIN

19.6 26

(dBV)

(1)(2)(3)

f

SPK_AMP

(kHz)

384

768

STATE OF

OPERATION

Idle

Mute

Standby

Powerdown

Idle

Mute

Standby

Powerdown

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

R

SPK

(Ω)

I

PVDD

(mA)

(4)

4 32.27 59.77 0.830 6 32.19 59.76 0.828 8 32.08 59.75 0.826 4 32.27 58.85 0.827 6 32.24 58.87 0.826 8 32.22 58.86 0.826 4 6.95 12.40 0.177 6 6.93 12.42 0.177 8 7.00 12.41 0.178 4 6.89 0.74 0.137 6 6.90 0.74 0.138 8 6.96 0.73 0.139 4 34.99 59.74 0.883 6 34.95 59.74 0.882 8 34.97 59.71 0.882 4 34.96 58.85 0.879 6 34.98 58.83 0.880 8 34.96 58.81 0.879 4 6.93 12.40 0.177 6 6.93 12.42 0.177 8 6.98 12.41 0.178 4 6.84 0.74 0.137 6 6.89 0.74 0.137 8 6.90 0.73 0.138

I

DVDD

(mA)

(5)

P

DISS

(W)

Product Folder Links: TAS5782M

19

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

Power Dissipation Characteristics (continued)

Free-air room temperature 25°C (unless otherwise noted)

V

PVDD

(V)

SPK_GAIN

24 26

(dBV)

(1)(2)(3)

f

SPK_AMP

(kHz)

384

768

STATE OF

OPERATION

Idle

Mute

Standby

Powerdown

Idle

Mute

Standby

Powerdown

R

SPK

(Ω)

I

PVDD

(mA)

(4)

I

DVDD

(mA)

(5)

4 36.93 59.80 1.084 6 36.87 59.81 1.082 8 36.77 59.76 1.080 4 36.94 58.91 1.081 6 36.89 58.89 1.080 8 36.85 58.90 1.079 4 8.73 12.40 0.250 6 8.72 12.40 0.250 8 8.71 12.40 0.250 4 8.64 0.74 0.210 6 8.66 0.74 0.210 8 8.69 0.73 0.211 4 36.84 59.73 1.081 6 36.86 59.76 1.082 8 36.83 59.78 1.081 4 36.85 58.85 1.079 6 36.84 58.84 1.078 8 36.82 58.83 1.078 4 8.66 12.40 0.249 6 8.68 12.40 0.249 8 8.71 12.40 0.250 4 8.63 0.74 0.210 6 8.64 0.74 0.210 8 8.65 0.73 0.210

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P

DISS

(W)

7.7 MCLK Timing

See Figure 18.

t

MCLK

t

MCLKH

t

MCLKL

MCLK period 20 1000 ns MCLK pulse width, high 9 ns MCLK pulse width, low 9 ns

7.8 Serial Audio Port Timing – Slave Mode

See Figure 19.

f

SCLK

t

SCLK

t

SCLKL

t

SCLKH

t

SL

t

LS

t

SU

t

DH

t

DFS

20

SCLK frequency 1.024 MHz SCLK period 40 ns SCLK pulse width, low 16 ns SCLK pulse width, high 16 ns SCLK rising to LRCK/FS edge 8 ns LRCK/FS Edge to SCLK rising edge 8 ns Data setup time, before SCLK rising edge 8 ns Data hold time, after SCLK rising edge 8 ns Data delay time from SCLK falling edge 15 ns

Product Folder Links: TAS5782M

MIN NOM MAX UNIT

www.ti.com

7.9 Serial Audio Port Timing – Master Mode

See Figure 20.

t

SCLK

t

SCLKL

t

SCLKH

t

LRD

t

SU

t

DH

t

DFS

SCLK period 40 ns SCLK pulse width, low 16 ns SCLK pulse width, high 16 ns LRCK/FS delay time from to SCLK falling edge –10 20 ns Data setup time, before SCLK rising edge 8 ns Data hold time, after SCLK rising edge 8 ns Data delay time from SCLK falling edge 15 ns

7.10 I2C Bus Timing – Standard

f

SCL

t

BUF

t

LOW

t

HI

t

RS-SU

t

S-HD

t

D-SU

t

D-HD

t

SCL-R

t

SCL-R1

t

SCL-F

t

SDA-R

t

SDA-F

t

P-SU

SCL clock frequency 100 kHz Bus free time between a STOP and START condition 4.7 µs Low period of the SCL clock 4.7 µs High period of the SCL clock 4 µs Setup time for (repeated) START condition 4.7 µs Hold time for (repeated) START condition 4 µs Data setup time 250 ns Data hold time 0 900 ns Rise time of SCL signal 20 + 0.1C Rise time of SCL signal after a repeated START condition and after an acknowledge bit 20 + 0.1C Fall time of SCL signal 20 + 0.1C Rise time of SDA signal 20 + 0.1C Fall time of SDA signal 20 + 0.1C Setup time for STOP condition 4 µs

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

MIN NOM MAX UNIT

MIN MAX UNIT

1000 ns

B

1000 ns

B

1000 ns

B

1000 ns

B

1000 ns

B

7.11 I2C Bus Timing – Fast

See Figure 21.

f

SCL

t

BUF

t

LOW

t

HI

t

RS-SU

t

RS-HD

t

D-SU

t

D-HD

t

SCL-R

t

SCL-R1

t

SCL-F

t

SDA-R

t

SDA-F

t

P-SU

t

SP

SCL clock frequency 400 kHz Bus free time between a STOP and START condition 1.3 µs Low period of the SCL clock 1.3 µs High period of the SCL clock 600 ns Setup time for (repeated)START condition 600 ns Hold time for (repeated)START condition 600 ns Data setup time 100 ns Data hold time 0 900 ns Rise time of SCL signal 20 + 0.1C Rise time of SCL signal after a repeated START condition and after an acknowledge bit 20 + 0.1C Fall time of SCL signal 20 + 0.1C Rise time of SDA signal 20 + 0.1C Fall time of SDA signal 20 + 0.1C Setup time for STOP condition 600 ns Pulse width of spike suppressed 50 ns

MIN MAX UNIT

B B B B B

300 ns 300 ns 300 ns 300 ns 300 ns

Product Folder Links: TAS5782M

21

SCLK

(Input)

0.5 × DVDD

t

SCLKH

0.5 × DVDD

t

SCLKL

t

SCLK

t

SL

t

SU

t

DH

0.5 × DVDD

t

DFS

t

LS

LRCK/FS

(Input)

DATA

(Input)

DATA

(Output)

"L"

"H"

0.7 × V

DVDD

t

MCLKH

t

MCLKL

t

MCLK

0.3 × V

DVDD

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

7.12 SPK_MUTE Timing

See Figure 22.

t

r

t

f

Rise time 20 ns Fall time 20 ns

Figure 18. Timing Requirements for MCLK Input

www.ti.com

MIN MAX UNIT

22

Figure 19. Serial Audio Port Timing in Slave Mode

Product Folder Links: TAS5782M

SPK_MUTE

t

f

<20ns

t

r

< 20 ns

t

f

< 20 ns

0.9 × DV

DD

0.1 × DV

DD

SDA

SCL

START

Repeated

START

STOP

t

D-SU

t

LOW

.

t

SCL-R

.

t

HI

.

t

S-HD

.

t

BUF

.

t

SCL-F

.

t

D-HD

t

RS-HD

t

RS-SU

t

SDA-R

t

SDA-FtP-SU

t

SP

t

BCL

LRCK/FS

(Input)

SCLK

(Input)

DATA

(Input)

DATA

(Output)

t

SCLK

.

t

BCL

t

SCLK

t

DH

t

DFS

t

LRD

0.5 × DVDD

t

SU

www.ti.com

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

Figure 20. Serial Audio Port Timing in Master Mode

Figure 21. I2C Communication Port Timing Diagram

Figure 22. SPK_MUTE Timing Diagram for Soft Mute Operation via Hardware Pin

Product Folder Links: TAS5782M

23

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

www.ti.com

7.13 Typical Characteristics

All performance plots were taken using the TAS5782MEVM Board at room temperature, unless otherwise noted. The term "traditional LC filter" refers to the output filter that is present by default on the TAS5782MEVM Board.

Table 1. Quick Reference Table

OUTPUT

CONFIGURATIONS

Bridge Tied Load (BTL)

Configuration Curves

Parallel Bridge Tied Load

(PBTL) Configuration

Frequency Response Figure 42 Output Power vs PVDD Figure 23 THD+N vs Frequency, V THD+N vs Frequency, V THD+N vs Frequency, V THD+N vs Frequency, V THD+N vs Power, V THD+N vs Power, V THD+N vs Power, V THD+N vs Power, V Idle Channel Noise vs PVDD Figure 32 Efficiency vs Output Power Figure 33 Efficiency vs Output Power Figure 34 Efficiency vs Output Power Figure 35 Idle Current Draw (Filterless) vs PVDD Figure 36 Crosstalk vs. Frequency Figure 37 PVDD PSRR vs Frequency Figure 38 DVDD PSRR vs Frequency Figure 39 AVDD PSRR vs Frequency Figure 40 CPVDD PSRR vs Frequency Figure 41 THD+N vs Frequency, V THD+N vs Frequency, V THD+N vs Frequency, V THD+N vs Frequency, V Output Power vs PVDD Figure 47 THD+N vs Frequency, V THD+N vs Frequency, V THD+N vs Frequency, V THD+N vs Frequency, V THD+N vs Power, V THD+N vs Power, V THD+N vs Power, V THD+N vs Power, V Idle Channel Noise vs PVDD Figure 56 Efficiency vs Output Power Figure 57 THD+N vs Frequency, V THD+N vs Frequency, V THD+N vs Frequency, V THD+N vs Frequency, V

PLOT TITLE FIGURE NUMBER

= 12 V Figure 24

PVDD

= 15 V Figure 25

PVDD

= 18 V Figure 26

PVDD

= 24 V Figure 27

PVDD

= 12 V Figure 28

PVDD

= 15 V Figure 29

PVDD

= 18 V Figure 30

PVDD

= 24 V Figure 31

PVDD

= 12 V Figure 43

PVDD

= 15 V Figure 44

PVDD

= 18 V Figure 45

PVDD

= 24 V Figure 46

PVDD

= 12 V Figure 48

PVDD

= 15 V Figure 49

PVDD

= 18 V Figure 50

PVDD

= 24 V Figure 51

PVDD

= 12 V Figure 52

PVDD

= 15 V Figure 53

PVDD

= 18 V Figure 54

PVDD

= 24 V Figure 55

PVDD

= 12 V Figure 60

PVDD

= 15 V Figure 61

PVDD

= 18 V Figure 62

PVDD

= 24 V Figure 63

PVDD

24

Product Folder Links: TAS5782M

Frequency (Hz)

THD+N (%)

0.001

0.01

0.1

1

10

100 1k 10k20 40k

D004

4 : Load 6 : Load 8 : Load

Frequency (Hz)

THD+N (%)

0.001

0.01

0.1

1

10

100 1k 10k20 40k

D005

4 : Load 6 : Load 8 : Load

Supply Voltage (V)

Output Power (W)

5 10 15 20 24

0

20

40

60

80

10 20

D002

8 : Load Peak 6 : Load Peak 4 : Load Peak 6 : Load Continous 4 : Load Continous

Frequency (Hz)

THD+N (%)

0.001

0.01

0.1

1

10

100 1k 10k20 40k

D003

4 : Load 6 : Load 8 : Load

TAS5782M

www.ti.com

SLASEG8A –MARCH 2016–REVISED JULY 2017

7.13.1 Bridge Tied Load (BTL) Configuration Curves

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5782MEVM board and Audio Precision System 2722 with Analog Analyzer filter set to 40-kHz brickwall filter. All measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 768 kHz, unless otherwise noted. For both the BTL plots and the PBTL plots, the LC filter used was 4.7 µH / 0.68 µF. Return to

Quick Reference Table.

A

V(SPK_AMP)

A

V(SPK_AMP)

= 26 dBV

Figure 23. Output Power vs PVDD – BTL

= 20 dBV PO= 1 W V

Figure 25. THD+N vs Frequency – BTL

PVDD

= 15 V

A

V(SPK_AMP)

A

V(SPK_AMP)

= 20 dBV PO= 1 W V

Figure 24. THD+N vs Frequency – BTL

= 26 dBV PO= 1 W V

Figure 26. THD+N vs Frequency – BTL

PVDD

= 12 V

= 18 V

Product Folder Links: TAS5782M

25

Output Power (W)

Total Harmonic Distortion + Noise (%)

0.001

0.01

0.1

1

10

10m 100m 1 10 50

D010

4 : Load 6 : Load 8 : Load

Supply Voltage (V)

Idle Channel Noise (PVrms)

0

10

20

30

40

50

60

70

80

90

100

1510 20

D011

Gain = 20 dB, PWM Freq = 384 kHz Gain = 26 dB, PWM Freq = 384 kHz Gain = 20 dB, PWM Freq = 768 kHz Gain = 26 dB, PWM Freq = 768 kHz

Output Power (W)

Total Harmonic Distortion + Noise (%)

0.001

0.01

0.1

1

10

10m 100m 1 10 40

D008

4 : Load 6 : Load 8 : Load

Output Power (W)

Total Harmonic Distortion + Noise (%)

0.001

0.01

0.1

1

10

10m 100m 1 10 50

D009

4 : Load 6 : Load 8 : Load

Frequency (Hz)

THD+N (%)

0.001

0.01

0.1

1

10

100 1k 10k20 40k

D006

4 : Load 6 : Load 8 : Load

Output Power (W)

Total Harmonic Distortion + Noise (%)

0.001

0.01

0.1

1

10

10m 100m 1 10 30

D007

4 : Load 6 : Load 8 : Load

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

www.ti.com

A

V(SPK_AMP)

A

V(SPK_AMP)

dBV

= 26 dBV PO= 1 W V

Figure 27. THD+N vs Frequency – BTL

= 20

Figure 29. THD+N vs Power – BTL

V

PVDD

= 24 V

= 15 V

A

V(SPK_AMP)

A

V(SPK_AMP)

dBV

= 20 dBV V

Figure 28. THD+N vs Power – BTL

= 26

Figure 30. THD+N vs Power – BTL

PVDD

= 12 V

V

PVDD

=

18 V

A

V(SPK_AMP)

26

= 26 dBV V

Figure 31. THD+N vs Power – BTL

= 24 V

PVDD

Product Folder Links: TAS5782M

R

= 4 Ω

SPK

Figure 32. Idle Channel Noise vs PVDD – BTL

Frequency (Hz)

Crosstalk (dB)

-120

-100

-80

-60

-40

-20

0

100 1k 10k20 40k

D016

Ch 1 to Ch 2 Ch 2 to Ch 1

Frequency

PSRR (dB)

-100

-80

-60

-40

-20

0

100 1k 10k20 40k

D017

Left Channel Right Channel

Output Power (W)

Efficiency (%)

0

10

20

30

40

50

60

70

80

90

100

0 20 40 60 80

D014

PVDD = 12 V PVDD = 15 V PVDD = 18 V PVDD = 24 V

Supply Voltage (V)

PVDD Idle Current (mA)

0

10

20

30

40

50

60

205 15 2510 20

D015

Output Power (W)

Efficiency (%)

0

10

20

30

40

50

60

70

80

90

100

0 20 40 60 80

D012

PVDD = 12 V PVDD = 15 V PVDD = 18 V PVDD = 24 V

Output Power (W)

Efficiency (%)

0

10

20

30

40

50

60

70

80

90

100

0 20 40 60 80

D013

PVDD = 12 V PVDD = 15 V PVDD = 18 V PVDD = 24 V

www.ti.com

R

= 4 Ω

SPK

Figure 33. Efficiency vs Output Power – BTL

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

R

= 6 Ω

SPK

Figure 34. Efficiency vs Output Power – BTL

R

SPK

Figure 35. Efficiency vs Output Power – BTL

A

V(SPK_AMP)

= 26 dBV V

Figure 37. Crosstalk vs Frequency – BTL

= 8 Ω

f

SPK_AMP

= 768 kHz R

Figure 36. Idle Current Draw (Filterless) vs V

PVDD

= 24 V

A

V(SPK_AMP)

Product Folder Links: TAS5782M

SPK

PVDD

= 26 dBV V

= 24 V + 250 mVac

PVDD

Figure 38. PVDD PSRR vs Frequency – BTL

= 8 Ω

– BTL

27

Frequency (Hz)

THD+N (%)

0.001

0.01

0.1

1

10

100 1k 10k20 20k

D035

4 : Load 6 : Load 8 : Load

Frequency (Hz)

THD+N (%)

0.001

0.01

0.1

1

10

100 1k 10k20 20k

D036

4 : Load 6 : Load 8 : Load

Frequency

PSRR (dB)

-100

-80

-60

-40

-20

0

100 1k 10k20 40k

D020

Left Channel Right Channel

Frequency (Hz)

Gain (dB)

12

16

20

24

28

100 1k 10k20 40k

D001

Frequency

PSRR (dB)

-100

-80

-60

-40

-20

0

100 1k 10k20 40k

D018

Left Channel Right Channel

Frequency

PSRR (dB)

-100

-80

-60

-40

-20

0

100 1k 10k20 40k

D019

Left Channel Right Channel

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

www.ti.com

A

V(SPK_AMP)

V

= 3.3 V + 250 mVac

DVDD

A

V(SPK_AMP)

V

= 3.3 V + 250 mVac

CPVDD

= 26 dBV V

PVDD

Figure 39. DVDD PSRR vs Frequency – BTL

= 26 dBV V

PVDD

Figure 41. CPVDD PSRR vs Frequency – BTL

= 24 V

A

V(SPK_AMP)

V

= 3.3 V + 250 mVac

AVDD

A

V(SPK_AMP)

= 26 dBV V

PVDD

Figure 40. AVDD PSRR vs Frequency – BTL

= 20 dB P

= 1 W PVDD = 12 V

OUT

Figure 42. Gain vs Frequency – BTL

= 24 V

A

V(SPK_AMP)

dB

= 20

P

= 1 W PVDD = 12 V

OUT

Figure 43. THD vs Frequency – BTL

28

A

V(SPK_AMP)

dB

Product Folder Links: TAS5782M

= 20

P

= 1 W PVDD = 15 V

OUT

Figure 44. THD vs Frequency - BTL

Frequency (Hz)

THD+N (%)

0.001

0.01

0.1

1

10

100 1k 10k20 20k

D037

4 : Load 6 : Load 8 : Load

Frequency (Hz)

THD+N (%)

0.001

0.01

0.1

1

10

100 1k 10k20 20k

D038

4 : Load 6 : Load 8 : Load

www.ti.com

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

A

V(SPK_AMP)

dB

= 20

P

= 1 W PVDD = 18 V

OUT

Figure 45. THD vs Frequency – BTL

A

V(SPK_AMP)

dB

= 20

P

= 1 W PVDD = 24 V

OUT

Figure 46. THD vs Frequency – BTL

29

Product Folder Links: TAS5782M

Frequency (Hz)

Total Harmonic Distortion + Noise (%)

0.001

0.01

0.1

1

10

100 1k 10k20 40k

D025

2 : Load 3 : Load 4 : Load

Output Power (W)

Total Harmonic Distortion + Noise (%)

0.001

0.01

0.1

1

10

10m 100m 1 10 50

D026

2 : Load 3 : Load 4 : Load

Frequency (Hz)

Total Harmonic Distortion + Noise (%)

0.001

0.01

0.1

1

10

100 1k 10k20 40k

D023

2 : Load 3 : Load 4 : Load

Frequency (Hz)

Total Harmonic Distortion + Noise (%)

0.001

0.01

0.1

1

10

100 1k 10k20 40k

D024

2 : Load 3 : Load 4 : Load

Supply Voltage (V)

Output Power (W)

5 10 15 20 24

0

20

40

60

80

100

120

140

160

10 20

D021

4 : Load Peak 3 : Load Peak 2 : Load Peak 3 : Load Continous 2 : Load Continous

Frequency (Hz)

Total Harmonic Distortion + Noise (%)

0.001

0.01

0.1

1

10

100 1k 10k20 40k

D022

2 : Load 3 : Load 4 : Load

TAS5782M

SLASEG8A –MARCH 2016–REVISED JULY 2017

7.13.2 Parallel Bridge Tied Load (PBTL) Configuration

Return to Quick Reference Table.

www.ti.com

A

V(SPK_AMP)

A

V(SPK_AMP)

= 26 dBV

Figure 47. Output Power vs PVDD – PBTL

= 20 dBV PO= 1 W V

PVDD

Figure 49. THD+N vs Frequency – PBTL

= 15 V

A

V(SPK_AMP)

A

V(SPK_AMP)

= 20 dBV PO= 1 W V

Figure 48. THD+N vs Frequency – PBTL

= 26 dBV PO= 1 W V

Figure 50. THD+N vs Frequency – PBTL

PVDD

= 12 V

= 18 V

A

V(SPK_AMP)

= 26 dBV PO= 1 W V

Figure 51. THD+N vs Frequency – PBTL

30

= 24 V

PVDD

Product Folder Links: TAS5782M

A

V(SPK_AMP)

= 20 dBV V

Figure 52. THD+N vs Power – PBTL

PVDD

= 12 V

Texas Instruments TAS5782M Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Features

2 Applications

3 Description

Table of Contents

4 Revision History

5 Device Comparison Table

6 Pin Configuration and Functions

6.1 Internal Pin Configurations

7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

7.6 Power Dissipation Characteristics

7.7 MCLK Timing

7.8 Serial Audio Port Timing – Slave Mode

7.9 Serial Audio Port Timing – Master Mode

7.10 I2C Bus Timing – Standard

7.11 I2C Bus Timing – Fast

7.12 SPK_MUTE Timing

7.13 Typical Characteristics

7.13.1 Bridge Tied Load (BTL) Configuration Curves

7.13.2 Parallel Bridge Tied Load (PBTL) Configuration