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TAS5782M
SLASEG8A –MARCH 2016–REVISED JULY 2017
TAS5782M 30 W Stereo Class-D Amplifier with 96-kHz Processing
•Flexible Audio I/O Configuration
–Supports I2S, TDM, LJ, RJ Digital Input
–Sample Rate Support
–BD Amplifier Modulation
–Supports 3-Wire Digital Audio Interface (No MCLK required)
•High-Performance Closed-Loop Architecture (PVDD = 12 V, RSPK = 8 Ω, SPK_GAIN = 20 dB)
–Closed-Loop = reduced component count/ smaller solution size
–Idle Channel Noise = 62 µVrms (A-Wtd)
–THD+N = 0.2% (at 1 W, 1 kHz)
–SNR = 103dB A-Wtd (Ref. to THD+N = 1%)
•Flexible Processing Features
–15 BiQuads / SmartEQ
–2 x 5 BiQuads for X-Over / EQ
–3-Band Advanced DRC + AGL
–Dynamic EQ and SmartBass
–Sound Field Spatializer (SFS)
–96-kHz Processor Sampling
•Communication Features
–Software Mode Control via I2C Port
–Two Address Select Pins – Up to 4 Devices
•Robustness and Reliability Features
–Clock Error , DC, and Short-Circuit Protection
–Overtemperature and Overcurrent Protection
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Simplified Block Diagram |
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TAS5782M |
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Control and |
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CH1 |
System |
Status |
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PCDSP |
DAC |
Power |
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Bridge |
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PP |
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Digital Audio |
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CH2 |
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I2C |
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Copyright © 2017, Texas Instruments Incorporated
•LCD, LED TV, and Multi-Purpose Monitors
•Sound Bars, Docking Stations, and PC Audio
•Wireless Subwoofers, Bluetooth Speakers, and Active Speakers
The TAS5782M device is a high-performance, stereo closed-loop Class-D amplifier with integrated audio processor with up to 96-kHz architecture. To convert from digital to analog, the device uses a high performance DAC with Burr Brown™ audio technology. It requires only two power supplies: one DVDD for low-voltage circuitry and one PVDD for high-voltage circuitry. It is controlled by a software control port using standard I2C communication.
An optimal mix of thermal performance and device
cost is provided in the 90 mΩ rDS(on) of the output MOSFETs. Additionally, a thermally enhanced 48-Pin
TSSOP provides excellent operation in the elevated ambient temperatures found in modern consumer electronic devices.
Device Information(1)
PART NUMBER |
PACKAGE |
BODY SIZE (NOM) |
TAS5782M |
TSSOP (48) |
12.50 mm × 6.10 mm |
(1)For all available packages, see the orderable addendum at the end of the data sheet.
Power at 10% THD+N vs PVDD (1)
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<![if ! IE]> <![endif]>(W) |
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: Load Continous |
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<![if ! IE]> <![endif]>Output Power |
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(1)Tested on TAS5782MEVM Board.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5782M
SLASEG8A –MARCH 2016–REVISED JULY 2017 www.ti.com
1 |
Features .................................................................. |
1 |
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9.2 |
Functional Block Diagram ....................................... |
34 |
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Applications ........................................................... |
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9.3 |
Feature Description................................................. |
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3 |
Description ............................................................. |
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9.4 |
Device Functional Modes........................................ |
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Revision History..................................................... |
2 |
10 |
Application and Implementation........................ |
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Device Comparison Table |
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10.1 |
Application Information.......................................... |
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10.2 |
Typical Applications |
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6 |
Pin Configuration and Functions |
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Power Supply Recommendations |
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6.1 |
Internal Pin Configurations |
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11.1 |
Power Supplies |
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Specifications |
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Layout |
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7.1 |
Absolute Maximum Ratings |
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12.1 |
Layout Guidelines |
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7.2 |
ESD Ratings |
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12.2 |
Layout Example |
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7.3 |
Recommended Operating Conditions |
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Register Maps |
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7.4 |
Thermal Information ................................................ |
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7.5 |
Electrical Characteristics |
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Registers - Page 0 ................................................ |
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13.2 |
Registers - Page 1 |
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7.6 |
Power Dissipation Characteristics |
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Device and Documentation Support |
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7.7 |
MCLK Timing ......................................................... |
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7.8 |
Serial Audio Port Timing – Slave Mode .................. |
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14.1 |
Device Support.................................................... |
120 |
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7.9 |
Serial Audio Port Timing – Master Mode ................ |
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14.2 |
Receiving Notification of Documentation |
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7.10 I2C Bus Timing – Standard ................................... |
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Updates.................................................................. |
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7.11 I2C Bus Timing – Fast........................................... |
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14.3 |
Community Resources........................................ |
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14.4 |
Trademarks ......................................................... |
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7.12 |
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SPK_MUTE Timing |
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14.5 |
Electrostatic Discharge Caution |
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7.13 |
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Typical Characteristics |
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14.6 |
Glossary |
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Parametric Measurement Information |
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15 Mechanical, Packaging, and Orderable |
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Detailed Description |
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Information |
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9.1 |
Overview |
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NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2017) to Revision A |
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• Added missing cross references to the Quick Reference Table .......................................................................................... |
24 |
• Changed Changed the Volume Ramp Up/Down Step default value to 11 .......................................................................... |
50 |
• Changed 5th bit of the I2C Slave Address table .................................................................................................................. |
54 |
• Added DSP Book, Page, and Register Update section ....................................................................................................... |
56 |
• Deleted Page 0 Registers 0x0A, 0x50, 0x51, 0x52, and 0x54............................................................................................. |
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• Changed the PLLE bit type of Register 4 from R to R/W..................................................................................................... |
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• Changed Bit configuration of Register 0x14......................................................................................................................... |
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• Changed PJDV bit in Register 21 from 5-4 to 5-0................................................................................................................ |
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• Changed Reset value of Register 0x3D to '00110000'......................................................................................................... |
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• Changed Bit configuration of Register 0x5D ...................................................................................................................... |
112 |
• Deleted Page 1 Registers 0x05 and 0x08.......................................................................................................................... |
116 |
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2 |
Submit Documentation Feedback |
Copyright © 2016–2017, Texas Instruments Incorporated |
Product Folder Links: TAS5782M
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TAS5782M |
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www.ti.com |
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SLASEG8A –MARCH 2016–REVISED JULY 2017 |
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5 Device Comparison Table |
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DEVICE NAME |
MODULATION STYLE |
PROCESSING TYPE |
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TAS5782MDCA |
BD Modulation |
100 MIPs, Flexible Process flow (Uses mixture of RAM and ROM |
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components to create several process flows) |
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TAS5754MDCA |
1SPW (Ternary) |
50 MIPs, HybridFlow (Uses mixture of RAM and ROM components to |
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create several process flows) |
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TAS5756MDCA |
BD Modulation |
50 MIPs, HybridFlow (Uses mixture of RAM and ROM components to |
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create several process flows) |
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TAS5766MDCA |
BD Modulation |
50 MIPs, Fixed-Function (Uses single ROM image of process flow) |
Copyright © 2016–2017, Texas Instruments Incorporated |
Submit Documentation Feedback |
3 |
Product Folder Links: TAS5782M
TAS5782M
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
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www.ti.com |
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6 Pin Configuration and Functions |
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DCA Package |
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48-Pin TSSOP with PowerPAD™ |
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Top View |
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BSTRPA- |
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BSTRPB- |
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SPK_OUTA- |
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SPK_OUTB- |
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PGND |
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PGND |
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SPK_OUTA+ |
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BSTRPB+ |
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BSTRPA+ |
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PVDD |
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PVDD |
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PVDD |
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PVDD |
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PVDD |
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SPK_GAIN/FSW |
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SPK_FAULT |
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PGND |
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SPK_INA- |
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SPK_INA+ |
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POWERPADTM |
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DAC_OUTA |
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AVDD |
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CPVSS |
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AGND |
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CN |
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SDA |
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GND |
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SCL |
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32 |
CP |
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CPVDD |
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RESET |
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DVDD |
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ADR1 |
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DGND |
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GPIO2 |
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28 |
DVDD_REG |
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MCLK |
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SCLK |
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ADR0 |
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SDIN |
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4 |
Submit Documentation Feedback |
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Copyright © 2016–2017, Texas Instruments Incorporated |
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Product Folder Links: TAS5782M |
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TAS5782M |
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www.ti.com |
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SLASEG8A –MARCH 2016–REVISED JULY 2017 |
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Pin Functions |
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PIN |
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TYPE(1) |
INTERNAL |
DESCRIPTION |
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NAME |
NO. |
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TERMINATION |
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ADR0 |
26 |
DI |
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Sets the LSB of the I2C address to 0 if pulled to GND, to 1 if pulled to DVDD |
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ADR1 |
20 |
DI |
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Sets the second LSB of the I2C address to 0 if pulled to GND, to 1 if pulled to DVDD |
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AGND |
10 |
G |
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Ground reference for analog circuitry(2) |
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AVDD |
14 |
P |
Figure 2 |
Power supply for internal analog circuitry |
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BSTRPA– |
1 |
P |
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Connection point for the SPK_OUTA– bootstrap capacitor which is used to create a power supply for |
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the high-side gate drive for SPK_OUTA– |
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BSTRPA+ |
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Connection point for the SPK_OUTA+ bootstrap capacitor which is used to create a power supply for |
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the high-side gate drive for SPK_OUTA+ |
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Figure 3 |
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BSTRPB– |
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P |
Connection point for the SPK_OUTB– bootstrap capacitor which is used to create a power supply for |
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BSTRPB+ |
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P |
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Connection point for the SPK_OUTB+ bootstrap capacitor which is used to create a power supply for |
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the high-side gate drive for SPK_OUTB+ |
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CN |
34 |
P |
Figure 14 |
Negative pin for capacitor connection used in the line-driver charge pump |
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CP |
32 |
P |
Figure 13 |
Positive pin for capacitor connection used in the line-driver charge pump |
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CPVDD |
31 |
P |
Figure 2 |
Power supply for charge pump circuitry |
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CPVSS |
35 |
P |
Figure 14 |
–3.3-V supply generated by charge pump for the DAC |
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DAC_OUTA |
13 |
AO |
Figure 8 |
Single-ended output for Channel A of the DAC |
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DAC_OUTB |
36 |
AO |
Single-ended output for Channel B of the DAC |
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DGND |
29 |
G |
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Ground reference for digital circuitry. Connect this pin to the system ground. |
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DVDD |
30 |
P |
Figure 2 |
Power supply for the internal digital circuitry |
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Voltage regulator derived from DVDD supply for use for internal digital circuitry. This pin is provided |
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DVDD_REG |
28 |
P |
Figure 15 |
as a connection point for filtering capacitors for this supply and must not be used to power any |
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external circuitry. |
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GND |
33 |
G |
— |
Ground pin for device. This pin should be connected to the system ground. |
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GPIO0 |
18 |
DI/O |
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General purpose input/output pins (GPIOx). Refer to GPIO registers for configuration. |
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GPIO2 |
21 |
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Voltage regulator derived from PVDD supply to generate the voltage required for the gate drive of |
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GVDD_REG |
8 |
P |
Figure 5 |
output MOSFETs. This pin is provided as a connection point for filtering capacitors for this supply and |
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|
|
|
must not be used to power any external circuitry. |
|
|
LRCK/FS |
25 |
DI/O |
|
Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ, and |
||
|
Figure 11 |
RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds |
|||||
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to the frame sync boundary. |
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||
|
MCLK |
22 |
DI |
|
Master clock used for internal clock tree and sub-circuit and state machine clocking |
||
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3 |
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PGND |
39 |
G |
— |
Ground reference for power device circuitry. Connect this pin to the system ground. |
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46 |
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6 |
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7 |
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PVDD |
41 |
P |
Figure 1 |
Power supply for internal power circuitry |
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42 |
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43 |
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19 |
DI |
Figure 17 |
Device reset input. Pull down to reset, pull up to activate device. |
|
|
RESET |
||||||
|
SCL |
17 |
DI |
Figure 10 |
I2C serial control port clock |
||
|
SCLK |
23 |
DI/O |
Figure 11 |
Bit clock for the digital signal that is active on the input data line of the serial data port |
||
|
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|
SDA |
16 |
DI/O |
Figure 9 |
I2C serial control port data |
||
|
SDIN |
24 |
D1 |
Figure 11 |
Data line to the serial data port |
||
|
SPK_INA– |
11 |
AI |
|
Negative pin for differential speaker amplifier input A |
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SPK_INA+ |
12 |
AI |
Figure 7 |
Positive pin for differential speaker amplifier input A |
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|
SPK_INB– |
38 |
AI |
Negative pin for differential speaker amplifier input B |
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||||||
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SPK_INB+ |
37 |
AI |
|
Positive pin for differential speaker amplifier input B |
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|
(1)AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P = Power, G = Ground (0 V)
(2)This pin should be connected to the system ground.
Copyright © 2016–2017, Texas Instruments Incorporated |
Submit Documentation Feedback |
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TAS5782M
SLASEG8A –MARCH 2016–REVISED JULY 2017 www.ti.com
|
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|
Pin Functions (continued) |
|
PIN |
|
TYPE(1) |
INTERNAL |
DESCRIPTION |
||
|
NAME |
NO. |
|
TERMINATION |
|
||
|
|
|
40 |
DO |
Figure 16 |
Fault pin which is pulled low when an overcurrent, overtemperature, or DC detect fault occurs |
|
|
SPK_FAULT |
||||||
|
SPK_GAIN/F |
9 |
AI |
Figure 6 |
Sets the gain and switching frequency of the speaker amplifier, latched in upon start-up of the device. |
||
|
REQ |
||||||
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SPK_OUTA– |
2 |
AO |
|
Negative pin for differential speaker amplifier output A |
||
|
SPK_OUTA+ |
4 |
AO |
Figure 4 |
Positive pin for differential speaker amplifier output A |
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SPK_OUTB– |
47 |
AO |
Negative pin for differential speaker amplifier output B |
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SPK_OUTB+ |
45 |
AO |
|
Positive pin for differential speaker amplifier output B |
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|
Speaker amplifier mute which must be pulled low (connected to DGND) to mute the device and |
|
SPK_MUTE |
27 |
I |
Figure 12 |
|||
|
pulled high (connected to DVDD) to unmute the device. |
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Provides both electrical and thermal connection from the device to the board. A matching ground pad |
|
PowerPAD |
— |
G |
— |
must be provided on the PCB and the device connected to it through solder. For proper electrical |
||
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operation, this ground pad must be connected to the system ground. |
PVDD |
DVDD |
30 V ESD |
3.3 V ESD |
Copyright © 2016, Texas Instruments Incorporated |
Copyright © 2016, Texas Instruments Incorporated |
Figure 1. PVDD Pins |
Figure 2. AVDD, DVDD and CPVDD Pins |
GVDD |
BSTRPxx |
PVDD |
|
|
7 V ESD |
|
SPK_OUTxx |
PVDD
SPK_OUTxx
Copyright © 2016, Texas Instruments Incorporated |
Copyright © 2016, Texas Instruments Incorporated |
Figure 3. BSTRPxx Pins |
Figure 4. SPK_OUTxx Pins |
6 |
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Copyright © 2016–2017, Texas Instruments Incorporated |
Product Folder Links: TAS5782M
|
TAS5782M |
www.ti.com |
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
Internal Pin Configurations (continued) |
|
|
GVDD |
PVDD |
|
10 Ÿ |
|
GVDD |
|
|
10 NŸ |
7 V ESD |
SPK_GAIN/FREQ |
|
|
|
7 V ESD |
Copyright © 2016, Texas Instruments Incorporated |
Copyright © 2016, Texas Instruments Incorporated |
|
Figure 5. GVDD_REG Pin |
Figure 6. SPK_GAIN/FREQ Pin |
SPK_INxx |
7 V ESD |
Gain Switch |
Copyright © 2016, Texas Instruments Incorporated
Figure 7. SPK_INxx Pins
AVDD
CPVSS
DAC_OUTA
Copyright © 2016, Texas Instruments Incorporated
Figure 8. DAC_OUTx Pins
DVDD |
SDA |
3.3 V |
ESD |
Copyright © 2016, Texas Instruments Incorporated
Figure 9. SDA Pin
DVDD |
SCL |
3.3 V |
ESD |
Copyright © 2016, Texas Instruments Incorporated
Figure 10. SCL Pin
Copyright © 2016–2017, Texas Instruments Incorporated |
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TAS5782M |
|
|
|
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
www.ti.com |
||
Internal Pin Configurations (continued) |
|
||
DVDD |
|
DVDD |
|
MCLK |
|
|
|
SCLK |
|
SPK_MUTE |
|
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|
||
SDIN |
3.3 V |
3.3 V |
|
ESD |
|||
|
|||
LRCK/FS |
ESD |
||
|
|||
|
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||
|
|
Copyright © 2016, Texas Instruments Incorporated |
Copyright © 2016, Texas Instruments Incorporated
Figure 11. SCLK, MCLK, SDIN, and LRCK/FS Pins |
Figure 12. SPK_MUTE Pin |
CVPDD
CP |
3.3 V |
ESD |
Copyright © 2016, Texas Instruments Incorporated
Figure 13. CP Pin
GND |
CN |
3.3 V |
ESD |
CPVSS |
3.3 V |
ESD |
Copyright © 2016, Texas Instruments Incorporated
Figure 14. CN and CPVSS Pins
DVDD
DVDD_REG |
1.8 V |
ESD |
Copyright © 2016, Texas Instruments Incorporated
Figure 15. DVDD_REG Pin
100 Ÿ |
SPK_FAULT |
28 V |
ESD |
Copyright © 2016, Texas Instruments Incorporated
Figure 16. SPK_FAULT Pin
8 |
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Copyright © 2016–2017, Texas Instruments Incorporated |
Product Folder Links: TAS5782M
TAS5782M
www.ti.com |
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
Internal Pin Configurations (continued)
DVDD |
RESET |
3.3 V |
ESD |
Copyright © 2016, Texas Instruments Incorporated
Figure 17. RESET Pin
Free-air room temperature 25°C (unless otherwise noted)(1)
|
|
|
|
MIN |
|
MAX |
UNIT |
|
DVDD, AVDD, |
Low-voltage digital, analog, charge pump supply |
–0.3 |
|
3.9 |
V |
|||
CPVDD |
|
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|
|
|
PVDD |
PVDD supply |
–0.3 |
|
30 |
V |
|||
VI(AmpCtrl) |
Input voltage for SPK_GAIN/FREQ and |
|
pins |
–0.3 |
VGVDD + 0.3 |
V |
||
SPK_FAULT |
||||||||
V |
DVDD referenced digital inputs(2) |
–0.5 |
V |
DVDD |
+ 0.5 |
V |
||
I(DigIn) |
|
|
|
|
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|
|
|
VI(SPK_INxx) |
Analog input into speaker amplifier |
–0.3 |
|
6.3 |
V |
|||
VI(SPK_OUTxx) |
Voltage at speaker output pins |
–0.3 |
|
32 |
V |
|||
|
Ambient operating temperature, TA |
–25 |
|
85 |
°C |
|||
TJ |
Operating junction temperature, digital die |
–40 |
|
125 |
°C |
|||
Operating junction temperature, power die |
–40 |
|
165 |
°C |
||||
|
|
|||||||
Tstg |
Storage temperature |
–40 |
|
125 |
°C |
(1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO2, LRCK/FS, MCLK, RESET, SCL, SCLK, SDA, SDIN, and SPK_MUTE.
|
|
|
VALUE |
UNIT |
|
V(ESD) |
Electrostatic |
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) |
±2000 |
V |
|
discharge |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) |
±500 |
|||
|
|
(1)JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
(2)JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2016–2017, Texas Instruments Incorporated |
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www.ti.com |
Free-air room temperature 25°C (unless otherwise noted)
|
|
|
MIN |
NOM |
MAX |
UNIT |
V(POWER) |
Power supply inputs |
DVDD, AVDD, CPVDD |
2.9 |
|
3.63 |
V |
PVDD |
4.5 |
|
26.4 |
|||
|
|
|
|
|||
RSPK |
Minimum speaker load |
BTL Mode |
3 |
|
|
Ω |
PBTL Mode |
2 |
|
|
Ω |
||
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|
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|
|||
V |
Input logic high for DVDD referenced digital inputs(1)(2) |
0.9 × V |
|
V |
V |
|
IH(DigIn) |
|
|
DVDD |
|
DVDD |
|
V |
Input logic low for DVDD referenced digital inputs(1)(3) |
V |
0 |
0.1 × V |
V |
|
IL(DigIn) |
|
|
DVDD |
|
DVDD |
|
LOUT |
Minimum inductor value in LC filter under short-circuit |
1 |
4.7 |
|
µH |
|
condition |
|
(1)DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO2, LRCK/FS, MCLK, RESET, SCL, SCLK, SDA, SDIN, and SPK_MUTE.
(2)The best practice for driving the input pins of the TAS5782M device is to power the drive circuit or pullup resistor from the same supply which provides the DVDD power supply.
(3)The best practice for driving the input pins of the TAS5782M device low is to pull them down, either actively or through pulldown resistors to the system ground.
|
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|
TAS5782M |
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|
DCA (TSSOP) |
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|
THERMAL METRIC(1) |
|
48 PINS |
|
UNIT |
|
|
JEDEC |
JEDEC |
|
TAS5782MEVM |
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|||
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|
STANDARD |
STANDARD |
|
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|
4-LAYER PCB |
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||
|
|
2-LAYER PCB |
4-LAYER PCB |
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|
||
RθJA |
Junction-to-ambient thermal resistance |
41.8 |
27.6 |
|
19.4 |
°C/W |
RθJC(top) |
Junction-to-case (top) thermal resistance |
14.4 |
14.4 |
|
14.4 |
°C/W |
RθJB |
Junction-to-board thermal resistance |
9.4 |
9.4 |
|
9.4 |
°C/W |
ψJT |
Junction-to-top characterization parameter |
0.6 |
0.6 |
|
2 |
°C/W |
ψJB |
Junction-to-board characterization parameter |
8.1 |
9.3 |
|
4.8 |
°C/W |
RθJC(bot) |
Junction-to-case (bottom) thermal resistance |
N/A |
N/A |
|
N/A |
°C/W |
(1)For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
10 |
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Copyright © 2016–2017, Texas Instruments Incorporated |
Product Folder Links: TAS5782M
TAS5782M
www.ti.com |
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5782MEVM board and Audio Precision System 2722 with Analog Analyzer filter set to 40 kHz brickwall filter. The device output PWM frequency was set to 768 kHz unless otherwise noted.
|
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
DIGITAL I/O |
|
|
|
|
|
|
|
Input logic high current level |
|
|
|
|
|
|IIH|1 |
for DVDD referenced digital |
VIN(DigIn) = VDVDD |
|
|
10 |
µA |
|
input pins(1) |
|
|
|
|
|
|
Input logic low current level |
|
|
|
|
|
|IIL|1 |
for DVDD referenced digital |
VIN(DigIn) = 0 V |
|
|
–10 |
µA |
|
input pins(1) |
|
|
|
|
|
|
Input logic high threshold for |
|
|
|
|
|
VIH1 |
DVDD referenced digital |
|
70% |
|
|
VDVDD |
|
inputs(1) |
|
|
|
|
|
|
Input logic low threshold for |
|
|
|
|
|
VIL1 |
DVDD referenced digital |
|
|
|
30% |
VDVDD |
|
inputs(1) |
|
|
|
|
|
VOH(DigOut) |
Output logic high voltage |
IOH = 4 mA |
80% |
|
|
VDVDD |
level(1) |
|
|
||||
VOL(DigOut) |
Output logic low voltage |
IOH = –4 mA |
|
|
22% |
VDVDD |
level(1) |
|
|
||||
VOL(SPK_FAULT) |
Output logic low voltage level |
With 100-kΩ pullup resistor |
|
|
0.8 |
V |
|
for SPK_FAULT |
|
|
|
|
|
GVDD_REG |
GVDD regulator voltage |
|
|
7 |
|
V |
|
|
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|
|
I2C CONTROL PORT |
|
|
|
|
|
|
CL(I2C) |
Allowable load capacitance |
|
|
|
400 |
pF |
for each I2C Line |
|
|
|
|||
fSCL(fast) |
Support SCL frequency |
No wait states, fast mode |
|
|
400 |
kHz |
fSCL(slow) |
Support SCL frequency |
No wait states, slow mode |
|
|
100 |
kHz |
|
Noise margin at High level for |
|
|
|
|
|
VNH |
each connected device |
|
0.2 × VDD |
|
|
V |
|
(including hysteresis) |
|
|
|
|
|
MCLK AND PLL SPECIFICATIONS |
|
|
|
|
|
|
DMCLK |
Allowable MCLK duty cycle |
|
40% |
|
60% |
|
fMCLK |
Supported MCLK frequencies |
Up to 50 MHz |
128 |
|
512 |
fS(2) |
|
|
Clock divider uses fractional divide |
6.7 |
|
20 |
|
|
|
D > 0, P = 1 |
|
|
||
fPLL |
PLL input frequency |
|
|
|
MHz |
|
Clock divider uses integer divide |
1 |
|
20 |
|||
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|
|||
|
|
D = 0, P = 1 |
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|
|
SERIAL AUDIO PORT |
|
|
|
|
|
|
tDLY |
Required LRCK/FS to SCLK |
|
5 |
|
|
ns |
rising edge delay |
|
|
|
|||
|
|
|
|
|
|
|
DSCLK |
Allowable SCLK duty cycle |
|
40% |
|
60% |
|
fS |
Supported input sample rates |
|
8 |
|
96 |
kHz |
fSCLK |
Supported SCLK frequencies |
|
32 |
|
64 |
fS(2) |
fSCLK |
SCLK frequency |
Either master mode or slave mode |
|
|
24.576 |
MHz |
SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS) |
|
|
|
|
||
|
|
SPK_GAIN/FREQ voltage < 3 V, |
|
|
|
|
|
|
see Adjustable Amplifier Gain and Switching |
|
20 |
|
|
AV(SPK_AMP) |
Speaker amplifier gain |
Frequency Selection |
|
|
|
dBV |
SPK_GAIN/FREQ voltage > 3.3 V, |
|
|
|
|||
|
|
see Adjustable Amplifier Gain and Switching |
|
26 |
|
|
|
|
Frequency Selection |
|
|
|
|
AV(SPK_AMP) |
Typical variation of speaker |
|
|
±1 |
|
dBV |
amplifier gain |
|
|
|
|||
|
|
|
|
|
|
(1)DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO2, LRCK/FS, MCLK,RESET, SCL, SCLK, SDA, SDIN, and SPK_MUTE.
(2)A unit of fS indicates that the specification is the value listed in the table multiplied by the sample rate of the audio used in the TAS5782M device.
Copyright © 2016–2017, Texas Instruments Incorporated |
Submit Documentation Feedback |
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SLASEG8A –MARCH 2016–REVISED JULY 2017 |
www.ti.com |
Electrical Characteristics (continued)
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5782MEVM board and Audio Precision System 2722 with Analog Analyzer filter set to 40 kHz brickwall filter. The device output PWM frequency was set to 768 kHz unless otherwise noted.
|
PARAMETER |
TEST CONDITIONS |
|
MIN |
TYP |
MAX |
UNIT |
|
|
Switching frequency depends on voltage |
|
|
|
|
|
|
Switching frequency of the |
presented at SPK_GAIN/FREQ pin and the |
|
|
|
|
|
fSPK_AMP |
clocking arrangement, including the incoming |
176.4 |
|
768 |
kHz |
||
speaker amplifier |
|
||||||
|
sample rate, see Adjustable Amplifier Gain and |
|
|
|
|
||
|
|
|
|
|
|
||
|
|
Switching Frequency Selection |
|
|
|
|
|
|
|
|
|
|
|
|
|
KSVR |
Power supply rejection ratio |
Injected Noise = 50 Hz to 60 Hz, 200 mVP-P, Gain |
|
60 |
|
dB |
|
= 26 dB, input audio signal = digital zero |
|
|
|
||||
|
|
|
|
|
|
|
|
|
Drain-to-source on resistance |
VPVDD = 24 V, I(SPK_OUT) = 500 mA, TJ = 25°C, |
|
120 |
|
|
|
|
includes PVDD/PGND pins, leadframe, bondwires |
|
|
|
|||
rDS(on) |
of the individual output |
and metallization layers. |
|
|
|
|
mΩ |
|
MOSFETs |
|
|
|
|
|
|
|
VPVDD = 24 V, I(SPK_OUT) = 500 mA, TJ = 25°C |
|
90 |
|
|
||
|
|
|
|
|
|||
OCETHRES |
SPK_OUTxx overcurrent |
|
|
|
7.5 |
|
A |
error threshold |
|
|
|
|
|||
|
|
|
|
|
|
|
|
OTETHRES |
Overtemperature error |
|
|
|
165 |
|
°C |
threshold |
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
Time required to clear |
|
|
|
|
|
|
OCECLRTIME |
overcurrent error after error |
|
|
|
1.3 |
|
s |
|
condition is removed. |
|
|
|
|
|
|
|
Time required to clear |
|
|
|
|
|
|
OTECLRTIME |
overtemperature error after |
|
|
|
1.3 |
|
s |
|
error condition is removed. |
|
|
|
|
|
|
OVETHRES(PVDD) |
PVDD overvoltage error |
|
|
|
27 |
|
V |
threshold |
|
|
|
|
|||
|
|
|
|
|
|
|
|
UVETHRES(PVDD) |
PVDD undervoltage error |
|
|
|
4.3 |
|
V |
threshold |
|
|
|
|
|||
|
|
|
|
|
|
|
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SPEAKER AMPLIFIER (STEREO BTL) |
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Measured differentially with zero input data, |
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SPK_GAIN/FREQ pin configured for 20 dB gain, |
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2 |
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|VOS| |
Amplifier offset voltage |
VPVDD = 12 V |
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mV |
Measured differentially with zero input data, |
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SPK_GAIN/FREQ pin configured for 26 dB gain, |
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5 |
15 |
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VPVDD = 24 V |
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VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK |
= 8 Ω, A- |
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49 |
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Weighted |
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VPVDD = 15 V, SPK_GAIN = 20 dB, RSPK |
= 8 Ω, A- |
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59 |
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Weighted |
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ICN(SPK) |
Idle channel noise |
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µVRMS |
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VPVDD = 19 V, SPK_GAIN = 26 dB, RSPK |
= 8 Ω, A- |
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81 |
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Weighted |
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VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK |
= 8 Ω, A- |
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82 |
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Weighted |
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VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK |
= 4 Ω, |
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14 |
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THD+N = 0.1% |
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VPVDD = 12 V, SPK_GAIN = 20 dB, RSPK |
= 8 Ω, |
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8 |
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THD+N = 0.1% |
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VPVDD = 15 V, SPK_GAIN = 26 dB, RSPK |
= 4 Ω, |
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23 |
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THD+N = 0.1% |
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VPVDD = 15 V, SPK_GAIN = 26 dB, RSPK |
= 8 Ω, |
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13 |
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THD+N = 0.1% |
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PO(SPK) |
Output Power (Per Channel) |
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W |
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VPVDD = 19 V, SPK_GAIN = 26 dB, RSPK |
= 4 Ω, |
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34 |
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THD+N = 0.1% |
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VPVDD = 19 V, SPK_GAIN = 26 dB, RSPK |
= 8 Ω, |
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20 |
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THD+N = 0.1% |
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VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK |
= 4 Ω, |
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40 |
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THD+N = 0.1% |
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VPVDD = 24 V, SPK_GAIN = 26 dB, RSPK |
= 8 Ω, |
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33 |
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THD+N = 0.1% |
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12 |
Submit Documentation Feedback |
Copyright © 2016–2017, Texas Instruments Incorporated |
Product Folder Links: TAS5782M
TAS5782M
www.ti.com |
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
Electrical Characteristics (continued)
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5782MEVM board and Audio Precision System 2722 with Analog Analyzer filter set to 40 kHz brickwall filter. The device output PWM frequency was set to 768 kHz unless otherwise noted.
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PARAMETER |
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TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
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VPVDD |
= 12 V, SPK_GAIN = |
20 dB, RSPK = 8 Ω, A- |
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103 |
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Weighted, –120 dBFS Input |
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Signal-to-noise ratio |
VPVDD = 15 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, A- |
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102 |
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Weighted, –120 dBFS Input |
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SNR |
(referenced to 0 dBFS input |
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dB |
VPVDD = 19 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, A- |
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signal) |
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103 |
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Weighted, –120 dBFS Input |
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VPVDD |
= 24 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, A- |
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105 |
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Weighted, –120 dBFS Input |
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VPVDD |
= 12 V, SPK_GAIN = |
20 dB, RSPK = 4 Ω, |
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0.021% |
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PO = 1 W, f = 1kHz |
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VPVDD |
= 12 V, SPK_GAIN = |
20 dB, RSPK = 8 Ω, |
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0.022% |
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PO = 1 W, f = 1kHz |
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VPVDD |
= 15 V, SPK_GAIN = |
26 dB, RSPK = 4 Ω, |
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0.02% |
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PO = 1 W, f = 1kHz |
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VPVDD |
= 15 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, |
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0.037% |
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Total harmonic distortion and |
PO = 1 W, f = 1kHz |
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THD+NSPK |
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noise |
VPVDD |
= 19 V, SPK_GAIN = |
26 dB, RSPK = 4 Ω, |
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0021% |
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PO = 1 W, f = 1kHz |
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VPVDD |
= 19 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, |
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0.028% |
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PO = 1 W, f = 1kHz |
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VPVDD |
= 24 V, SPK_GAIN = |
26 dB, RSPK = 4 Ω, |
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0.027% |
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PO = 1 W, f = 1kHz |
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VPVDD |
= 24 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, |
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0.038% |
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PO = 1 W, f = 1kHz |
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VPVDD = 12 V, SPK_GAIN = |
20 dB, RSPK = 8 Ω, |
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–90 |
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Input Signal 250 mVrms, |
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1-kHz Sine, across f(S) |
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VPVDD = 15 V, SPK_GAIN = |
26 dBV, RSPK = 8 Ω, |
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–102 |
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Cross-talk (worst case |
Input Signal 250 mVrms, |
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1-kHz Sine, across f(S) |
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X-talkSPK |
between left-to-right and |
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dB |
VPVDD = 19 V, SPK_GAIN = |
26 dBV, RSPK = 8 Ω, |
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right-to-left coupling) |
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–93 |
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Input Signal 250 mVrms, |
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1-kHz Sine, across f(S) |
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VPVDD = 24 V, SPK_GAIN = |
26 dBV, RSPK = 8 Ω, |
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–93 |
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Input Signal 250 mVrms, |
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1-kHz Sine, across f(S) |
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SPEAKER AMPLIFIER (MONO PBTL) |
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Measured differentially with zero input data, |
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SPK_GAIN/FREQ pin configured for 20 dB gain, |
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0.7 |
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|VOS| |
Amplifier offset voltage |
VPVDD |
= 12 V |
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mV |
Measured differentially with zero input data, |
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SPK_GAIN/FREQ pin configured for 26 dB gain, |
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4 |
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VPVDD = 24 V |
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VPVDD |
= 12 V, SPK_GAIN = |
20 dB, RSPK = 8 Ω, A- |
|
48 |
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Weighted |
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VPVDD |
= 15 V, SPK_GAIN = |
20 dB, RSPK = 8 Ω, |
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49 |
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A-Weighted |
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ICN |
Idle channel noise |
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µVRMS |
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VPVDD |
= 19 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, |
|
83 |
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A-Weighted |
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VPVDD |
= 24 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, A- |
|
82 |
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Weighted |
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Copyright © 2016–2017, Texas Instruments Incorporated |
Submit Documentation Feedback |
13 |
Product Folder Links: TAS5782M
TAS5782M
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
www.ti.com |
Electrical Characteristics (continued)
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5782MEVM board and Audio Precision System 2722 with Analog Analyzer filter set to 40 kHz brickwall filter. The device output PWM frequency was set to 768 kHz unless otherwise noted.
|
PARAMETER |
|
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
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VPVDD |
= 12 V, SPK_GAIN = |
20 dB, RSPK = 2 Ω, |
|
30 |
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THD+N = 0.1%, Unless otherwise noted |
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VPVDD |
= 12 V, SPK_GAIN = |
20 dB, RSPK = 4 Ω, |
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16 |
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THD+N = 0.1%, Unless otherwise noted |
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VPVDD |
= 12 V, SPK_GAIN = |
20 dB, RSPK = 8 Ω, |
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9 |
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THD+N = 0.1% |
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VPVDD |
= 15 V, SPK_GAIN = |
26 dB, RSPK = 2 Ω, |
|
44 |
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THD+N = 0.1%, Unless otherwise noted |
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VPVDD |
= 15 V, SPK_GAIN = |
26 dB, RSPK = 4 Ω, |
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22 |
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THD+N = 0.1%, Unless otherwise noted |
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VPVDD |
= 15 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, |
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13 |
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THD+N = 0.1% |
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PO |
Output power (per channel) |
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W |
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VPVDD |
= 19 V, SPK_GAIN = |
26 dB, RSPK = 2 Ω, |
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50 |
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THD+N = 0.1%, Unless otherwise noted |
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VPVDD |
= 19 V, SPK_GAIN = |
26 dB, RSPK = 4 Ω, |
|
36 |
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THD+N = 0.1%, Unless otherwise noted |
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VPVDD |
= 19 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, |
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20 |
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THD+N = 0.1% |
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VPVDD |
= 24 V, SPK_GAIN = |
26 dB, RSPK = 2 Ω, |
|
40 |
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THD+N = 0.1%, Unless otherwise noted |
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VPVDD |
= 24 V, SPK_GAIN = |
26 dB, RSPK = 4 Ω, |
|
61 |
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THD+N = 0.1%, Unless otherwise noted |
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VPVDD |
= 24 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, |
|
34 |
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THD+N = 0.1% |
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VPVDD |
= 12 V, SPK_GAIN = |
20 dB, RSPK = 8 Ω, A- |
|
105 |
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Weighted, –120 dBFS Input |
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Signal-to-noise ratio |
VPVDD = 15 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, A- |
|
104 |
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Weighted, –120 dBFS Input |
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SNR |
(referenced to 0 dBFS input |
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dB |
VPVDD = 19 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, A- |
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signal) |
|
105 |
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Weighted, –120 dBFS Input |
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VPVDD |
= 24 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, A- |
|
107 |
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Weighted, –120 dBFS Input |
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VPVDD |
= 12 V, SPK_GAIN = |
20 dB, RSPK = 2 Ω, |
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0.014% |
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PO = 1 W, f = 1kHz |
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VPVDD |
= 12 V, SPK_GAIN = |
20 dB, RSPK = 4 Ω, |
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0.011% |
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PO = 1 W, f = 1kHz |
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VPVDD |
= 12 V, SPK_GAIN = |
20 dB, RSPK = 8 Ω, |
|
0.014% |
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PO = 1 W, f = 1kHz |
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VPVDD |
= 15 V, SPK_GAIN = |
26 dB, RSPK = 2 Ω, |
|
0.015% |
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PO = 1 W, f = 1kHz |
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VPVDD |
= 15 V, SPK_GAIN = |
26 dB, RSPK = 4 Ω, |
|
0.013% |
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PO = 1 W, f = 1kHz |
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|
Total harmonic distortion and |
VPVDD |
= 15 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, |
|
0.015% |
|
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THD+N |
PO = 1 W, f = 1kHz |
|
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noise |
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VPVDD |
= 19 V, SPK_GAIN = |
26 dB, RSPK = 2 Ω, |
|
0.018% |
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PO = 1 W, f = 1kHz |
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V, RSPK = 4 Ω, PO = 1 W, f = 1kHz |
|
0.012% |
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VPVDD |
= 19 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, |
|
0.020% |
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PO = 1 W, f = 1kHz |
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VPVDD |
= 24 V, SPK_GAIN = |
26 dB, RSPK = 2 Ω, |
|
0.028% |
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PO = 1 W, f = 1kHz |
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VPVDD |
= 24 V, SPK_GAIN = |
26 dB, RSPK = 4 Ω, |
|
0.02% |
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PO = 1 W, f = 1kHz |
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VPVDD |
= 24 V, SPK_GAIN = |
26 dB, RSPK = 8 Ω, |
|
0.027% |
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PO = 1 W, f = 1kHz |
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|
14 |
Submit Documentation Feedback |
Copyright © 2016–2017, Texas Instruments Incorporated |
Product Folder Links: TAS5782M
TAS5782M
www.ti.com |
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
Free-air room temperature 25°C (unless otherwise noted)
VPVDD |
SPK_GAIN(1)(2)(3) |
fSPK_AMP |
STATE OF |
RSPK |
IPVDD(4) |
IDVDD(5) |
PDISS |
(V) |
(dBV) |
(kHz) |
OPERATION |
(Ω) |
(mA) |
(mA) |
(W) |
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|
4 |
21.30 |
59.70 |
0.355 |
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Idle |
6 |
21.33 |
59.68 |
0.355 |
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8 |
21.30 |
59.70 |
0.355 |
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4 |
21.33 |
58.82 |
0.352 |
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Mute |
6 |
21.34 |
58.81 |
0.352 |
|
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384 |
|
8 |
21.36 |
58.81 |
0.352 |
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4 |
2.08 |
12.41 |
0.056 |
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Standby |
6 |
2.11 |
12.41 |
0.057 |
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8 |
2.17 |
12.41 |
0.057 |
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4 |
2.03 |
0.730 |
0.017 |
|
|
|
Powerdown |
6 |
2.04 |
0.740 |
0.018 |
7.4 |
20 |
|
|
8 |
2.06 |
0.740 |
0.018 |
|
|
4 |
27.48 |
59.7 |
0.400 |
||
|
|
|
|
||||
|
|
|
Idle |
6 |
27.49 |
59.73 |
0.401 |
|
|
|
|
8 |
24.46 |
59.72 |
0.378 |
|
|
|
|
4 |
27.50 |
58.8 |
0.398 |
|
|
|
Mute |
6 |
27.51 |
58.8 |
0.398 |
|
|
768 |
|
8 |
27.52 |
58.81 |
0.398 |
|
|
|
4 |
2.04 |
12.41 |
0.056 |
|
|
|
|
|
||||
|
|
|
Standby |
6 |
2.08 |
12.41 |
0.056 |
|
|
|
|
8 |
2.11 |
12.41 |
0.057 |
|
|
|
|
4 |
2.06 |
0.73 |
0.018 |
|
|
|
Powerdown |
6 |
2.07 |
0.74 |
0.018 |
|
|
|
|
8 |
2.08 |
0.74 |
0.018 |
(1)Mute: B0-P0-R3-D0,D4 = 1
(2)Standby: B0-P0-R2-D4 = 1
(3)Power down: B0-P0-R2-D0 = 1
(4)IPVDD refers to all current that flows through the PVDD supply for the DUT. Any other current sinks not directly related to the DUT current draw were removed.
(5)IDVDD refers to all current that flows through the DVDD (3.3-V) supply for the DUT. Any other current sinks not directly related to the DUT current draw were removed.
Copyright © 2016–2017, Texas Instruments Incorporated |
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TAS5782M
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www.ti.com |
Power Dissipation Characteristics (continued)
Free-air room temperature 25°C (unless otherwise noted)
VPVDD |
SPK_GAIN(1)(2)(3) |
fSPK_AMP |
STATE OF |
RSPK |
IPVDD(4) |
IDVDD(5) |
PDISS |
(V) |
(dBV) |
(kHz) |
OPERATION |
(Ω) |
(mA) |
(mA) |
(W) |
|
|
|
|
4 |
24.33 |
59.74 |
0.467 |
|
|
|
Idle |
6 |
24.32 |
59.74 |
0.467 |
|
|
|
|
8 |
24.36 |
59.70 |
0.467 |
|
|
|
|
4 |
24.36 |
58.81 |
0.464 |
|
|
|
Mute |
6 |
24.32 |
58.82 |
0.464 |
|
|
384 |
|
8 |
24.37 |
58.84 |
0.465 |
|
|
|
4 |
3.58 |
12.40 |
0.081 |
|
|
|
|
|
||||
|
|
|
Standby |
6 |
3.57 |
12.41 |
0.081 |
|
|
|
|
8 |
3.58 |
12.42 |
0.081 |
|
|
|
|
4 |
3.52 |
0.74 |
0.042 |
|
|
|
Powerdown |
6 |
3.52 |
0.74 |
0.042 |
11.1 |
20 |
|
|
8 |
3.54 |
0.74 |
0.042 |
|
|
4 |
30.70 |
59.70 |
0.538 |
||
|
|
|
|
||||
|
|
|
Idle |
6 |
30.65 |
59.72 |
0.537 |
|
|
|
|
8 |
30.67 |
59.71 |
0.537 |
|
|
|
|
4 |
3.072 |
58.80 |
0.528 |
|
|
|
Mute |
6 |
30.69 |
58.81 |
0.535 |
|
|
768 |
|
8 |
30.69 |
58.81 |
0.535 |
|
|
|
4 |
3.54 |
12.40 |
0.080 |
|
|
|
|
|
||||
|
|
|
Standby |
6 |
3.54 |
12.41 |
0.080 |
|
|
|
|
8 |
3.58 |
12.42 |
0.081 |
|
|
|
|
4 |
3.53 |
0.74 |
0.042 |
|
|
|
Powerdown |
6 |
3.53 |
0.74 |
0.042 |
|
|
|
|
8 |
3.55 |
0.74 |
0.042 |
16 |
Submit Documentation Feedback |
Copyright © 2016–2017, Texas Instruments Incorporated |
Product Folder Links: TAS5782M
TAS5782M
www.ti.com |
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
Power Dissipation Characteristics (continued)
Free-air room temperature 25°C (unless otherwise noted)
VPVDD |
SPK_GAIN(1)(2)(3) |
fSPK_AMP |
STATE OF |
RSPK |
IPVDD(4) |
IDVDD(5) |
PDISS |
(V) |
(dBV) |
(kHz) |
OPERATION |
(Ω) |
(mA) |
(mA) |
(W) |
|
|
|
|
4 |
25.07 |
59.72 |
0.498 |
|
|
|
Idle |
6 |
25.08 |
59.73 |
0.498 |
|
|
|
|
8 |
25.10 |
59.71 |
0.498 |
|
|
|
|
4 |
25.12 |
58.84 |
0.496 |
|
|
|
Mute |
6 |
25.08 |
58.82 |
0.495 |
|
|
384 |
|
8 |
25.11 |
58.82 |
0.495 |
|
|
|
4 |
3.92 |
12.40 |
0.088 |
|
|
|
|
|
||||
|
|
|
Standby |
6 |
3.93 |
12.41 |
0.088 |
|
|
|
|
8 |
3.94 |
12.41 |
0.088 |
|
|
|
|
4 |
3.87 |
0.75 |
0.049 |
|
|
|
Powerdown |
6 |
3.85 |
0.74 |
0.049 |
12 |
20 |
|
|
8 |
3.87 |
0.75 |
0.049 |
|
|
4 |
31.31 |
59.72 |
0.573 |
||
|
|
|
|
||||
|
|
|
Idle |
6 |
31.29 |
59.71 |
0.573 |
|
|
|
|
8 |
31.31 |
59.74 |
0.573 |
|
|
|
|
4 |
31.31 |
58.80 |
0.570 |
|
|
|
Mute |
6 |
31.33 |
58.81 |
0.570 |
|
|
768 |
|
8 |
31.32 |
58.81 |
0.570 |
|
|
|
4 |
3.88 |
12.40 |
0.087 |
|
|
|
|
|
||||
|
|
|
Standby |
6 |
3.90 |
12.41 |
0.088 |
|
|
|
|
8 |
3.91 |
12.41 |
0.088 |
|
|
|
|
4 |
3.89 |
0.75 |
0.049 |
|
|
|
Powerdown |
6 |
3.91 |
0.74 |
0.049 |
|
|
|
|
8 |
3.88 |
0.75 |
0.049 |
Copyright © 2016–2017, Texas Instruments Incorporated |
Submit Documentation Feedback |
17 |
Product Folder Links: TAS5782M
TAS5782M
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
www.ti.com |
Power Dissipation Characteristics (continued)
Free-air room temperature 25°C (unless otherwise noted)
VPVDD |
SPK_GAIN(1)(2)(3) |
fSPK_AMP |
STATE OF |
RSPK |
IPVDD(4) |
IDVDD(5) |
PDISS |
(V) |
(dBV) |
(kHz) |
OPERATION |
(Ω) |
(mA) |
(mA) |
(W) |
|
|
|
|
4 |
27.94 |
59.73 |
0.616 |
|
|
|
Idle |
6 |
27.91 |
59.75 |
0.616 |
|
|
|
|
8 |
27.75 |
59.69 |
0.613 |
|
|
|
|
4 |
27.98 |
58.84 |
0.614 |
|
|
|
Mute |
6 |
27.94 |
58.87 |
0.613 |
|
|
384 |
|
8 |
27.88 |
58.85 |
0.612 |
|
|
|
4 |
5.09 |
12.41 |
0.117 |
|
|
|
|
|
||||
|
|
|
Standby |
6 |
5.12 |
12.41 |
0.118 |
|
|
|
|
8 |
5.19 |
12.41 |
0.119 |
|
|
|
|
4 |
5.02 |
0.74 |
0.078 |
|
|
|
Powerdown |
6 |
5.06 |
0.74 |
0.078 |
15 |
26 |
|
|
8 |
5.14 |
0.74 |
0.080 |
|
|
4 |
33.05 |
59.7 |
0.693 |
||
|
|
|
|
||||
|
|
|
Idle |
6 |
33.03 |
59.72 |
0.693 |
|
|
|
|
8 |
33.08 |
59.68 |
0.693 |
|
|
|
|
4 |
33.03 |
58.81 |
0.690 |
|
|
|
Mute |
6 |
33.04 |
58.81 |
0.690 |
|
|
768 |
|
8 |
33.05 |
58.80 |
0.690 |
|
|
|
4 |
5.07 |
12.41 |
0.117 |
|
|
|
|
|
||||
|
|
|
Standby |
6 |
5.09 |
12.41 |
0.117 |
|
|
|
|
8 |
5.14 |
12.41 |
0.118 |
|
|
|
|
4 |
5.02 |
0.74 |
0.078 |
|
|
|
Powerdown |
6 |
5.04 |
0.74 |
0.078 |
|
|
|
|
8 |
5.09 |
0.74 |
0.079 |
18 |
Submit Documentation Feedback |
Copyright © 2016–2017, Texas Instruments Incorporated |
Product Folder Links: TAS5782M
TAS5782M
www.ti.com |
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
Power Dissipation Characteristics (continued)
Free-air room temperature 25°C (unless otherwise noted)
VPVDD |
SPK_GAIN(1)(2)(3) |
fSPK_AMP |
STATE OF |
RSPK |
IPVDD(4) |
IDVDD(5) |
PDISS |
(V) |
(dBV) |
(kHz) |
OPERATION |
(Ω) |
(mA) |
(mA) |
(W) |
|
|
|
|
4 |
32.27 |
59.77 |
0.830 |
|
|
|
Idle |
6 |
32.19 |
59.76 |
0.828 |
|
|
|
|
8 |
32.08 |
59.75 |
0.826 |
|
|
|
|
4 |
32.27 |
58.85 |
0.827 |
|
|
|
Mute |
6 |
32.24 |
58.87 |
0.826 |
|
|
384 |
|
8 |
32.22 |
58.86 |
0.826 |
|
|
|
4 |
6.95 |
12.40 |
0.177 |
|
|
|
|
|
||||
|
|
|
Standby |
6 |
6.93 |
12.42 |
0.177 |
|
|
|
|
8 |
7.00 |
12.41 |
0.178 |
|
|
|
|
4 |
6.89 |
0.74 |
0.137 |
|
|
|
Powerdown |
6 |
6.90 |
0.74 |
0.138 |
19.6 |
26 |
|
|
8 |
6.96 |
0.73 |
0.139 |
|
|
4 |
34.99 |
59.74 |
0.883 |
||
|
|
|
|
||||
|
|
|
Idle |
6 |
34.95 |
59.74 |
0.882 |
|
|
|
|
8 |
34.97 |
59.71 |
0.882 |
|
|
|
|
4 |
34.96 |
58.85 |
0.879 |
|
|
|
Mute |
6 |
34.98 |
58.83 |
0.880 |
|
|
768 |
|
8 |
34.96 |
58.81 |
0.879 |
|
|
|
4 |
6.93 |
12.40 |
0.177 |
|
|
|
|
|
||||
|
|
|
Standby |
6 |
6.93 |
12.42 |
0.177 |
|
|
|
|
8 |
6.98 |
12.41 |
0.178 |
|
|
|
|
4 |
6.84 |
0.74 |
0.137 |
|
|
|
Powerdown |
6 |
6.89 |
0.74 |
0.137 |
|
|
|
|
8 |
6.90 |
0.73 |
0.138 |
Copyright © 2016–2017, Texas Instruments Incorporated |
Submit Documentation Feedback |
19 |
Product Folder Links: TAS5782M
TAS5782M
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
www.ti.com |
Power Dissipation Characteristics (continued)
Free-air room temperature 25°C (unless otherwise noted)
VPVDD |
SPK_GAIN(1)(2)(3) |
fSPK_AMP |
STATE OF |
RSPK |
IPVDD(4) |
IDVDD(5) |
PDISS |
(V) |
(dBV) |
(kHz) |
OPERATION |
(Ω) |
(mA) |
(mA) |
(W) |
|
|
|
|
4 |
36.93 |
59.80 |
1.084 |
|
|
|
Idle |
6 |
36.87 |
59.81 |
1.082 |
|
|
|
|
8 |
36.77 |
59.76 |
1.080 |
|
|
|
|
4 |
36.94 |
58.91 |
1.081 |
|
|
|
Mute |
6 |
36.89 |
58.89 |
1.080 |
|
|
384 |
|
8 |
36.85 |
58.90 |
1.079 |
|
|
|
4 |
8.73 |
12.40 |
0.250 |
|
|
|
|
|
||||
|
|
|
Standby |
6 |
8.72 |
12.40 |
0.250 |
|
|
|
|
8 |
8.71 |
12.40 |
0.250 |
|
|
|
|
4 |
8.64 |
0.74 |
0.210 |
|
|
|
Powerdown |
6 |
8.66 |
0.74 |
0.210 |
24 |
26 |
|
|
8 |
8.69 |
0.73 |
0.211 |
|
|
4 |
36.84 |
59.73 |
1.081 |
||
|
|
|
|
||||
|
|
|
Idle |
6 |
36.86 |
59.76 |
1.082 |
|
|
|
|
8 |
36.83 |
59.78 |
1.081 |
|
|
|
|
4 |
36.85 |
58.85 |
1.079 |
|
|
|
Mute |
6 |
36.84 |
58.84 |
1.078 |
|
|
768 |
|
8 |
36.82 |
58.83 |
1.078 |
|
|
|
4 |
8.66 |
12.40 |
0.249 |
|
|
|
|
|
||||
|
|
|
Standby |
6 |
8.68 |
12.40 |
0.249 |
|
|
|
|
8 |
8.71 |
12.40 |
0.250 |
|
|
|
|
4 |
8.63 |
0.74 |
0.210 |
|
|
|
Powerdown |
6 |
8.64 |
0.74 |
0.210 |
|
|
|
|
8 |
8.65 |
0.73 |
0.210 |
See Figure 18.
|
|
MIN NOM |
MAX |
UNIT |
tMCLK |
MCLK period |
20 |
1000 |
ns |
tMCLKH |
MCLK pulse width, high |
9 |
|
ns |
tMCLKL |
MCLK pulse width, low |
9 |
|
ns |
See Figure 19.
|
|
|
MIN |
NOM |
MAX |
UNIT |
fSCLK |
SCLK frequency |
|
1.024 |
|
|
MHz |
tSCLK |
SCLK period |
|
40 |
|
|
ns |
tSCLKL |
SCLK pulse width, low |
|
16 |
|
|
ns |
tSCLKH |
SCLK pulse width, high |
|
16 |
|
|
ns |
tSL |
SCLK rising to LRCK/FS edge |
|
8 |
|
|
ns |
tLS |
LRCK/FS Edge to SCLK rising edge |
|
8 |
|
|
ns |
tSU |
Data setup time, before SCLK rising edge |
|
8 |
|
|
ns |
tDH |
Data hold time, after SCLK rising edge |
|
8 |
|
|
ns |
tDFS |
Data delay time from SCLK falling edge |
|
|
|
15 |
ns |
|
|
|
|
|
|
|
20 |
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||||
|
|
Product Folder Links: TAS5782M |
|
|
|
TAS5782M
www.ti.com SLASEG8A –MARCH 2016–REVISED JULY 2017
See Figure 20.
|
|
MIN NOM |
MAX |
UNIT |
tSCLK |
SCLK period |
40 |
|
ns |
tSCLKL |
SCLK pulse width, low |
16 |
|
ns |
tSCLKH |
SCLK pulse width, high |
16 |
|
ns |
tLRD |
LRCK/FS delay time from to SCLK falling edge |
–10 |
20 |
ns |
tSU |
Data setup time, before SCLK rising edge |
8 |
|
ns |
tDH |
Data hold time, after SCLK rising edge |
8 |
|
ns |
tDFS |
Data delay time from SCLK falling edge |
|
15 |
ns |
|
|
MIN |
MAX |
UNIT |
fSCL |
SCL clock frequency |
|
100 |
kHz |
tBUF |
Bus free time between a STOP and START condition |
4.7 |
|
µs |
tLOW |
Low period of the SCL clock |
4.7 |
|
µs |
tHI |
High period of the SCL clock |
4 |
|
µs |
tRS-SU |
Setup time for (repeated) START condition |
4.7 |
|
µs |
tS-HD |
Hold time for (repeated) START condition |
4 |
|
µs |
tD-SU |
Data setup time |
250 |
|
ns |
tD-HD |
Data hold time |
0 |
900 |
ns |
tSCL-R |
Rise time of SCL signal |
20 + 0.1CB |
1000 |
ns |
tSCL-R1 |
Rise time of SCL signal after a repeated START condition and after an acknowledge bit |
20 + 0.1CB |
1000 |
ns |
tSCL-F |
Fall time of SCL signal |
20 + 0.1CB |
1000 |
ns |
tSDA-R |
Rise time of SDA signal |
20 + 0.1CB |
1000 |
ns |
tSDA-F |
Fall time of SDA signal |
20 + 0.1CB |
1000 |
ns |
tP-SU |
Setup time for STOP condition |
4 |
|
µs |
See Figure 21.
|
|
MIN |
MAX |
UNIT |
fSCL |
SCL clock frequency |
|
400 |
kHz |
tBUF |
Bus free time between a STOP and START condition |
1.3 |
|
µs |
tLOW |
Low period of the SCL clock |
1.3 |
|
µs |
tHI |
High period of the SCL clock |
600 |
|
ns |
tRS-SU |
Setup time for (repeated)START condition |
600 |
|
ns |
tRS-HD |
Hold time for (repeated)START condition |
600 |
|
ns |
tD-SU |
Data setup time |
100 |
|
ns |
tD-HD |
Data hold time |
0 |
900 |
ns |
tSCL-R |
Rise time of SCL signal |
20 + 0.1CB |
300 |
ns |
tSCL-R1 |
Rise time of SCL signal after a repeated START condition and after an acknowledge bit |
20 + 0.1CB |
300 |
ns |
tSCL-F |
Fall time of SCL signal |
20 + 0.1CB |
300 |
ns |
tSDA-R |
Rise time of SDA signal |
20 + 0.1CB |
300 |
ns |
tSDA-F |
Fall time of SDA signal |
20 + 0.1CB |
300 |
ns |
tP-SU |
Setup time for STOP condition |
600 |
|
ns |
tSP |
Pulse width of spike suppressed |
|
50 |
ns |
Copyright © 2016–2017, Texas Instruments Incorporated |
Submit Documentation Feedback |
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See Figure 22.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MIN |
MAX |
UNIT |
tr |
Rise time |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
20 |
ns |
tf |
Fall time |
|
|
|
|
|
|
|
|
|
|
|
|
|
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ns |
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tMCLKH |
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"H" |
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0.7 × V DVDD |
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"L" |
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0.3 × V DVDD |
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tMCLKL |
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tMCLK |
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Figure 18. Timing Requirements for MCLK Input
LRCK/FS |
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(Input) |
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tSCLKH |
tSCLKL |
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SCLK |
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(Input) |
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tSCLK |
tSL |
DATA |
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(Input) |
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tSU |
tDH |
DATA |
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(Output) |
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tLS
tDFS
0.5 × DVDD
0.5 × DVDD
0.5 × DVDD
0.5 × DVDD
Figure 19. Serial Audio Port Timing in Slave Mode
22 |
Submit Documentation Feedback |
Copyright © 2016–2017, Texas Instruments Incorporated |
Product Folder Links: TAS5782M
|
|
TAS5782M |
www.ti.com |
|
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
tSCLK. |
ttBCL |
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SCLK |
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0.5 × DVDD |
(Input) |
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tSCLK |
tLRD |
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LRCK/FS |
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(Input) |
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0.5 × DVDD |
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tDFS |
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DATA |
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0.5 × DVDD |
(Input) |
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tSU |
tDH |
DATA |
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0.5 × DVDD |
(Output) |
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Figure 20. Serial Audio Port Timing in Master Mode
START |
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tD-SU |
tD-HD |
tBUF. |
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SDA |
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tSCL-R. |
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SCL |
tLOW. |
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tHI. |
tS-HD. |
tSCL-F. |
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Repeated |
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START |
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STOP |
tSDA-R |
tSDA-F |
tP-SU |
tRS-HD |
tSP |
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tRS-SU
Figure 21. I2C Communication Port Timing Diagram
0.9 × DV DD
0.1 × DV DD
SPK_MUTE |
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tr |
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tf |
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< 20 ns |
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<20nsns |
Figure 22. SPK_MUTE Timing Diagram for Soft Mute Operation via Hardware Pin
Copyright © 2016–2017, Texas Instruments Incorporated |
Submit Documentation Feedback |
23 |
Product Folder Links: TAS5782M
TAS5782M
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
www.ti.com |
All performance plots were taken using the TAS5782MEVM Board at room temperature, unless otherwise noted. The term "traditional LC filter" refers to the output filter that is present by default on the TAS5782MEVM Board.
Table 1. Quick Reference Table
OUTPUT |
PLOT TITLE |
FIGURE NUMBER |
|
CONFIGURATIONS |
|||
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Frequency Response |
Figure 42 |
|
|
Output Power vs PVDD |
Figure 23 |
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THD+N vs Frequency, VPVDD = 12 V |
Figure 24 |
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THD+N vs Frequency, VPVDD = 15 V |
Figure 25 |
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THD+N vs Frequency, VPVDD = 18 V |
Figure 26 |
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THD+N vs Frequency, VPVDD = 24 V |
Figure 27 |
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THD+N vs Power, VPVDD = 12 V |
Figure 28 |
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THD+N vs Power, VPVDD = 15 V |
Figure 29 |
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THD+N vs Power, VPVDD = 18 V |
Figure 30 |
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THD+N vs Power, VPVDD = 24 V |
Figure 31 |
|
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Idle Channel Noise vs PVDD |
Figure 32 |
|
Bridge Tied Load (BTL) |
Efficiency vs Output Power |
Figure 33 |
|
Configuration Curves |
Efficiency vs Output Power |
Figure 34 |
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Efficiency vs Output Power |
Figure 35 |
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Idle Current Draw (Filterless) vs PVDD |
Figure 36 |
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Crosstalk vs. Frequency |
Figure 37 |
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PVDD PSRR vs Frequency |
Figure 38 |
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DVDD PSRR vs Frequency |
Figure 39 |
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AVDD PSRR vs Frequency |
Figure 40 |
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CPVDD PSRR vs Frequency |
Figure 41 |
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THD+N vs Frequency, VPVDD = 12 V |
Figure 43 |
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THD+N vs Frequency, VPVDD = 15 V |
Figure 44 |
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THD+N vs Frequency, VPVDD = 18 V |
Figure 45 |
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THD+N vs Frequency, VPVDD = 24 V |
Figure 46 |
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Output Power vs PVDD |
Figure 47 |
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THD+N vs Frequency, VPVDD = 12 V |
Figure 48 |
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THD+N vs Frequency, VPVDD = 15 V |
Figure 49 |
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THD+N vs Frequency, VPVDD = 18 V |
Figure 50 |
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THD+N vs Frequency, VPVDD = 24 V |
Figure 51 |
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THD+N vs Power, VPVDD = 12 V |
Figure 52 |
|
Parallel Bridge Tied Load |
THD+N vs Power, VPVDD = 15 V |
Figure 53 |
|
THD+N vs Power, VPVDD = 18 V |
Figure 54 |
||
(PBTL) Configuration |
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THD+N vs Power, VPVDD = 24 V |
Figure 55 |
||
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|||
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Idle Channel Noise vs PVDD |
Figure 56 |
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Efficiency vs Output Power |
Figure 57 |
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THD+N vs Frequency, VPVDD = 12 V |
Figure 60 |
|
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THD+N vs Frequency, VPVDD = 15 V |
Figure 61 |
|
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THD+N vs Frequency, VPVDD = 18 V |
Figure 62 |
|
|
THD+N vs Frequency, VPVDD = 24 V |
Figure 63 |
24 |
Submit Documentation Feedback |
Copyright © 2016–2017, Texas Instruments Incorporated |
Product Folder Links: TAS5782M
TAS5782M
www.ti.com |
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5782MEVM board and Audio Precision System 2722 with Analog Analyzer filter set to 40-kHz brickwall filter. All measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 768 kHz, unless otherwise noted. For both the BTL plots and the PBTL plots, the LC filter used was 4.7 µH / 0.68 µF. Return to
Quick Reference Table.
|
80 |
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10 |
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8 : Load Peak |
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4 : Load |
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6 : Load Peak |
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6 : Load |
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4 : Load Peak |
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8 : Load |
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60 |
6 : Load Continous |
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1 |
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4 : Load Continous |
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40 |
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<![if ! IE]> <![endif]>THD+N (%) |
0.1 |
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<![if ! IE]> <![endif]>OutputPower(W) |
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20 |
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0.01 |
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0 |
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0.001 |
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5 |
10 |
15 |
20 |
24 |
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20 |
100 |
1k |
10k |
40k |
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Supply Voltage (V) |
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D002 |
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Frequency (Hz) |
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D003 |
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AV(SPK_AMP) = 26 dBV |
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AV(SPK_AMP) = 20 dBV |
PO = 1 W |
VPVDD = 12 V |
||||
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Figure 23. Output Power vs PVDD – BTL |
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Figure 24. THD+N vs Frequency – BTL |
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10 |
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10 |
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4 : Load |
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4 : Load |
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6 : Load |
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6 : Load |
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8 : Load |
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8 : Load |
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1 |
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1 |
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<![if ! IE]> <![endif]>(%) |
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<![if ! IE]> <![endif]>(%) |
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<![if ! IE]> <![endif]>THD+N |
0.1 |
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<![if ! IE]> <![endif]>THD+N |
0.1 |
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0.01 |
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0.01 |
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0.001 |
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0.001 |
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20 |
100 |
1k |
10k |
40k |
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20 |
100 |
1k |
10k |
40k |
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Frequency (Hz) |
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D004 |
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Frequency (Hz) |
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D005 |
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AV(SPK_AMP) = 20 dBV |
PO = 1 W |
VPVDD = 15 V |
AV(SPK_AMP) = 26 dBV |
PO = 1 W |
VPVDD = 18 V |
||||||
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Figure 25. THD+N vs Frequency – BTL |
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Figure 26. THD+N vs Frequency – BTL |
|
Copyright © 2016–2017, Texas Instruments Incorporated |
Submit Documentation Feedback |
25 |
Product Folder Links: TAS5782M
TAS5782M |
|
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SLASEG8A –MARCH 2016–REVISED JULY 2017 |
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www.ti.com |
|||
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10 |
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10 |
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4 : Load |
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<![if ! IE]> <![endif]>(%) |
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4 : Load |
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6 : Load |
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6 : Load |
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8 : Load |
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<![if ! IE]> <![endif]>+ Noise |
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8 : Load |
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1 |
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1 |
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<![if ! IE]> <![endif]>THD+N (%) |
0.1 |
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<![if ! IE]> <![endif]>Harmonic Distortion |
0.1 |
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0.01 |
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0.01 |
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<![if ! IE]> <![endif]>Total |
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0.001 |
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0.001 |
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20 |
100 |
1k |
10k |
40k |
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10m |
100m |
1 |
10 |
30 |
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Frequency (Hz) |
|
D006 |
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Output Power (W) |
|
D007 |
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AV(SPK_AMP) = 26 dBV |
PO = 1 W |
VPVDD = 24 V |
AV(SPK_AMP) = 20 dBV |
|
VPVDD = 12 V |
||||||
|
|
Figure 27. THD+N vs Frequency – BTL |
|
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Figure 28. THD+N vs Power – BTL |
|
||||
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10 |
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10 |
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<![if ! IE]> <![endif]>(%) |
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4 : Load |
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<![if ! IE]> <![endif]>(%) |
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4 : Load |
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6 : Load |
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6 : Load |
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<![if ! IE]> <![endif]>+ Noise |
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8 : Load |
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<![if ! IE]> <![endif]>+ Noise |
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8 : Load |
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1 |
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1 |
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<![if ! IE]> <![endif]>Distortion |
0.1 |
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<![if ! IE]> <![endif]>Distortion |
0.1 |
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<![if ! IE]> <![endif]>Total Harmonic |
0.01 |
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<![if ! IE]> <![endif]>Total Harmonic |
0.01 |
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0.001 |
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0.001 |
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10m |
100m |
1 |
10 |
40 |
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10m |
100m |
1 |
10 |
50 |
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Output Power (W) |
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D008 |
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Output Power (W) |
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D009 |
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AV(SPK_AMP) = 20 |
|
VPVDD = 15 V |
AV(SPK_AMP) = 26 |
|
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VPVDD = |
|||||
dBV |
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dBV |
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18 V |
||
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Figure 29. THD+N vs Power – BTL |
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Figure 30. THD+N vs Power – BTL |
|
||||
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10 |
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100 |
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<![if ! IE]> <![endif]>(%) |
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4 : Load |
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90 |
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6 : Load |
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<![if ! IE]> <![endif]>Harmonic Distortion + Noise |
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8 : Load |
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<![if ! IE]> <![endif]>IdleChannel Noise (PVrms) |
80 |
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0.1 |
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50 |
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40 |
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0.01 |
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30 |
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20 |
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Gain = 20 dB, PWM Freq = 384 kHz |
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Gain = 26 dB, PWM Freq = 384 kHz |
|||||
<![if ! IE]> <![endif]>Total |
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10 |
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Gain = 20 dB, PWM Freq = 768 kHz |
|||
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0 |
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Gain = 26 dB, PWM Freq = 768 kHz |
||
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0.001 |
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10 |
15 |
20 |
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10m |
100m |
1 |
10 |
50 |
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Output Power (W) |
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D010 |
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Supply Voltage (V) |
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D011 |
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||
AV(SPK_AMP) = 26 dBV |
|
VPVDD = 24 V |
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|
RSPK = 4 Ω |
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|||
|
|
Figure 31. THD+N vs Power – BTL |
|
|
Figure 32. Idle Channel Noise vs PVDD – BTL |
26 |
Submit Documentation Feedback |
Copyright © 2016–2017, Texas Instruments Incorporated |
Product Folder Links: TAS5782M
|
|
|
|
|
TAS5782M |
www.ti.com |
|
|
|
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
|
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100 |
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100 |
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90 |
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90 |
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80 |
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80 |
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70 |
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70 |
|
<![if ! IE]> <![endif]>(%) |
60 |
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<![if ! IE]> <![endif]>(%) |
60 |
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<![if ! IE]> <![endif]>Efficiency |
50 |
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<![if ! IE]> <![endif]>Efficiency |
50 |
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40 |
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40 |
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30 |
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30 |
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20 |
PVDD = 12 V |
|
20 |
PVDD = 12 V |
|
PVDD = 15 V |
|
PVDD = 15 V |
||
|
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||
|
10 |
PVDD = 18 V |
|
10 |
PVDD = 18 V |
|
0 |
PVDD = 24 V |
|
0 |
PVDD = 24 V |
|
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0 |
20 |
40 |
60 |
80 |
0 |
20 |
40 |
60 |
80 |
|
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Output Power (W) |
|
D012 |
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Output Power (W) |
|
D013 |
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||
|
|
RSPK = 4 Ω |
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RSPK = 6 Ω |
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|
Figure 33. Efficiency vs Output Power – BTL |
|
|
Figure 34. Efficiency vs Output Power – BTL |
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100 |
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60 |
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90 |
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80 |
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50 |
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<![if ! IE]> <![endif]>(mA) |
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<![if ! IE]> <![endif]>(%)Efficiency |
70 |
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40 |
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<![if ! IE]> <![endif]>CurrentIdlePVDD |
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60 |
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50 |
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30 |
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40 |
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30 |
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20 |
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20 |
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PVDD = 12 V |
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PVDD = 15 V |
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PVDD = 18 V |
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PVDD = 24 V |
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25 |
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Output Power (W) |
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D014 |
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Supply Voltage (V) |
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D015 |
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RSPK = 8 Ω |
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fSPK_AMP = 768 kHz |
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RSPK = 8 Ω |
Figure 35. Efficiency vs Output Power – BTL |
Figure 36. Idle Current Draw (Filterless) vs VPVDD – BTL |
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Ch 1 to Ch 2 |
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Ch 2 to Ch 1 |
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<![if ! IE]> <![endif]>(dB)Crosstalk |
-40 |
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<![if ! IE]> <![endif]>(dB)PSRR |
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-80 |
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-100 |
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-80 |
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-120 |
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-100 |
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1k |
10k |
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Frequency (Hz) |
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D016 |
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Frequency |
D017 |
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AV(SPK_AMP) = 26 dBV |
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VPVDD = 24 V |
AV(SPK_AMP) = 26 dBV |
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VPVDD = 24 V + 250 mVac |
Figure 37. Crosstalk vs Frequency – BTL |
Figure 38. PVDD PSRR vs Frequency – BTL |
Copyright © 2016–2017, Texas Instruments Incorporated |
Submit Documentation Feedback |
27 |
Product Folder Links: TAS5782M
TAS5782M |
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SLASEG8A –MARCH 2016–REVISED JULY 2017 |
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www.ti.com |
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Left Channel |
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Left Channel |
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Right Channel |
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Right Channel |
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-20 |
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-20 |
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<![if ! IE]> <![endif]>PSRR (dB) |
-40 |
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<![if ! IE]> <![endif]>PSRR (dB) |
-40 |
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-60 |
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-60 |
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-80 |
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-80 |
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-100 |
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-100 |
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20 |
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1k |
10k |
40k |
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20 |
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1k |
10k |
40k |
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Frequency |
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D018 |
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Frequency |
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D019 |
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AV(SPK_AMP) = 26 dBV |
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VPVDD = 24 V |
AV(SPK_AMP) = 26 dBV |
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VPVDD = 24 V |
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VDVDD = 3.3 V + 250 mVac |
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VAVDD = 3.3 V + 250 mVac |
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Figure 39. DVDD PSRR vs Frequency – BTL |
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Figure 40. AVDD PSRR vs Frequency – BTL |
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Left Channel |
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Right Channel |
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-20 |
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24 |
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<![if ! IE]> <![endif]>PSRR (dB) |
-40 |
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<![if ! IE]> <![endif]>Gain (dB) |
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20 |
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-60 |
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-80 |
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16 |
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-100 |
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12 |
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20 |
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1k |
10k |
40k |
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20 |
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1k |
10k |
40k |
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Frequency |
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D020 |
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Frequency (Hz) |
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D001 |
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AV(SPK_AMP) = 26 dBV |
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VPVDD = 24 V |
AV(SPK_AMP) = 20 dB |
POUT = 1 W |
PVDD = 12 V |
||||||
VCPVDD = 3.3 V + 250 mVac |
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Figure 41. CPVDD PSRR vs Frequency – BTL |
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Figure 42. Gain vs Frequency – BTL |
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10 |
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10 |
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4 : Load |
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4 : Load |
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6 : Load |
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6 : Load |
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8 : Load |
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8 : Load |
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1 |
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1 |
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<![if ! IE]> <![endif]>(%) |
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<![if ! IE]> <![endif]>(%) |
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<![if ! IE]> <![endif]>THD+N |
0.1 |
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<![if ! IE]> <![endif]>THD+N |
0.1 |
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0.01 |
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0.01 |
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0.001 |
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0.001 |
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20 |
100 |
1k |
10k |
20k |
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20 |
100 |
1k |
10k |
20k |
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Frequency (Hz) |
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D035 |
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Frequency (Hz) |
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D036 |
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AV(SPK_AMP) = 20 |
POUT = 1 W |
PVDD = 12 V |
AV(SPK_AMP) = 20 |
POUT = 1 W |
PVDD = 15 V |
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dB |
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dB |
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Figure 43. THD vs Frequency – BTL |
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Figure 44. THD vs Frequency - BTL |
|
28 |
Submit Documentation Feedback |
Copyright © 2016–2017, Texas Instruments Incorporated |
Product Folder Links: TAS5782M
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TAS5782M |
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www.ti.com |
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SLASEG8A –MARCH 2016–REVISED JULY 2017 |
||||
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10 |
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10 |
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4 : Load |
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4 : Load |
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6 : Load |
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6 : Load |
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8 : Load |
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8 : Load |
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1 |
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1 |
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<![if ! IE]> <![endif]>(%) |
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<![if ! IE]> <![endif]>(%) |
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<![if ! IE]> <![endif]>THD+N |
0.1 |
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<![if ! IE]> <![endif]>THD+N |
0.1 |
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0.01 |
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0.01 |
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0.001 |
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0.001 |
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20 |
100 |
1k |
10k |
20k |
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20 |
100 |
1k |
10k |
20k |
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Frequency (Hz) |
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D037 |
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Frequency (Hz) |
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D038 |
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AV(SPK_AMP) = 20 |
POUT = 1 W |
PVDD = 18 V |
AV(SPK_AMP) = 20 |
POUT = 1 W |
PVDD = 24 V |
||||||
dB |
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dB |
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Figure 45. THD vs Frequency – BTL
Figure 46. THD vs Frequency – BTL
Copyright © 2016–2017, Texas Instruments Incorporated |
Submit Documentation Feedback |
29 |
Product Folder Links: TAS5782M
TAS5782M
SLASEG8A –MARCH 2016–REVISED JULY 2017 |
www.ti.com |
Return to Quick Reference Table.
|
160 |
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10 |
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4 : Load Peak |
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<![if ! IE]> <![endif]>(%) |
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2 : Load |
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140 |
3 : Load Peak |
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3 : Load |
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2 : Load Peak |
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<![if ! IE]> <![endif]>Harmonic Distortion + Noise |
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4 : Load |
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120 |
3 : Load Continous |
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1 |
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<![if ! IE]> <![endif]>Output Power (W) |
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2 : Load Continous |
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100 |
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80 |
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0.1 |
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60 |
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40 |
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0.01 |
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20 |
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<![if ! IE]> <![endif]>Total |
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0 |
10 |
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20 |
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0.001 |
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5 |
15 |
24 |
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20 |
100 |
1k |
10k |
40k |
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Supply Voltage (V) |
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D021 |
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Frequency (Hz) |
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D022 |
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||
AV(SPK_AMP) = 26 dBV |
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AV(SPK_AMP) = 20 dBV |
PO = 1 W |
VPVDD = 12 V |
|||||
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Figure 47. Output Power vs PVDD – PBTL |
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Figure 48. THD+N vs Frequency – PBTL |
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||||
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10 |
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10 |
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<![if ! IE]> <![endif]>(%) |
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2 : Load |
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<![if ! IE]> <![endif]>(%) |
|
2 : Load |
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3 : Load |
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3 : Load |
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<![if ! IE]> <![endif]>+ Noise |
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4 : Load |
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<![if ! IE]> <![endif]>+ Noise |
|
4 : Load |
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1 |
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1 |
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<![if ! IE]> <![endif]>Distortion |
0.1 |
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<![if ! IE]> <![endif]>Distortion |
0.1 |
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<![if ! IE]> <![endif]>Total Harmonic |
0.01 |
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<![if ! IE]> <![endif]>Total Harmonic |
0.01 |
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0.001 |
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0.001 |
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20 |
100 |
1k |
10k |
40k |
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20 |
100 |
1k |
10k |
40k |
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Frequency (Hz) |
|
D023 |
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Frequency (Hz) |
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D024 |
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||
AV(SPK_AMP) = 20 dBV |
PO = 1 W |
VPVDD = 15 V |
AV(SPK_AMP) = 26 dBV |
PO = 1 W |
VPVDD = 18 V |
||||||
|
|
Figure 49. THD+N vs Frequency – PBTL |
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Figure 50. THD+N vs Frequency – PBTL |
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||||
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10 |
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10 |
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<![if ! IE]> <![endif]>(%) |
|
2 : Load |
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<![if ! IE]> <![endif]>(%) |
|
2 : Load |
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3 : Load |
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3 : Load |
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<![if ! IE]> <![endif]>+ Noise |
|
4 : Load |
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<![if ! IE]> <![endif]>+ Noise |
|
4 : Load |
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1 |
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1 |
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<![if ! IE]> <![endif]>Distortion |
0.1 |
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<![if ! IE]> <![endif]>Distortion |
0.1 |
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<![if ! IE]> <![endif]>Total Harmonic |
0.01 |
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<![if ! IE]> <![endif]>Total Harmonic |
0.01 |
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0.001 |
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0.001 |
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20 |
100 |
1k |
10k |
40k |
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10m |
100m |
1 |
10 |
50 |
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Frequency (Hz) |
|
D025 |
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Output Power (W) |
|
D026 |
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||
AV(SPK_AMP) = 26 dBV |
PO = 1 W |
VPVDD = 24 V |
AV(SPK_AMP) = 20 dBV |
|
VPVDD = 12 V |
||||||
|
|
Figure 51. THD+N vs Frequency – PBTL |
|
|
|
Figure 52. THD+N vs Power – PBTL |
|
30 |
Submit Documentation Feedback |
Copyright © 2016–2017, Texas Instruments Incorporated |
Product Folder Links: TAS5782M