TAS5733L - Digital Input Audio Power Amplifier with EQ and 3-Band AGL
1Features
1
•Audio Input/Output
– One-Stereo Serial Audio Input
– Supports 44.1-kHz and 48-kHz Sample Rates
(LJ/RJ/I²S)
– Supports 3-Wire I²S Mode (no MCLK required)
– Automatic Audio Port Rate Detection
– Supports BTL and PBTL Configuration
– P
•Audio/PWM Processing
– Independent Channel Volume Controls With
– Programmable Three-Band Automatic Gain
– 20 Programmable Biquads for Speaker EQ
•General Features
– 104-dB SNR, A-Weighted, Referenced to Full
– I²C Serial Control Interface w/ two Addresses
– Thermal, Short-Circuit, and Undervoltage
– Up to 90% Efficient
– AD, BD, and Ternary Modulation
– PWM Level Meter
= 10 W @ 10% THD+N
OUT
– PVDD = 12 V, 8 Ω, 1 kHz
Gain of 24 dB to Mute in 0.125-dB Steps
Limiting (AGL)
and Other Audio-Processing Features
Scale (0 dB)
Protection
Power vs PVDD
2Applications
•LCD TV, LED TV
•Low-Cost Audio Equipment
3Description
The TAS5733L device is an efficient, digital-input
audio amplifier for driving stereo speakers configured
as a bridge tied load (BTL). In parallel bridge tied
load (PBTL) in can produce higher power by driving
the parallel outputs into a single lower impedance
load. One serial data input allows processing of up to
two discrete audio channels and seamless integration
tomostdigitalaudioprocessorsandMPEG
decoders. The device accepts a wide range of input
data and data rates. A fully programmable data path
routes these channels to the internal speaker drivers.
The TAS5733Ldeviceis aslave-only device
receiving all clocks from external sources. The
TAS5733L device operates with a PWM carrier
between a 384-kHz switching rate and a 288-kHz
switching rate, depending on the input sample rate.
Oversampling combined with a fourth-order noise
shaper provides a flat noise floor and excellent
dynamic range from 20 Hz to 20 kHz.
Device Information
PART NUMBERPACKAGEBODY SIZE (NOM)
TAS5733LHTSSOP (48)12.50 mm × 6.10 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
(1)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2016) to Revision APage
•Moved from Product Preview to Production Data release. ................................................................................................... 1
AMP_OUT_D43
AVDD18PPower supply for internal analog circuitry
AVDD_REF17P
AVDD_REG38P
BSTRP_A9
BSTRP_B1
BSTRP_C48
BSTRP_D40
DGND34P
DVDD33PPower supply for the internal digital circuitry
DVDD_REG23P
GVDD_REG39P
LRCLK25DI
(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
48-Pin HTSSOP With PowerPAD™
DCA Package
Top View
Pin Functions
(1)
Dual function terminal which sets the LSB of the I²C Address to 0 if pulled to GND, 1 if
pulled to AVDD. Also, if configured to be a fault output by the methods described in the
Fault Indication section, this terminal will be pulled low when an internal fault occurs.
Ground reference for analog circuitry (NOTE: This terminal should be connected to the
system ground)
AOSpeaker amplifier outputs
Internal power supply (NOTE: This terminal is provided as a connection point for filtering
capacitors for this supply and must not be used to power any external circuitry)
Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a
connection point for filtering capacitors for this supply and must not be used to power
any external circuitry)
P
Connection points to for the bootstrap capacitors, which are used to create a power
supply for the gate drive for the high-side device
Ground reference for digital circuitry (NOTE: This terminal should be connected to the
system ground)
Voltage regulator derived from DVDD supply (NOTE: This terminal is provided as a
connection point for filtering capacitors for this supply and must not be used to power
any external circuitry)
Voltage regulator derived from PVDD supply (NOTE: This terminal is provided as a
connection point for filtering capacitors for this supply and must not be used to power
any external circuitry)
Word select clock for the digital signal that is active on the input data line of the serial
port
MCLK20DIMaster clock used for internal clock tree and sub-circuit/state machine clocking
12
13
(2)
NC
30
36
37
OSC_GND22P
OSC_RES21AO
PBTL11DI
PDN24DIPlaces the device in power down when pulled low
4
PGND
5
44
45
PLL_FLTM15AONegative connection point for the PLL loop filter components
PLL_FLTP16AOPositive connection point for the PLL loop filter components
PLL_GND14P
7
PVDD
8
41
42
RST31DIPlaces the devices in reset when pulled low
SCL29DII²C serial control port clock
SCLK26DIBit clock for the digital signal that is active on the input data line of the serial data port
SDA28DI/DOI²C serial control port data
SDIN27DIData line to the serial data port
SSTIMER10AO
TEST32—
PowerPAD—P
(2) Although these pins are not connected internally, optimum thermal performance is realized when these pins are connected to the ground
plane. Doing so allows copper on the PCB to fill up to and including these pins, providing a path for heat to conduct away from the
device and into the surrounding PCB area.
(1)
TYPE
P
Not connected inside the device (all "no connect" terminals should be connected to
system ground)
Ground reference for oscillator circuitry (NOTE: These terminals should be connected to
the system ground)
Connection point for precision resistor used by internal oscillator circuit. Details for this
resistor are shown in the Typical Applications section
Places the power stage in BTL mode when pulled low, or in PBTL mode when pulled
high
—
Ground reference for power device circuitry (NOTE: This terminal should be connected
to the system ground)
Ground reference for PLL circuitry (NOTE: This terminal should be connected to the
system ground)
PPower supply for internal power circuitry
Connection point for the capacitor that is used by the ramp timing circuit, as described in
the SSTIMER Pin Functionality section
Used by TI for testing during device production (NOTE: This terminal should be
connected to system ground)
Exposed metal pad on the underside of the device, which serves as an electrical
connection point for ground as well as a heat conduction path from the device into the
board (NOTE: This terminal should be connected to ground through a land pattern
defined in the Mechanical Data section)
over operating free-air temperature range (unless otherwise noted)
Supply voltage
Input voltage
AMP_OUT_x to GND22
BSTRP_x to GND29
Operating free-air temperature0 to 85°C
Storage temperature range, T
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2) 5-V tolerant inputs are PDN, RST, SCLK, LRCK, MCLK, SDIN, SDA, and SCL.
(3) Maximum pin voltage should not exceed 6 V.
(4) DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.
DVDD, AVDD–0.3 to 3.6V
PVDD–0.3 to 20
3.3-V digital input–0.5 to DVDD + 0.5
(2)
digital input (except MCLK)–0.5 to DVDD + 2.5
5-V tolerant MCLK input–0.5 to AVDD + 2.5
stg
6.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V
(ESD)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-
(2)
C101
(1)
VALUEUNIT
(3)
(3)
(4)
(4)
V5-V tolerant
V
V
–40 to 125°C
VALUEUNIT
(1)
±4000
±1500
V
6.3 Recommended Operating Conditions
MINNOMMAXUNIT
DVDD, AVDDDigital, analog supply voltage33.33.6V
PVDDOutput power devices supply voltage816.5
V
IH
V
IL
T
A
(2)
T
J
R
L
R
L
L
O
High-level input voltage5-V tolerant2V
Low-level input voltage5-V tolerant0.8V
Operating ambient temperature range085°C
Operating junction temperature range0125°C
Load impedance48Ω
Load impedance in PBTL2Ω
Output-filter inductance
Minimum output inductance under
short-circuit condition
10μH
(1) For operation at PVDD levels greater than 14.5 V, the modulation limit must be set to 96.1% or lower via the control port register 0x10.
(2) 16.5 V is the maximum recommended voltage for continuous operation of the TAS5733L device. Testing and characterization of the
device is performed up to and including 16.5 V to ensure “in system” design margin. However, continuous operation at these levels is
not recommended. Operation above the maximum recommended voltage may result in reduced performance, errant operation, and
reduction in device reliability.
PVDD = 12 V, BTL BD mode, AVDD = DVDD = 3.3 V, fS= 48 KHz, RL= 8 Ω, audio frequency = 1 kHz, AES17 filter, f
384 kHz, TA= 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions
and as tested on the TAS5733L EVM.
Pulse duration, RST active100μs
Time to enable I²C after RST goes high13.5ms
Frequency, SCL400kHz
Pulse duration, SCL high0.6μs
Pulse duration, SCL low1.3μs
Rise time, SCL and SDA300ns
Fall time, SCL and SDA300ns
Setup time, SDA to SCL100ns
Hold time, SCL to SDA0ns
Bus free time between stop and start conditions1.3μs
Setup time, SCL to start condition0.6μs
Hold time, start condition to SCL0.6μs
Setup time, SCL to stop condition0.6μs
Load capacitance for each bus line400pF
6.10 Serial Audio Port Timing Requirements
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
f
SCLKIN
t
su1
t
h1
t
su2
t
h2
t
(edge)
tr/t
f
Frequency, SCLK 32 × fS, 48 × fS, 64 × f
S
Setup time, LRCK to SCLK rising edge10ns
Hold time, LRCK from SCLK rising edge10ns
Setup time, SDIN to SCLK rising edge10ns
Hold time, SDIN from SCLK rising edge10ns
LRCK frequency84848kHz
SCLK duty cycle40%50%60%
LRCK duty cycle40%50%60%
SCLK rising edges between LRCK rising edges3264
LRCK clock edge with respect to the falling edge of SCLK–1/41/4
Rise/fall time for SCLK/LRCK8ns
NOTE: On power up, hold the TAS5733L RST LOW for at least 100 μs after DVDD has reached 3 V.
NOTE: If RST is asserted LOW while PDN is LOW, then RST must continue to be held LOW for at least 100 μs after PDN is
The TAS5733L device is an efficient, digital-input audio amplifier for driving stereo speakers configured as a
bridge tied load (BTL). In parallel bridge tied load (PBTL) in can produce higher power by driving the parallel
outputs into a single lower impedance load. One serial data input allows processing of up to two discrete audio
channels and seamless integration to most digital audio processors and MPEG decoders. The device accepts a
wide range of input data and data rates. A fully programmable data path routes these channels to the internal
speaker drivers.
The TAS5733L device is a slave-only device receiving all clocks from external sources. The TAS5733L device
operates with a PWM carrier between a 384-kHz switching rate and a 288-kHz switching rate, depending on the
input sample rate. Oversampling combined with a fourth-order noise shaper provides a flat noise floor and
excellent dynamic range from 20 Hz to 20 kHz.
The TAS5733L device is an I²S slave device. The TAS5733L device accepts MCLK, SCLK, and LRCK. The
digital audio processor (DAP) supports all the sample rates and MCLK rates that are defined in the Clock Control
Register.
The TAS5733L device checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only
supports a 1 × fSLRCK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The
clock section uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to
produce the internal clock (DCLK) running at 512 times the PWM switching frequency.
The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock
rates as defined in the Clock Control Register.
The TAS5733L device has robust clock error handling that uses the built-in trimmed oscillator clock to quickly
detect changes/errors. Once the system detects a clock change/error, the system mutes the audio (through a
single-step mute) and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks
are stable, the system autodetects the new rate and reverts to normal operation. During this process, the default
volume is restored in a single step (also called hard unmute). The ramp process can be programmed to ramp
back slowly (also called soft unmute) as defined in the Volume Configuration Register.
7.4.2 PWM Section
The TAS5733L DAP device uses noise-shaping and customized nonlinear correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to
increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP
and outputs two BTL PWM audio output channels.
The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz.
The PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%. For PVDD > 14.5 V the
modulation index must be limited to 96.1% for safe and reliable operation.
7.4.3 PWM Level Meter
The structure in Figure 29 shows the PWM level meter that can be used to study the power profile.
7.4.4 Automatic Gain Limiter (AGL)
The AGL scheme has three AGL blocks. One ganged AGL exists for the high-band left/right channels, the midband left/right channels, and the low-band left/right channels.
The AGL input/output diagram is shown in Figure 30.
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
• Each AGL has adjustable threshold levels.
• Programmable attack and decay time constants
• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
www.ti.com
Figure 30. Automatic Gain Limiter
T = 9.23 format, all other AGL coefficients are 3.23 format
ADR/FAULT is an input pin during power up. This pin can be programmed after RST to be an output by writing 1
to bit 0 of I²C register 0x05. In that mode, the ADR/FAULT pin has the definition shown in Table 2.
Any fault resulting in device shutdown is signaled by the ADR/FAULT pin going low (see Table 2). A latched
version of this pin is available on D1 of register 0x02. This bit can be reset only by an I²C write.
Table 2. ADR/FAULT Output States
ADR/FAULTDESCRIPTION
0Overcurrent (OC) or undervoltage (UVP) error or overtemperature error (OTE) or overvoltage
The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when
exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current
source, and the charge time determines the rate at which the output transitions from a near-zero duty cycle to the
desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is
shut down, the drivers are placed in the high-impedance state and transition slowly down through an internal 3kΩ resistor, similarly minimizing pops and clicks. The shutdown transition time is independent of the SSTIMER
pin capacitance. Larger capacitors increase the start-up time, while smaller capacitors decrease the start-up
time. The SSTIMER pin can be left floating for BD modulation.
7.4.7 Device Protection System
7.4.7.1 Overcurrent (OC) Protection With Current Limiting
The TAS5733L device has independent, fast-reacting current detectors on all high-side and low-side power-stage
FETs. The detector outputs are closely monitored to prevent the output current from increasing beyond the
overcurrent threshold defined in the Protection Characteristics table.
If the output current increases beyond the overcurrent threshold, the device shuts down and the outputs
transition to the off or high impedance (Hi-Z) state. The device returns to normal operation once the fault
condition (i.e., a short circuit on the output) is removed. Current-limiting and overcurrent protection are not
independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent
fault, half-bridges A, B, C, and D shut down.
7.4.7.2 Overtemperature Protection
The TAS5733L device has an overtemperature-protection system. If the device junction temperature exceeds
150°C (nominal), the device enters thermal shutdown, where all half-bridge outputs enter the high-impedance
(Hi-Z) state, and ADR/FAULT asserts low if the device is configured to function as a fault output. The TAS5733L
device recovers automatically once the junction temperature of the device drops approximately 30°C.
7.4.7.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the TAS5733L device fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD
and AVDD are independently monitored. For PVDD, if the supply voltage drops below the UVP threshold, the
protection feature immediately sets all half-bridge outputs to the high-impedance (Hi-Z) state and asserts
ADR/FAULT low.
7.5 Device Functional Modes
The TAS5733L device is a digital input class-d amplifier with audio processing capabilities. The TAS5733L
device has numerous modes to configure and control the device.
7.5.1 Serial Audio Port Operating Modes
The serial audio port in the TAS5733L device supports industry-standard audio data formats, including I²S, Leftjustified(LJ) and Right-justified(RJ) formats. To select the data format that will be used with the device can
controlled by using the serial data interface registers 0x04. The default is 24bit, I²S mode. The timing diagrams
for the various serial audio port are shown in the Serial Interface Control and Timing section
7.5.2 Communication Port Operating Modes
The TAS5733L device is configured via an I²C communication port. The I²C communication protocol is detailed in
the 7.7 I²C Serial Control Port Requirements and Specifications section.
Stereo mode is the most common option for the TAS5733L. TAS5733L can be connected in 2.0 mode to drive
stereo channels. Detailed application section regarding the stereo mode is discussed in the Stereo Bridge Tied
Load Application section.
7.5.3.2 Mono Mode
Mono mode is described as the operation where the two BTL outputs of amplifier are placed in parallel with one
another to provide increase in the output power capability. This mode is typically used to drive subwoofers, which
require more power to drive larger loudspeakers with high-amplitude, low-frequency energy. Detailed application
section regarding the mono mode is discussed in the Mono Parallel Bridge Tied Load Application section.
7.6 Programming
7.6.1 I²C Serial Control Interface
The TAS5733L device has a bidirectional I²C interface that is compatible with the Inter IC (I²C) bus protocol and
supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations.
This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The
control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I²C bus operation (100 kHz maximum) and the fast I²C bus operation
(400 kHz maximum). The DAP performs all I²C operations without I²C wait cycles.
7.6.1.1 General I²C Operation
The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A
high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 32. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5733L device holds SDA low during the
acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte
of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible
devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor
must be used for the SDA and SCL signals to set the high level for the bus.
No limit exists for the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 32.
The 7-bit address for the TAS5733L device is 0101 010 (0x54) or 0101 011 (0x56) as defined by ADR/FAULT
(external pulldown for 0x54 and pullup for 0x56).
7.6.1.2 I²C Slave Address
The ADR/FAULT is an input pin during power-up and after each toggle of RST, which is used to set the I²C subaddress of the device. The ADR/FAULT can also operate as a fault output after power-up is complete and the
address has been latched in.
At power-up, and after each toggle of RST, the pin is read to determine its voltage level. If the pin is left floating,
an internal pull-up will set the I²C sub-address to 0x56. This will also be the case if an external resistor is used to
pull the pin up to AVDD. To set the sub-address to 0x54, an external resistor (specified in Typical Applications )
must be connected to the system ground.
As mentioned, the pin can also be reconfigured as an output driver via I²C for fault monitoring. Use System
Control Register 2 (0x05) to set ADR/FAULT pin to be used as a fault output during fault conditions.
I²C Device Address Change Procedure
1. Write to device address change enable register, 0xF8 with a value of 0xF9A5 A5A5.
2. Write to device register 0xF9 with a value of 0x0000 00XX, where XX is the new address.
3. Any writes after that should use the new device address XX.
7.6.1.3 Single- and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses
0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiplebyte read/write operations (in multiples of 4 bytes).
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does
not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes
that are required for each specific subaddress. For example, if a write command is received for a biquad
subaddress, the DAP must receive five 32-bit words. If fewer than five 32-bit data words have been received
when a stop command (or another start command) is received, the received data is discarded.
Supplying a subaddress for each subaddress transaction is referred to as random I²C addressing. The
TAS5733L device also supports sequential I²C addressing. For write transactions, if a subaddress is issued
followed by data for that subaddress and the 15 subaddresses that follow, a sequential I²C write transaction has
taken place, and the data for all 16 subaddresses is successfully received by the TAS5733L device. For I²C
sequential-write transactions, the subaddress then serves as the start address, and the amount of data
subsequently transmitted before a stop or start is transmitted determines how many subaddresses are written.
As was true for random addressing, sequential addressing requires that a complete set of data be transmitted. If
only a partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However,
all other data written is accepted; only the incomplete data is discarded.
As shown in Figure 33, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I²C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I²C device address
and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or
bytes corresponding to the internal memory address being accessed. After receiving the address byte, the
TAS5733L device again responds with an acknowledge bit. Next, the master device transmits the data byte to be
written to the memory address being accessed. After receiving the data byte, the TAS5733L device again
responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the singlebyte data-write transfer.
Figure 33. Single-Byte Write Transfer
7.6.1.5 Multiple-Byte Write
A multiple-byte data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 34. After receiving each data byte, the
TAS5733L device responds with an acknowledge bit.
Figure 34. Multiple-Byte Write Transfer
7.6.1.6 Single-Byte Read
As shown in Figure 35, a single-byte data-read transfer begins with the master device transmitting a start
condition, followed by the I²C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5733L address
and the read/write bit, TAS5733L device responds with an acknowledge bit. In addition, after sending the internal
memory address byte or bytes, the master device transmits another start condition followed by the TAS5733L
address and the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After
receiving the address and the read/write bit, the TAS5733L device again responds with an acknowledge bit.
Next, the TAS5733L device transmits the data byte from the memory address being read. After receiving the
data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the singlebyte data-read transfer.
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the TAS5733L device to the master device as shown in Figure 36. Except for the last data
byte, the master device responds with an acknowledge bit after receiving each data byte.
Figure 36. Multiple-Byte Read Transfer
7.6.2 Serial Interface Control and Timing
7.6.2.1 Serial Data Interface
Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5733L DAP accepts serial data
in 16-bit, 20-bit, or 24-bit left-justified, right-justified, and I²S serial data formats.
7.6.2.2 I²S Timing
I²S timing uses LRCK to define when the data being transmitted is for the left channel and when the data is for
the right channel. LRCK is low for the left channel and high for the right channel. A bit clock running at 32 × fS,
48 × fS, or 64 × fSis used to clock in the data. A delay of one bit clock exists from the time the LRCK signal
changes state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge
of bit clock. The DAP masks unused trailing data bit positions.
Left-justified (LJ) timing uses LRCK to define when the data being transmitted is for the left channel and when
the data is for the right channel. LRCK is high for the left channel and low for the right channel. A bit clock
running at 32 × fS, 48 × fS, or 64 × fSis used to clock in the data. The first bit of data appears on the data lines at
the same time LRCK toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The
DAP masks unused trailing data bit positions.
NOTE: All data presented in two's-complement form with MSB first.
Right-justified (RJ) timing uses LRCK to define when the data being transmitted is for the left channel and when
the data is for the right channel. LRCK is high for the left channel and low for the right channel. A bit clock
running at 32 × fS, 48 × fS, or 64 × fSis used to clock in the data. The first bit of data appears on the data 8 bitclock periods (for 24-bit data) after LRCK toggles. In RJ mode, the LSB of data is always clocked by the last bit
clock before LRCK transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP
masks unused leading data bit positions.
All data presented in two's-complement form with MSB first.
All data presented in two's-complement form with MSB first.
Figure 44. Right-Justified 48-fSFormat
All data presented in two's-complement form with MSB first.
Figure 45. Right-Justified 32-fSFormat
7.6.3 26-Bit 3.23 Number Format
All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23
numbers mean that the binary point has 3 bits to the left and 23 bits to the right. This is shown in Figure 46.
The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 46. If the
most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct
number. If the most significant bit is a logic 1, then the number is a negative number. In the case every bit must
be inverted, a 1 added to the result, and then the weighting shown in Figure 47 applies to obtain the magnitude
of the negative number.
Figure 47. Conversion Weighting Factors—3.23 Format to Floating Point
Gain coefficients, entered via the I²C bus, must be entered as 32-bit binary numbers. The format of the 32-bit
number (4-byte or 8-digit hexadecimal number) is shown in Figure 48.
Figure 48. Alignment of 3.23 Coefficient in 32-Bit I²C Word
Product Folder Links: TAS5733L
www.ti.com
7.7 Register Maps
7.7.1 Register Summary
SLASE77A –MARCH 2016–REVISED MARCH 2016
Table 3. Sample Calculation for 3.23 Format
dbLinearDecimalHex (3.23 Format)
018,388,608800000
51.7714,917,28800E3 9EA8
–50.564,717,2600047 FACC
XL = 10
(X / 20)
D = 8,388,608 × L H = dec2hex (D, 8)
Table 4. Sample Calculation for 9.17 Format
dbLinearDecimalHex (9.17 Format)
01131,07220000
51.77231,9973 8A3D
–50.5673,4001 1EB8
XL = 10
(X / 20)
D = 131,072 × LH = dec2hex (D, 8)
TAS5733L
SUBADDRESSREGISTER NAME
NO. OF
BYTES
CONTENTS
A u indicates unused bits.
0x00Clock control register1Description shown in subsequent section0x6C
0x01Device ID register1Description shown in subsequent section0x40
0x02Error status register1Description shown in subsequent section0x00
0x03System control register 11Description shown in subsequent section0xA0
0x04Serial data interface register1Description shown in subsequent section0x05
0x05System control register 21Description shown in subsequent section0x40
0x06Soft mute register1Description shown in subsequent section0x00
0x07Master volume2Description shown in subsequent section0x03FF (mute)
0x08Channel 1 vol2Description shown in subsequent section0x00C0 (0 dB)
0x09Channel 2 vol2Description shown in subsequent section0x00C0 (0 dB)
0x0AChannel 3 vol2Description shown in subsequent section0x00C0 (0 dB)
0x0BReserved2Reserved
0x0C2Reserved
0x0D1Reserved
(1)
(1)
(1)
0x0EVolume configuration register1Description shown in subsequent section0xF0
0x0FReserved1Reserved
(1)
0x10Modulation limit register1Description shown in subsequent section0x01
0x11IC delay channel 11Description shown in subsequent section0xAC
0x12IC delay channel 21Description shown in subsequent section0x54
0x13IC delay channel 31Description shown in subsequent section0xAC
0x14IC delay channel 41Description shown in subsequent section0x54
0x15Reserved1Reserved
(1)
0x160x54
0x170x00
0x18PWM Start0x0F
0x19PWM Shutdown Group Register1Description shown in subsequent section0x30
0x1AStart/stop period register1Description shown in subsequent section0x68
0x1BOscillator trim register1Description shown in subsequent section0x82
0xF8Update device address key4Dev Id Update Key[31:0] (Key =
(1)
0x0000 0000
0x0000 0054
0xF9A5A5A5)
0xF9Update device address4u[31:8],New Dev Id[7:0] (New Dev Id = 0x54
0x0000 0054
for TAS5733L)
0xFA–0xFF4Reserved
(1)
0x0000 0000
All DAP coefficients are 3.23 format unless specified otherwise.
Registers 0x3B through 0x46 should be altered only during the initialization phase.
7.7.2 Detailed Register Descriptions
7.7.2.1 Clock Control Register (0x00)
The clocks and data rates are automatically determined by the TAS5733L. The clock control register contains the
autodetected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.
100–––––fS= 16-kHz sample rate
101–––––fS= 22.05/24-kHz sample rate
110–––––fS= 8-kHz sample rate
111–––––fS= 11.025/12-kHz sample rate
–––000––MCLK frequency = 64 × f
–––0011–MCLK frequency = 128 × f
00001000MCLK frequency = 192 × f
–––011––MCLK frequency = 256 × f
(1)
(2)
S
(2)
S
(3)
S
(1)(4)
S
(1) Default values are in bold.
(2) Only available for 44.1-kHz and 48-kHz rates
(3) Rate only available for 32/44.1/48-KHz sample rates
(4) Not available at 8 kHz
Table 5. Clock Control Register (0x00) (continued)
D7D6D5D4D3D2D1D0FUNCTION
–––100––MCLK frequency = 384 × f
–––101––MCLK frequency = 512 × f
–––110––Reserved
–––111––Reserved
––––––0–Reserved
–––––––0Reserved
S
S
7.7.2.2 Device ID Register (0x01)
The device ID register contains the ID code for the firmware revision.
Table 6. General Status Register (0x01)
D7D6D5D4D3D2D1D0FUNCTION
00000000Identification code
(1) Default values are in bold.
(1)
7.7.2.3 Error Status Register (0x02)
The error bits are sticky and are not cleared by the hardware. This means that the software must clear the
register (write zeroes) and then read them to determine if they are persistent errors.
Error definitions:
•MCLK error: MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
•SCLK error: The number of SCLKs per LRCLK is changing.
•LRCLK error: LRCLK frequency is changing.
•Frame slip: LRCLK phase is drifting with respect to internal frame sync.
Bit D7:If 0, the dc-blocking filter for each channel is disabled.
If 1, the dc-blocking filter (–3 dB cutoff <1 Hz) for each channel is enabled.
Bit D5:If 0, use soft unmute on recovery from a clock error. This is a slow recovery. Unmute takes the
same time as the volume ramp defined in register 0x0E.
If 1, use hard unmute on recovery from clock error. This is a fast recovery, a single-step volume
0–––Ternary modulation disabled
––––1–––Ternary modulation enabled
–––––0––Reserved
––––––0–configured as input
––––––1–configured configured as output to function as fault output pin.
–––––––0Reserved
(1) Default values are in bold.
(1)
(1)
(1)
(1)
(1)
(1)
Ternary modulation is disabled by default. To enable ternary modulation, the following writes are required before
bringing the system out of shutdown:
1. Set bit D3 of register 0x05 to 1.
2. Write the following ICD settings:
(a) 0x11= 80
(b) 0x12= 7C
(c) 0x13= 80
(d) 0x14 =7C
3. Set the input mux register as follows:
(a) 0x20 = 00 89 77 72
7.7.2.7 Soft Mute Register (0x06)
Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).
The volume register 0x07, 0x08, and 0x09 correspond to master volume, channel 1 volume, and channel 2
volume, respectively. Step size is 0.125 dB and volume registers are 2 bytes.
Master volume– 0x07 (default is mute, 0x03FF)
Channel-1 volume– 0x08 (default is 0 dB, 0x00C0)
Volume slew rate (used to control volume change and MUTE ramp rates). These bits control the
number of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of
the I2S data as follows:
0x11101011––Default value for channel 1
0x12010101––Default value for channel 2
0x13101011––Default value for channel 1
0x14010101––Default value for channel 2
(1) Default values are in bold.
(1)
(1)
(1)
(1)
ICD settings have high impact on audio performance (e.g., dynamic range, THD, crosstalk, etc.) Therefore,
appropriate ICD settings must be used. By default, the device has ICD settings for the AD mode. If used in BD
mode, then update these registers before coming out of all-channel shutdown.
MODEAD MODEBD MODE
0x11ACB8
0x125460
0x13ACA0
0x145448
7.7.2.12 PWM Shutdown Group Register (0x19)
Settings of this register determine which PWM channels are active. The functionality of this register is tied to the
state of bit D5 in the system control register.
This register defines which channels belong to the shutdown group. If a 1 is set in the shutdown group register,
that particular channel is not started following an exit out of all-channel shutdown command (if bit D5 is set to 0
in system control register 2, 0x05).
–0––––––Reserved
––1–––––Reserved
–––1––––Reserved
––––0–––PWM channel 4 does not belong to shutdown group.
(1)
(1)
(1)
(1)
(1)
––––1–––PWM channel 4 belongs to shutdown group.
–––––0––PWM channel 3 does not belong to shutdown group.
(1)
–––––1––PWM channel 3 belongs to shutdown group.
––––––0–PWM channel 2 does not belong to shutdown group.
(1)
––––––1–PWM channel 2 belongs to shutdown group.
–––––––0PWM channel 1 does not belong to shutdown group.
(1)
–––––––1PWM channel 1 belongs to shutdown group.
(1) Default values are in bold.
7.7.2.13 Start/Stop Period Register (0x1A)
This register is used to control the soft-start and soft-stop period following an enter/exit all-channel shutdown
command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown. The times
are only approximate and vary depending on device activity level and I2S clock stability.
Table 17. Start/Stop Period Register (0x1A)
D7D6 D5D4D3D2D1D0FUNCTION
0–––––––SSTIMER enabled
1–––––––SSTIMER disabled
–11–––––Reserved
(1)
–––00–––No 50% duty cycle start/stop period
–––0100016.5-ms 50% duty cycle start/stop period
–––0100123.9-ms 50% duty cycle start/stop period
–––0101031.4-ms 50% duty cycle start/stop period
–––0101140.4-ms 50% duty cycle start/stop period
–––0110053.9-ms 50% duty cycle start/stop period
–––0110170.3-ms 50% duty cycle start/stop period
–––0111094.2-ms 50% duty cycle start/stop period
–––01111125.7-ms 50% duty cycle start/stop period
–––10000164.6-ms 50% duty cycle start/stop period
–––10001239.4-ms 50% duty cycle start/stop period
–––10010314.2-ms 50% duty cycle start/stop period
–––10011403.9-ms 50% duty cycle start/stop period
–––10100538.6-ms 50% duty cycle start/stop period
–––10101703.1-ms 50% duty cycle start/stop period
–––10110942.5-ms 50% duty cycle start/stop period
–––101111256.6-ms 50% duty cycle start/stop period
–––110001728.1-ms 50% duty cycle start/stop period
–––110012513.6-ms 50% duty cycle start/stop period
–––110103299.1-ms 50% duty cycle start/stop period
–––110114241.7-ms 50% duty cycle start/stop period
–––111005655.6-ms 50% duty cycle start/stop period
–––111017383.7-ms 50% duty cycle start/stop period
Table 17. Start/Stop Period Register (0x1A) (continued)
D7D6 D5D4D3D2D1D0FUNCTION
–––111109897.3-ms 50% duty cycle start/stop period
–––1111113,196.4-ms 50% duty cycle start/stop period
7.7.2.14 Oscillator Trim Register (0x1B)
The TAS5733L PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This
reduces system cost because an external reference is not required. A reference resistor must be connected
between pin 16 and 17, as shown in Table 18.
Writing 0x00 to register 0x1B enables the trim that was programmed at the factory.
Note that trim must always be run following reset of the device.
Table 18. Oscillator Trim Register (0x1B)
D7D6D5 D4D3D2D1D0FUNCTION
1–––––––Reserved
–0––––––Oscillator trim not done (read-only)
–1––––––Oscillator trim done (read only)
––0000––Reserved
––––––0–Select factory trim (Write a 0 to select factory trim; default is 1.)
––––––1–Factory trim disabled
–––––––0Reserved
(1) Default values are in bold.
(1)
(1)
(1)
(1)
(1)
7.7.2.15 BKND_ERR Register (0x1C)
When a back-end error signal is received from the internal power stage, the power stage is reset, stopping all
PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 19 before attempting
to re-start the power stage.
Table 19. BKND_ERR Register (0x1C)
D7D6 D5D4D3D2D1D0FUNCTION
0101xxxXReserved
––––0010Set back-end reset period to 299 ms
––––0011Set back-end reset period to 449 ms
––––0100Set back-end reset period to 598 ms
––––0101Set back-end reset period to 748 ms
––––0110Set back-end reset period to 898 ms
––––0111Set back-end reset period to 1047 ms
––––1000Set back-end reset period to 1197 ms
––––1001Set back-end reset period to 1346 ms
––––101XSet back-end reset period to 1496 ms
––––111XSet back-end reset period to 1496 ms
(1) This register can be written only with a non-reserved value. The RSTz pin must be toggled between subsequent writes to this register.
(2) Default values are in bold.
This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal
channels.
Table 20. Input Multiplexer Register (0x20)
D31D30D29D28D27D26D25D24FUNCTION
00000000Reserved
D23D22D21D20D19D18D17D16FUNCTION
0–––––––Channel-1 AD mode
1–––––––Channel-1 BD mode
–000––––SDIN-L to channel 1
–001––––SDIN-R to channel 1
–010––––Reserved
–011––––Reserved
–100––––Reserved
–101––––Reserved
–110––––Ground (0) to channel 1
–111––––Reserved
––––0–––Channel 2 AD mode
––––1–––Channel 2 BD mode
–––––000SDIN-L to channel 2
–––––001SDIN-R to channel 2
–––––010Reserved
–––––011Reserved
–––––100Reserved
–––––101Reserved
–––––110Ground (0) to channel 2
–––––111Reserved
(1)
(1)
(1)
(1)
(1)
D15D14D13D12D11D10D9D8FUNCTION
01110111Reserved
D7D6D5D4D3D2D1D0FUNCTION
01110010Reserved
(1) Default values are in bold.
(1)
(1)
7.7.2.17 PWM Output MUX Register (0x25)
This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be
output to any external output pin.
Bits D21–D20:Selects which PWM channel is output to AMP_OUT_A
Bits D17–D16:Selects which PWM channel is output to AMP_OUT_B
Bits D13–D12:Selects which PWM channel is output to AMP_OUT_C
Bits D09–D08:Selects which PWM channel is output to AMP_OUT_D
Note that channels are encoded so that channel 1 = 0x00, channel 2 = 0x01, …, channel 4 = 0x03.
–––0––––Reserved
––––0–––AGL4 turned OFF
––––1–––AGL4 turned ON
–––––0––AGL3 turned OFF
–––––1––AGL3 turned ON
––––––0–AGL2 turned OFF
––––––1–AGL2 turned ON
–––––––0AGL1 turned OFF
–––––––1AGL1 turned ON
(1) Default values are in bold.
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
TAS5733L
7.7.2.19 PWM Switching Rate Control Register (0x4F)
PWM switching rate should be selected through the register 0x4F before coming out of all-channnel shutdown.
Table 23. PWM Switching Rate Control Register (0x4F)
1–––––––EQ OFF (bypass BQ 1–11 of channels 1 and 2)
–0––––––Reserved
––0–––––Ignore bank-mapping in bits D31–D8. Use default mapping.
1Use bank-mapping in bits D31–D8.
–––0––––L and R can be written independently.
L and R are ganged for EQ biquads; a write to the left-channel
–––1––––
biquad is also written to the right-channel biquad. (0x29–0x2F is
ganged to 0x30–0x36. Also, 0x58–0x5B is ganged to 0x5C–0x5F.
––––0–––Reserved
–––––000No bank switching. All updates to DAP
–––––001Configure bank 1 (32 kHz by default)
–––––01XReserved
–––––1XXReserved
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
As mentioned previously, the TAS5733L device can be used in stereo and mono mode. This section describes
the information required to configure the device for several popular configurations and for integrating the
TAS5733L device into the larger system.
8.1.1 External Component Selection Criteria
The Supporting Component Requirements table in each application description section lists the details of the
supporting required components in each of the System Application Schematics. Where possible, the supporting
component requirements have been consolidated to minimize the number of unique components which are used
in the design. Component list consolidation is a method to reduce the number of unique part numbers in a
design. Consolidation is done to ease inventory management and reduce the manufacturing steps during board
assembly. For this reason, some capacitors are specified at a higher voltage than what would normally be
required. An example of this is a 50-V capacitor can be used for decoupling of a 3.3-V power supply net.
In this example, a higher voltage capacitor can be used even on the lower voltage net to consolidate all caps of
that value into a single component type. Similarly, several unique resistors, all having the same size and value
but different power ratings can be consolidated by using the highest rated power resistor for each instance of that
resistor value.
While this consolidation can seem excessive, the benefits of having fewer components in the design can far
outweigh the trivial cost of a higher voltage capacitor. If lower voltage capacitors are already available elsewhere
in the design, they can be used instead of the higher voltage capacitors. In all situations, the voltage rating of the
capacitors must be at least 1.45 times the voltage of the voltage which appears across them. The power rating of
the capacitors should be 1.5 times to 1.75 times the power dissipated in the capacitors during normal use case.
8.1.1.1 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
Because the layout is important to the overall performance of the circuit, the package size of the components
shown in the component list were intentionally chosen to allow for proper board layout, component placement,
and trace routing. In some cases, traces are passed in between two surface mount pads or ground plane
extends from the TAS5733L device between two pads of a surface mount component and into to the surrounding
copper for increased heat-sinking of the device. While components can be offered in smaller or larger package
sizes, the package size should remain identical to that used in the application circuit as shown. This consistency
ensures that the layout and routing can be matched very closely, optimizing thermal, electromagnetic, and audio
performance of the TAS5733L device in circuit in the final system.
8.1.1.2 Amplifier Output Filtering
The TAS5733L device is often used with a low-pass filter, which is used to filter out the carrier frequency of the
PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive
element L and a capacitive element C to make up the 2-pole filter. The L-C filter removes the carrier frequency,
reducing electromagnetic emissions and smoothing the current waveform which is drawn from the power supply.
The presence and size of the L-C filter is determined by several system level constraints. In some low-power use
cases that do not have other circuits which are sensitive to EMI, a simple ferrite bead or ferrite bead and
capacitor can replace the traditional large inductor and capacitor that are commonly used. In other high-power
applications, large toroid inductors are required for maximum power and film capacitors can be preferred due to
audio characteristics. Refer to the application report Class-D Filter Design (SLOA119) for a detailed description
of proper component selection and design of an L-C filter based upon the desired load and response.
These typical connection diagrams highlight the required external components and system level connections for
proper operation of the device in several popular use cases. Each of these configurations can be realized using
the Evaluation Module (EVM) for the device. These flexible modules allow full evaluation of the device in the
most common modes of operation. Any design variation can be supported by TI through schematic and layout
reviews. Visit http://e2e.ti.com for design assistance and join the audio amplifier discussion forum for additional
information.
8.2.1 Stereo Bridge Tied Load Application
A stereo system generally refers to a system inside which are two full range speakers without a separate
amplifier path for the speakers that reproduce the low-frequency content. In this system, two channels are
presented to the amplifier via the digital input signal. These two channels are amplified and then sent to two
separate speakers.
Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the
audio for the left channel and the other channel containing the audio for the right channel. While the two
channels can contain any two audio channels, such as two surround channels of a multi-channel speaker
system, the most popular occurrence in two channels systems is a stereo pair.
The Stereo BTL Configuration is shown in Figure 49.
(1) Refer to SLOA119 for a detailed description on the filter design.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Component Selection and Hardware Connections
The typical connections required for proper operation of the device can be found on the TAS5733L User’s Guide.
The device was tested with this list of components, deviation from this typical application components unless
recommended by this document can produce unwanted results, which could range from degradation of audio
performance to destructive failure of the device. The application report Class-D Filter Design (SLOA119) offers a
detailed description of proper component selection and design of the output filter based upon the modulation
used, desired load and response.
I²C Compliant Master
GPIO Control
(1)
8.2.1.2.2 Control and Software Integration
The TAS5733L device has a bidirectional I²C used to program the registers of the device and to read device
status. The TAS5733LEVM and the PurePath Console GUI are powerful tools that allow the TAS5733L
evaluation, control and configuration. The Register Dump feature of the PurePath Console software can be used
to generate a custom configuration file for any end-system operating mode. Prior approval is required to
download PurePath Console GUI. Please request access at http://www.ti.com/tool/purepathconsole.
8.2.1.2.3 I²C Pullup Resistors
Customary pullup resistors are required on the SCL and SDA signal lines. They are not shown in the Typical
Application Circuits, because they are shared by all of the devices on the I²C bus and are considered to be part
of the associated passive components for the System Processor. These resistor values should be chosen per the
guidance provided in the I²C Specification.
8.2.1.2.4 Digital I/O Connectivity
The digital I/O lines of the TAS5733L are described in previous sections. As discussed, whenever a static digital
pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to
DVDD through a pull-up resistor to control the slew rate of the voltage presented to the digital I/O pins. However,
having a separate pull-up resistor for each static digital I/O line is not necessary. Instead, a single resistor can be
used to tie all static I/O lines HIGH to reduce BOM count.
t has to be greater than 240 ms + 1.3 t, after the first trim command following AVDD/DVDD power-up. It does not apply to trim commands following subsequent resets.
t/t = PWM start/stop time as defined in register 0x1A
PLLSTART
START STOP
TAS5733L
SLASE77A –MARCH 2016–REVISED MARCH 2016
8.2.1.2.5 Recommended Startup and Shutdown Procedures
www.ti.com
Figure 50. Recommended Start-Up and Shutdown Sequence
8.2.1.2.5.1 Start-Up Sequence
Use the following sequence to power up and initialize the device:
1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V.
2. Initialize digital inputs and PVDD supply as follows:
– Drive RST = 0, PDN = 1, and other digital inputs to their desired state. Wait at least 100 µs, drive RST
high
– Wait ≥ 13.5 ms.
– Ramp up PVDD to at least 8 V while ensuring that it remains below 6 V for at least 100 µs after
AVDD/DVDD reaches 3 V.
– Wait ≥ 10 µs.
3. Trim oscillator (write 0x00 to register 0x1B) and wait at least 50 ms.
4. Configure the Digital Audio Processor of the Amplifier via I²C, refer to Section 8.5 Register Maps for more
information.
5. Configure remaining registers.
6. Exit shutdown (sequence defined in Shutdown Sequence).
8.2.1.2.5.2 Normal Operation
The following are the only events supported during normal operation:
1. Writes to master/channel volume registers.
2. Writes to soft-mute register.
3. Enter and exit shutdown (sequence defined in Shutdown Sequence).
52
Event 3 is not supported for 240 ms + 1.3 × t
up ramp (where t
3. If desired, reconfigure by returning to step 4 of initialization sequence.
Exit:
1. Write 0x00 to register 0x05 (exit shutdown command can not be serviced for as much as 240 ms after trim
following AVDD/DVDD power-up ramp).
2. Wait at least 1 ms + 1.3 × t
start
(where t
is specified by register 0x1A).
start
3. Proceed with normal operation.
8.2.1.2.5.4 Power-Down Sequence
Use the following sequence to power down the device and its supplies:
1. If time permits, enter shutdown (sequence defined in Shutdown Sequence); else, in case of sudden power
loss, assert PDN = 0 and wait at least 2 ms.
2. Assert RST = 0.
3. Drive digital inputs low and ramp down PVDD supply as follows:
– Drive all digital inputs low after RST has been low for at least 2 µs.
– Ramp down PVDD while ensuring that it remains above 8 V until RST has been low for at least 2 µs.
4. Ramp down AVDD/DVDD while ensuring that it remains above 3 V until PVDD is below 6 V.
8.2.1.3 Application Performance Plots
CURVE TITLEFIGURE
Output Power Vs Supply Voltage Stereo BTL ModeFigure 5
Total Harmonic Distortion + Noise Vs Output Power Stereo BTL ModeFigure 10
Total Harmonic Distortion + Noise Vs Frequency Stereo BTL ModeFigure 7
Power Efficiency Vs Output Power Stereo BTL ModeFigure 13
Crosstalk Vs Frequency Stereo BTL ModeFigure 15
8.2.2 Mono Parallel Bridge Tied Load Application
A mono system refers to a system in which the amplifier is used to drive a single loudspeaker. Parallel Bridge
Tied Load (PBTL) indicates that the two full-bridge channels of the device are placed in parallel and drive the
loudspeaker simultaneously using an identical audio signal. The primary benefit of operating this device in PBTL
operation is to reduce the power dissipation and increase the current sourcing capabilities of the amplifier output.
In this mode of operation, the current limit of the audio amplifier is approximately doubled while the on-resistance
is approximately halved.
The loudspeaker can be a full-range transducer or one that only reproduces the low-frequency content of an
audio signal, as in the case of a powered subwoofer. Often in this use case, two stereo signals are mixed
together and sent through a low-pass filter to create a single audio signal which contains the low-frequency
information of the two channels.
The Mono PBTL Configuration is shown in Figure 51.
Output Power Vs Supply Voltage Mono PBTL ModeFigure 23
Total Harmonic Distortion + Noise Vs Output Power Mono PBTL ModeFigure 20
Total Harmonic Distortion + Noise Vs Frequency Mono PBTL ModeFigure 17
Power Efficiency Vs Output Power Mono PBTL ModeFigure 24
9Power Supply Recommendations
To facilitate system design, the TAS5733L device requires only a 3.3-V supply in addition to the PVDD powerstage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry.
Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by
built-in bootstrap circuitry requiring only a few external capacitors.
To provide good electrical and acoustical characteristics, the PWM signal path for the output stage is designed
as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BSTRP_x),
and power-stage supply pins (PVDD). The gate-drive voltage (GVDD_REG) is derived from the PVDD voltage.
Place all decoupling capacitors as close to their associated pins as possible. In addition, avoid inductance
between the power-supply pins and the decoupling capacitors.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BSTRP_x) to the power-stage output pin (AMP_OUT_X). When the power-stage output is low, the bootstrap
capacitor is charged through an internal diode connected between the gate-drive regulator output pin
(GVDD_REG) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is
shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. The
capacitors shown in Typical Applications ensure sufficient energy storage, even during minimal PWM duty
cycles, to keep the high-side power-stage FET (LDMOS) fully turned on during the remaining part of the PWM
cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD). For
optimal electrical performance, EMI compliance, and system reliability, each PVDD pin should be decoupled with
a 100-nF, X7R ceramic capacitor placed as close as possible to each supply pin.
The TAS5733L device is fully protected against erroneous power-stage turn-on due to parasitic gate charging.
Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and
the layout of the supporting components used around them. The system level performance metrics, including
thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all
affected by the device and supporting component layout. Ideally, the guidance provided in the Application
Information section with regard to device and component selection can be followed by precise adherence to the
layout guidance shown in Figure 52. The examples represent exemplary baseline balance of the engineering
trade-offs involved with laying out the device. The designs can be modified slightly as needed to meet the needs
of a given application. For example, in some applications, solution size can be compromised to improve thermal
performance through the use of additional contiguous copper near the device. Conversely, EMI performance can
be prioritized over thermal performance by routing on internal traces and incorporating a via picket-fence and
additional filtering components.
10.1.1 Decoupling Capacitors
Placing the bypassing and decoupling capacitors close to supply has been long understood in the industry. The
placement of the capacitors applies to AVDD and PVDD. However, the capacitors on the PVDD net for the
TAS5733L device deserve special attention. The small bypass capacitors on the PVDD lines of the DUT must be
placed as close the PVDD pins as possible. Not only does placing these devices far away from the pins increase
the electromagnetic interference in the system, but doing so can also negatively affect the reliability of the device.
Placement of these components too far from the TAS5733L device may cause ringing on the output pins that can
cause the voltage on the output pin to exceed the maximum allowable ratings shown in the Absolute Maximum
Ratings table, damaging the device. For that reason, the capacitors on the PVDD net must be no further away
from their associated PVDD pins than what is shown in the example layouts in the Layout Example section.
10.1.2 Thermal Performance and Grounding
Follow the layout examples shown in the Layout Example section of this document to achieve the best balance
of solution size, thermal, audio, and electromagnetic performance. In some cases, deviation from this guidance
may be required due to design constraints which cannot be avoided. In these instances, the system designer
should ensure that the heat can get out of the device and into the ambient air surrounding the device.
Fortunately, the heat created in the device naturally travels away from the device and into the lower temperature
structures around the device.
Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures.
These tips should be followed to achieve that goal:
•Avoid placing other heat-producing components or structures near the amplifier (including above or below in
the end equipment).
•Use a higher layer count PCB if possible to provide more heat sinking capability for the TAS5733L device and
to prevent traces of copper signal and power planes from breaking up the contiguous copper on the top and
bottom layer.
•Place the TAS5733L device away from the edge of the PCB when possible to ensure that heat can travel
away from the device on all four sides.
•Avoid cutting off the flow of heat from the TAS5733L device to the surrounding areas with traces or via
strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular
to the device.
•Unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads, orient it so that the narrow end of the passive component is facing the TAS5733L
device. Because the ground pins are the best conductors of heat in the package, maintain a contiguous
ground plane from the ground pins to the PCB area surrounding the device for as many of the ground pins as
possible.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
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