TEXAS INSTRUMENTS TAS5713 Technical data

TAS5713

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SLOS637 –DECEMBER 2009

25-W DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC

Check for Samples: TAS5713

FEATURES

•Audio Input/Output

–25-W Into an 8-Ω Load From a 20-V Supply

–Wide PVDD Range, From 8 V to 26 V

–Supports BTL Configuration With 4-Ω Load

–Efficient Class-D Operation Eliminates Need for Heatsinks

–One Serial Audio Input (Two Audio Channels)

–I2C Address Selection Pin (Chip Select)

–Single Output Filter PBTL Support

–Supports 8-kHz to 48-kHz Sample Rate (LJ/RJ/I2S)

•Audio/PWM Processing

–Independent Channel Volume Controls With Gain of 24 dB to Mute

–Programmable Two-Band Dynamic-Range Control

–22 Programmable Biquads for Speaker EQ and Other Audio-Processing Features

–Programmable Coefficients for DRC Filters

–DC Blocking Filters

•General Features

–I2C Serial Control Interface Operational Without MCLK

–Requires Only 3.3 V and PVDD

–No External Oscillator: Internal Oscillator for Automatic Rate Detection

–Surface-Mount, 48-Pin, 7-mm × 7-mm HTQFP Package

–Thermal and Short-Circuit Protection

–106-dB SNR, A-Weighted

–AD and BD PWM-Mode Support

–Up to 90% Efficient

•Benefits

–EQ: Speaker Equalization Improves Audio Performance

–DRC: Dynamic Range Compression. Can Be Used As Power Limiter. Enables Speaker Protection, Easy Listening, Night-Mode Listening

–Autobank Switching: Preload Coefficients for Different Sample Rates. No Need to Write New Coefficients to the Part When Sample Rate Changes

–Autodetect: Automatically Detects Sample-Rate Changes. No Need for External Microprocessor Intervention

DESCRIPTION

The TAS5713 is a 25-W, efficient, digital-audio power amplifier for driving stereo bridge-tied speakers. One serial data input allows processing of up to two discrete audio channels and seamless integration to most digital audio processors and MPEG decoders. The device accepts a wide range of input data and data rates. A fully programmable data path routes these channels to the internal speaker drivers.

The TAS5713 is a slave-only device receiving all clocks from external sources. The TAS5713 operates with a PWM carrier between a 384-kHz switching rate and a 352-KHz switching rate, depending on the input sample rate. Oversampling combined with a fourth-order noise shaper provides a flat noise floor and excellent dynamic range from 20 Hz to 20 kHz..

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPad is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.	Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

TAS5713

SLOS637 –DECEMBER 2009

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

SIMPLIFIED APPLICATION DIAGRAM

3.3 V

8 V–26 V

AVDD/DVDD

PVDD

LRCLK

OUT_A

Digital

SCLK

Audio

MCLK

BST_A

Source

LCBTL

Left

SDIN

BST_B

OUT_B

2

C

SDA

I

Control

SCL

OUT_C

A_SEL(FAULT)

RESET

Control

BST_C

Inputs

Right

PDN

BST_D

LCBTL

Loop

PLL_FLTP

OUT_D

Filter(1)

PLL_FLTM

B0264-10

(1) See the TAS5713 User'sGuide for loop filter values

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FUNCTIONAL VIEW

					OUT_A
					2× HB
				4th	FET Out
	Serial			Order	OUT_B
SDIN	Audio		S
		Digital Audio Processor		Noise
	Port		R
		(DAP)		Shaper
			C
				and
					OUT_C
				PWM	2× HB
					FET Out
					OUT_D
					Protection
					Logic
MCLK	Sample Rate		Click and Pop
			Control
SCLK	Autodetect
LRCLK	and PLL
		Microcontroller
SDA	Serial	Based
		System
SCL	Control
		Control
	Terminal Control
					B0262-06

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FAULT

VALID

PWM_D	PWM
	Rcv
PWMController
PWM_C	PWM
	Rcv

PWM_B	PWM
	Rcv

PWM_A	PWM
	Rcv

FAULT

Under-

4

voltage

4

Protection

Power

On

Protection

Reset

AGND

and

I/O Logic

Temp.

Sense

GND

Overcurrent

Isense

Protection

				BST_D
				PVDD_D
	Ctrl	Timing	Gate	OUT_D
			Drive
				Pulldown Resistor
			GVDD	PGND_CD
			Regulator	GVDD_OUT
				BST_C
				PVDD_C
	Ctrl	Timing	Gate	OUT_C
			Drive
				Pulldown Resistor
				PGND_CD
				BST_B
				PVDD_B
	Ctrl	Timing	Gate	OUT_B
			Drive
				Pulldown Resistor
			GVDD	PGND_AB
			Regulator
				BST_A
				PVDD_A
	Ctrl	Timing	Gate	OUT_A
			Drive
				Pulldown Resistor

PGND_AB

B0034-06

Figure 1. Power-Stage Functional Block Diagram

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DAP Process Structure
	I2C SUBADDRESS IN RED
0X72	0X70
R
+	2BQ
	7BQ
	58, 59	VOL1
	29–2F
0X73
	0X71
	DRC	0X46[0]
0X76	0X74 V2IM1	VOL2
L
+	2BQ
	7BQ
	5C, 5D
	30–36	I2C:57	I2C:56
0X77
		VDISTB	VDISTA
	0X75
	2BQ
	5E, 5F	VOL
	DRC	0X46[1]
		VOL
	2BQ
	5A, 5B
			B0321-09

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PIN ASSIGNMENT

OUT_A

PVDD_A

PVDD_A

BST_A

NC

SSTIMER

NC

PBTL

AVSS

PLL_FLTM

PLL_FLTP

VR_ANA

DEVICE INFORMATION

PHP Package

(Top View)

PGND_AB			PGND_AB			OUT_B			PVDD_B			PVDD_B			BST_B			BST_C			PVDD_C			PVDD_C			OUT_C			PGND_CD			PGND_CD
48			47			46			45			44			43			42			41			40			39			38			37
1																																	36
2																																	35
3																																	34
4																																	33
5																																	32
6														TAS5713																			31
7																																	30
8																																	29
9																																	28
10																																	27
11																																	26
12																																	25
13			14			15			16			17			18			19			20			21			22			23			24
AVDD				SEL FAULT		MCLK				OSC RES			DVSSO			VR DIG			PDN		LRCLK				SCLK			SDIN			SDA			SCL
				A_

OUT_D PVDD_D PVDD_D BST_D GVDD_OUT VREG AGND

GND

DVSS

DVDD

STEST

RESET

P0075-09

PIN FUNCTIONS

		PIN			TYPE(1)	5-V	TERMINATION(2)	DESCRIPTION
	NAME			NO.		TOLERANT
	AGND			30	P			Local analog ground for power stage
	A_SEL_			14	DIO			This pin is monitored on the rising edge of		A value of 0
		FAULT							RESET.
								(15-kΩ pulldown) sets the I2C device address to 0x34 and a value of
								1 (15-kΩ pullup) sets it to 0x36. this dual-function pin can be
								programmed to output internal power-stage errors.
	AVDD			13	P			3.3-V analog power supply
	AVSS			9	P			Analog 3.3-V supply ground
	BST_A			4	P			High-side bootstrap supply for half-bridge A
	BST_B			43	P			High-side bootstrap supply for half-bridge B
	BST_C			42	P			High-side bootstrap supply for half-bridge C
	BST_D			33	P			High-side bootstrap supply for half-bridge D
	DVDD			27	P			3.3-V digital power supply

(1)TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output

(2)All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input).

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							PIN FUNCTIONS (continued)
			PIN		TYPE(1)	5-V	TERMINATION(2)		DESCRIPTION
		NAME		NO.		TOLERANT
	DVSS			28	P			Digital ground
	DVSSO			17	P			Oscillator ground
	GND			29	P			Analog ground for power stage
	GVDD_OUT			32	P			Gate drive internal regulator output
	LRCLK			20	DI	5-V	Pulldown	Input serial audio data left/right clock (sample-rate clock)
	MCLK			15	DI	5-V	Pulldown	Master clock input
	NC			5, 7	–			No connect
	OSC_RES			16	AO			Oscillator trim resistor. Connect an 18.2-kΩ, 1% resistor to DVSSO.
	OUT_A			1	O			Output, half-bridge A
	OUT_B			46	O			Output, half-bridge B
	OUT_C			39	O			Output, half-bridge C
	OUT_D			36	O			Output, half-bridge D
	PBTL			8	DI			Low means BTL or SE mode; high means PBTL mode. Information
								goes directly to power stage.
				19	DI	5-V	Pullup	Power down, active-low.		prepares the device for loss of power
	PDN								PDN
								supplies by shutting down the noise shaper and initiating the PWM
								stop sequence.
	PGND_AB			47, 48	P			Power ground for half-bridges A and B
	PGND_CD			37, 38	P			Power ground for half-bridges C and D
	PLL_FLTM			10	AO			PLL negative loop-filter terminal
	PLL_FLTP			11	AO			PLL positive loop-filter terminal
	PVDD_A			2, 3	P			Power-supply input for half-bridge output A
	PVDD_B			44, 45	P			Power-supply input for half-bridge output B
	PVDD_C			40, 41	P			Power-supply input for half-bridge output C
	PVDD_D			34, 35	P			Power-supply input for half-bridge output D
				25	DI	5-V	Pullup	Reset, active-low. A system reset is generated by applying a logic
	RESET
								low to this pin. RESET is an asynchronous control signal that
								restores the DAP to its default conditions and places the PWM in the
								hard-mute (high-impedance) state.
	SCL			24	DI	5-V		I2C serial control clock input
	SCLK			21	DI	5-V	Pulldown	Serial audio-data clock (shift clock). SCLK is the serial-audio-port
								input-data bit clock.
	SDA			23	DIO	5-V		I2C serial control data interface input/output
	SDIN			22	DI	5-V	Pulldown	Serial audio data input. SDIN supports three discrete (stereo) data
								formats.
	SSTIMER			6	AI			Controls ramp time of OUT_x to minimize pop. Leave this pin
								floating for BD mode. Requires capacitor of 2.2 nF to GND in AD
								mode. The capacitor determines the ramp time.
	STEST			26	DI			Factory test pin. Connect directly to DVSS.
	VR_ANA			12	P			Internally regulated 1.8-V analog supply voltage. This pin must not
								be used to power external devices.
	VR_DIG			18	P			Internally regulated 1.8-V digital supply voltage. This pin must not be
								used to power external devices.
	VREG			31	P			Digital regulator output. Not to be used for powering external
								circuitry.

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted) (1)

			VALUE	UNIT
Supply voltage		DVDD, AVDD	–0.3 to 3.6	V
		PVDD_x	–0.3 to 30	V
		3.3-V digital input	–0.5 to DVDD + 0.5	V
Input voltage		5-V tolerant(2) digital input (except MCLK)	–0.5 to DVDD + 2.5(3)
		5-V tolerant MCLK input	–0.5 to AVDD + 2.5(3)
OUT_x to PGND_x			32(4)	V
BST_x to PGND_x			43(4)	V
Input clamp current, IIK			±20	mA
Output clamp current, IOK			±20	mA
Operating free-air temperature			0 to 85	°C
Operating junction temperature range			0 to 150	°C
Storage temperature range, Tstg			–40 to 125	°C

(1)Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.

(2)5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.

(3)Maximum pin voltage should not exceed 6 V.

(4)DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.

DISSIPATION RATINGS(1)

	PACKAGE	DERATING FACTOR	TA ≤ 25°C	TA = 45°C	TA = 70°C
		ABOVE TA = 25°C	POWER RATING	POWER RATING	POWER RATING
	7-mm × 7-mm HTQFP	40 mW/°C	5 W	4.2 W	3.2 W

(1)This data was taken using 1-oz. (0.035-mm thick) trace and copper pad that is soldered directly to a JEDEC-standard high-k PCB. The

thermal pad must be soldered to a thermal land on the printed-circuit board. See the PowerPad™ Thermally Enhanced Package application report (SLMA002) for more information about using the HTQFP thermal pad.

RECOMMENDED OPERATING CONDITIONS

			MIN	NOM	MAX	UNIT
	Digital/analog supply voltage	DVDD, AVDD	3	3.3	3.6	V
	Half-bridge supply voltage	PVDD_x	8		26	V
VIH	High-level input voltage	5-V tolerant	2			V
VIL	Low-level input voltage	5-V tolerant			0.8	V
TA	Operating ambient temperature range		0		85	°C
T (1)	Operating junction temperature range		0		125	°C
J
RL (BTL)	Load impedance	Output filter: L = 15 μH, C = 680 nF	4	8		Ω
RL (PBTL)	Load impedance	Output filter: L = 15 μH, C = 680 nF	2	4		Ω
LO (BTL)	Output-filter inductance	Minimum output inductance under	10			μH
		short-circuit condition

(1)Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.

PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS

	PARAMETER	TEST CONDITIONS	VALUE	UNIT
	Output sample rate	11.025/22.05/44.1-kHz data rate ±2%	352.8	kHz
		48/24/12/8/16/32-kHz data rate ±2%	384

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PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
fMCLKI	MCLK frequency		2.8224		24.576	MHz
	MCLK duty cycle		40%	50%	60%
tr /	Rise/fall time for MCLK				5	ns
tf(MCLK)
	LRCLK allowable drift before LRCLK reset				4	MCLKs
	External PLL filter capacitor C1	SMD 0603 X7R		47		nF
	External PLL filter capacitor C2	SMD 0603 X7R		4.7		nF
	External PLL filter resistor R	SMD 0603, metal film		470		Ω

ELECTRICAL CHARACTERISTICS

DC Characteristics

TA = 25°, PVCC_x = 18 V, DVDD = AVDD = 3.3 V, RL= 8 Ω, BTL AD mode, fS = 48 kHz (unless otherwise noted)

	PARAMETER					TEST CONDITIONS			MIN TYP	MAX	UNIT
						IOH = –4 mA
VOH	High-level output voltage		A_SEL_FAULT and SDA						2.4		V
						DVDD = 3 V
						IOL = 4 mA
VOL	Low-level output voltage		A_SEL_FAULT and SDA							0.5	V
						DVDD = 3 V
IIL	Low-level input current					VI < VIL ; DVDD = AVDD				75	μA
						= 3.6V
IIH	High-level input current					VI > VIH ; DVDD =				75(1)	μA
						AVDD = 3.6V
			3.3 V supply voltage (DVDD,			Normal mode			48	83
IDD	3.3 V supply current										mA
						Reset (RESET = low,			26	40
			AVDD)
						PDN = high)
						Normal mode			41	75
IPVDD	Supply current		No load (PVDD_x)								mA
						Reset		= low,	5	13
							(RESET
						PDN = high)
(2)	Drain-to-source resistance, LS		TJ = 25°C, includes metallization resistance						110
	Drain-to-source resistance,										mΩ
rDS(on)			TJ = 25°C, includes metallization resistance						110
	HS
I/O Protection
Vuvp	Undervoltage protection limit		PVDD falling						7.2		V
Vuvp,hyst	Undervoltage protection limit		PVDD rising						7.6		V
OTE(3)	Overtemperature error								150		°C
(3)	Extra temperature drop
OTEHYST	required to recover from error								30		°C
OLPC	Overload protection counter		fPWM = 384 kHz						0.63		ms
IOC	Overcurrent limit protection								4.5		A
IOCT	Overcurrent response time								150		ns
RPD	Internal pulldown resistor at		Connected when drivers are tristated to provide bootstrap						3		kΩ
	the output of each half-bridge		capacitor charge.

(1)IIH for the PBTL pin has a maximum limit of 200 µA due to an internal pulldown on the pin.

(2)This does not include bond-wire or pin resistance.

(3)Specified by design

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AC Characteristics (BTL, PBTL)

PVDD_x = 18 V, BTL AD mode, fS = 48 KHz, RL = 8 Ω, ROCP = 22 KΩ, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter, fPWM = 384 kHz, TA = 25°C (unless otherwise specified). All performance is in accordance with recommended operating

conditions (unless otherwise specified).

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
		PVDD = 18 V,10% THD, 1-kHz input signal		21.5
		PVDD = 18 V, 7% THD, 1-kHz input signal		20.3
		PVDD = 12 V, 10% THD, 1-kHz input signal		9.6
		PVDD = 12 V, 7% THD, 1-kHz input signal		9.1
		PVDD = 8 V, 10% THD, 1-kHz input signal		4.2
		PVDD = 8 V, 7% THD, 1-kHz input signal		4
PO	Power output per channel					W
		PBTL mode, PVDD = 12 V, RL = 4 Ω,		18.7
		10% THD, 1-kHz input signal
		PBTL mode, PVDD = 12 V, RL = 4 Ω,		17.7
		7% THD, 1-kHz input signal
		PBTL mode, PVDD = 18 V, RL = 4 Ω,		41.5
		10% THD, 1-kHz input signal
		PBTL mode, PVDD = 18 V, RL = 4 Ω,		39
		7% THD, 1-kHz input signal
		PVDD = 18 V, PO = 1 W		0.07%
THD+N	Total harmonic distortion + noise	PVDD = 12 V, PO = 1 W		0.03%
		PVDD = 8 V, PO = 1 W		0.1%
Vn	Output integrated noise (rms)	A-weighted		56		μV
	Crosstalk	PO = 0.25 W, f = 1 kHz (BD Mode)		–82		dB
		PO = 0.25 W, f = 1 kHz (AD Mode)		–69		dB
SNR	Signal-to-noise ratio(1)	A-weighted, f = 1 kHz, maximum power at		106		dB
		THD < 1%

(1)SNR is calculated relative to 0-dBFS input level.

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SERIAL AUDIO PORTS SLAVE MODE

over recommended operating conditions (unless otherwise noted)

	PARAMETER	TEST	MIN	TYP	MAX	UNIT
		CONDITIONS
fSCLKIN	Frequency, SCLK 32 × fS, 48 × fS, 64 × fS	CL = 30 pF	1.024		12.288	MHz
tsu1	Setup time, LRCLK to SCLK rising edge		10			ns
th1	Hold time, LRCLK from SCLK rising edge		10			ns
tsu2	Setup time, SDIN to SCLK rising edge		10			ns
th2	Hold time, SDIN from SCLK rising edge		10			ns
	LRCLK frequency		8	48	48	kHz
	SCLK duty cycle		40%	50%	60%
	LRCLK duty cycle		40%	50%	60%
	SCLK rising edges between LRCLK rising edges		32		64	SCLK
						edges
t(edge)	LRCLK clock edge with respect to the falling edge of SCLK		–1/4		1/4	SCLK
						period
tr/tf	Rise/fall time for SCLK/LRCLK				8	ns

tr	tf
SCLK
(Input)
t(edge)
th1
tsu1
LRCLK
(Input)
	th2
	tsu2
SDIN

T0026-04

Figure 2. Slave-Mode Serial Data-Interface Timing

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I2C SERIAL CONTROL PORT OPERATION

Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted)

	PARAMETER	TEST CONDITIONS	MIN MAX		UNIT
fSCL	Frequency, SCL	No wait states	400		kHz
tw(H)	Pulse duration, SCL high		0.6		μs
tw(L)	Pulse duration, SCL low		1.3		μs
tr	Rise time, SCL and SDA		300		ns
tf	Fall time, SCL and SDA		300		ns
tsu1	Setup time, SDA to SCL		100		ns
th1	Hold time, SCL to SDA		0		ns
t(buf)	Bus free time between stop and start conditions		1.3		μs
tsu2	Setup time, SCL to start condition		0.6		μs
th2	Hold time, start condition to SCL		0.6		μs
tsu3	Setup time, SCL to stop condition		0.6		μs
CL	Load capacitance for each bus line		400		pF

TW(H)				TW(L)		TR

SCL

TSU1								TH1

SDA

Figure 3. SCL and SDA Timing

SCL

th2

tsu3

t(buf)

tsu2

SDA

Start	Stop
Condition	Condition

Figure 4. Start and Stop Conditions Timing

TF

T0027-01

T0028-01

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RESET TIMING (RESET)

Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended Use Model section on usage of all terminals.

			PARAMETER	MIN	TYP MAX	UNIT
tw(RESET)	Pulse duration,		active	100		μs
		RESET
td(I2C_ready)	Time to enable I2C				12.0	ms

RESET

tw(RESET)

I2C Active		I2C Active

td(I2C_ready)

System Initialization.

Enable via I2C.

T0421-01

NOTES: On power up, it is recommended that the TAS5713 RESET be held LOW for at least 100 μs after DVDD has reached 3 V.

If RESET is asserted LOW while PDN is LOW, then RESET must continue to be held LOW for at least 100 μs after PDN is deasserted (HIGH).

Figure 5. Reset Timing

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THD+N (%)

TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω

TOTAL HARMONIC DISTORTION + NOISE

TOTAL HARMONIC DISTORTION + NOISE

		VS						VS
		FREQUENCY						FREQUENCY
10						10
PVDD = 8V							PVDD = 12V
RL = 8Ω							RL = 8Ω
TA = 25°C							TA = 25°C
1						1		PO = 5W
	PO = 2.5W
									PO = 2.5W
					(%)
0.1					THD+N	0.1
PO	= 0.5W	PO = 1W
								PO = 1W
0.01						0.01
0.001						0.001
20	100	1k	10k	20k		20	100	1k	10k	20k
		Frequency (Hz)		G001				Frequency (Hz)		G002

Figure 6.	Figure 7.
TOTAL HARMONIC DISTORTION + NOISE	TOTAL HARMONIC DISTORTION + NOISE

			VS						VS
			FREQUENCY						FREQUENCY
	10						10
		PVDD = 18V						PVDD = 24V
		RL = 8Ω						RL = 8Ω
		TA = 25°C						TA = 25°C
	1						1
		PO = 5W							PO = 5W
(%)						(%)				PO = 1W
THD+N	0.1					THD+N	0.1
		PO = 1W	PO = 2.5W						PO = 2.5W
	0.01						0.01
	0.001						0.001
	20	100	1k	10k	20k		20	100	1k	10k	20k
			Frequency (Hz)		G003				Frequency (Hz)		G004
			Figure 8.						Figure 9.

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SLOS637 –DECEMBER 2009

TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω (continued)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE	TOTAL HARMONIC DISTORTION + NOISE
VS	VS
OUTPUT POWER	OUTPUT POWER

10						10
	PVDD = 8V						PVDD = 12V
	RL = 8Ω						RL = 8Ω
	TA = 25°C						TA = 25°C
1						1
	f = 20Hz
					(%)			f = 1kHz
0.1					THD+N	0.1
			f = 1kHz						f = 20Hz
0.01						0.01
		f = 10kHz						f = 10kHz
0.001						0.001
0.01	0.1	1	10	40		0.01	0.1	1	10	40
		Output Power (W)		G005				Output Power (W)		G006

Figure 10.

Figure 11.

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

TOTAL HARMONIC DISTORTION + NOISE

		VS						VS
		OUTPUT POWER						OUTPUT POWER
10						10
	PVDD = 18V						PVDD = 24V
	RL = 8Ω						RL = 8Ω
	TA = 25°C						TA = 25°C
1						1
		f = 20Hz						f = 1kHz
		f = 1kHz			(%)
							f = 20Hz
					THD+N
0.1						0.1
0.01						0.01
			f = 10kHz					f = 10kHz
0.001						0.001
0.01	0.1	1	10	40		0.01	0.1	1	10	40
		Output Power (W)		G007				Output Power (W)		G008
		Figure 12.						Figure 13.

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω (continued)

				OUTPUT POWER											EFFICIENCY
						VS										VS
				SUPPLY VOLTAGE										TOTAL OUTPUT POWER
	40											100
		RL = 8Ω										90
	35	°
		TA = 25 C
												80
	30																PVDD = 24V
												70
Output Power (W)	25															PVDD = 18V
		THD+N = 10%									Efficiency (%)	60
																PVDD = 12V
	20											50
															PVDD = 8V
	15											40
							THD+N = 1%					30
	10
												20
	5											10							RL = 8Ω
																			TA = 25°C
	0											0
	8	10	12	14	16	18	20	22	24	26		0	5	10	15	20	25	30	35	40
				Supply Voltage (V)						G009					Total Output Power (W)					G010

NOTE: Dashed lines represent thermally limited regions.

Figure 14.

NOTE: Dashed lines represent thermally limited regions.

Figure 15.

			CROSSTALK						CROSSTALK
			VS						VS
			FREQUENCY						FREQUENCY
	0						0
	-10	PO = 1W					-10	PO = 1W
		PVDD = 8V						PVDD = 12V
		RL = 8Ω						RL = 8Ω
	-20	TA = 25°C					-20	TA = 25°C
	-30						-30
(dB)	-40					(dB)	-40
Crosstalk	-60					Crosstalk	-60
	-50						-50
	-70		Right to Left				-70
									Left to Right
	-80						-80
			Left to Right
	-90						-90
									Right to Left
	-100						-100
	20	100	1k	10k	20k		20	100	1k	10k	20k
			Frequency (Hz)		G011				Frequency (Hz)		G012
			Figure 16.						Figure 17.

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SLOS637 –DECEMBER 2009

TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω (continued)

Crosstalk (dB)

CROSSTALK

VS

FREQUENCY

0
-10		PO = 1W
		PVDD = 18V
		RL = 8Ω
-20		TA = 25°C

-30

-40

-50

-60

-70	Right to Left

-80

-90

Left to Right

-100
20		100						1k	10k	20k
			Frequency (Hz)								G013

Figure 18.

Crosstalk (dB)

																		CROSSTALK
																						VS
																		FREQUENCY
0
-10			PO = 1W
			PVDD = 24V
			RL = 8Ω
-20			TA = 25°C
-30
-40
-50
-60
																Right to Left
-70
-80

-90
							Left to Right
-100
20		100												1k			10k	20k
								Frequency (Hz)											G014

Figure 19.

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 4 Ω

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

			VS						VS
			FREQUENCY						FREQUENCY
	10						10
		PVDD = 12V						PVDD = 18V
		RL = 4Ω						RL = 4Ω
		TA = 25°C						TA = 25°C
			PO = 5W
	1						1
				PO = 2.5W					PO = 5W
(%)						(%)
THD+N	0.1					THD+N	0.1
			PO = 1W						PO = 1W
	0.01						0.01
									PO = 2.5W
	0.001						0.001
	20	100	1k	10k	20k		20	100	1k	10k	20k
			Frequency (Hz)		G021				Frequency (Hz)		G022
			Figure 20.						Figure 21.

TOTAL HARMONIC DISTORTION + NOISE

TOTAL HARMONIC DISTORTION + NOISE

			VS						VS
			OUTPUT POWER						OUTPUT POWER
	10						10
		PVDD = 12V						PVDD = 18V
		RL = 4Ω						RL = 4Ω
		TA = 25°C						TA = 25°C
	1						1
		f = 1kHz							f = 1kHz
(%)						(%)
THD+N	0.1					THD+N	0.1
										f = 20Hz
	0.01						0.01
				f = 10kHz					f = 10kHz
			f = 20Hz
	0.001						0.001
	0.01	0.1	1	10	40		0.01	0.1	1	10	50
			Output Power (W)		G026				Output Power (W)		G027
			Figure 22.						Figure 23.

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SLOS637 –DECEMBER 2009

TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 4 Ω (continued)

			CROSSTALK						CROSSTALK
			VS						VS
			FREQUENCY						FREQUENCY
	0						0
	-10	PO = 1W					-10	PO = 1W
		PVDD = 12V						PVDD = 18V
	-20	RL = 4Ω					-20	RL = 4Ω
		TA = 25°C						TA = 25°C
	-30						-30
(dB)	-40					(dB)	-40
	-50						-50
Crosstalk						Crosstalk
	-60		Right to Left				-60		Right to Left
	-70						-70
	-80						-80
			Left to Right						Left to Right
	-90						-90
	-100						-100
	-110						-110
	20	100	1k	10k	20k		20	100	1k	10k	20k
			Frequency (Hz)		G023				Frequency (Hz)		G024

Figure 24.

Figure 25.

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THD+N (%)

TYPICAL CHARACTERISTICS, PBTL CONFIGURATION, 4 Ω

TOTAL HARMONIC DISTORTION + NOISE

TOTAL HARMONIC DISTORTION + NOISE

		VS						VS
		FREQUENCY						FREQUENCY
10						10
	PVDD = 12V						PVDD = 24V
	RL = 4Ω						RL = 4Ω
	TA = 25°C						TA = 25°C
1						1
		PO = 2.5W					PO = 5W
		PO = 5W					PO = 2.5W
					(%)
0.1					THD+N	0.1
0.01		PO = 1W				0.01
								PO	= 1W
0.001						0.001
20	100	1k	10k	20k		20	100	1k	10k	20k
		Frequency (Hz)		G015				Frequency (Hz)		G016

Figure 26.

Figure 27.

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE	TOTAL HARMONIC DISTORTION + NOISE
VS	VS
OUTPUT POWER	OUTPUT POWER

10						10
	PVDD = 12V						PVDD = 24V
	RL = 4Ω						RL = 4Ω
	TA = 25°C						TA = 25°C
1						1
		f = 1kHz							f = 20Hz
		f = 20Hz			(%)
0.1					THD+N	0.1
									f = 1kHz
0.01						0.01
	f = 10kHz						f = 10kHz
0.001						0.001
0.01	0.1	1	10	50		0.01	0.1	1	10	40
		Output Power (W)		G017				Output Power (W)		G018

Figure 28.

Figure 29.

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