TAS5713
www.ti.com |
SLOS637 –DECEMBER 2009 |
25-W DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC
Check for Samples: TAS5713
•Audio Input/Output
–25-W Into an 8-Ω Load From a 20-V Supply
–Wide PVDD Range, From 8 V to 26 V
–Supports BTL Configuration With 4-Ω Load
–Efficient Class-D Operation Eliminates Need for Heatsinks
–One Serial Audio Input (Two Audio Channels)
–I2C Address Selection Pin (Chip Select)
–Single Output Filter PBTL Support
–Supports 8-kHz to 48-kHz Sample Rate (LJ/RJ/I2S)
•Audio/PWM Processing
–Independent Channel Volume Controls With Gain of 24 dB to Mute
–Programmable Two-Band Dynamic-Range Control
–22 Programmable Biquads for Speaker EQ and Other Audio-Processing Features
–Programmable Coefficients for DRC Filters
–DC Blocking Filters
•General Features
–I2C Serial Control Interface Operational Without MCLK
–Requires Only 3.3 V and PVDD
–No External Oscillator: Internal Oscillator for Automatic Rate Detection
–Surface-Mount, 48-Pin, 7-mm × 7-mm HTQFP Package
–Thermal and Short-Circuit Protection
–106-dB SNR, A-Weighted
–AD and BD PWM-Mode Support
–Up to 90% Efficient
•Benefits
–EQ: Speaker Equalization Improves Audio Performance
–DRC: Dynamic Range Compression. Can Be Used As Power Limiter. Enables Speaker Protection, Easy Listening, Night-Mode Listening
–Autobank Switching: Preload Coefficients for Different Sample Rates. No Need to Write New Coefficients to the Part When Sample Rate Changes
–Autodetect: Automatically Detects Sample-Rate Changes. No Need for External Microprocessor Intervention
The TAS5713 is a 25-W, efficient, digital-audio power amplifier for driving stereo bridge-tied speakers. One serial data input allows processing of up to two discrete audio channels and seamless integration to most digital audio processors and MPEG decoders. The device accepts a wide range of input data and data rates. A fully programmable data path routes these channels to the internal speaker drivers.
The TAS5713 is a slave-only device receiving all clocks from external sources. The TAS5713 operates with a PWM carrier between a 384-kHz switching rate and a 352-KHz switching rate, depending on the input sample rate. Oversampling combined with a fourth-order noise shaper provides a flat noise floor and excellent dynamic range from 20 Hz to 20 kHz..
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPad is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. |
Copyright © 2009, Texas Instruments Incorporated |
Products conform to specifications per the terms of the Texas |
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Instruments standard warranty. Production processing does not |
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necessarily include testing of all parameters. |
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TAS5713
SLOS637 –DECEMBER 2009 |
www.ti.com |
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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3.3 V |
8 V–26 V |
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AVDD/DVDD |
PVDD |
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LRCLK |
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MCLK |
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BST_A |
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Source |
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LCBTL |
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Left |
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SDIN |
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C |
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SDA |
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I |
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Control |
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SCL |
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OUT_C |
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A_SEL(FAULT) |
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RESET |
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Control |
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BST_C |
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Inputs |
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Right |
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PDN |
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BST_D |
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LCBTL |
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Loop |
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PLL_FLTP |
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OUT_D |
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Filter(1) |
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PLL_FLTM |
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B0264-10
(1) See the TAS5713 User'sGuide for loop filter values
2 |
Submit Documentation Feedback |
Copyright © 2009, Texas Instruments Incorporated |
Product Folder Link(s): TAS5713
TAS5713
www.ti.com |
SLOS637 –DECEMBER 2009 |
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OUT_A |
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2× HB |
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4th |
FET Out |
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Serial |
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Order |
OUT_B |
SDIN |
Audio |
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S |
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Digital Audio Processor |
Noise |
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R |
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(DAP) |
Shaper |
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C |
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and |
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OUT_C |
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PWM |
2× HB |
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FET Out |
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OUT_D |
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Protection |
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Logic |
MCLK |
Sample Rate |
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Click and Pop |
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Control |
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SCLK |
Autodetect |
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LRCLK |
and PLL |
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Microcontroller |
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SDA |
Serial |
Based |
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System |
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SCL |
Control |
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Control |
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Terminal Control |
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B0262-06 |
Copyright © 2009, Texas Instruments Incorporated |
Submit Documentation Feedback |
3 |
Product Folder Link(s): TAS5713
TAS5713
SLOS637 –DECEMBER 2009 |
www.ti.com |
FAULT
VALID
PWM_D |
PWM |
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Rcv |
PWMController |
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PWM_C |
PWM |
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Rcv |
PWM_B |
PWM |
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Rcv |
PWM_A |
PWM |
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Rcv |
FAULT
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Under- |
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4 |
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Protection |
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On |
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Protection |
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Reset |
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AGND |
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I/O Logic |
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Temp. |
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Sense |
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GND |
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Overcurrent |
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Isense |
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Protection |
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BST_D |
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PVDD_D |
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Ctrl |
Timing |
Gate |
OUT_D |
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Drive |
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Pulldown Resistor |
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GVDD |
PGND_CD |
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Regulator |
GVDD_OUT |
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BST_C |
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PVDD_C |
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Timing |
Gate |
OUT_C |
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Pulldown Resistor |
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PGND_CD |
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BST_B |
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PVDD_B |
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Timing |
Gate |
OUT_B |
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Pulldown Resistor |
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GVDD |
PGND_AB |
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BST_A |
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PVDD_A |
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Timing |
Gate |
OUT_A |
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Pulldown Resistor |
PGND_AB
B0034-06
Figure 1. Power-Stage Functional Block Diagram
4 |
Submit Documentation Feedback |
Copyright © 2009, Texas Instruments Incorporated |
Product Folder Link(s): TAS5713
|
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TAS5713 |
www.ti.com |
|
SLOS637 –DECEMBER 2009 |
|
DAP Process Structure |
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I2C SUBADDRESS IN RED |
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0X72 |
0X70 |
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R |
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+ |
2BQ |
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7BQ |
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58, 59 |
VOL1 |
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29–2F |
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0X73 |
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0X71 |
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DRC |
0X46[0] |
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0X76 |
0X74 V2IM1 |
VOL2 |
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+ |
2BQ |
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7BQ |
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5C, 5D |
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30–36 |
I2C:57 |
I2C:56 |
0X77 |
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VDISTB |
VDISTA |
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0X75 |
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2BQ |
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5E, 5F |
VOL |
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DRC |
0X46[1] |
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VOL |
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2BQ |
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5A, 5B |
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B0321-09 |
Copyright © 2009, Texas Instruments Incorporated |
Submit Documentation Feedback |
5 |
Product Folder Link(s): TAS5713
TAS5713
SLOS637 –DECEMBER 2009 |
www.ti.com |
OUT_A
PVDD_A
PVDD_A
BST_A
NC
SSTIMER
NC
PBTL
AVSS
PLL_FLTM
PLL_FLTP
VR_ANA
PHP Package
(Top View)
PGND_AB |
PGND_AB |
OUT_B |
PVDD_B |
PVDD_B |
BST_B |
BST_C |
PVDD_C |
PVDD_C |
OUT_C |
PGND_CD |
PGND_CD |
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48 |
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46 |
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37 |
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1 |
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2 |
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3 |
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34 |
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AVDD |
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SEL FAULT |
MCLK |
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OSC RES |
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DVSSO |
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VR DIG |
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PDN |
LRCLK |
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SCLK |
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SDIN |
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SDA |
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SCL |
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A_ |
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OUT_D PVDD_D PVDD_D BST_D GVDD_OUT VREG AGND
GND
DVSS
DVDD
STEST
RESET
P0075-09
PIN FUNCTIONS
|
PIN |
|
TYPE(1) |
5-V |
TERMINATION(2) |
DESCRIPTION |
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NAME |
NO. |
TOLERANT |
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AGND |
30 |
P |
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Local analog ground for power stage |
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A_SEL_ |
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14 |
DIO |
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This pin is monitored on the rising edge of |
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A value of 0 |
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FAULT |
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RESET. |
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(15-kΩ pulldown) sets the I2C device address to 0x34 and a value of |
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1 (15-kΩ pullup) sets it to 0x36. this dual-function pin can be |
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programmed to output internal power-stage errors. |
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AVDD |
13 |
P |
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3.3-V analog power supply |
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AVSS |
9 |
P |
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Analog 3.3-V supply ground |
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BST_A |
4 |
P |
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High-side bootstrap supply for half-bridge A |
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BST_B |
43 |
P |
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High-side bootstrap supply for half-bridge B |
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BST_C |
42 |
P |
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High-side bootstrap supply for half-bridge C |
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BST_D |
33 |
P |
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High-side bootstrap supply for half-bridge D |
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DVDD |
27 |
P |
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3.3-V digital power supply |
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(1)TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2)All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input).
6 |
Submit Documentation Feedback |
Copyright © 2009, Texas Instruments Incorporated |
Product Folder Link(s): TAS5713
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TAS5713 |
www.ti.com |
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SLOS637 –DECEMBER 2009 |
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PIN FUNCTIONS (continued) |
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PIN |
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TYPE(1) |
5-V |
TERMINATION(2) |
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DESCRIPTION |
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NAME |
NO. |
TOLERANT |
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DVSS |
28 |
P |
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Digital ground |
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DVSSO |
17 |
P |
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Oscillator ground |
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GND |
29 |
P |
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Analog ground for power stage |
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GVDD_OUT |
32 |
P |
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Gate drive internal regulator output |
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LRCLK |
20 |
DI |
5-V |
Pulldown |
Input serial audio data left/right clock (sample-rate clock) |
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MCLK |
15 |
DI |
5-V |
Pulldown |
Master clock input |
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NC |
5, 7 |
– |
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No connect |
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OSC_RES |
16 |
AO |
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Oscillator trim resistor. Connect an 18.2-kΩ, 1% resistor to DVSSO. |
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OUT_A |
1 |
O |
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Output, half-bridge A |
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OUT_B |
46 |
O |
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Output, half-bridge B |
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OUT_C |
39 |
O |
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Output, half-bridge C |
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OUT_D |
36 |
O |
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Output, half-bridge D |
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PBTL |
8 |
DI |
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Low means BTL or SE mode; high means PBTL mode. Information |
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goes directly to power stage. |
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19 |
DI |
5-V |
Pullup |
Power down, active-low. |
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prepares the device for loss of power |
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PDN |
PDN |
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supplies by shutting down the noise shaper and initiating the PWM |
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stop sequence. |
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PGND_AB |
47, 48 |
P |
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Power ground for half-bridges A and B |
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PGND_CD |
37, 38 |
P |
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Power ground for half-bridges C and D |
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PLL_FLTM |
10 |
AO |
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PLL negative loop-filter terminal |
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PLL_FLTP |
11 |
AO |
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PLL positive loop-filter terminal |
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PVDD_A |
2, 3 |
P |
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Power-supply input for half-bridge output A |
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PVDD_B |
44, 45 |
P |
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Power-supply input for half-bridge output B |
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PVDD_C |
40, 41 |
P |
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Power-supply input for half-bridge output C |
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PVDD_D |
34, 35 |
P |
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Power-supply input for half-bridge output D |
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25 |
DI |
5-V |
Pullup |
Reset, active-low. A system reset is generated by applying a logic |
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RESET |
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low to this pin. RESET is an asynchronous control signal that |
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restores the DAP to its default conditions and places the PWM in the |
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hard-mute (high-impedance) state. |
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SCL |
24 |
DI |
5-V |
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I2C serial control clock input |
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SCLK |
21 |
DI |
5-V |
Pulldown |
Serial audio-data clock (shift clock). SCLK is the serial-audio-port |
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input-data bit clock. |
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SDA |
23 |
DIO |
5-V |
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I2C serial control data interface input/output |
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SDIN |
22 |
DI |
5-V |
Pulldown |
Serial audio data input. SDIN supports three discrete (stereo) data |
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formats. |
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SSTIMER |
6 |
AI |
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Controls ramp time of OUT_x to minimize pop. Leave this pin |
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floating for BD mode. Requires capacitor of 2.2 nF to GND in AD |
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mode. The capacitor determines the ramp time. |
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STEST |
26 |
DI |
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Factory test pin. Connect directly to DVSS. |
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VR_ANA |
12 |
P |
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Internally regulated 1.8-V analog supply voltage. This pin must not |
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be used to power external devices. |
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VR_DIG |
18 |
P |
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Internally regulated 1.8-V digital supply voltage. This pin must not be |
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used to power external devices. |
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VREG |
31 |
P |
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Digital regulator output. Not to be used for powering external |
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circuitry. |
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Copyright © 2009, Texas Instruments Incorporated |
Submit Documentation Feedback |
7 |
Product Folder Link(s): TAS5713
TAS5713
SLOS637 –DECEMBER 2009 www.ti.com
over operating free-air temperature range (unless otherwise noted) (1)
|
|
|
VALUE |
UNIT |
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|
Supply voltage |
|
DVDD, AVDD |
–0.3 to 3.6 |
V |
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PVDD_x |
–0.3 to 30 |
V |
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|||
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3.3-V digital input |
–0.5 to DVDD + 0.5 |
V |
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Input voltage |
|
5-V tolerant(2) digital input (except MCLK) |
–0.5 to DVDD + 2.5(3) |
|
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|
5-V tolerant MCLK input |
–0.5 to AVDD + 2.5(3) |
|
OUT_x to PGND_x |
|
32(4) |
V |
|
BST_x to PGND_x |
|
43(4) |
V |
|
Input clamp current, IIK |
±20 |
mA |
||
Output clamp current, IOK |
±20 |
mA |
||
Operating free-air temperature |
0 to 85 |
°C |
||
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Operating junction temperature range |
0 to 150 |
°C |
||
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Storage temperature range, Tstg |
–40 to 125 |
°C |
(1)Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2)5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.
(3)Maximum pin voltage should not exceed 6 V.
(4)DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.
PACKAGE |
DERATING FACTOR |
TA ≤ 25°C |
TA = 45°C |
TA = 70°C |
|
ABOVE TA = 25°C |
POWER RATING |
POWER RATING |
POWER RATING |
||
|
|||||
7-mm × 7-mm HTQFP |
40 mW/°C |
5 W |
4.2 W |
3.2 W |
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|
(1)This data was taken using 1-oz. (0.035-mm thick) trace and copper pad that is soldered directly to a JEDEC-standard high-k PCB. The
thermal pad must be soldered to a thermal land on the printed-circuit board. See the PowerPad™ Thermally Enhanced Package application report (SLMA002) for more information about using the HTQFP thermal pad.
|
|
|
MIN |
NOM |
MAX |
UNIT |
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|
Digital/analog supply voltage |
DVDD, AVDD |
3 |
3.3 |
3.6 |
V |
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Half-bridge supply voltage |
PVDD_x |
8 |
|
26 |
V |
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VIH |
High-level input voltage |
5-V tolerant |
2 |
|
|
V |
VIL |
Low-level input voltage |
5-V tolerant |
|
|
0.8 |
V |
TA |
Operating ambient temperature range |
|
0 |
|
85 |
°C |
T (1) |
Operating junction temperature range |
|
0 |
|
125 |
°C |
J |
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RL (BTL) |
Load impedance |
Output filter: L = 15 μH, C = 680 nF |
4 |
8 |
|
Ω |
RL (PBTL) |
Load impedance |
Output filter: L = 15 μH, C = 680 nF |
2 |
4 |
|
Ω |
LO (BTL) |
Output-filter inductance |
Minimum output inductance under |
10 |
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μH |
short-circuit condition |
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(1)Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.
PARAMETER |
TEST CONDITIONS |
VALUE |
UNIT |
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|
|
Output sample rate |
11.025/22.05/44.1-kHz data rate ±2% |
352.8 |
kHz |
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|||
48/24/12/8/16/32-kHz data rate ±2% |
384 |
|||
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|||
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8 |
Submit Documentation Feedback |
Copyright © 2009, Texas Instruments Incorporated |
Product Folder Link(s): TAS5713
|
|
|
|
|
|
TAS5713 |
www.ti.com |
|
|
SLOS637 –DECEMBER 2009 |
|||
PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS |
|
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||
|
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
|
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|
|
fMCLKI |
MCLK frequency |
|
2.8224 |
|
24.576 |
MHz |
|
MCLK duty cycle |
|
40% |
50% |
60% |
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tr / |
Rise/fall time for MCLK |
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5 |
ns |
tf(MCLK) |
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LRCLK allowable drift before LRCLK reset |
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4 |
MCLKs |
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External PLL filter capacitor C1 |
SMD 0603 X7R |
|
47 |
|
nF |
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External PLL filter capacitor C2 |
SMD 0603 X7R |
|
4.7 |
|
nF |
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External PLL filter resistor R |
SMD 0603, metal film |
|
470 |
|
Ω |
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|
TA = 25°, PVCC_x = 18 V, DVDD = AVDD = 3.3 V, RL= 8 Ω, BTL AD mode, fS = 48 kHz (unless otherwise noted)
|
PARAMETER |
|
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|
TEST CONDITIONS |
MIN TYP |
MAX |
UNIT |
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IOH = –4 mA |
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||
VOH |
High-level output voltage |
|
A_SEL_FAULT and SDA |
2.4 |
|
V |
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DVDD = 3 V |
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IOL = 4 mA |
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VOL |
Low-level output voltage |
|
A_SEL_FAULT and SDA |
|
0.5 |
V |
|||||
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DVDD = 3 V |
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|||||||||
IIL |
Low-level input current |
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VI < VIL ; DVDD = AVDD |
|
75 |
μA |
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= 3.6V |
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IIH |
High-level input current |
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VI > VIH ; DVDD = |
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75(1) |
μA |
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AVDD = 3.6V |
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3.3 V supply voltage (DVDD, |
Normal mode |
48 |
83 |
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IDD |
3.3 V supply current |
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mA |
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Reset (RESET = low, |
26 |
40 |
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AVDD) |
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PDN = high) |
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Normal mode |
41 |
75 |
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IPVDD |
Supply current |
|
No load (PVDD_x) |
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mA |
||
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Reset |
|
= low, |
5 |
13 |
||||||
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(RESET |
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PDN = high) |
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(2) |
Drain-to-source resistance, LS |
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TJ = 25°C, includes metallization resistance |
110 |
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Drain-to-source resistance, |
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mΩ |
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rDS(on) |
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TJ = 25°C, includes metallization resistance |
110 |
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HS |
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I/O Protection |
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Vuvp |
Undervoltage protection limit |
|
PVDD falling |
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7.2 |
|
V |
||
Vuvp,hyst |
Undervoltage protection limit |
|
PVDD rising |
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7.6 |
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V |
||
OTE(3) |
Overtemperature error |
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150 |
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°C |
(3) |
Extra temperature drop |
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OTEHYST |
required to recover from error |
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30 |
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°C |
OLPC |
Overload protection counter |
|
fPWM = 384 kHz |
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0.63 |
|
ms |
||
IOC |
Overcurrent limit protection |
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4.5 |
|
A |
IOCT |
Overcurrent response time |
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150 |
|
ns |
RPD |
Internal pulldown resistor at |
|
Connected when drivers are tristated to provide bootstrap |
3 |
|
kΩ |
|||||
the output of each half-bridge |
|
capacitor charge. |
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(1)IIH for the PBTL pin has a maximum limit of 200 µA due to an internal pulldown on the pin.
(2)This does not include bond-wire or pin resistance.
(3)Specified by design
Copyright © 2009, Texas Instruments Incorporated |
Submit Documentation Feedback |
9 |
Product Folder Link(s): TAS5713
TAS5713
SLOS637 –DECEMBER 2009 |
www.ti.com |
PVDD_x = 18 V, BTL AD mode, fS = 48 KHz, RL = 8 Ω, ROCP = 22 KΩ, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter, fPWM = 384 kHz, TA = 25°C (unless otherwise specified). All performance is in accordance with recommended operating
conditions (unless otherwise specified).
|
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
|
|
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PVDD = 18 V,10% THD, 1-kHz input signal |
|
21.5 |
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PVDD = 18 V, 7% THD, 1-kHz input signal |
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20.3 |
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PVDD = 12 V, 10% THD, 1-kHz input signal |
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9.6 |
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PVDD = 12 V, 7% THD, 1-kHz input signal |
|
9.1 |
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PVDD = 8 V, 10% THD, 1-kHz input signal |
|
4.2 |
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PVDD = 8 V, 7% THD, 1-kHz input signal |
|
4 |
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PO |
Power output per channel |
|
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|
W |
PBTL mode, PVDD = 12 V, RL = 4 Ω, |
|
18.7 |
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10% THD, 1-kHz input signal |
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PBTL mode, PVDD = 12 V, RL = 4 Ω, |
|
17.7 |
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7% THD, 1-kHz input signal |
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PBTL mode, PVDD = 18 V, RL = 4 Ω, |
|
41.5 |
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10% THD, 1-kHz input signal |
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PBTL mode, PVDD = 18 V, RL = 4 Ω, |
|
39 |
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7% THD, 1-kHz input signal |
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PVDD = 18 V, PO = 1 W |
|
0.07% |
|
|
THD+N |
Total harmonic distortion + noise |
PVDD = 12 V, PO = 1 W |
|
0.03% |
|
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PVDD = 8 V, PO = 1 W |
|
0.1% |
|
|
Vn |
Output integrated noise (rms) |
A-weighted |
|
56 |
|
μV |
|
Crosstalk |
PO = 0.25 W, f = 1 kHz (BD Mode) |
|
–82 |
|
dB |
|
PO = 0.25 W, f = 1 kHz (AD Mode) |
|
–69 |
|
dB |
|
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|
|||
SNR |
Signal-to-noise ratio(1) |
A-weighted, f = 1 kHz, maximum power at |
|
106 |
|
dB |
|
|
THD < 1% |
|
|
|
|
(1)SNR is calculated relative to 0-dBFS input level.
10 |
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Copyright © 2009, Texas Instruments Incorporated |
Product Folder Link(s): TAS5713
TAS5713
www.ti.com |
SLOS637 –DECEMBER 2009 |
over recommended operating conditions (unless otherwise noted)
|
PARAMETER |
TEST |
MIN |
TYP |
MAX |
UNIT |
|
CONDITIONS |
|||||
|
|
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|
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|
fSCLKIN |
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS |
CL = 30 pF |
1.024 |
|
12.288 |
MHz |
tsu1 |
Setup time, LRCLK to SCLK rising edge |
|
10 |
|
|
ns |
th1 |
Hold time, LRCLK from SCLK rising edge |
|
10 |
|
|
ns |
tsu2 |
Setup time, SDIN to SCLK rising edge |
|
10 |
|
|
ns |
th2 |
Hold time, SDIN from SCLK rising edge |
|
10 |
|
|
ns |
|
LRCLK frequency |
|
8 |
48 |
48 |
kHz |
|
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|
SCLK duty cycle |
|
40% |
50% |
60% |
|
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|
LRCLK duty cycle |
|
40% |
50% |
60% |
|
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|
SCLK rising edges between LRCLK rising edges |
|
32 |
|
64 |
SCLK |
|
|
|
edges |
|||
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|
t(edge) |
LRCLK clock edge with respect to the falling edge of SCLK |
|
–1/4 |
|
1/4 |
SCLK |
|
|
|
|
|
|
period |
tr/tf |
Rise/fall time for SCLK/LRCLK |
|
|
|
8 |
ns |
tr |
tf |
SCLK |
|
(Input) |
|
t(edge) |
|
th1 |
|
tsu1 |
|
LRCLK |
|
(Input) |
|
|
th2 |
|
tsu2 |
SDIN |
|
T0026-04
Figure 2. Slave-Mode Serial Data-Interface Timing
Copyright © 2009, Texas Instruments Incorporated |
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11 |
Product Folder Link(s): TAS5713
TAS5713
SLOS637 –DECEMBER 2009 |
www.ti.com |
Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted)
|
PARAMETER |
TEST CONDITIONS |
MIN MAX |
UNIT |
|
|
|
|
|
|
|
fSCL |
Frequency, SCL |
No wait states |
400 |
kHz |
|
tw(H) |
Pulse duration, SCL high |
|
0.6 |
|
μs |
tw(L) |
Pulse duration, SCL low |
|
1.3 |
|
μs |
tr |
Rise time, SCL and SDA |
|
300 |
ns |
|
tf |
Fall time, SCL and SDA |
|
300 |
ns |
|
tsu1 |
Setup time, SDA to SCL |
|
100 |
|
ns |
th1 |
Hold time, SCL to SDA |
|
0 |
|
ns |
t(buf) |
Bus free time between stop and start conditions |
|
1.3 |
|
μs |
tsu2 |
Setup time, SCL to start condition |
|
0.6 |
|
μs |
th2 |
Hold time, start condition to SCL |
|
0.6 |
|
μs |
tsu3 |
Setup time, SCL to stop condition |
|
0.6 |
|
μs |
CL |
Load capacitance for each bus line |
|
400 |
pF |
TW(H) |
|
|
|
TW(L) |
|
TR |
|
|
|
||||
|
|
|
SCL
TSU1 |
|
|
|
|
|
|
|
TH1 |
|
|
|
|
SDA
Figure 3. SCL and SDA Timing
SCL
|
|
|
|
|
th2 |
|
tsu3 |
|
|
|
|
|
t(buf) |
|
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||||
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tsu2 |
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||||||
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|
|
SDA
Start |
Stop |
Condition |
Condition |
Figure 4. Start and Stop Conditions Timing
TF
T0027-01
T0028-01
12 |
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Copyright © 2009, Texas Instruments Incorporated |
Product Folder Link(s): TAS5713
TAS5713
www.ti.com |
SLOS637 –DECEMBER 2009 |
Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended Use Model section on usage of all terminals.
|
|
|
PARAMETER |
MIN |
TYP MAX |
UNIT |
|
|
|
|
|
|
|
tw(RESET) |
Pulse duration, |
|
active |
100 |
|
μs |
RESET |
|
|||||
td(I2C_ready) |
Time to enable I2C |
|
12.0 |
ms |
RESET
tw(RESET)
I2C Active |
|
I2C Active |
|
td(I2C_ready)
System Initialization.
Enable via I2C.
T0421-01
NOTES: On power up, it is recommended that the TAS5713 RESET be held LOW for at least 100 μs after DVDD has reached 3 V.
If RESET is asserted LOW while PDN is LOW, then RESET must continue to be held LOW for at least 100 μs after PDN is deasserted (HIGH).
Figure 5. Reset Timing
Copyright © 2009, Texas Instruments Incorporated |
Submit Documentation Feedback |
13 |
Product Folder Link(s): TAS5713
TAS5713
SLOS637 –DECEMBER 2009 |
www.ti.com |
THD+N (%)
TOTAL HARMONIC DISTORTION + NOISE |
TOTAL HARMONIC DISTORTION + NOISE |
|
|
VS |
|
|
|
|
|
VS |
|
|
|
|
FREQUENCY |
|
|
|
|
|
FREQUENCY |
|
|
10 |
|
|
|
|
|
10 |
|
|
|
|
PVDD = 8V |
|
|
|
|
|
PVDD = 12V |
|
|
|
|
RL = 8Ω |
|
|
|
|
|
RL = 8Ω |
|
|
|
|
TA = 25°C |
|
|
|
|
|
TA = 25°C |
|
|
|
|
1 |
|
|
|
|
|
1 |
|
PO = 5W |
|
|
|
|
|
|
|
|
|
|
|
||
|
PO = 2.5W |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PO = 2.5W |
|
|
|
|
|
|
(%) |
|
|
|
|
|
0.1 |
|
|
|
|
THD+N |
0.1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
PO |
= 0.5W |
PO = 1W |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PO = 1W |
|
|
0.01 |
|
|
|
|
|
0.01 |
|
|
|
|
0.001 |
|
|
|
|
|
0.001 |
|
|
|
|
20 |
100 |
1k |
10k |
20k |
|
20 |
100 |
1k |
10k |
20k |
|
|
Frequency (Hz) |
|
G001 |
|
|
|
Frequency (Hz) |
|
G002 |
|
|
|
|
|
|
|
|
|
Figure 6. |
Figure 7. |
TOTAL HARMONIC DISTORTION + NOISE |
TOTAL HARMONIC DISTORTION + NOISE |
|
|
|
VS |
|
|
|
|
|
VS |
|
|
|
|
|
FREQUENCY |
|
|
|
|
|
FREQUENCY |
|
|
|
10 |
|
|
|
|
|
10 |
|
|
|
|
|
|
PVDD = 18V |
|
|
|
|
|
PVDD = 24V |
|
|
|
|
|
RL = 8Ω |
|
|
|
|
|
RL = 8Ω |
|
|
|
|
|
TA = 25°C |
|
|
|
|
|
TA = 25°C |
|
|
|
|
1 |
|
|
|
|
|
1 |
|
|
|
|
|
|
PO = 5W |
|
|
|
|
|
|
PO = 5W |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(%) |
|
|
|
|
|
(%) |
|
|
|
PO = 1W |
|
|
|
|
|
|
|
|
|
|
|
||
THD+N |
0.1 |
|
|
|
|
THD+N |
0.1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
PO = 1W |
PO = 2.5W |
|
|
|
|
|
PO = 2.5W |
|
|
|
0.01 |
|
|
|
|
|
0.01 |
|
|
|
|
|
0.001 |
|
|
|
|
|
0.001 |
|
|
|
|
|
20 |
100 |
1k |
10k |
20k |
|
20 |
100 |
1k |
10k |
20k |
|
|
|
Frequency (Hz) |
|
G003 |
|
|
|
Frequency (Hz) |
|
G004 |
|
|
|
|
|
|
|
|
|
|
||
|
|
|
Figure 8. |
|
|
|
|
|
Figure 9. |
|
|
14 |
Submit Documentation Feedback |
Copyright © 2009, Texas Instruments Incorporated |
Product Folder Link(s): TAS5713
TAS5713
www.ti.com |
SLOS637 –DECEMBER 2009 |
TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω (continued)
THD+N (%)
TOTAL HARMONIC DISTORTION + NOISE |
TOTAL HARMONIC DISTORTION + NOISE |
VS |
VS |
OUTPUT POWER |
OUTPUT POWER |
10 |
|
|
|
|
|
10 |
|
|
|
|
|
PVDD = 8V |
|
|
|
|
|
PVDD = 12V |
|
|
|
|
RL = 8Ω |
|
|
|
|
|
RL = 8Ω |
|
|
|
|
TA = 25°C |
|
|
|
|
|
TA = 25°C |
|
|
|
1 |
|
|
|
|
|
1 |
|
|
|
|
|
f = 20Hz |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(%) |
|
|
f = 1kHz |
|
|
|
|
|
|
|
|
|
|
|
|
|
0.1 |
|
|
|
|
THD+N |
0.1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
f = 1kHz |
|
|
|
|
|
f = 20Hz |
|
0.01 |
|
|
|
|
|
0.01 |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
f = 10kHz |
|
|
|
|
|
f = 10kHz |
|
|
|
|
|
|
|
|
|
|
|
|
|
0.001 |
|
|
|
|
|
0.001 |
|
|
|
|
0.01 |
0.1 |
1 |
10 |
40 |
|
0.01 |
0.1 |
1 |
10 |
40 |
|
|
Output Power (W) |
|
G005 |
|
|
|
Output Power (W) |
|
G006 |
|
|
|
|
|
|
|
|
|
Figure 10. |
Figure 11. |
THD+N (%)
TOTAL HARMONIC DISTORTION + NOISE |
TOTAL HARMONIC DISTORTION + NOISE |
|
|
VS |
|
|
|
|
|
VS |
|
|
|
|
OUTPUT POWER |
|
|
|
|
OUTPUT POWER |
|
|
|
10 |
|
|
|
|
|
10 |
|
|
|
|
|
PVDD = 18V |
|
|
|
|
|
PVDD = 24V |
|
|
|
|
RL = 8Ω |
|
|
|
|
|
RL = 8Ω |
|
|
|
|
TA = 25°C |
|
|
|
|
|
TA = 25°C |
|
|
|
1 |
|
|
|
|
|
1 |
|
|
|
|
|
|
f = 20Hz |
|
|
|
|
|
f = 1kHz |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
f = 1kHz |
|
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(%) |
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f = 20Hz |
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THD+N |
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0.1 |
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0.1 |
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0.01 |
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0.01 |
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f = 10kHz |
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f = 10kHz |
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0.001 |
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0.001 |
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0.01 |
0.1 |
1 |
10 |
40 |
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0.01 |
0.1 |
1 |
10 |
40 |
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Output Power (W) |
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G007 |
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Output Power (W) |
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G008 |
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Figure 12. |
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Figure 13. |
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Copyright © 2009, Texas Instruments Incorporated |
Submit Documentation Feedback |
15 |
Product Folder Link(s): TAS5713
TAS5713
SLOS637 –DECEMBER 2009 |
www.ti.com |
TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω (continued)
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OUTPUT POWER |
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EFFICIENCY |
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VS |
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VS |
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SUPPLY VOLTAGE |
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TOTAL OUTPUT POWER |
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40 |
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100 |
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RL = 8Ω |
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90 |
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35 |
° |
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TA = 25 C |
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80 |
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30 |
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PVDD = 24V |
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70 |
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Output Power (W) |
25 |
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PVDD = 18V |
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THD+N = 10% |
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Efficiency (%) |
60 |
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PVDD = 12V |
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20 |
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50 |
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PVDD = 8V |
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15 |
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40 |
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THD+N = 1% |
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30 |
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10 |
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20 |
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5 |
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10 |
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RL = 8Ω |
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TA = 25°C |
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0 |
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0 |
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8 |
10 |
12 |
14 |
16 |
18 |
20 |
22 |
24 |
26 |
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0 |
5 |
10 |
15 |
20 |
25 |
30 |
35 |
40 |
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Supply Voltage (V) |
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G009 |
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Total Output Power (W) |
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G010 |
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NOTE: Dashed lines represent thermally limited regions.
Figure 14.
NOTE: Dashed lines represent thermally limited regions.
Figure 15.
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CROSSTALK |
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CROSSTALK |
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VS |
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VS |
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FREQUENCY |
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FREQUENCY |
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0 |
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0 |
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-10 |
PO = 1W |
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-10 |
PO = 1W |
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PVDD = 8V |
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PVDD = 12V |
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||
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RL = 8Ω |
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RL = 8Ω |
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-20 |
TA = 25°C |
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-20 |
TA = 25°C |
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-30 |
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-30 |
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(dB) |
-40 |
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(dB) |
-40 |
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Crosstalk |
-60 |
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Crosstalk |
-60 |
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-50 |
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-50 |
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-70 |
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Right to Left |
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-70 |
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Left to Right |
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-80 |
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-80 |
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Left to Right |
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-90 |
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-90 |
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Right to Left |
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-100 |
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-100 |
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20 |
100 |
1k |
10k |
20k |
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20 |
100 |
1k |
10k |
20k |
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Frequency (Hz) |
|
G011 |
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Frequency (Hz) |
|
G012 |
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||
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Figure 16. |
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Figure 17. |
|
|
16 |
Submit Documentation Feedback |
Copyright © 2009, Texas Instruments Incorporated |
Product Folder Link(s): TAS5713
TAS5713
www.ti.com |
SLOS637 –DECEMBER 2009 |
TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω (continued)
Crosstalk (dB)
CROSSTALK
VS
FREQUENCY
0 |
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-10 |
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PO = 1W |
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PVDD = 18V |
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|||||||||||
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RL = 8Ω |
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||||||||
-20 |
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TA = 25°C |
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-30
-40
-50
-60
-70 |
Right to Left |
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-80 |
-90 |
Left to Right
-100 |
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20 |
100 |
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1k |
10k |
20k |
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Frequency (Hz) |
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G013 |
|||||
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Figure 18.
Crosstalk (dB)
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CROSSTALK |
|||||||||||||
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VS |
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FREQUENCY |
|||||||||||||
0 |
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-10 |
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PO = 1W |
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||||||||||||
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PVDD = 24V |
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RL = 8Ω |
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||||||||||||
-20 |
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TA = 25°C |
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-30 |
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-40 |
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-50 |
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-60 |
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Right to Left |
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-70 |
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-80 |
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-90 |
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Left to Right |
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||||||||
-100 |
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20 |
100 |
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1k |
10k |
20k |
||||||
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Frequency (Hz) |
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G014 |
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Figure 19.
Copyright © 2009, Texas Instruments Incorporated |
Submit Documentation Feedback |
17 |
Product Folder Link(s): TAS5713
TAS5713
SLOS637 –DECEMBER 2009 www.ti.com
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
|
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|
VS |
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VS |
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|
FREQUENCY |
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FREQUENCY |
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10 |
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10 |
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PVDD = 12V |
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PVDD = 18V |
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RL = 4Ω |
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RL = 4Ω |
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TA = 25°C |
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TA = 25°C |
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PO = 5W |
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1 |
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1 |
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PO = 2.5W |
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PO = 5W |
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(%) |
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(%) |
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THD+N |
0.1 |
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THD+N |
0.1 |
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||
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PO = 1W |
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PO = 1W |
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0.01 |
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0.01 |
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PO = 2.5W |
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||
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0.001 |
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0.001 |
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20 |
100 |
1k |
10k |
20k |
|
20 |
100 |
1k |
10k |
20k |
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Frequency (Hz) |
|
G021 |
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Frequency (Hz) |
|
G022 |
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||
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Figure 20. |
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|
Figure 21. |
|
|
TOTAL HARMONIC DISTORTION + NOISE |
TOTAL HARMONIC DISTORTION + NOISE |
|
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|
VS |
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VS |
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OUTPUT POWER |
|
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|
OUTPUT POWER |
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10 |
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10 |
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PVDD = 12V |
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PVDD = 18V |
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RL = 4Ω |
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RL = 4Ω |
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TA = 25°C |
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TA = 25°C |
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1 |
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1 |
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f = 1kHz |
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f = 1kHz |
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(%) |
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(%) |
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THD+N |
0.1 |
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THD+N |
0.1 |
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f = 20Hz |
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0.01 |
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0.01 |
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f = 10kHz |
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f = 10kHz |
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f = 20Hz |
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0.001 |
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0.001 |
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0.01 |
0.1 |
1 |
10 |
40 |
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0.01 |
0.1 |
1 |
10 |
50 |
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Output Power (W) |
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G026 |
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Output Power (W) |
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G027 |
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Figure 22. |
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Figure 23. |
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18 |
Submit Documentation Feedback |
Copyright © 2009, Texas Instruments Incorporated |
Product Folder Link(s): TAS5713
TAS5713
www.ti.com |
SLOS637 –DECEMBER 2009 |
TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 4 Ω (continued)
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CROSSTALK |
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CROSSTALK |
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VS |
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VS |
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FREQUENCY |
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FREQUENCY |
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0 |
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0 |
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-10 |
PO = 1W |
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-10 |
PO = 1W |
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PVDD = 12V |
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PVDD = 18V |
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-20 |
RL = 4Ω |
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-20 |
RL = 4Ω |
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TA = 25°C |
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TA = 25°C |
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-30 |
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-30 |
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(dB) |
-40 |
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(dB) |
-40 |
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-50 |
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-50 |
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Crosstalk |
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Crosstalk |
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-60 |
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Right to Left |
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-60 |
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Right to Left |
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-70 |
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-70 |
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-80 |
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-80 |
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Left to Right |
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Left to Right |
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-90 |
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-90 |
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-100 |
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-100 |
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-110 |
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-110 |
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20 |
100 |
1k |
10k |
20k |
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20 |
100 |
1k |
10k |
20k |
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Frequency (Hz) |
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G023 |
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Frequency (Hz) |
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G024 |
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Figure 24. |
Figure 25. |
Copyright © 2009, Texas Instruments Incorporated |
Submit Documentation Feedback |
19 |
Product Folder Link(s): TAS5713
TAS5713
SLOS637 –DECEMBER 2009 |
www.ti.com |
THD+N (%)
TOTAL HARMONIC DISTORTION + NOISE |
TOTAL HARMONIC DISTORTION + NOISE |
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VS |
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VS |
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FREQUENCY |
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FREQUENCY |
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10 |
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10 |
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PVDD = 12V |
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PVDD = 24V |
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RL = 4Ω |
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RL = 4Ω |
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TA = 25°C |
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TA = 25°C |
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1 |
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1 |
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PO = 2.5W |
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PO = 5W |
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PO = 5W |
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PO = 2.5W |
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(%) |
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0.1 |
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THD+N |
0.1 |
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0.01 |
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PO = 1W |
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0.01 |
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PO |
= 1W |
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0.001 |
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0.001 |
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20 |
100 |
1k |
10k |
20k |
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20 |
100 |
1k |
10k |
20k |
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Frequency (Hz) |
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G015 |
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Frequency (Hz) |
G016 |
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Figure 26. |
Figure 27. |
THD+N (%)
TOTAL HARMONIC DISTORTION + NOISE |
TOTAL HARMONIC DISTORTION + NOISE |
VS |
VS |
OUTPUT POWER |
OUTPUT POWER |
10 |
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10 |
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PVDD = 12V |
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PVDD = 24V |
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RL = 4Ω |
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RL = 4Ω |
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TA = 25°C |
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TA = 25°C |
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1 |
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1 |
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f = 1kHz |
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f = 20Hz |
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f = 20Hz |
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(%) |
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0.1 |
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THD+N |
0.1 |
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f = 1kHz |
|
0.01 |
|
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0.01 |
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f = 10kHz |
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f = 10kHz |
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0.001 |
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0.001 |
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0.01 |
0.1 |
1 |
10 |
50 |
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0.01 |
0.1 |
1 |
10 |
40 |
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Output Power (W) |
|
G017 |
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Output Power (W) |
|
G018 |
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|
Figure 28. |
Figure 29. |
20 |
Submit Documentation Feedback |
Copyright © 2009, Texas Instruments Incorporated |
Product Folder Link(s): TAS5713