TEXAS INSTRUMENTS TAS5711 Technical data

TAS5711

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SLOS600 –DECEMBER 2009

20-W DIGITAL AUDIO-POWER AMPLIFIER WITH EQ, DRC, AND 2.1 MODE

Check for Samples: TAS5711

1

FEATURES

2

• Audio Input/Output
– 20-W Into an 8-Ω Load From an 18-V Supply – Up to 90% Efficient
– Wide PVDD Range, From 8 V to 26 V – AD and BD Filter Mode Support
– Efficient Class-D Operation Eliminates – SNR: 106 dB, A-Weighted

Need for Heatsinks

– One Serial Audio Input (Two Audio Performance

Channels)
– 2.1 Mode (2 SE + 1 BTL) Be Used As Power Limiter. Enables
– 2.0 Mode (2 BTL)
– Single-Filter PBTL Mode Support
– I2C Address Selection Pin (Chip Select)
– Supports 8-kHz to 48-kHz Sample Rate

(LJ/RJ/I2S)

• Audio/PWM Processing
– Independent Channel Volume Controls With

24-dB to Mute

– Separate Dynamic Range Control for

Satellite and Subchannels

– 21 Programmable Biquads for Speaker EQ

and Other Audio Processing Features

– Programmable Coefficients for DRC Filters APPLICATIONS – DC Blocking Filters – Support for 3D Effects

• General Features
– Serial Control Interface Operational Without

MCLK

– Factory-Trimmed Internal Oscillator for

Automatic Rate Detection

– Surface Mount, 48-Pin, 7-mm × 7-mm

HTQFP Package
– Thermal and Short-Circuit Protection
– Support for AD or BD Mode

• Benefits

– EQ: Speaker Equalization Improves Audio

– DRC: Dynamic Range Compression. Can

Speaker Protection, Easy Listening,
Night-Mode Listening.

– Separate DRC for Satellite and

Subchannels

– Autobank Switching: Preload Coefficients

for Different Sample Rates. No Need to
Write new Coefficients to the Part When
Sample Rate Changes.

– Autodetect: Automatically Detects

Sample-Rate Changes. No Need for
External Microprocessor Intervention

• Requires Only 3.3 V and PVDD

• Television

• iPod™ Dock

• Sound Bar

DESCRIPTION

The TAS5711 is a 20-W, efficient, digital audio power
amplifier for driving stereo bridge-tied speakers. One
serial data input allows processing of up to two
discrete audio channels and seamless integration to
most digital audio processors and MPEG decoders.
The device accepts a wide range of input data and
data rates. A fully programmable data path routes
these channels to the internal speaker drivers.

The TAS5711 is an I2S slave-only device receiving all
clocks from external sources. The TAS5711 operates
with a PWM carrier between 384-kHz switching rate
and 352-KHz switching rate depending on the input
sample rate. Oversampling combined with a
fourth-order noise shaper provides a flat noise floor
and excellent dynamic range from 20 Hz to 20 kHz.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2iPod is a trademark of Apple Inc.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2009, Texas Instruments Incorporated

SDIN

LRCLK

SCLK

MCLK

RESET

PDN

SDA

PLL_FLTM

PLL_FLTP

AVDD/DVDD

PVDD

OUT_A

OUT_C

OUT_B

OUT_D

BST_A

BST_C

BST_B

BST_D

3.3 V 8 V–26 V

SCL

Digital

Audio

Source

I C

Control

2

Control

Inputs

LC

SE

LC

BTL

B0264-09

Loop

Filter

(1)

LC

SE

PVDD

PVDD

A_SEL( )FAULT

TAS5711

SLOS600 –DECEMBER 2009

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

SIMPLIFIED APPLICATION DIAGRAM

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(1) See TAS5711 EVM User's Guide (SLOU280) for loop filter values.

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SDIN

MCLK

SCLK

LRCLK

Serial
Audio

Port

Protection

Logic

ClickandPop

Control

Digital AudioProcessor

(DAP)

SDA

SCL

4

Order

th

Noise

Shaper

and

PWM

S
R
C

SampleRate

Autodetect

andPLL

Serial

Control

Microcontroller

Based
System
Control

TerminalControl

OUT_A

OUT_B

2 HB´

FET Out

OUT_C

OUT_D

2 HB´

FET Out

B0262-06

TAS5711

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FUNCTIONAL VIEW

SLOS600 –DECEMBER 2009

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Temp.
Sense

VALID

FAULT

AGND

OC_ADJ

Power

On

Reset

Under-

voltage

Protection

GND

PWM_D

OUT_D

PGND_CD

PVDD_D

BST_D

Gate
Drive

PWM

Rcv

Overcurrent

Protection

4

Protection

and

I/OLogic

PWM_C

OUT_C

PGND_CD

PVDD_C

BST_C

Timing

Gate
Drive

Ctrl

PWM

Rcv

GVDD_CD

PWM_B

OUT_B

PGND_AB

PVDD_B

BST_B

Timing

Gate
Drive

Ctrl

PWM

Rcv

PWM_A

OUT_A

PGND_AB

PVDD_A

BST_A

Timing

Gate
Drive

Ctrl

PWM

Rcv

GVDD_AB

Ctrl

PulldownResistor

PulldownResistor

PulldownResistor

PulldownResistor

4

GVDD_CD

Regulator

GVDD_AB

Regulator

Timing

I

sense

B0034-05

PWMController

FAULT

TAS5711

SLOS600 –DECEMBER 2009

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Figure 1. Power Stage Functional Block Diagram

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+

L

R

+

+

+

+

+

Vol1

Vol2

ealpha

1BQ

1BQ

1BQ

1BQ

6BQ

6BQ

1BQ

1BQ

1BQ

Input Muxing

Log

Math

Attack

Decay

1

Master ON/OFF

(0x46[0])

Energy

MAXMUX

ealpha

B0321-08

1

1

1

1

1

1

51 V1OM

52 V2OM

I2C:57
VDISTB

I2C:56
VDISTA

60 V6OM

55

2A

I2C:53 – V1IM

31

2B–2F, 58

32–36, 5C

59

I C Subaddress in Red

2

5D

5E

29

30

I2C:54 – V2IM

L

R

1BQ

1BQ

Vol1

5A

5B

21 (D8, D9)

½

½

61

+

+

+

–1

0

Auto-lp

(0x46 Bit 5)

Log

Math

Attack

Decay

1

Master ON/OFF

(0x46[1])

Energy

MAXMUX

ealpha

ealpha

ealpha

Vol2

+

+

3D

3D

3A

3A

TAS5711

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DAP Process Structure

SLOS600 –DECEMBER 2009

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SSTIMER

OC_ADJ

PLL_FLTP

VR_ANA

PBTL

AVSS

PLL_FLTM

BST_A

GVDD_OUT

PVDD_A

OUT_A

RESET

PVDD_A

STEST

PDN

VR_DIG

OSC_RES

DVSSO

DVDD

MCLK

A_SEL

SCLK

SDIN

LRCLK

AVDD

SDA

SCL

DVSS

GND

VREG

BST_B

PVDD_B

PVDD_C

OUT_C

PVDD_D

BST_D

PGND_AB

OUT_B

PGND_CD

OUT_D

AGND

PGND_AB

PVDD_B

PGND_CD

PVDD_D

BST_C

PVDD_C

GVDD_OUT

P0075-08

PHP Package

(TopView)

TAS5711

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15 161718 19 20

21 222324

25

26

27

28

29

30

31

32

484746

45 44

43 42 41 40 39 38 37

36

35

34

33

TAS5711

SLOS600 –DECEMBER 2009

PIN ASSIGNMENT

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DEVICE INFORMATION

PIN

NAME NO.

AGND 30 P Analog ground for power stage
A_SEL 14 DIO A value of 0 (15-kΩ pulldown) makes the I2C device address 0x34,

AVDD 13 P 3.3-V analog power supply
AVSS 9 P Analog 3.3-V supply ground
BST_A 4 P High-side bootstrap supply for half-bridge A
BST_B 43 P High-side bootstrap supply for half-bridge B
BST_C 42 P High-side bootstrap supply for half-bridge C
BST_D 33 P High-side bootstrap supply for half-bridge D
DVDD 27 P 3.3-V digital power supply
DVSSO 17 P Oscillator ground

(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic

levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input).

(1)

TYPE

5-V

TOLERANT

TERMINATION

PIN FUNCTIONS

(2)

and a value of 1 (15-kΩ pullup) makes it 0x36. This pin can be
programmed after RESET to be an output by writing 1 to bit 0 of I2C
register 0x05. In that mode, the A_SEL pin is redefined as FAULT
(see ERROR REPORTING for details).

DESCRIPTION

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TAS5711

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SLOS600 –DECEMBER 2009

PIN FUNCTIONS (continued)

PIN

NAME NO.

DVSS 28 P Digital ground
GND 29 P Analog ground for power stage
GVDD_OUT 5, 32 P Gate drive internal regulator output. This pin must not be used to

LRCLK 20 DI 5-V Pulldown Input serial audio data left/right clock (sample rate clock)
MCLK 15 DI 5-V Pulldown Master clock input
OC_ADJ 7 AO Analog overcurrent programming. Requires resistor to ground.
OSC_RES 16 AO Oscillator trim resistor. Connect an 18.2-kΩ 1% resistor to DVSSO.
OUT_A 1 O Output, half-bridge A
OUT_B 46 O Output, half-bridge B
OUT_C 39 O Output, half-bridge C
OUT_D 36 O Output, half-bridge D
PBTL 8 DI Low means BTL or SE mode; high means PBTL mode. Information

PDN 19 DI 5-V Pullup Power down, active-low. PDN prepares the device for loss of power

PGND_AB 47, 48 P Power ground for half-bridges A and B
PGND_CD 37, 38 P Power ground for half-bridges C and D
PLL_FLTM 10 AO PLL negative loop filter terminal
PLL_FLTP 11 AO PLL positive loop filter terminal
PVDD_A 2, 3 P Power supply input for half-bridge output A
PVDD_B 44, 45 P Power supply input for half-bridge output B
PVDD_C 40, 41 P Power supply input for half-bridge output C
PVDD_D 34, 35 P Power supply input for half-bridge output D
RESET 25 DI 5-V Pullup Reset, active-low. A system reset is generated by applying a logic

SCL 24 DI 5-V I2C serial control clock input
SCLK 21 DI 5-V Pulldown Serial audio data clock (shift clock). SCLK is the serial audio port

SDA 23 DIO 5-V I2C serial control data interface input/output
SDIN 22 DI 5-V Pulldown Serial audio data input. SDIN supports three discrete (stereo) data

SSTIMER 6 AI Controls ramp time of OUT_x to minimize pop. Leave this pin

STEST 26 DI Factory test pin. Connect directly to DVSS.
VR_ANA 12 P Internally regulated 1.8-V analog supply voltage. This pin must not

VR_DIG 18 P Internally regulated 1.8-V digital supply voltage. This pin must not be

VREG 31 P Digital regulator output. Not to be used for powering external

TYPE

(1)

5-V

TOLERANT

TERMINATION

(2)

drive external devices.

goes directly to power stage.

supplies by shutting down the Noise Shaper and initiating PWM stop
sequence.

low to this pin. RESET is an asynchronous control signal that
restores the DAP to its default conditions, and places the PWM in
the hard mute state (tristated).

input data bit clock.

formats.

floating for BD mode. Requires capacitor of 2.2 nF to GND in AD
mode. The capacitor determines the ramp time.

be used to power external devices.

used to power external devices.

circuitry.

DESCRIPTION

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TAS5711

SLOS600 –DECEMBER 2009

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage

Input voltage

OUT_x to PGND_x 32
BST_x to PGND_x 43
Input clamp current, I
Output clamp current, I
Operating free-air temperature 0 to 85 °C
Operating junction temperature range 0 to 150 °C
Storage temperature range, T

(1) Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are

not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2) 5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.
(3) Maximum pin voltage should not exceed 6.0V
(4) DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.

DVDD, AVDD –0.3 to 3.6 V
PVDD_x –0.3 to 30 V
OC_ADJ –0.3 to 4.2 V

3.3-V digital input –0.5 to DVDD + 0.5 V
5-V tolerant

(2)

digital input (except MCLK) –0.5 to DVDD + 2.5

5-V tolerant MCLK input –0.5 to AVDD + 2.5

IK

OK

stg

(1)

VALUE UNIT

(3)

(3)
(4)
(4)

V
V
V

V
±20 mA
±20 mA

–40 to 125 °C

DISSIPATION RATINGS

PACKAGE

(1)

DERATING FACTOR TA≤ 25°C TA= 45°C TA= 70°C

ABOVE TA= 25°C POWER RATING POWER RATING POWER RATING

7-mm × 7-mm HTQFP 40 mW/°C 5 W 4.2 W 3.2 W

(1) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must

be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the
HTQFP thermal pad

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

Digital/analog supply voltage DVDD, AVDD 3 3.3 3.6 V
Half-bridge supply voltage PVDD_x 8 26 V

V

IH

V

IL

T

A

(1)

T

J

High-level input voltage 5-V tolerant 2 V
Low-level input voltage 5-V tolerant 0.8 V
Operating ambient temperature range 0 85 °C
Operating junction temperature range 0 125 °C

RL(BTL) Load impedance Output filter: L = 15 μH, C = 680 nF. 6 8 Ω
LO(BTL) Output-filter inductance μH

Minimum output inductance under 10
short-circuit condition

(1) Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.

PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS

PARAMETER TEST CONDITIONS VALUE UNIT

Output sample rate

11.025/22.05/44.1-kHz data rate ±2% 352.8 kHz
48/24/12/8/16/32-kHz data rate ±2% 384

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SLOS600 –DECEMBER 2009

PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

MCLKI

MCLK Frequency 2.8224 24.576 MHz
MCLK duty cycle 40% 50% 60%

tr /
tf

(MCLK)

Rise/fall time for MCLK 5 ns
LRCLK allowable drift before LRCLK reset 4 MCLKs

External PLL filter capacitor C1 SMD 0603 X7R 47 nF
External PLL filter capacitor C2 SMD 0603 X7R 4.7 nF
External PLL filter resistor R SMD 0603, metal film 470 Ω

ELECTRICAL CHARACTERISTICS
DC Characteristics

TA = 25°, PVCC_x = 18V, DVDD = AVDD = 3.3V, RL= 8Ω, BTL AD Mode, FS = 48KHz (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

V

OL

I

IL

I

IH

I

DD

I

PVDD

r

DS(on)

I/O Protection

V

uvp

V

uvp,hyst

(3)

OTE
OTE

HYST

OLPC Overload protection counter f
I

OC

I

OCT

R

OCP

R

PD

(1) IIHfor the PBTL pin has a maximum limit of 200 µA due to an intenal pulldown on the pin.
(2) This does not include bond-wire or pin resistance.
(3) Specified by design

High-level output voltage A_SEL and SDA IOH= –4 mA 2.4 V

DVDD = AVDD = 3 V

Low-level output voltage A_SEL and SDA IOL= 4 mA 0.5 V

DVDD = AVDD = 3 V

Low-level input current μA

High-level input current μA

3.3 V supply current mA

3.3 V supply voltage (DVDD,
AVDD)

VI< VIL; DVDD = AVDD 75
= 3.6V

VI> VIH; DVDD = 75
AVDD = 3.6V

Normal Mode 48 70
Reset (RESET = low, 24 32

PDN = high)
Normal Mode 30 55

Half-bridge supply current No load (PVDD_x) mA

Reset (RESET = low, 5 13
PDN = high)

Drain-to-source resistance, LS TJ= 25°C, includes metallization resistance 180

(2)

Drain-to-source resistance,
HS

TJ= 25°C, includes metallization resistance 180

Undervoltage protection limit PVDD falling 7.2 V
Undervoltage protection limit PVDD rising 7.6 V
Overtemperature error 150 °C
Extra temperature drop

(3)

required to recover from error

= 384 kHz 0.63 ms

PWM

Overcurrent limit protection Resistor—programmable, max. current, R

= 22 kΩ 4.5 A

OCP

30 °C

Overcurrent response time 150 ns
OC programming resistor Resistor tolerance = 5% for typical value; the minimum

range resistance should not be less than 20 kΩ.
Internal pulldown resistor at Connected when drivers are tristated to provide bootstrap

the output of each half-bridge capacitor charge.

20 22 kΩ

3 kΩ

(1)

mΩ

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TAS5711

SLOS600 –DECEMBER 2009

AC Characteristics (BTL)

PVDD_x = 18 V, BTL AD mode, FS = 48 KHz, RL= 8 Ω, R
f

= 384 kHz, TA= 25°C (unless otherwise specified). All performance is in accordance with recommended operating

PWM

conditions (unless otherwise specified).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PVDD = 18 V, 10% THD, 1-kHz input signal 21
PVDD = 18 V, 7% THD, 1-kHz input signal 20
PVDD = 12 V, 10% THD, 1-kHz input signal 9.5
PVDD = 12 V, 7% THD, 1-kHz input signal 9
PVDD = 8 V, 10% THD, 1-kHz input signal 4.1
PVDD = 8 V, 7% THD, 1-kHz input signal 3.9
PBTL mode, PVDD = 12 V, RL= 4 Ω,

10% THD, 1-kHz input signal
PBTL mode, PVDD = 12 V, RL= 4 Ω,

7% THD, 1-kHz input signal

P

O

THD+N Total harmonic distortion + noise PVDD = 12 V, PO= 1 W 0.08%

V

n

SNR Signal-to-noise ratio

(1) SNR is calculated relative to 0-dBFS input level.

Power output per channel W

Output integrated noise (rms) A-weighted 44 μV

Crosstalk

(1)

PBTL mode, PVDD = 18 V, RL= 4 Ω,
10% THD, 1-kHz input signal

PBTL mode, PVDD = 18 V, RL= 4 Ω,
7% THD, 1-kHz input signal

SE mode, PVDD = 12 V, RL= 4 Ω,
10% THD, 1-kHz input signal

SE mode, PVDD = 12 V, RL= 4 Ω,
7% THD, 1-kHz input signal

SE mode, PVDD = 24 V, RL= 4 Ω,
10% THD, 1-kHz input signal

SE mode, PVDD = 24 V, RL= 4 Ω,
7% THD, 1-kHz input signal

PVDD = 18 V, PO= 1 W 0.06%

PVDD = 8 V, PO= 1 W 0.2%

PO= 0.25 W, f = 1 kHz (BD Mode) –82 dB
PO= 0.25 W, f = 1 kHz (AD Mode) –69 dB
A-weighted, f = 1 kHz, maximum power at

THD < 1%

= 22 KΩ, C

OCP

= 33 nF, audio frequency = 1 kHz, AES17 filter,

BST

19.2

18

42.8

40

4.6

4.3

17.8

16

106 dB

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t

h1

t

su1

t

(edge)

t

su2

t

h2

SCLK

(Input)

LRCLK

(Input)

SDIN

T0026-04

t

r

t

f

TAS5711

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SERIAL AUDIO PORTS SLAVE MODE

over recommended operating conditions (unless otherwise noted)

PARAMETER MIN TYP MAX UNIT

f

SCLKIN

t

su1

t

h1

t

su2

t

h2

t

(edge)

tr/t

f

Frequency, SCLK 32 × fS, 48 × fS, 64 × f

S

Setup time, LRCLK to SCLK rising edge 10 ns
Hold time, LRCLK from SCLK rising edge 10 ns
Setup time, SDIN to SCLK rising edge 10 ns
Hold time, SDIN from SCLK rising edge 10 ns
LRCLK frequency 8 48 48 kHz
SCLK duty cycle 40% 50% 60%
LRCLK duty cycle 40% 50% 60%

SCLK rising edges between LRCLK rising edges 32 64

LRCLK clock edge with respect to the falling edge of SCLK –1/4 1/4
Rise/fall time for SCLK/LRCLK 8 ns

SLOS600 –DECEMBER 2009

TEST

CONDITIONS

CL= 30 pF 1.024 12.288 MHz

SCLK
edges

SCLK

period

Figure 2. Slave Mode Serial Data Interface Timing

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SCL

SDA

t

w(H)

t

w(L)

t

r

t

f

t

su1

t

h1

T0027-01

SCL

SDA

t

h2

t

(buf)

t

su2

t

su3

Start

Condition

Stop

Condition

T0028-01

TAS5711

SLOS600 –DECEMBER 2009

I2C SERIAL CONTROL PORT OPERATION

Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

f
t
t
t
t
t
t
t
t
t
t
C

SCL
w(H)
w(L)
r
f
su1
h1
(buf)
su2
h2
su3

Frequency, SCL No wait states 400 kHz
Pulse duration, SCL high 0.6 μs
Pulse duration, SCL low 1.3 μs
Rise time, SCL and SDA 300 ns
Fall time, SCL and SDA 300 ns
Setup time, SDA to SCL 100 ns
Hold time, SCL to SDA 0 ns
Bus free time between stop and start condition 1.3 μs
Setup time, SCL to start condition 0.6 μs
Hold time, start condition to SCL 0.6 μs
Setup time, SCL to stop condition 0.6 μs
Load capacitance for each bus line 400 pF

L

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Figure 3. SCL and SDA Timing

Figure 4. Start and Stop Conditions Timing

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t

w(RESET)

RESET

t

d(I2C_ready)

SystemInitialization.

EnableviaI C.

2

T0421-01

I C Active

2

I C Active

2

TAS5711

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SLOS600 –DECEMBER 2009

RESET TIMING (RESET)

Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended
Use Model section on usage of all terminals.

PARAMETER MIN TYP MAX UNIT

t

w(RESET)

t

d(I2C_ready)

NOTES: On power up, it is recommended that the TAS5711 RESET be held LOW for at least 100 μs after DVDD has

reached 3 V.
If the RESET is asserted LOW while PDN is LOW, then the RESET must continue to be held LOW for at least 100 μs

after PDN is deasserted (HIGH).

Pulse duration, RESET active 100 µs
Time to enable I2C 12.0 ms

Figure 5. Reset Timing

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Frequency (Hz)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

vs

FREQUENCY

0.001

0.01

0.1

1

10

20 100 1k 10k 20k

PO = 0.5W

PO = 1W

PO = 2.5W

G001

PVDD = 8V
RL = 8Ω
TA = 25°C

Frequency (Hz)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

vs

FREQUENCY

0.001

0.01

0.1

1

10

20 100 1k 10k 20k

PO = 1W

PO = 2.5W

PO = 5W

G002

PVDD = 12V
RL = 8Ω
TA = 25°C

Frequency (Hz)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

vs

FREQUENCY

0.001

0.01

0.1

1

10

20 100 1k 10k 20k

PO = 1W

PO = 2.5W

PO = 5W

G003

PVDD = 18V
RL = 8Ω
TA = 25°C

Frequency (Hz)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

vs

FREQUENCY

0.001

0.01

0.1

1

10

20 100 1k 10k 20k

PO = 1W

PO = 2.5W

PO = 5W

G004

PVDD = 24V
RL = 8Ω
TA = 25°C

TAS5711

SLOS600 –DECEMBER 2009

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION

Figure 6. Figure 7.

Figure 8. Figure 9.

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Output Power (W)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

vs

OUTPUT POWER

0.01 0.1 1 10 50

0.001

0.01

0.1

1

10

f = 20Hz

f = 1kHz

f = 10kHz

G005

PVDD = 8V
RL = 8Ω
TA = 25°C

Output Power (W)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

vs

OUTPUT POWER

0.01 0.1 1 10 50

0.001

0.01

0.1

1

10

f = 20Hz

f = 1kHz

f = 10kHz

G006

PVDD = 12V
RL = 8Ω
TA = 25°C

Output Power (W)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

vs

OUTPUT POWER

0.01 0.1 1 10 50

0.001

0.01

0.1

1

10

f = 20Hz

f = 1kHz

f = 10kHz

G007

PVDD = 18V
RL = 8Ω
TA = 25°C

Output Power (W)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

vs

OUTPUT POWER

0.01 0.1 1 10 50

0.001

0.01

0.1

1

10

f = 20Hz

f = 1kHz

f = 10kHz

G008

PVDD = 24V
RL = 8Ω
TA = 25°C

TAS5711

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SLOS600 –DECEMBER 2009

TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)

Figure 10. Figure 11.

Figure 12. Figure 13.

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Supply Voltage (V)

Output Power (W)

OUTPUT POWER

vs

SUPPLY VOLTAGE

8 10 12 14 16 18 20 22 24 26

0

5

10

15

20

25

30

35

40

THD+N = 1%

THD+N = 10%

G009

RL = 8Ω
TA = 25°C

Total Output Power (W)

Efficiency (%)

EFFICIENCY

vs

TOTAL OUTPUT POWER

0 5 10 15 20 25 30 35 40

0

10

20

30

40

50

60

70

80

90

100

PVDD = 8V

PVDD = 12V

PVDD = 18V

PVDD = 24V

G010

RL = 8Ω
TA = 25°C

Frequency (Hz)

Crosstalk (dB)

CROSSTALK

vs

FREQUENCY

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

20 100 1k 10k 20k

Left to Right

Right to Left

G011

PO = 1W
PVDD = 8V
RL = 8Ω
TA = 25°C

Frequency (Hz)

Crosstalk (dB)

CROSSTALK

vs

FREQUENCY

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

20 100 1k 10k 20k

Left to Right

Right to Left

G012

PO = 1W
PVDD = 12V
RL = 8Ω
TA = 25°C

TAS5711

SLOS600 –DECEMBER 2009

TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)

www.ti.com

Figure 14. Figure 15.

Figure 16. Figure 17.

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Frequency (Hz)

Crosstalk (dB)

CROSSTALK

vs

FREQUENCY

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

20 100 1k 10k 20k

Left to Right

Right to Left

G013

PO = 1W
PVDD = 18V
RL = 8Ω
TA = 25°C

Frequency (Hz)

Crosstalk (dB)

CROSSTALK

vs

FREQUENCY

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

20 100 1k 10k 20k

Left to Right

Right to Left

G014

PO = 1W
PVDD = 24V
RL = 8Ω
TA = 25°C

TAS5711

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SLOS600 –DECEMBER 2009

TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)

Figure 18. Figure 19.

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Frequency (Hz)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

vs

FREQUENCY

0.001

0.01

0.1

1

10

20 100 1k 10k 20k

PO = 0.5W

PO = 1W

PO = 2.5W

G015

PVDD = 12V
RL = 4Ω
TA = 25°C

Frequency (Hz)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

vs

FREQUENCY

0.001

0.01

0.1

1

10

20 100 1k 10k 20k

PO = 1W

PO = 2.5W

PO = 5W

G016

PVDD = 18V
RL = 4Ω
TA = 25°C

Frequency (Hz)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

vs

FREQUENCY

0.001

0.01

0.1

1

10

20 100 1k 10k 20k

PO = 1W

PO = 2.5W

PO = 5W

G017

PVDD = 24V
RL = 4Ω
TA = 25°C

Output Power (W)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

vs

OUTPUT POWER

0.01 0.1 1 10 50

0.001

0.01

0.1

1

10

PVDD = 12V

PVDD = 18V

PVDD = 24V

G018

f = 1kHz
RL = 4Ω
TA = 25°C

TAS5711

SLOS600 –DECEMBER 2009

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TYPICAL CHARACTERISTICS, SE CONFIGURATION

Figure 20. Figure 21.

Figure 22. Figure 23.

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Supply Voltage (V)

Output Power (W)

OUTPUT POWER

vs

SUPPLY VOLTAGE

8 10 12 14 16 18 20 22 24 26

0

2

4

6

8

10

12

14

16

18

20

22

THD+N = 1%

THD+N = 10%

G019

RL = 4Ω
TA = 25°C

Total Output Power (W)

Efficiency (%)

EFFICIENCY

vs

TOTAL OUTPUT POWER

0 3 6 9 12 15

0

10

20

30

40

50

60

70

80

90

100

PVDD = 12V

PVDD = 24V

G020

RL = 4Ω
TA = 25°C

TAS5711

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SLOS600 –DECEMBER 2009

TYPICAL CHARACTERISTICS, SE CONFIGURATION (continued)

Figure 24. Figure 25.

Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Link(s): TAS5711

Frequency (Hz)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

vs

FREQUENCY

0.001

0.01

0.1

1

10

20 100 1k 10k 20k

PO = 1W

PO = 2W

PO = 5W

G021

PVDD = 8V
RL = 4Ω
TA = 25°C

Frequency (Hz)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

vs

FREQUENCY

0.001

0.01

0.1

1

10

20 100 1k 10k 20k

PO = 1W

PO = 2W

PO = 5W

G022

PVDD = 12V
RL = 4Ω
TA = 25°C

Frequency (Hz)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

vs

FREQUENCY

0.001

0.01

0.1

1

10

20 100 1k 10k 20k

PO = 1W

PO = 2W

PO = 5W

G023

PVDD = 18V
RL = 4Ω
TA = 25°C

Frequency (Hz)

THD+N (%)

TOTAL HARMONIC DISTORTION + NOISE

vs

FREQUENCY

0.001

0.01

0.1

1

10

20 100 1k 10k 20k

PO = 1W

PO = 2W

PO = 5W

G024

PVDD = 24V
RL = 4Ω
TA = 25°C

TAS5711

SLOS600 –DECEMBER 2009

www.ti.com

TYPICAL CHARACTERISTICS, PBTL CONFIGURATION

Figure 26. Figure 27.

Figure 28. Figure 29.

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