Texas Instruments TAS5707, TAS5707A User Manual

TAS5707, TAS5707A

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SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC

Check for Samples: TAS5707 TAS5707A

FEATURES

• Audio Input/Output – 20-W Into an 8-Ω Load From an 18-V Supply – Autobank Switching: Preload Coefficients – Wide PVDD Range, From 8 V to 26 V – Efficient Class-D Operation Eliminates

Need for Heatsinks – Requires Only 3.3 V and PVDD – One Serial Audio Input (Two Audio

Channels) – Supports 8-kHz to 48-kHz Sample Rate

(LJ/RJ/I2S)

• Audio/PWM Processing – Independent Channel Volume Controls With

24 dB to Mute – Soft Mute (50% Duty Cycle) – Programmable Dynamic Range Control – 14 Programmable Biquads for Speaker EQ

and Other Audio Processing Features – Programmable Coefficients for DRC Filters – DC Blocking Filters

• General Features – Serial Control Interface Operational Without

MCLK The TAS5707 is a slave-only device receiving all

– Factory-Trimmed Internal Oscillator for

Automatic Rate Detection

– Surface Mount, 48-PIN, 7-mm × 7-mm

HTQFP Package

– Thermal and Short-Circuit Protection

• Benefits – EQ: Speaker Equalization Improves Audio

Performance

– DRC: Dynamic Range Compression. Can

Be Used As Power Limiter. Enables Speaker Protection, Easy Listening,

Night-Mode Listening

for Different Sample Rates. No Need to Write New Coefficients to the Part When Sample Rate Changes.

– Autodetect: Automatically Detects

Sample-Rate Changes. No Need for External Microprocessor Intervention

APPLICATIONS

• Television

• iPod™ Dock

• Sound Bar

DESCRIPTION

The TAS5707 is a 20-W, efficient, digital-audio power amplifier for driving stereo bridge-tied speakers. One serial data input allows processing of up to two discrete audio channels and seamless integration to most digital audio processors and MPEG decoders. The device accepts a wide range of input data and data rates. A fully programmable data path routes these channels to the internal speaker drivers.

clocks from external sources. The TAS5707 operates with a PWM carrier between a 384-kHz switching rate and 352-KHz switching rate, depending on the input sample rate. Oversampling combined with a fourth-order noise shaper provides a flat noise floor and excellent dynamic range from 20 Hz to 20 kHz..

The TAS5707A is identical in function to the HTQFP packaged TAS5707, but has a unique I2C device address. The address of the TAS5707 is 0x36. The address of the TAS5707A is 0x3A.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2iPod is a trademark of Apple Inc. 3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SDIN

LRCLK

SCLK

MCLK

RESET

PDN

SDA

PLL_FLTM

PLL_FLTP

AVDD/DVDD PVDD

OUT_A

OUT_C

OUT_B

OUT_D

BST_A

BST_C

BST_B

BST_D

3.3V 8V–26V

SCL

Digital

Audio

Source

I C

Control

Inputs

Left

Right

B0264-11

Loop

Filter

(1)

TAS5707, TAS5707A

SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

SIMPLIFIED APPLICATION DIAGRAM

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(1)See user's guide for loop-filter details.

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SDIN

MCLK

SCLK

LRCLK

Serial Audio

Port

7BQ

V O L U M E

DRC

Protection

Logic

ClickandPop

Control

7BQ

SDA

SCL

Order

Noise

Shaper

and

PWM

S R C

mDAP

SampleRate

Autodetect

andPLL

Serial

Control

Microcontroller

Based System Control

TerminalControl

OUT_A

OUT_B

2 HB´

FET Out

OUT_C

OUT_D

2 HB´

FET Out

B0262-02

TAS5707, TAS5707A

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FUNCTIONAL VIEW

SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

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Temp.

Sense

VALID

FAULT

AGND

OC_ADJ

Power

Reset

Under-

voltage

Protection

GND

PWM_D

OUT_D

PGND_CD

PVDD_D

BST_D

Gate Drive

PWM

Rcv

Overcurrent

Protection

and

I/OLogic

PWM_C

OUT_C

PGND_CD

PVDD_C

BST_C

Timing

Gate Drive

Ctrl

PWM

Rcv

GVDD_CD

PWM_B

OUT_B

PGND_AB

PVDD_B

BST_B

Timing

Gate Drive

Ctrl

PWM

Rcv

PWM_A

OUT_A

PGND_AB

PVDD_A

BST_A

Timing

Gate Drive

Ctrl

PWM

Rcv

GVDD_AB

Ctrl

PulldownResistor

GVDD_CD

Regulator

GVDD_AB

Regulator

Timing

sense

B0034-05

PWMController

FAULT

TAS5707, TAS5707A

SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

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Figure 1. Power Stage Functional Block Diagram

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Vol1

7 BQ EQ

ealpha

7 BQ EQ

Input Muxing

Vol2

B0341-01

Energy

MAXMUX

Attack Decay

DRC1

DRC

ON/OFF

50[D7]

30–36

29–2F

3B–3C

46[D0]

To PWM

Hex numbers refer to I2C subaddresses

[Di] = bit "i" of subaddress

SSTIMER

OC_ADJ

PLL_FLTP

VR_ANA

AVSS

PLL_FLTM

BST_A

GVDD_OUT

PVDD_A

OUT_A

RESET

PVDD_A

STEST

PDN

VR_DIG

OSC_RES

DVSSO

DVDD

MCLK

FAULT

SCLK

SDIN

LRCLK

AVDD

SDA

SCL

DVSS

GND

VREG

BST_B

PVDD_B

PVDD_C

OUT_C

PVDD_D

BST_D

PGND_AB

OUT_B

PGND_CD

OUT_D

AGND

PGND_AB

PVDD_B

PGND_CD

PVDD_D

BST_C

PVDD_C

GVDD_OUT

P0075-01

PHP Package

(TopView)

TAS5707

15 161718 19 20

21 222324

484746

45 44

43 42 41 40 39 38 37

TAS5707, TAS5707A

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DAP Process Structure

48-TERMINAL, HTQFP PACKAGE (TOP VIEW)

SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

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PIN FUNCTIONS

NAME NO.

AGND 30 P Analog ground for power stage AVDD 13 P 3.3-V analog power supply AVSS 9 P Analog 3.3-V supply ground BST_A 4 P High-side bootstrap supply for half-bridge A BST_B 43 P High-side bootstrap supply for half-bridge B BST_C 42 P High-side bootstrap supply for half-bridge C BST_D 33 P High-side bootstrap supply for half-bridge D DVDD 27 P 3.3-V digital power supply DVSSO 17 P Oscillator ground DVSS 28 P Digital ground FAULT 14 DO Backend error indicator. Asserted LOW for over temperature, over

GND 29 P Analog ground for power stage GVDD_OUT 5, 32 P Gate drive internal regulator output LRCLK 20 DI 5-V Pulldown Input serial audio data left/right clock (sample rate clock) MCLK 15 DI 5-V Pulldown Master clock input NC 8 – No connection OC_ADJ 7 AO Analog overcurrent programming. Requires resistor to ground. OSC_RES 16 AO Oscillator trim resistor. Connect an 18.2-kΩ 1% resistor to DVSSO. OUT_A 1 O Output, half-bridge A OUT_B 46 O Output, half-bridge B OUT_C 39 O Output, half-bridge C OUT_D 36 O Output, half-bridge D PDN 19 DI 5-V Pullup Power down, active-low. PDN prepares the device for loss of power

PGND_AB 47, 48 P Power ground for half-bridges A and B PGND_CD 37, 38 P Power ground for half-bridges C and D PLL_FLTM 10 AO PLL negative loop filter terminal PLL_FLTP 11 AO PLL positive loop filter terminal PVDD_A 2, 3 P Power supply input for half-bridge output A PVDD_B 44, 45 P Power supply input for half-bridge output B PVDD_C 40, 41 P Power supply input for half-bridge output C PVDD_D 34, 35 P Power supply input for half-bridge output D RESET 25 DI 5-V Pullup Reset, active-low. A system reset is generated by applying a logic low

SCL 24 DI 5-V I2C serial control clock input SCLK 21 DI 5-V Pulldown Serial audio data clock (shift clock). SCLK is the serial audio port input

SDA 23 DIO 5-V I2C serial control data interface input/output SDIN 22 DI 5-V Pulldown Serial audio data input. SDIN supports three discrete (stereo) data

TYPE 5-V TERMINATION

(1)

TOLERANT

(2)

DESCRIPTION

current, over voltage, and under voltage error conditions. De-asserted upon recovery from error condition.

supplies by shutting down the noise shaper and initiating PWM stop sequence.

to this pin. RESET is an asynchronous control signal that restores the DAP to its default conditions, and places the PWM in the hard mute state (tristated).

data bit clock.

formats.

(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output (2) All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic

levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input).

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SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

PIN FUNCTIONS (continued)

NAME NO.

SSTIMER 6 AI Controls ramp time of OUT_X to minimize pop. Leave this pin floating

STEST 26 DI Factory test pin. Connect directly to DVSS. VR_ANA 12 P Internally regulated 1.8-V analog supply voltage. This pin must not be

VR_DIG 18 P Internally regulated 1.8-V digital supply voltage. This pin must not be

VREG 31 P Digital regulator output. Not to be used for powering external circuitry.

TYPE 5-V TERMINATION

(1)

TOLERANT

(2)

DESCRIPTION

for BD mode. Requires capacitor of 2.2 nF to GND in AD mode. The capacitor determines the ramp time.

used to power external devices.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage

Input voltage

OUT_x to PGND_X 32 BST_x to PGND_X 43 Input clamp current, I Output clamp current, I Operating free-air temperature 0 to 85 °C Operating junction temperature range 0 to 150 °C Storage temperature range, T

(1) Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are

not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability. (2) 5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL. (3) Maximum pin voltage should not exceed 6.0Vele (4) DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.

DVDD, AVDD –0.3 to 3.6 V PVDD_X –0.3 to 30 V OC_ADJ –0.3 to 4.2 V

3.3-V digital input –0.5 to DVDD + 0.5 V 5-V tolerant

(2)

digital input (except MCLK) –0.5 to DVDD + 2.5

5-V tolerant MCLK input –0.5 to AVDD + 2.5

stg

(1)

VALUE UNIT

(3) (3)

(4)

V V V

V ±20 mA ±20 mA

–40 to 125 °C

DISSIPATION RATINGS

PACKAGE

(1)

DERATING FACTOR TA≤ 25°C TA= 45°C TA= 70°C

ABOVE TA= 25°C POWER RATING POWER RATING POWER RATING

7-mm × 7-mm HTQFP 40 mW/°C 5 W 4.2 W 3.2 W

(1) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must

be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the HTQFP thermal pad

RECOMMENDED OPERATING CONDITIONS

Digital/analog supply voltage DVDD, AVDD 3 3.3 3.6 V Half-bridge supply voltage PVDD_X 8 26 V

High-level input voltage 5-V tolerant 2 V Low-level input voltage 5-V tolerant 0.8 V Operating ambient temperature range 0 85 °C

MIN NOM MAX UNIT

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RECOMMENDED OPERATING CONDITIONS (continued)

MIN NOM MAX UNIT

(1)

RL(BTL) Load impedance Output filter: L = 15 μH, C = 680 nF. 6 8 Ω LO(BTL) Output-filter inductance μH

(1) Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.

Operating junction temperature range 0 125 °C

Minimum output inductance under 10 short-circuit condition

PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS

PARAMETER TEST CONDITIONS VALUE UNIT

Output sample rate

11.025/22.05/44.1-kHz data rate ±2% 352.8 kHz 48/24/12/8/16/32-kHz data rate ±2% 384

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SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

MCLKI

MCLK Frequency 2.8224 24.576 MHz MCLK duty cycle 40% 50% 60%

tr / tf

(MCLK)

Rise/fall time for MCLK 5 ns LRCLK allowable drift before LRCLK reset 4 MCLKs

External PLL filter capacitor C1 SMD 0603 Y5V 47 nF External PLL filter capacitor C2 SMD 0603 Y5V 4.7 nF External PLL filter resistor R SMD 0603, metal film 470 Ω

ELECTRICAL CHARACTERISTICS DC Characteristics

TA = 25°, PVCC_X = 18V, DVDD = AVDD = 3.3V, RL= 8Ω, BTL AD Mode, FS = 48KHz (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PVDD

DS(on)

I/O Protection

uvp

uvp,hyst

(2)

OTE OTE

HYST

OTW Overtemperature warning 125 °C OTW

HYST

OLPC Overload protection counter f I

OCT

OCP

(1) This does not include bond-wire or pin resistance. (2) Specified by design

High-level output voltage FAULTZ and SDA IOH= –4 mA 2.4 V

DVDD = AVDD = 3 V

Low-level output voltage FAULTZ and SDA IOL= 4 mA 0.5 V

DVDD = AVDD = 3 V

Low-level input current μA

High-level input current μA

3.3 V supply current mA

3.3 V supply voltage (DVDD, AVDD)

VI< VIL; DVDD = AVDD 75 = 3.6V

VI> VIH; DVDD = 75 AVDD = 3.6V

Normal Mode 48 83 Reset (RESET = low, 24 32

PDN = high) Normal Mode 30 55

Half-bridge supply current No load (PVDD_X) mA

Reset (RESET = low, 5 13 PDN = high)

Drain-to-source resistance, LS TJ= 25°C, includes metallization resistance 180

(1)

Drain-to-source resistance, HS

TJ= 25°C, includes metallization resistance 180

Undervoltage protection limit PVDD falling 7.2 V Undervoltage protection limit PVDD rising 7.6 V Overtemperature error 150 °C Extra temperature drop

(2)

required to recover from error

Temperature drop required to recover from warning

= 384 kHz 0.63 ms

PWM

Overcurrent limit protection Resistor—programmable, max. current, R

= 22 kΩ 4.5 A

OCP

30 °C

25 °C

Overcurrent response time 150 ns OC programming resistor Resistor tolerance = 5% for typical value; the minimum

range resistance should not be less than 20 kΩ. Internal pulldown resistor at Connected when drivers are tristated to provide bootstrap

the output of each half-bridge capacitor charge.

20 22 kΩ

3 kΩ

mΩ

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SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

AC Characteristics (BTL)

PVDD_X = 18 V, BTL AD mode, FS = 48 KHz, RL= 8 Ω, R f

= 384 kHz, TA= 25°C (unless otherwise noted). All performance is in accordance with recommended operating

PWM

conditions, unless otherwise specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PVDD = 18 V,10% THD, 1-kHz input signal 20.6 PVDD = 18 V, 7% THD, 1-kHz input signal 19.5 PVDD = 12 V, 10% THD, 1-kHz input

THD+N Total harmonic distortion + noise PVDD= 12 V; PO= 1 W 0.13%

SNR Signal-to-noise ratio

(1) SNR is calculated relative to 0-dBFS input level.

Power output per channel W

Output integrated noise (rms) A-weighted 56 μV

Crosstalk

(1)

signal PVDD = 12 V, 7% THD, 1-kHz input signal 8.9 PVDD = 8 V, 10% THD, 1-kHz input signal 4.1 PVDD = 8 V, 7% THD, 1-kHz input signal 3.8 PVDD= 18 V; PO= 1 W 0.06%

PVDD= 8 V; PO= 1 W 0.2%

PO= 0.25 W, f = 1kHz (BD Mode) –82 dB PO= 0.25 W, f = 1kHz (AD Mode) -69 dB A-weighted, f = 1 kHz, maximum power at

THD < 1%

= 22 KΩ, C

OCP

= 33 nF, audio frequency = 1 kHz, AES17 filter,

BST

106 dB

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9.4

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su1

(edge)

su2

SCLK

(Input)

LRCLK

(Input)

SDIN

T0026-04

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SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

SERIAL AUDIO PORTS SLAVE MODE

over recommended operating conditions (unless otherwise noted)

PARAMETER MIN TYP MAX UNIT

SCLKIN

su1

su2

Frequency, SCLK 32 × fS, 48 × fS, 64 × f

Setup time, LRCLK to SCLK rising edge 10 ns Hold time, LRCLK from SCLK rising edge 10 ns Setup time, SDIN to SCLK rising edge 10 ns Hold time, SDIN from SCLK rising edge 10 ns LRCLK frequency 8 48 48 kHz SCLK duty cycle 40% 50% 60% LRCLK duty cycle 40% 50% 60%

SCLK rising edges between LRCLK rising edges 32 64

(edge)

tr / ns tf

(SCLK/LRCLK)

LRCLK clock edge with respect to the falling edge of SCLK –1/4 1/4

Rise/fall time for SCLK/LRCLK 8

TEST

CONDITIONS

CL= 30 pF 1.024 12.288 MHz

SCLK edges

SCLK

period

Figure 2. Slave Mode Serial Data Interface Timing

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SCL

SDA

w(H)

w(L)

su1

T0027-01

SCL

SDA

(buf)

su2

su3

Start

Condition

Stop

Condition

T0028-01

TAS5707, TAS5707A

SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

I2C SERIAL CONTROL PORT OPERATION

Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

f t t t t t t t t t t C

SCL w(H) w(L) r f su1 h1 (buf) su2 h2 su3

Frequency, SCL No wait states 400 kHz Pulse duration, SCL high 0.6 μs Pulse duration, SCL low 1.3 μs Rise time, SCL and SDA 300 ns Fall time, SCL and SDA 300 ns Setup time, SDA to SCL 100 ns Hold time, SCL to SDA 0 ns Bus free time between stop and start condition 1.3 μs Setup time, SCL to start condition 0.6 μs Hold time, start condition to SCL 0.6 μs Setup time, SCL to stop condition 0.6 μs Load capacitance for each bus line 400 pF

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Figure 3. SCL and SDA Timing

Figure 4. Start and Stop Conditions Timing

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w(RESET)

RESET

d(I2C_ready)

SystemInitialization.

EnableviaI C.

T0421-01

I C Active

f − Frequency − Hz

PVDD = 18 V RL = 8 Ω

100 1k 10k

THD+N − Total Harmonic Distortion + Noise − %

20k

G001

P = 1 W

P = 5 W

0.001

0.01

0.1

f − Frequency − Hz

PVDD = 12 V RL = 8 Ω

100 1k 10k

THD+N − Total Harmonic Distortion + Noise − %

20k

G002

P = 2.5 W

0.001

0.01

0.1

P = 0.5 W

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SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

RESET TIMING (RESET)

Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended Use Model section on usage of all terminals.

PARAMETER MIN TYP MAX UNIT

w(RESET)

d(I2C_ready)

NOTE: On power up, it is recommended that the TAS5707 RESET be held LOW for at least 100 μs after DVDD has reached

3.0 V

NOTE: If the RESET is asserted LOW while PDN is LOW, then the RESET must continue to be held LOW for at least 100 μs

after PDN is deasserted (HIGH).

Pulse duration, RESET active 100 us Time to enable I2C 13.5 ms

Figure 5. Reset Timing

TYPICAL CHARACTERISTICS, BTL CONFIGURATION

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

FREQUENCY FREQUENCY

Figure 6. Figure 7.

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f − Frequency − Hz

PVDD = 8 V RL = 8 Ω

100 1k 10k

THD+N − Total Harmonic Distortion + Noise − %

20k

G003

P = 0.5 W

P = 1 W

0.001

0.01

0.1

P = 2.5 W

PO − Output Power − W

0.01

PVDD = 18 V RL = 8 Ω

0.1 1 10

THD+N − Total Harmonic Distortion + Noise − %

0.001

0.01

0.1

G004

f = 20 Hz

f = 1 kHz

f = 10 kHz

PO − Output Power − W

0.01

PVDD = 12 V RL = 8 Ω

0.1 1 10

THD+N − Total Harmonic Distortion + Noise − %

0.001

0.01

0.1

G005

f = 20 Hz

f = 1 kHz

f = 10 kHz

PO − Output Power − W

0.01

PVDD = 8 V RL = 8 Ω

0.1 1 10

THD+N − Total Harmonic Distortion + Noise − %

0.001

0.01

0.1

G006

f = 20 Hz

f = 1 kHz

f = 10 kHz

TAS5707, TAS5707A

SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

FREQUENCY OUTPUT POWER

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Figure 8. Figure 9.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

OUTPUT POWER OUTPUT POWER

Figure 10. Figure 11.

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PVDD − Supply Voltage − V

8 9 10 11 12 13 14 15 16 17 18

− Output Power − W

G010

RL = 8 Ω

THD+N = 1%

THD+N = 10%

PO − Output Power (Per Channel) − W

100

0 4 8 12 16 20 24 28 32 36 40

Efficiency − %

G012

PVDD = 12 V

PVDD = 18 V

RL = 8 Ω

PVDD = 8 V

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

f − Frequency − Hz

Crosstalk − dB

G013

20 100 1k 10k 20k

Left to Right

Right to Left

PO = 0.25 W PVDD = 18 V RL = 8 Ω

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

f − Frequency − Hz

Crosstalk − dB

G014

20 100 1k 10k 20k

Left to Right

Right to Left

PO = 0.25 W PVDD = 12 V RL = 8 Ω

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SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)

OUTPUT POWER EFFICIENCY

vs vs

SUPPLY VOLTAGE OUTPUT POWER

Figure 12. Figure 13.

CROSSTALK CROSSTALK

vs vs

FREQUENCY FREQUENCY

Figure 14. Figure 15.

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−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

f − Frequency − Hz

Crosstalk − dB

G015

20 100 1k 10k 20k

Left to Right

Right to Left

PO = 0.25 W PVDD = 8 V RL = 8 Ω

TAS5707, TAS5707A

SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)

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CROSSTALK

FREQUENCY

Figure 16.

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SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

DETAILED DESCRIPTION

POWER SUPPLY

To facilitate system design, the TAS5707 needs only a 3.3-V supply in addition to the (typical) 18-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.

In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). The gate drive voltages (GVDD_AB and GVDD_CD) are derived from the PVDD voltage. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins and decoupling capacitors must be avoided.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive regulator output pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin.

The TAS5707 is fully protected against erroneous power-stage turnon due to parasitic gate charging.

ERROR REPORTING

Any fault resulting in device shutdown is signaled by the FAULT pin going low (see Table 1). A sticky version of this pin is available on D1 of register 0X02.

Table 1. FAULT Output States

FAULT DESCRIPTION

0 Overcurrent (OC) or undervoltage (UVP) error or overtemperature error (OTE) or over

1 No faults (normal operation)

voltage ERROR

DEVICE PROTECTION SYSTEM

Overcurrent (OC) Protection With Current Limiting

The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The detector outputs are closely monitored by two protection systems. The first protection system controls the power stage in order to prevent the output current further increasing, i.e., it performs a cycle-by-cycle current-limiting function, rather than prematurely shutting down during combinations of high-level music transients and extreme speaker load impedance drops. If the high-current condition situation persists, i.e., the power stage is being overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state. The device returns to normal operation once the fault condition (i.e., a short circuit on the output) is removed. Current limiting and overcurrent protection are not independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent fault, half-bridges A, B, C, and D are shut down.

Product Folder Link(s): TAS5707 TAS5707A

TAS5707, TAS5707A

SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

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Overtemperature Protection

The TAS5707 has a two-level temperature-protection system that asserts an active-high warning signal (OTW) when the device junction temperature exceeds 125°C (nominal) and, if the device junction temperature exceeds 150°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and FAULT being asserted low. The TAS5707 recovers from shutdown automatically once the temperature drops approximately 30°C. The overtemperature warning (OTW) is disabled once the temperature drops approximately 25°C.

Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5707 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD and AVDD are independently monitored, a supply voltage drop below the UVP threshold on AVDD or either PVDD pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low.

SSTIMER FUNCTIONALITY

The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current source, and the charge time determines the rate at which the output transitions from a near zero duty cycle to the desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is shutdown the drivers are tristated and transition slowly down through a 3K resistor, similarly minimizing pops and clicks. The shutdown transition time is independent of SSTIMER pin capacitance. Larger capacitors will increase the start-up time, while capacitors smaller than 2.2 nF will decrease the start-up time. The SSTIMER pin should be left floating for BD modulation.

CLOCK, AUTO DETECTION, AND PLL

The TAS5707 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP) supports all the sample rates and MCLK rates that are defined in the clock control register .

The TAS5707 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 × fSLRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the internal clock (DCLK) running at 512 time the PWM switching frequency.

The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock rates as defined in the clock control register.

TAS5707 has robust clock error handling that uses the bulit-in trimmed oscillator clock to quickly detect changes/errors. Once the system detects a clock change/error, it will mute the audio (through a single step mute) and then force PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the system will auto detect the new rate and revert to normal operation. During this process, the default volume will be restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly (also called soft unmute) as defined in volume register (0X0E).

SERIAL DATA INTERFACE

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5707 DAP accepts serial data in 16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.

PWM Section

The TAS5707 DAP device uses noise-shaping and sophisticated non-linear correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP and outputs two BTL PWM audio output channels.

Product Folder Link(s): TAS5707 TAS5707A

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Texas Instruments TAS5707, TAS5707A User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual