Texas Instruments TAS5706EVM2 User Manual

User's Guide

SLOU220 – September 2008

TAS5706EVM2

This manual describes the operation of the TAS5706EVM2 to evaluate the performance of the TAS5706A. This main contents of this document are:

• Details on how to properly connect a TAS5706A Evaluation Module (TAS5706EVM2) and the details of the EVM.

• Details on how to install and use the GUI to program the TAS5706A.

• Details on how to use the audio processing features like EQ and DRC.

• Quick-Start Guide for the common modes in which TAS5706EVM2 can be used

Contents

1 Overview ...................................................................................................................... 2

1.1 TAS5706EVM2 and MC57xxPSIA Features .................................................................... 4

2 Installation .................................................................................................................... 4

2.1 EVM Installation ..................................................................................................... 5

2.2 Software Installation ................................................................................................ 9

3 Using the EVM Software .................................................................................................. 11

3.1 Connect the GUI to the EVM .................................................................................... 11

3.2 I2C Memory Tool .................................................................................................. 11

3.3 Volume Function .................................................................................................. 12

3.4 Biquad GUI ......................................................................................................... 12

3.5 DRC GUI ........................................................................................................... 13

3.6 Disable Biquads ................................................................................................... 15

4 TAS5706EVM2 Quick-Start Setup Guide ............................................................................... 15

5 Jumpers and Control Utilities on MC57xxPSIA board ................................................................. 16

5.1 RCA/OPTICAL Jumpers .......................................................................................... 16

5.2 Switches ............................................................................................................ 16

5.3 LED Indicators ..................................................................................................... 16

6 Board Layouts, Bill of Materials, and Schematic ...................................................................... 16

6.1 TAS5706EVM2 and MC57xxPSIA Board Layouts ............................................................ 17

6.2 Bill of Materials .................................................................................................... 18

6.3 Schematic .......................................................................................................... 18

7 Quick-Start Setup Guide .................................................................................................. 18

7.1 2 X BTL BD (Default: BD mode) ................................................................................ 20

7.2 2.1 AD (2 x SE + 1 x BTL via OutC and OutD) ............................................................... 21

7.3 2.1 BD (2 x BTL + 1 x BTL via external subwoofer amplifier TAS5601) ................................... 22

7.4 4 x SE AD .......................................................................................................... 23

7.5 4.1 AD (4 x SE + 1 x BTL via external subwoofer amplifier TAS5601) .................................... 24

7.6 Headphone AD .................................................................................................... 25

7.7 AD 2.1 Mode and Line Out (2 x BTL Speaker Out + 1 Subwoofer Out + 1 Line Out, AD

MODE) .............................................................................................................. 26

0 BD 2.1 Mode and Line Out (2 x BTL Speaker Out + 1 Subwoofer Out + 1 Line Out, BD

MODE) .............................................................................................................. 26

Appendix A 2 X BTL BD (Default: BD mode) ................................................................................ 28

Appendix B 2.1 AD (2 x SE + 1 x BTL via OutC and OutD) ............................................................... 29

Appendix C 2.1 BD (2 x BTL + 1 x BTL via External Subwoofer TAS5601) ............................................ 30

Appendix D 4 x SE AD ......................................................................................................... 31

Equibit is a trademark of Texas Instruments. I2C is a trademark of Philips Corporation.

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Overview

Appendix E 4.1 AD (4 x SE + 1 x BTL via External Subwoofer TAS5601) .............................................. 32

Appendix F Headphone AD ................................................................................................... 33

Appendix G 2.1 and Line out AD (2 x BTL Speaker Out + 1 Subwoofer + 1 Line out, AD MODE) .................. 34

Appendix H 2.1 and Line out BD (2 x BTL Speaker + 1 Subwoofer Out + 1 Line out, BD MODE) .................. 35

List of Figures

1 TAS5706EVM2 Printed-Circuit Board ..................................................................................... 3

2 Complete System and EVM Signal Path Overview ..................................................................... 4

3 General Connection Picture ................................................................................................ 5

4 Connecting TAS5706EVM2 to MC57xxPSIA ............................................................................ 6

5 BTL Connection .............................................................................................................. 7

6 Single-Ended Connection ................................................................................................... 8

7 Graphical User Interface Initial Window ................................................................................. 10

8 Memory Tool Window ...................................................................................................... 11

9 Volume Control ........................................................................................................... 12

10 Selecting Biquad GUI ...................................................................................................... 12

11 Filter Creation Tool Window .............................................................................................. 13

12 DRC Parameters ........................................................................................................... 13

13 Activating the DRC GUI ................................................................................................... 14

14 Time Constants Button .................................................................................................... 14

15 Disabling the Biquads ...................................................................................................... 15

16 TAS5706EVM2 Top Assembly ........................................................................................... 17

17 MC57xxPSIA Top Assembly .............................................................................................. 17

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List of Tables

1 Recommended Power Supplies ........................................................................................... 6

2 Bill of Materials for TAS5706EVM2 ...................................................................................... 18

1 Overview

The TAS5706A evaluation module (TAS5706EVM2) demonstrates the TAS5706A device from Texas Instruments.

The TAS5706A combines a high-performance PWM processor with a class-D audio power amplifier. This EVM can be configured with two bridge-tied loads (BTL) (2.0) or two single-ended (SE) and one BTL sub (2.1) or four SE (4.0) modes. When operated with an external subwoofer power stage such as the TAS5601EVM4. TAS5706A supports two bridge-tied channels plus a bridge-tied subwoofer using an external TAS5601amplifier.For detailed information about the TAS5706A device, review the device data sheet, document number SLOS606 . Pulse Width Modulator (PWM) is based on TI's Equibit™ technology. Review the board schematic and TAS5601EVM4 documents for additional information, and more specific application information on the subwoofer daughter card and connectors between the two boards.

The EVM software with its graphic user interface facilitates evaluation by providing access to the TAS5706A registers through a USB port. Refer to the Using the EVM Software section for further details.

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Overview

Figure 1. TAS5706EVM2 Printed-Circuit Board

The TAS5706EVM2, together with other TI components on this board, is a complete 2.1-channel digital audio amplifier system. The MC57XXPSIA Controller board includes a USB interface, a digital input (SPDIF), analog inputs via the ADC (PCM1808), power inputs and other features like a mute function and power down.

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2CH AnalogInput

FromOtherSource/

DigitalOut

PCInterface

SPDIF/

Optical,Coax

TAS5706A

TAS5601EVM4

(Subwoofer)

Left

Right

PWM

Output

TAS5706EVM2MC57xxPSIA

Installation

Figure 2. Complete System and EVM Signal Path Overview

1.1 TAS5706EVM2 and MC57xxPSIA Features

• Channel evaluation module design.

• Self-contained protection systems and control pins

• USB interface

• Standard I2S data input using optical or coaxial inputs

• Analog input through analog to digital converter

• Subwoofer connection—the PWM terminal provides the PWM signal and power to an external

subwoofer board

• Double-sided plated-through PCB, 1-oz copper

• Access to control signal gain and data format through EVM-software graphic user interface (GUI)

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2 Installation

This section describes the EVM and software installation.

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AnalogInto ADC

CoaxialSPDIFInput

OpticalSPDIFInput

USBPort

5VSupplyfor SystemPower

10-26VSupplyforOutputPower

Speaker Out A &B

Speaker OutC&D

TAS5706EVM2&MC-57xxPSIA GeneralConnectionPicture

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Installation

2.1 EVM Installation

The following are the basic tools for the initial EVM power up.

• 5-V, 1-A power supply (VIN)

• 10–26-V, 4-A power supply (PVCC)

• Banana-style test leads for power supplies and speakers

• Optical or coaxial cable for SPDIF interface based on signal source

• USB cable

• EVM software

• Two 8- Ω speakers or loads

The following sections describe the TAS5706EVM2 board in regards to power supply (PSU) and system interfaces.

2.1.1 Connecting the TAS5706EVM2 to MC57xxPSIA

On the right side of the MC57xxPSIA is a terminal block and another on the left of the TAS5706EVM2 (labeled J1). Carefully place the MC57xxPSIA block above the TAS5706EVM2 block and gently push down.

Figure 3. General Connection Picture

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Installation

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2.1.2 PSU Interface

Figure 4. Connecting TAS5706EVM2 to MC57xxPSIA

The TAS5706EVM2 is powered by two power supplies connected to the MC57xx controller board: a 5-V power supply (VIN) and a 10-V to 26-V (PVCC) power supply. The 3.3-V level is generated on the board by a voltage regulator from the 5-V supply.

Note: The power-supply cable length must be minimized. Increasing the length of the PSU cable

increases the distortion of the amplifier at high output levels and low frequencies

The maximum output-stage supply voltage depends on the speaker load resistance. Check the recommended maximum supply voltage in the TAS5706A (SLOS606 ) data sheet.

Table 1. Recommended Power Supplies

Description Voltage Limitations (8- Ω Load) Current Recommendations

System power supply 5 V 1 A Output power stage supply 10–26 V 4 A

(1)

The rated current corresponds to two channels, full scale.

(1)

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OUTB

JP1-Closed

JP2-Closed

OUT A

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2.1.3 Loudspeaker Connectors

Loudspeaker connections vary by device setup. Consult the quick-start guide (Section 7 ) for more details. However, the following is a general guideline:

When connecting a speaker in BTL mode, connect the speaker’s two terminals (“+” and “-“) across two outputs on the TAS5706EVM2. Ensure that the jumper (JP1 - JP4) on each output is in place.

When connecting a speaker in Single-Ended (SE) mode, connect the speaker’s “+” terminal to one EVM output, and the speaker’s “–“ terminal must be grounded at the output power ground (next to PVCC on the MC-57xxPSIA). Ensure that the jumper (JP1 - JP4) on each output is removed.

Speakers or loads can be connected to the outputs A-D with clip leads, or cables can be made with female connectors (JST VHR-2N) that can mate to male connectors on the EVM board.

Installation

CAUTION

All speaker outputs are biased at Vcc/2 and may not be connected to ground

(e.g., through an oscilloscope ground).

Figure 5. BTL Connection

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OUT A

JP1-Open

OUTB

JP2-Open

Installation

2.1.4 USB Interface

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Figure 6. Single-Ended Connection

The TAS5706A registers are accessed through I2C™ bus lines SDA and SCL. The USB circuit and USB connector on the MC57xxPSIA board facilitates the connection between a host computer and the device. The EVM USB circuit is powered by the 5-V USB line of the host PC and is independent of the power supplies available on the board. The USB device that is used is a TAS1020B from Texas Instruments.

2.1.5 Digital Audio Interface SPDIF (RCA/OPTO)

The Digital Audio Interface accepts digital audio data using the I2S protocol. See the TAS5706A data sheet (SLOS606 ) for more information.

The RCA connector and the OPTO connector are the two SPDIF interfaces on the MC57xxPSIA board. The switch S3 toggles between the OPTO and RCA connector to accommodate the signal source. When the RCA cable or optical cable is connected and the signal source is powered up, verify that the SPDIF lock indicator (blue LED5) illuminates, confirming that a viable signal is available to the device. Install a jumper on JP4 across the middle pin and the pin marked SPDIF to connect the digital source to SDIN1.Install jumper on JP5 to connect the digital source to SDIN2.

For detailed information on how the data and clocks are provided to the TAS5706A, see the schematic appearing at the end of this document and the DIR9001 device data sheet (SLES198 ).

2.1.6 ADC Interface

In the absence of a digital signal source, the PCM1808 ADC can be used to convert an analog audio signal to a digital signal to the TAS5706A. The DIR9001 still provides clock signals to the ADC in this process. The DIR9001 oscillator frequency (Y2) determines the sampling frequency in the absence of a digital signal. If the OSC frequency is 24 MHz, the sampling frequency is set at 96 kHz; if the OSC is set at 12 MHz, the sampling frequency defaults to 48 kHz when no signal is on the SPDIF input terminals. A 12-MHz crystal is installed on the MC57xxPSIA board. The ADC is an additional feature of this board to provide flexibility in sourcing an audio signal to the TAS5706A. Review the PCM1808 data sheet (SLES177 ) for a detailed description of the ADC on this EVM. Install the jumper on JP4 across the middle pin and the pin marked ADC to select ADC as the source for SDIN1.Do the same for JP5 to select the ADC as the source for SDIN2. The jumpers JP2 and JP3 on MC57xxPSIA board are IN for 1 Vrms analog input and OUT for 2 Vrms inputs.

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2.1.7 Board Power Up General Guidelines

Connect the MC-57xx and the TAS5706EVM2 boards by locating pin 1 on each board, indicated by a small white triangle. The MC-57xx plugs down onto the TAS5706EVM2 board (i.e., the TAS5706EVM2 board fits underneath the MC57xxPSIA board). Pin 1 on each board must be connected to each other.

Install the EVM software on the PC before powering up the board. After connecting the loudspeakers or other loads, power supplies, and the data line, power up the 5-V power supply first; then power up the PVCC power supply. It is recommended initially to set the PVCC level to 10 V, then ramp it up to 20 V to verify cable connections.

2.2 Software Installation

Download the TAS570X GDE from the CD or from the TI Web site, which always has the latest release of the GUI. Check versions for any updates to the GUI on the TI website .

Execute the GUI install program, Setup_TAS570X_version_number.exe Once the program is installed, the program group and shortcut icon is created in Start → Program →

Texas Instruments Inc → TAS570X GDE. THE GUI come ups as shown in Figure 7 . Select the appropriate tab; in this case, select the TAS5705/TAS5706 tab. It has two subwindows. One shows the Process Flow window. From the Process Flow window, each of

the signal processing function tools can be selected by clicking on it. The Biquad GUI and the DRC GUI can be opened by using the right button of the mouse. This window also shows input select, Mode select, Channel, and Master Volume. All functions are shown in the order that they are in the device.

The other subwindow, Properties window, has the properties where a user can update by selecting from the available options. The properties that are available depends on the device selected. From the main window, the user must set three properties before connecting to the EVM.

Select the device, Enable/Disable auto bank switch function and set the sample rate. The TAS5706A automatically detects sample rates. The setting here is simply to synchronize the GUI and the device.

Installation

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Installation

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Figure 7. Graphical User Interface Initial Window

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3 Using the EVM Software

3.1 Connect the GUI to the EVM

Once the properties window selections have been made, go to the menu Target → Connect. This sends the initialization commands to the device. Master volume is in mute. Select the master volume

function. Type the required volume in the properties window. For TAS5706A, type –12 dB. For TAS5705, type 0 dB. The difference is due the power stage gain in both devices. At this time, audio, if connected properly, plays through the device. Check All channel shutdown button. It must be un-checked. When the Connect command is issued, if an error appears that indicates a USB problem. Check the connections and press USB RESET button on the controller board. Then disconnect and re-connect from the Target menu.

3.2 I2C Memory Tool

This tool can be opened from GDE (Tools → I2C Memory Tool) or independent of GDE from Start → Program → Texas Instruments Inc → Memory Tool

Select I2C as show in Figure 8 .

Using the EVM Software

Figure 8. Memory Tool Window

I2C registers can be written or read using this tool. I2C command file can be sent by selecting the command file and Execute command.

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Using the EVM Software

3.3 Volume Function

Individual and Master volume can be selected, and the required volume value can be entered by typing on the property Window after selecting the function with the mouse (see Figure 9 ).

3.4 Biquad GUI

Using the right button of mouse, select Biquad GUI (Figure 10 ).

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Figure 9. Volume Control

Figure 10. Selecting Biquad GUI

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Using the EVM Software

Figure 11. Filter Creation Tool Window

Check mark selects the Biquad. If not selected, the Biquad is in ALL PASS Mode. Frequency response for the current settings can be viewed and adjusted in Frequency Response

Window Tab (Figure 11 ). Individual Biquad Gains must be within ± 12 db. Apply from the filter data window sends all the three banks of coefficients (providing auto bank is

enabled).

3.5 DRC GUI

Clicking on the function selects DRC GUI (Figure 12 ). Click on the DRC function, and check to see if DRC is enabled in the property window.

Figure 12. DRC Parameters

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Using the EVM Software

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Next, using the right button of the mouse, select Activate DRC GUI (Figure 13 ).

Figure 13. Activating the DRC GUI

Set the compression ratio to a value between 1 and 50. The offset has a range of ± 6 dB. A value of 0 is illegal. If no offset is required, set the offset to 0. Offset is

generally not required in a DRC application because is just provides a gain.

Threshold is selected with a value of 0 to –72 dB.

Figure 14. Time Constants Button

Time constants: Select the time constants to adjust the energy, attack, and decay filters (Figure 14 ).

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3.6 Disable Biquads

TAS5706EVM2 Quick-Start Setup Guide

The Biquads on channel1 and channel2 can be disabled from the GUI (Figure 15 ). Ensure that this is properly enabled before using Biquad GUI. Otherwise, changes on the GUI do not appear on the device output because the biquads (channel1 and channel2) are bypassed.

4 TAS5706EVM2 Quick-Start Setup Guide

This section discusses the five most common configurations of the TAS5706EVM2, and how to enable the headphone mode. For faster setup, you can load the I2C initialization script of each configuration from the CD. Directions for loading initialization scripts follow this section.

Common Configurations: Corresponding I2C script

1. 2 × BTL BD TAS5706_BD_2xBTL.ini

2. 2.1 AD (2 × SE via OutA and OutB) + 1 × BTL via TAS5706_AD_2_1_2xSE_1BTL.ini

OutC and OutD)

3. 2.1 BD (2 × BTL + 1 × BTL via J4 and external TAS5706_BD_2_1_BTL_TAS5601.ini TAS5601EVM4)

4. 4 × SE AD TAS5706_AD_4xSE.ini

5. 4.1 AD (4 × SE + 1 × BTL via J4 and external TAS5706_AD_4_1_4xSE.ini

TAS5601EVM4)

6. Headphone mode (J4) HP_mode.ini

7. 2.1 and Lineout AD (2xBTL + 1 Subwoofer + 1 AD_BTL_subout_Lineout.ini

Lineout)

Figure 15. Disabling the Biquads

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Jumpers and Control Utilities on MC57xxPSIA board

8. 2.1 and Lineout BD (2xBTL + 1 Subwoofer + 1 BD_BTL_subout_Lineout.ini Lineout)

See Section 7 for details on how to set up each of these modes. Note: AD : AD Modulation- Outputs are 180 ° out of phase BD : BD Modulation BTL : Bridge-Tied Load SE: Single-Ended Load

5 Jumpers and Control Utilities on MC57xxPSIA board

5.1 RCA/OPTICAL Jumpers

Select the jumper to reflect the source whether it is RCA or OPTICAL.

5.2 Switches

Reset is an active-low function. Pressing the master reset switch (S2) resets the TAS5706A resets device, USB RESET (S1) reset the USB bus, PDNZ(S4) power down TAS5706A and MUTE(S5) mutes (volume mute) TAS5706A.

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5.3 LED Indicators

LED1 : USB Power connector installed at J1 LED2 : 3.3V Power is valid LED3: RCA connection made LED4: Optical connection made LED5: SPDIF signal locked LED6: FAULT (Not used with TAS5706EVM2) LED7: PDN switch (S4) is depressed LED8: MUTE switch (S5) is depressed

6 Board Layouts, Bill of Materials, and Schematic

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6.1 TAS5706EVM2 and MC57xxPSIA Board Layouts

Board Layouts, Bill of Materials, and Schematic

Figure 16. TAS5706EVM2 Top Assembly

Figure 17. MC57xxPSIA Top Assembly

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Quick-Start Setup Guide

6.2 Bill of Materials

Table 2. Bill of Materials for TAS5706EVM2

TI SEMICONDUCTORS

Item Description Ref Des Qty MFG MFG:Part No. Vendor Vendor: Part No. Alt. Part No.

1 Modulator/HBRIDGE U1 1 Texas TAS5706APAP Texas TAS5706APAP No Alt. Part Num

TQFP64-PAP Instruments Instruments

CAPACITORS

2 CAP 4700PFD 50V CERM 0603 X7R C11, C14 2 Panasonic ECJ-1VB1H472K Digi-Key PCC1780TR PCC1780CT 3 CAP 0.047UFD 16V CERM 0603 X7R C10, C13 2 Panasonic ECJ-1VB1C473K Digi-Key PCC1758TR PCC1758CT 4 CAP 0.1UFD 16V CERM 0603 X7R C3, C6, C8, C9 4 Panasonic ECJ-1VB1C104K Digi-Key PCC1762TR PCC1762CT 5 CAP 0.1UFD 50V CERM 0603 X7R C1, C7, C12, C22, 5 Murata GRM188R71H104KA93D Digi-Key 490-1519-2 490-1519-1

6 CAP 0.22UFD 25V CERM 0603 X7R C15–C18 4 Murata GRM188R71E224KA88D Digi-Key 490-3290-2 490-3290-1

7 CAP 4.7UFD 6.3V CERM 0603 X5R C5 1 TDK Corp. C1608X5R0J475M Digi-Key 445-1417-2 445-1417-1 8 CAP 1.0UFD 25V CERM 0603 X5R ROHS C19–C21 3 Taiyo Yuden TMK107BJ105KA-T Digi-Key 587-1248-2 587-1248-1 9 CAP 0.68UFD 50V CERM 1206 X7R C29–C32 4 Kemet C1206C684K5RACTU Digi-Key 399-3500-2 399-3500-1

ROHS 10 CAP 10UFD 16V ALUM ELEC SMD VSA C2, C4 2 Panasonic ECE-V1CS100SR Digi-Key PCE3061TR PCE3061CT 11 CAP 15UFD 50V RAD ALUM ELEC FC C26 1 Panasonic EEU-FC1H150 Digi-Key P10317 No Alt. Part Num 12 CAP 470UFD 35V HE ALUM ELEC ROHS C33-C36 4 Panasonic UHE1V471MHD6 Nichicon 493-1583 No Alt. Part Num 13 CAP 100UFD 35V RAD ALUM ELEC M C24, C25, C27, 4 Panasonic ECA-1VM101 Digi-Key P5165 P10418TB

14 RES 0.0 Ω 1/16W 5% SMD 0603 R1 1 Panasonic ERJ-3GEY0R00V Digi-Key P0.0GTR P0.0GCT 15 RES 470 Ω 1/10W 5% SMD 0603 R2, R7 2 Panasonic ERJ-3GEYJ471V Digi-Key P470GTR P470GCT 16 RES 4.7K OHM 1/10W 5% SMD 0603 R9-R12 4 Panasonic ERJ-3GEYJ472V Digi-Key P4.7KGTR P4.7KGCT 17 RES 10 k Ω 1/16W 5% SMD 0603 R3, R4, R6, R8 4 Panasonic 9C06031A1002JLHFT Digi-Key 311-10KGTR 311-10KGCT 18 RES 18.2 k Ω 1/10W 1% SMD 0603 R5 1 Yageo 9C06031A1822FKHFT Digi-Key 311-18.2KHTR 311-18.2KHCT

19 INDUCTOR, SERIES 11RHBP, 22UH L1–L4 4 Toko No Manfact. Part Num Toko America A7503AY-220M No Alt. Part Num

20 Header, 2 Pin Male, PCB-RA, TIN W/Lock J2, J3 2 JST B2PS-VH Digi-Key 455-1255 No Alt. Part Num 21 Header, 2 Pin Male, PCB Straight Gold JP1, JP4 2 Sullins PBC02SAAN Digi-Key S1011E-02 No Alt. Part Num

ROHS 22 Header, 2X9 Pin Male, PCB Straight Gold J1 1 Sullins BC09DAAN Digi-Key S2011E-09 No Alt. Part Num

ROHS 23 Socket Header, 2x8 Pin Female Gold J4 1 Samtec SSW-108-02-G-D-RA Samtec SSW-108-02-G-D-RA No Alt. Part Num

PCB-RA

24 SHUNT, BLACK AU FLASH 0.100 JP1-JP4 4 Sullins SPC02SYAN Digi-Key S9001 No Alt. Part Num

25 Standoff 4–40 Threaded M/F 0.50 in. HW1–HW4 4 Keystone 8401 Digi-Key 8401K No Alt. Part Num

ALUM-HEX Electronics 26 Hex Nut, 4-40, Zinc/Steel HW1–HW4 4 Building HNZ440 Digi-Key H216 No Alt. Part Num

C23

Electronics

C28

RESISTORS

INDUCTORS

America

HEADERS

SHUNTS

STANDOFFS AND HARDWARE

Fasteners

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6.3 Schematic

The schematic for TAS5706EVM2 and MC57xxPSIA are located at the end of this document.

7 Quick-Start Setup Guide

This section discusses the five most common configurations of the TAS5706EVM2, and how to enable the Headphone mode.

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Quick-Start Setup Guide

Common Configurations: Corresponding I2C Script

1. 2 × BTL BD TAS5706_BD_2xBTL.ini

2. 2.1 AD (2 × SE + 1 × BTL via OutC and OutD) TAS5706_AD_2_1_2xSE_1BTL.ini

3. 2.1 BD (2 × BTL + 1 × BTL via TAS5601) TAS5706_BD_2_1_BTL_TAS5601.ini

4. 4 × SE AD TAS5706_AD_4xSE.ini

5. 4.1 AD (4 × SE + 1 × BTL via TAS5601) TAS5706_AD_4_1_4xSE.ini

6. Headphone mode HP_mode.ini

7. 2.1 and Line out AD (2xBTL + 1 Subwoofer + 1 Line AD_BTL_subout_Lineout.ini

out)

8. 2.1 and Line out BD (2xBTL + 1 Subwoofer + 1 Line BD_BTL_subout_Lineout.ini out)

Before you begin:

• Follow all steps in the EVM Installation section (Section 2.1 ).

• Click on GUI background, and in the Properties sidebar, set Device to TAS5706A:

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OUT A

OUTB

OUTC

OUTD

Left

closed

Right

closed

JP1

JP2

JP3

JP4

Quick-Start Setup Guide

7.1 2 X BTL BD (Default: BD mode)

1. Set up the hardware as shown in the following illustration. Ensure that all the four jumpers (JP1-JP4) are plugged in. This provides you with BTL output configurations for both left and right channels.

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2. Go to Appendix A of this document, and save the script as NAME.ini. ( OR use the corresponding script from the CD or TI website).The format for the config file can be .ini or .CFG

3. Connect to the device: Target > Connect.

4. Go to Tools > I2C Memory Tools.

5. Click on the I2C tab, and upload the saved configuration script NAME.ini into the I2C command File window. Click Execute.

20 TAS5706EVM2 SLOU220 – September 2008

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open

closed

BTL

closed

OUT A

OUTB

OUTC

OUTD

JP1

JP2

JP3

JP4

J2(A)

J2(B)

J3(C)

J3(D)

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6. Finally uncheck the shutdown box to bring the device out of Shutdown mode, and adjust the Master Volume as desired.

7.2 2.1 AD (2 x SE + 1 x BTL via OutC and OutD)

1. Set up the hardware configuration as shown in the following illustration. Ensure that the jumpers (JP1-JP4) for the two SE output channels (Out A and Out B) are removed, and jumpers for BTL output (Out C and Out D) are plugged in.

Quick-Start Setup Guide

2. Go to Appendix B of this document, and save the script as NAME.ini.

3. Repeat steps 3 to 6 in Section 7.1 to load the I2C command file.

SLOU220 – September 2008 TAS5706EVM2 21

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Left

closed

Right

closed

OUT A

OUTB

OUTC

OUTD

JP3

JP2

JP1

JP4

PVCC

DVDD SUB_PWM+

SUB_PWM–

BKND-ERR

VALID

PVCC

DVDD PWM_AP

PWM_CP

BKND-ERR VALID

TAS5601EVM4

Quick-Start Setup Guide

7.3 2.1 BD (2 x BTL + 1 x BTL via external subwoofer amplifier TAS5601)

1. Set up the hardware as it is shown in the following illustration. Ensure that the jumpers (JP1-JP4) for OUT A, OUT B, OUT C, and OUTD are all plugged in. Connect the TAS5601EVM to the TAS5706EVM2 as well.

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2. Go to Appendix C of this document, and save the script as NAME.ini

3. Repeat steps 3 to 6 in Section 7.1 to load I2C command file.

TAS5706EVM2 22 SLOU220 – September 2008

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open

OUT A

OUTB

OUTC

OUTD

JP1

JP2

JP3

JP4

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7.4 4 x SE AD

1. Connect the hardware as shown in the following illustration. Remove all four jumpers. This enables the

Quick-Start Setup Guide

DC blocking capacitors and provides SE output configurations for all four channels.

2. Go to Appendix D of this document, and save the script as NAME.ini

3. Repeat steps 3 to 6 in Section 7.1 to load I2C command file.

SLOU220 – September 2008 TAS5706EVM2 23

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open

OUT A

OUTB

OUTC

OUTD

JP3

JP2

JP1

JP4

PVCC

DVDD SUB_PWM+

SUB_PWM–

BKND-ERR

VALID

PVCC

DVDD PWM_AP

PWM_CP

BKND-ERR VALID

TAS5601EVM4

Quick-Start Setup Guide

7.5 4.1 AD (4 x SE + 1 x BTL via external subwoofer amplifier TAS5601)

1. Set up the hardware as shown in the following illustration. Remove all the four jumpers for the SE output configurations. Connect the TAS5601EVM to the TAS5706EVM2.

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2. Then go to Appendix E of this document, and save the script as NAME.ini

3. Repeat steps 3 to 6 in Section 7.1 to load I2C command file.

TAS5706EVM2 24 SLOU220 – September 2008

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OUT A

OUTB

OUTC

OUTD

Left

closed

Right

closed

TPA6110A2

(HP Amplifier)

Filter

HPR_PWM(Pin13)

HPL_PWM(Pin15)

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7.6 Headphone AD

1. Set up the hardware as shown in the following illustration.

Quick-Start Setup Guide

SLOU220 – September 2008 TAS5706EVM2 25

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2. Go to Appendix F of this document, and save the script as NAME.ini

3. Repeat steps 3 to 6 in Section 7.1 to load I2C command file.

Left

closed

Right

closed

OUT A

OUTB

OUTC

OUTD

JP3

JP2

JP1

JP4

PVCC

DVDD SUB_PWM+

SUB_PWM–

BKND-ERR

VALID

PVCC

DVDD PWM_AP

PWM_CP

BKND-ERR VALID

TAS5601EVM4

TPA6110A2

(HP Amplifier)

Filter

HPR_PWM(Pin13)

HPL_PWM(Pin15)

Quick-Start Setup Guide

7.7 AD 2.1 Mode and Line Out (2 x BTL Speaker Out + 1 Subwoofer Out + 1 Line Out, AD MODE)

1. Set up the hardware as shown in the following illustration.

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0 BD 2.1 Mode and Line Out (2 x BTL Speaker Out + 1 Subwoofer Out + 1 Line Out, BD

26 TAS5706EVM2 SLOU220 – September 2008

2. Go to Appendix G of this document, and save the script as NAME.ini

3. Repeat steps 3 to 6 in Section 7.1 to load I2C command file.

MODE)

1. The hardware setup for the BD mode is the same as the setup for AD mode (step 1 of Section 7.7 ).

All the speakers, subwoofer, and the headphone need to be connected to the TAS5706A.

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www.ti.com

Quick-Start Setup Guide

2. Go to Appendix H of this document, and save the script as NAME.ini

3. Repeat steps 3 to 6 in Section 7.1 to load I2C command file.

SLOU220 – September 2008 TAS5706EVM2 27

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Appendix A

Appendix A 2 X BTL BD (Default: BD mode)

Following initial scripts may also be found on the installation CD or TI website. The following scripts use .ini format where the first column is type of write command ("01" means single byte, "02" means multi-byte, "00" means comment), the following column is the I2C address and then followed by data(s).

01 1B 00 Oscillator Trim 01 03 A0 System Control Register 1 01 04 05 Serial Data Interface Register 01 05 00 System Control Register 2 01 06 00 Soft Mute Register 01 07 FF Master Volume Register (0xFF = Mute) 01 08 30 Channel 1 Volume 01 09 30 Channel 2 Volume 01 0A 30 Channel 3 Volume 01 0B 30 Channel 4 Volume 01 0C 30 Channel 5 Volume 01 0D 1C Channel 6 Volume 01 0E 91 Micro Register 01 10 02 Modulation Limit 01 18 0F PWM Start Register 01 19 30 Shutdown Group Resister 01 1A 0A Split Capacitor Charge Period 01 1C 02 Back-end Error Register 00 01 (Below) Input Mux Register 02 20 00 89 77 7A 00 01 (Below) Downmix Register 02 21 00 00 42 03 00 01 (Below) AM Mode Register 02 22 00 00 00 00 00 01 (Below) Biquad1 Coeff 02 23 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 (Below) Biquad2 Coeff 02 24 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 (Below) PWM Output MUX Register (Note: Writes to this register affect Inter-Channel Delay) 02 25 01 02 13 45 00 01 (Below) 1/G 02 26 00 80 00 00 00 01 (Below) Scale = 1/(1-1/G) 02 28 00 80 00 00 01 11 4C Inter-Channel Delay Channel 1 01 12 34 Inter-Channel Delay Channel 2 01 13 1C Inter-Channel Delay Channel 3 01 14 64 Inter-Channel Delay Channel 4 01 15 D0 Inter-Channel Delay Channel 5 01 16 90 Inter-Channel Delay Channel 6 01 17 00 Offset Register (Absolute Delay)

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2 X BTL BD (Default: BD mode)28 SLOU220 – September 2008

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Appendix B 2.1 AD (2 x SE + 1 x BTL via OutC and OutD)

01 1B 00 Oscillator Trim 01 03 A0 System Control Register 1 01 04 05 Serial Data Interface Register 01 05 00 System Control Register 2 01 06 00 Soft Mute Register 01 07 FF Master Volume Register (0xFF = Mute) 01 08 30 Channel 1 Volume 01 09 30 Channel 2 Volume 01 0A 30 Channel 3 Volume 01 0B 30 Channel 4 Volume 01 0C 30 Channel 5 Volume 01 0D 1C Channel 6 Volume 01 0E 91 Micro Register 01 10 02 Modulation Limit 01 18 0F PWM Start Register 01 19 30 Shutdown Group Resister 01 1A 0A Split Capacitor Charge Period 01 1C 02 Back-end Error Register 00 01 (Below) Input Mux Register 02 20 02 01 66 72 00 01 (Below) Downmix Register 02 21 00 00 40 03 00 01 (Below) AM Mode Register 02 22 00 00 00 00 00 01 (Below) Biquad1 Coeff 02 23 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 (Below) Biquad2 Coeff 02 24 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 (Below) PWM Output MUX Register (Note: Writes to this register affect Inter-Channel Delay) 02 25 01 01 54 23 00 01 (Below) 1/G 02 26 00 80 00 00 00 01 (Below) Scale = 1/(1-1/G) 02 28 00 80 00 00 01 11 3C Inter-Channel Delay Channel 1 01 12 C0 Inter-Channel Delay Channel 2 01 13 00 Inter-Channel Delay Channel 3 01 14 00 Inter-Channel Delay Channel 4 01 15 00 Inter-Channel Delay Channel 5 01 16 08 Inter-Channel Delay Channel 6 01 17 00 Offset Register (Absolute Delay)

Appendix B

SLOU220 – September 2008 2.1 AD (2 x SE + 1 x BTL via OutC and OutD) 29

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Appendix C

Appendix C 2.1 BD (2 x BTL + 1 x BTL via External Subwoofer TAS5601)

01 1B 00 Oscillator Trim 01 03 A0 System Control Register 1 01 04 05 Serial Data Interface Register 01 05 20 System Control Register 2 01 06 00 Soft Mute Register 01 07 FF Master Volume Register (0xFF = Mute) 01 08 30 Channel 1 Volume 01 09 30 Channel 2 Volume 01 0A 30 Channel 3 Volume 01 0B 30 Channel 4 Volume 01 0C 30 Channel 5 Volume 01 0D 1C Channel 6 Volume 01 0E 91 Micro Register 01 10 02 Modulation Limit 01 18 0F PWM Start Register 01 19 00 Shutdown Group Resister 01 1A 0A Split Capacitor Charge Period 01 1C 02 Back-end Error Register 00 01 (Below) Input Mux Register 02 20 00 89 77 7A 00 01 (Below) Downmix Register 02 21 00 00 40 03 00 01 (Below) AM Mode Register 02 22 00 00 00 00 00 01 (Below) Biquad1 Coeff 02 23 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 (Below) Biquad2 Coeff 02 24 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 (Below) PWM Output MUX Register (Note: Writes to this register affect Inter-Channel Delay) 02 25 01 02 13 45 00 01 (Below) 1/G 02 26 00 80 00 00 00 01 (Below) Scale = 1/(1-1/G) 02 28 00 80 00 00 01 11 4C Inter-Channel Delay Channel 1 01 12 34 Inter-Channel Delay Channel 2 01 13 1C Inter-Channel Delay Channel 3 01 14 64 Inter-Channel Delay Channel 4 01 15 D0 Inter-Channel Delay Channel 5 01 16 90 Inter-Channel Delay Channel 6 01 17 00 Offset Register (Absolute Delay)

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2.1 BD (2 x BTL + 1 x BTL via External Subwoofer TAS5601)30 SLOU220 – September 2008

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Appendix D 4 x SE AD

01 1B 00 Oscillator Trim 01 03 A0 System Control Register 1 01 04 05 Serial Data Interface Register 01 05 00 System Control Register 2 01 06 00 Soft Mute Register 01 07 FF Master Volume Register (0xFF = Mute) 01 08 30 Channel 1 Volume 01 09 30 Channel 2 Volume 01 0A 30 Channel 3 Volume 01 0B 30 Channel 4 Volume 01 0C 30 Channel 5 Volume 01 0D 1C Channel 6 Volume 01 0E 91 Micro Register 01 10 02 Modulation Limit 01 18 0F PWM Start Register 01 19 30 Shutdown Group Resister 01 1A 95 Split Capacitor Charge Period 01 1C 02 Back-end Error Register 00 01 (Below) Input Mux Register 02 20 0A 01 23 66 00 01 (Below) Downmix Register 02 21 00 00 40 03 00 01 (Below) AM Mode Register 02 22 00 00 00 00 00 01 (Below) Biquad1 Coeff 02 23 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 (Below) Biquad2 Coeff 02 24 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 (Below) PWM Output MUX Register (Note: Writes to this register affect Inter-Channel Delay) 02 25 01 01 23 45 00 01 (Below) 1/G 02 26 00 80 00 00 00 01 (Below) Scale = 1/(1-1/G) 02 28 00 80 00 00 01 11 20 Inter-Channel Delay Channel 1 01 12 A0 Inter-Channel Delay Channel 2 01 13 E0 Inter-Channel Delay Channel 3 01 14 60 Inter-Channel Delay Channel 4 01 15 04 Inter-Channel Delay Channel 5 01 16 FC Inter-Channel Delay Channel 6 01 17 00 Offset Register (Absolute Delay)

Appendix D

SLOU220 – September 2008 4 x SE AD 31

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Appendix E

Appendix E 4.1 AD (4 x SE + 1 x BTL via External Subwoofer TAS5601)

01 1B 00 Oscillator Trim 01 03 A0 System Control Register 1 01 04 05 Serial Data Interface Register 01 05 20 System Control Register 2 01 06 00 Soft Mute Register 01 07 FF Master Volume Register (0xFF = Mute) 01 08 30 Channel 1 Volume 01 09 30 Channel 2 Volume 01 0A 30 Channel 3 Volume 01 0B 30 Channel 4 Volume 01 0C 30 Channel 5 Volume 01 0D 1C Channel 6 Volume 01 0E 91 Micro Register 01 10 02 Modulation Limit 01 18 0F PWM Start Register 01 19 00 Shutdown Group Resister 01 1A 95 Split Capacitor Charge Period 01 1C 02 Back-end Error Register 00 01 (Below) Input Mux Register 02 20 0A 01 23 72 00 01 (Below) Downmix Register 02 21 00 00 42 03 00 01 (Below) AM Mode Register 02 22 00 00 00 00 00 01 (Below) Biquad1 Coeff 02 23 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 (Below) Biquad2 Coeff 02 24 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 (Below) PWM Output MUX Register (Note: Writes to this register affect Inter-Channel Delay) 02 25 01 01 23 45 00 01 (Below) 1/G 02 26 00 80 00 00 00 01 (Below) Scale = 1/(1-1/G) 02 28 00 80 00 00 01 11 20 Inter-Channel Delay Channel 1 01 12 A0 Inter-Channel Delay Channel 2 01 13 E0 Inter-Channel Delay Channel 3 01 14 60 Inter-Channel Delay Channel 4 01 15 04 Inter-Channel Delay Channel 5 01 16 FC Inter-Channel Delay Channel 6 01 17 00 Offset Register (Absolute Delay)

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4.1 AD (4 x SE + 1 x BTL via External Subwoofer TAS5601)32 SLOU220 – September 2008

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Appendix F Headphone AD

01 1B 00 Oscillator Trim 01 03 A0 System Control Register 1 01 04 05 Serial Data Interface Register 01 05 02 System Control Register 2 01 06 00 Soft Mute Register 01 07 FF Master Volume Register (0xFF = Mute) 01 08 30 Channel 1 Volume 01 09 30 Channel 2 Volume 01 0A 30 Channel 3 Volume 01 0B 30 Channel 4 Volume 01 0C 30 Channel 5 Volume 01 0D 1C Channel 6 Volume 01 0E 91 Micro Register 01 10 02 Modulation Limit 01 18 0F PWM Start Register 01 19 3C Shutdown Group Resister 01 1A 95 Split Capacitor Charge Period 01 1C 02 Back-end Error Register 00 01 (Below) Input Mux Register 02 20 00 01 66 66 00 01 (Below) Downmix Register 02 21 00 00 42 03 00 01 (Below) AM Mode Register 02 22 00 00 00 00 00 01 (Below) Biquad1 Coeff 02 23 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 (Below) Biquad2 Coeff 02 24 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 (Below) PWM Output MUX Register (Note: Writes to this register affect Inter-Channel Delay) 02 25 01 02 13 45 00 01 (Below) 1/G 02 26 00 80 00 00 00 01 (Below) Scale = 1/(1-1/G) 02 28 00 80 00 00 01 11 5C Inter-Channel Delay Channel 1 01 12 24 Inter-Channel Delay Channel 2 01 13 54 Inter-Channel Delay Channel 3 01 14 2C Inter-Channel Delay Channel 4 01 15 A4 Inter-Channel Delay Channel 5 01 16 AC Inter-Channel Delay Channel 6 01 17 00 Offset Register (Absolute Delay)

Appendix F

SLOU220 – September 2008 Headphone AD 33

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Appendix G

Appendix G 2.1 and Line out AD (2 x BTL Speaker Out + 1 Subwoofer + 1 Line out, AD MODE)

01 1B 00 Oscillator Trim 01 03 A0 System Control Register 1 01 04 05 Serial Data Interface Register 01 05 24 System Control Register 2 01 06 00 Soft Mute Register 01 07 FF Master Volume Register (0xFF = Mute) 01 08 30 Channel 1 Volume 01 09 30 Channel 2 Volume 01 0A 30 Channel 3 Volume 01 0B 30 Channel 4 Volume 01 0C 30 Channel 5 Volume 01 0D 1C Channel 6 Volume 01 0E 91 Micro Register 01 10 02 Modulation Limit 01 18 0F PWM Start Register 01 19 00 Shutdown Group Resister 01 1A 0F Split Capacitor Charge Period 01 1C 02 Back-end Error Register 00 01 (Below) Input Mux Register 02 20 00 01 77 72 00 01 (Below) Downmix Register 02 21 00 00 40 03 00 01 (Below) AM Mode Register 02 22 00 00 00 00 00 01 (Below) Biquad1 Coeff 02 23 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 (Below) Biquad2 Coeff 02 24 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 (Below) PWM Output MUX Register (Note: Writes to this register affect Inter-Channel Delay) 02 25 01 02 13 45 00 01 (Below) 1/G 02 26 00 80 00 00 00 01 (Below) Scale = 1/(1-1/G) 02 28 00 80 00 00 01 11 5C Inter-Channel Delay Channel 1 01 12 24 Inter-Channel Delay Channel 2 01 13 54 Inter-Channel Delay Channel 3 01 14 2C Inter-Channel Delay Channel 4 01 15 A4 Inter-Channel Delay Channel 5 01 16 AC Inter-Channel Delay Channel 6 01 17 00 Offset Register (Absolute Delay)

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2.1 and Line out AD (2 x BTL Speaker Out + 1 Subwoofer + 1 Line out, AD MODE)34 SLOU220 – September 2008

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Appendix H 2.1 and Line out BD (2 x BTL Speaker + 1 Subwoofer Out + 1 Line out, BD MODE)

01 1B 00 Oscillator Trim 01 03 A0 System Control Register 1 01 04 05 Serial Data Interface Register 01 05 24 System Control Register 2 01 06 00 Soft Mute Register 01 07 FF Master Volume Register (0xFF = Mute) 01 08 30 Channel 1 Volume 01 09 30 Channel 2 Volume 01 0A 30 Channel 3 Volume 01 0B 30 Channel 4 Volume 01 0C 30 Channel 5 Volume 01 0D 1C Channel 6 Volume 01 0E 91 Micro Register 01 10 02 Modulation Limit 01 18 0F PWM Start Register 01 19 00 Shutdown Group Resister 01 1A 0A Split Capacitor Charge Period 01 1C 02 Back-end Error Register 00 01 (Below) Input Mux Register 02 20 00 89 77 7A 00 01 (Below) Downmix Register 02 21 00 00 40 03 00 01 (Below) AM Mode Register 02 22 00 00 00 00 00 01 (Below) Biquad1 Coeff 02 23 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 (Below) Biquad2 Coeff 02 24 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 (Below) PWM Output MUX Register (Note: Writes to this register affect Inter-Channel Delay) 02 25 01 02 13 45 00 01 (Below) 1/G 02 26 00 80 00 00 00 01 (Below) Scale = 1/(1-1/G) 02 28 00 80 00 00 01 11 4C Inter-Channel Delay Channel 1 01 12 34 Inter-Channel Delay Channel 2 01 13 1C Inter-Channel Delay Channel 3 01 14 64 Inter-Channel Delay Channel 4 01 15 D0 Inter-Channel Delay Channel 5 01 16 90 Inter-Channel Delay Channel 6 01 17 00 Offset Register (Absolute Delay)

Appendix H

SLOU220 – September 2008 2.1 and Line out BD (2 x BTL Speaker + 1 Subwoofer Out + 1 Line out, BD MODE) 35

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TAS5706A 2.0/2.1/4.0 SE/BTL Evalulation Board

FROM MC-57xx

PGND

TAS5706APAP

BOOT

STRAP

DECOUPLING

MODE

2.0

2.1

4.0

OUTPUT CONFIGURATIONS

TYPE

2xBTL

SE/BTL

4xSE

J2-1

Ch1+ Chan1 Chan1

J2-2

Ch1Chan2 Chan2

J3-1

Ch2+ Sub+

Chan3

J3-2

Ch2Sub-

Chan4

JP1/2

IN IN OUT OUT

JP3/4

OUTPUTS

OUT

BOM ONLY

PGND

JP1

JP3

JP2

JP4

PGND

SUBWOOFER

DAUGHTERCARD

PGND

PROJECT:

Design Team:

Schematic Rev:

Save Date:

Filename:

March 20, 2008

TAS5706EVM2.SCH

2.0/2.1/4.0 SE/BTL TAS5706 Eval Board

RYAN KEHR, DON DAPKUS, Y B QUEK, STEPHEN CRUMP

NC NC 1

Mod: PCB Rev: Sheet

NC 3

Print Date

Thu Mar 20, 2008

Drawn By:

LDN

USB INTERFACE

USB BOOT EPROM

(A0 IN DEFAULT)

ENGINEERING EVALUATION ONLY

TO EVM BOARD

USB I/O

TAS1020BPFB

USB RESET

DECOUPLING

PROJECT:

Design Team:

Schematic Rev:

Save Date:

Filename:

MAY 29, 2008 MC57xxPSIA.sch

EVM CONTROLLER BOARD

YONG GWAN KIM

Mod: PCB Rev: Sheet

NC 1

Print Date

Thu May 29, 2008

5NC

Drawn By:

LDN

SPDIF RECEIVER

ENGINEERING EVALUATION ONLY

SPDIF INPUT

SELECT

1-2:

OPTO INPUT

2-3:

RCA INPUT

(LOW)

OPTO INPUT

(HIGH)

JP1 IN: SCKO = 512 Fs JP1 OUT: SCKO = 256 Fs

(DEFAULT)

DIR9001PW

24Bit/MSB/I2S

FMT1

H H

SPDIF

LOCK

FMT0DATA FORMAT

ADC

MASTER RESET

5V POWER INPUT

TO ADC

EVM BOARD

TO EVM BOARD

SPDIF DECOUPLING

TO SPDIF

3.3V@1A TO ADC

PROJECT:

Design Team:

Schematic Rev:

Save Date:

Filename:

MAY 29, 2008 MC57xxPSIA.sch

EVM CONTROLLER BOARD

YONG GWAN KIM

Mod: PCB Rev: Sheet

NC 2

NC 5

Print Date

Thu May 29, 2008

Drawn By:

LDN

ADC / CONNECTOR I/O

ENGINEERING EVALUATION ONLY

TO EVM BOARDS

FAULT

ANALOG INPUTS

FROM SPDIF

NOTES ON JUMPERS

IN: LIN/RIN = 1Vrms MAX. OUT: LIN/RIN = 2Vrms MAX.

PDN

MUTE

ADC

(SDIN1)

(SDIN2)

PCM1808PW

FROM USB

FROM

MASETER RESET

FROM VR1

HIGH POWER INPUT

3.3V DECOUPLING

5V DECOUPLING

MC012 PSIA

(1-2) (2-3)

PROJECT:

Design Team:

Schematic Rev:

Save Date:

Filename:

MAY 29, 2008 MC57xxPSIA.sch

EVM CONTROLLER BOARD

YONG GWAN KIM

Mod: PCB Rev: Sheet

NC 3

NC 5

Print Date

Thu May 29, 2008

Drawn By:

LDN

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Texas Instruments: TAS5706EVM2

Texas Instruments TAS5706EVM2 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Overview

1.1 TAS5706EVM2 and MC57xxPSIA Features

2 Installation

2.1 EVM Installation

2.1.1 Connecting the TAS5706EVM2 to MC57xxPSIA

2.1.2 PSU Interface

2.1.3 Loudspeaker Connectors

2.1.4 USB Interface

2.1.5 Digital Audio Interface SPDIF (RCA/OPTO)

2.1.6 ADC Interface

2.1.7 Board Power Up General Guidelines

2.2 Software Installation

3 Using the EVM Software

3.1 Connect the GUI to the EVM

3.2 I2C Memory Tool

3.3 Volume Function

3.4 Biquad GUI

3.5 DRC GUI

3.6 Disable Biquads

4 TAS5706EVM2 Quick-Start Setup Guide

5 Jumpers and Control Utilities on MC57xxPSIA board

5.1 RCA/OPTICAL Jumpers

5.2 Switches

5.3 LED Indicators

6 Board Layouts, Bill of Materials, and Schematic

6.1 TAS5706EVM2 and MC57xxPSIA Board Layouts

6.2 Bill of Materials

6.3 Schematic

7 Quick-Start Setup Guide

7.1 2 X BTL BD (Default: BD mode)

7.2 2.1 AD (2 x SE + 1 x BTL via OutC and OutD)

7.3 2.1 BD (2 x BTL + 1 x BTL via external subwoofer amplifier TAS5601)

7.4 4 x SE AD

7.5 4.1 AD (4 x SE + 1 x BTL via external subwoofer amplifier TAS5601)

7.6 Headphone AD

7.7 AD 2.1 Mode and Line Out (2 x BTL Speaker Out + 1 Subwoofer Out + 1 Line Out, AD MODE)

Appendix A 2 X BTL BD (Default: BD mode)

Appendix B 2.1 AD (2 x SE + 1 x BTL via OutC and OutD)

Appendix C 2.1 BD (2 x BTL + 1 x BTL via External Subwoofer TAS5601)

Appendix D 4 x SE AD

Appendix E 4.1 AD (4 x SE + 1 x BTL via External Subwoofer TAS5601)

Appendix F Headphone AD

Appendix G 2.1 and Line out AD (2 x BTL Speaker Out + 1 Subwoofer + 1 Line out, AD MODE)

Appendix H 2.1 and Line out BD (2 x BTL Speaker + 1 Subwoofer Out + 1 Line out, BD MODE)