Texas instruments TAS5508C Data Manual

TAS5508C

8-Channel Digital Audio PWM Processor

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SLES257

September 2010

TAS5508C

SLES257–SEPTEMBER 2010

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Contents

1 Introduction PWM ............................................................................................................... 9

1.1 Features ...................................................................................................................... 9

1.2 Overview .................................................................................................................... 10

1.3 TAS5508C System Diagrams ............................................................................................ 12

2 Description ....................................................................................................................... 15

2.1 Physical Characteristics .................................................................................................. 15

2.1.1 Terminal Assignments ......................................................................................... 15

2.1.2 Ordering Information ........................................................................................... 15

2.1.3 PIN Descriptions ................................................................................................ 16

2.2 TAS5508C Functional Description ...................................................................................... 17

2.2.1 Power Supply ................................................................................................... 18

2.2.2 Clock, PLL, and Serial Data Interface ....................................................................... 18

2.2.2.1 Serial Audio Interface .............................................................................. 18

2.2.3 I

2.2.4 Device Control .................................................................................................. 19

2.2.5 Digital Audio Processor (DAP) ................................................................................ 19

2.3 TAS5508C DAP Architecture ............................................................................................ 21

2.3.1 TAS5508C DAP Architecture Diagrams ..................................................................... 21

2.3.2 I

2.4 Input Crossbar Mixer ...................................................................................................... 28

2.5 Biquad Filters .............................................................................................................. 28

2.6 Bass and Treble Controls ................................................................................................ 29

2.7 Volume, Automute, and Mute ............................................................................................ 30

2.8 Automute and Mute ....................................................................................................... 30

2.9 Loudness Compensation ................................................................................................. 31

2.9.1 Loudness Example ............................................................................................. 32

2.10 Dynamic Range Control (DRC) .......................................................................................... 33

2.10.1 DRC Implementation ........................................................................................... 36

2.10.2 Compression/Expansion Coefficient Computation Engine Parameters ................................. 36

2.11 Output Mixer ............................................................................................................... 38

2.12 PWM ........................................................................................................................ 39

2.12.1 DC Blocking (High-Pass Enable/Disable) ................................................................... 40

2.12.2 De-Emphasis Filter ............................................................................................. 40

2.12.3 Power-Supply Volume Control (PSVC) ...................................................................... 40

2.12.4 AM Interference Avoidance ................................................................................... 41

3 TAS5508C Controls and Status ........................................................................................... 43

3.1 I

C Status Registers ....................................................................................................... 43

3.1.1 General Status Register (0x01) ............................................................................... 43

C Serial-Control Interface ................................................................................... 19

2.2.5.1 TAS5508C Audio-Processing Configurations .................................................. 19

2.2.5.2 TAS5508C Audio Signal-Processing Functions ................................................ 20

C Coefficient Number Formats ............................................................................. 24

2.3.2.1 28-Bit 5.23 Number Format ....................................................................... 24

2.3.2.2 48-Bit 25.23 Number Format ..................................................................... 26

2.3.2.3 TAS5508C Audio Processing .................................................................... 27

2.10.2.1 Threshold Parameter Computation .............................................................. 37

2.10.2.2 Offset Parameter Computation ................................................................... 37

2.10.2.3 Slope Parameter Computation ................................................................... 38

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3.1.2 Error Status Register (0x02) .................................................................................. 43

3.2 TAS5508C Pin Controls .................................................................................................. 43

3.2.1 Reset (RESET) ................................................................................................. 43

3.2.2 Power Down (PDN) ............................................................................................ 45

3.2.3 Back-End Error (BKND_ERR) ................................................................................ 46

3.2.4 Speaker/Headphone Selector (HP_SEL) .................................................................... 46

3.2.5 Mute (MUTE) .................................................................................................... 46

3.3 Device Configuration Controls ........................................................................................... 47

3.3.1 Channel Configuration Registers ............................................................................. 47

3.3.2 Headphone Configuration Registers ......................................................................... 48

3.3.3 Audio System Configurations ................................................................................. 48

3.3.3.1 Using Line Outputs in 6-Channel Configurations .............................................. 49

3.3.4 Recovery from Clock Error .................................................................................... 49

3.3.5 Power-Supply Volume-Control Enable ....................................................................... 49

3.3.6 Volume and Mute Update Rate ............................................................................... 49

3.3.7 Modulation Index Limit ......................................................................................... 50

3.3.8 Interchannel Delay .............................................................................................. 50

3.4 Master Clock and Serial Data Rate Controls .......................................................................... 50

3.4.1 PLL Operation ................................................................................................... 51

3.5 Bank Controls .............................................................................................................. 51

3.5.1 Manual Bank Selection ........................................................................................ 52

3.5.2 Automatic Bank Selection ..................................................................................... 52

3.5.2.1 Coefficient Write Operations While Automatic Bank Switch Is Enabled .................... 52

3.5.3 Bank Set ......................................................................................................... 52

3.5.4 Bank-Switch Timeline .......................................................................................... 52

3.5.5 Bank-Switching Example 1 .................................................................................... 53

3.5.6 Bank-Switching Example 2 .................................................................................... 53

4 Electrical Specifications ..................................................................................................... 55

4.1 Absolute Maximum Ratings .............................................................................................. 55

4.2 Dissipation Rating Table (High-k Board, 105°C Junction) ........................................................... 55

4.3 Dynamic Performance At Recommended Operating Conditions at 25°C .......................................... 55

4.4 Recommended Operating Conditions .................................................................................. 55

4.5 Electrical Characteristics ................................................................................................. 56

4.6 PWM Operation ............................................................................................................ 56

4.7 Switching Characteristics ................................................................................................. 56

4.7.1 Clock Signals .................................................................................................... 56

4.7.2 Serial Audio Port ................................................................................................ 57

4.7.3 I

4.7.4 Reset Timing (RESET) ......................................................................................... 59

4.7.5 Power-Down (PDN) Timing ................................................................................... 59

4.7.6 Back-End Error (BKND_ERR) ................................................................................ 60

4.7.7 Mute Timing (MUTE) ........................................................................................... 60

4.7.8 Headphone Select (HP_SEL) ................................................................................. 61

4.7.9 Volume Control ................................................................................................. 62

4.8 Serial Audio Interface Control and Timing ............................................................................. 62

4.8.1 I

4.8.2 Left-Justified Timing ............................................................................................ 63

C Serial Control Port Operation ............................................................................. 58

S Timing ....................................................................................................... 62

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4.8.3 Right-Justified Timing .......................................................................................... 64

5 I

C Serial-Control Interface (Slave Address 0x36) .................................................................. 65

5.1 General I

C Operation .................................................................................................... 65

5.2 Single- and Multiple-Byte Transfers ..................................................................................... 65

5.3 Single-Byte Write .......................................................................................................... 66

5.4 Multiple-Byte Write ........................................................................................................ 66

5.5 Incremental Multiple-Byte Write ......................................................................................... 67

5.6 Single-Byte Read .......................................................................................................... 67

5.7 Multiple-Byte Read ........................................................................................................ 68

6 Serial-Control I

C Register Summary ................................................................................... 69

7 Serial-Control Interface Register Definitions ......................................................................... 73

7.1 Clock Control Register (0x00) ........................................................................................... 73

7.2 General Status Register 0 (0x01) ....................................................................................... 73

7.3 Error Status Register (0x02) ............................................................................................. 74

7.4 System Control Register 1 (0x03) ....................................................................................... 74

7.5 System Control Register 2 (0x04) ....................................................................................... 74

7.6 Channel Configuration Control Registers (0x05–0x0C) .............................................................. 74

7.7 Headphone Configuration Control Register (0x0D) ................................................................... 75

7.8 Serial Data Interface Control Register (0x0E) ......................................................................... 75

7.9 Soft Mute Register (0x0F) ................................................................................................ 76

7.10 Automute Control Register (0x14) ....................................................................................... 77

7.11 Automute PWM Threshold and Back-End Reset Period Register (0x15) .......................................... 78

7.12 Modulation Index Limit Register (0x16) ................................................................................. 79

7.13 Interchannel Delay Registers (0x1B–0x22) ............................................................................ 79

7.14 Channel Offset Register (0x23) .......................................................................................... 79

7.15 Bank-Switching Command Register (0x40) ............................................................................ 80

7.16 Input Mixer Registers, Channels 1–8 (0x41–0x48) ................................................................... 80

7.17 Bass Management Registers (0x49–0x50) ............................................................................ 84

7.18 Biquad Filter Register (0x51–0x88) ..................................................................................... 84

7.19 Bass and Treble Bypass Register, Channels 1–8 (0x89–0x90) ..................................................... 85

7.20 Loudness Registers (0x91–0x95) ....................................................................................... 85

7.21 DRC1 Control Registers, Channels 1–7 (0x96) ....................................................................... 86

7.22 DRC2 Control Register, Channel 8 (0x97) ............................................................................. 87

7.23 DRC1 Data Registers (0x98–0x9C) ..................................................................................... 87

7.24 DRC2 Data Registers (0x9D–0xA1) .................................................................................... 88

7.25 DRC Bypass Registers (0xA2–0xA9) ................................................................................... 88

7.26 8×2 Output Mixer Registers (0xAA–0xAF) ............................................................................. 88

7.27 8×3 Output Mixer Registers (0xB0–0xB1) ............................................................................. 89

7.28 Volume Biquad Register (0xCF) ......................................................................................... 91

7.29 Volume, Treble, and Bass Slew Rates Register (0xD0) ............................................................. 92

7.30 Volume Registers (0xD1–0xD9) ......................................................................................... 92

7.31 Bass Filter Set Register (0xDA) ......................................................................................... 94

7.32 Bass Filter Index Register (0xDB) ....................................................................................... 95

7.33 Treble Filter Set Register (0xDC) ....................................................................................... 96

7.34 Treble Filter Index (0xDD) ................................................................................................ 97

7.35 AM Mode Register (0xDE) ............................................................................................... 97

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7.36 PSVC Range Register (0xDF) ........................................................................................... 99

7.37 General Control Register (0xE0) ........................................................................................ 99

7.38 Incremental Multiple-Write Append Register (0xFE) .................................................................. 99

SLES257–SEPTEMBER 2010

8 TAS5508C Example Application Schematic ......................................................................... 101

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List of Figures

1-1 TAS5508C Functional Structure................................................................................................ 12

1-2 Typical TAS5508C Application (DVD Receiver) ............................................................................. 12

1-3 Recommended TAS5508C and TAS5121 Channel Configuraton......................................................... 13

2-1 TAS5508C DAP Architecture With I 2-2 TAS5508C Architecture With I

2-3 TAS5508C Detailed Channel Processing..................................................................................... 24

2-4 5.23 Format ....................................................................................................................... 25

2-5 Conversion Weighting Factors—5.23 Format to Floating Point............................................................ 25

2-6 Alignment of 5.23 Coefficient in 32-Bit I

2-7 25.23 Format...................................................................................................................... 26

2-8 Alignment of 5.23 Coefficient in 32-Bit I 2-9 Alignment of 25.23 Coefficient in Two 32-Bit I

2-10 TAS5508C Digital Audio Processing .......................................................................................... 28

2-11 Input Crossbar Mixer............................................................................................................. 28

2-12 Biquad Filter Structure........................................................................................................... 29

2-13 Automute Threshold ............................................................................................................. 31

2-14 Loudness Compensation Functional Block Diagram ........................................................................ 32

2-15 Loudness Example Plots........................................................................................................ 33

2-16 DRC Positioning in TAS5508C Processing Flow ............................................................................ 34

2-17 Dynamic Range Compression (DRC) Transfer Function Structure........................................................ 35

2-18 Output Mixers..................................................................................................................... 39

2-19 De-Emphasis Filter Characteristics............................................................................................ 40

2-20 Power-Supply and Digital Gains (Log Space)................................................................................ 41

2-21 Power-Supply and Digital Gains (Linear Space)............................................................................. 41

2-22 Block Diagrams of Typical Systems Requiring TAS5508C Automatic AM Interference-Avoidance Circuit .......... 42

4-1 Slave Mode Serial Data Interface Timing..................................................................................... 57

4-2 SCL and SDA Timing............................................................................................................ 58

4-3 Start and Stop Conditions Timing.............................................................................................. 58

4-4 Reset Timing...................................................................................................................... 59

4-5 Power-Down Timing ............................................................................................................. 59

4-6 Error Recovery Timing........................................................................................................... 60

4-7 Mute Timing....................................................................................................................... 60

4-8 HP_SEL Timing................................................................................................................... 62

4-9 I

S 64-Fs Format................................................................................................................. 63

4-10 Left-Justified 64-Fs Format ..................................................................................................... 63

4-11 Right-Justified 64-Fs Format.................................................................................................... 64

5-1 Typical I

C Sequence............................................................................................................ 65

5-2 Single-Byte Write Transfer ...................................................................................................... 66

5-3 Multiple-Byte Write Transfer .................................................................................................... 67

5-4 Single-Byte Read Transfer...................................................................................................... 68

5-5 Multiple-Byte Read Transfer .................................................................................................... 68

C Registers (Fs ≤ 96 kHz)........................................................... 23

C Registers (Fs = 176.4 kHz or Fs = 192 kHz) ......................................... 24

C Word............................................................................. 25

C Word............................................................................. 26

C Words.................................................................... 27

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List of Tables

2-1 Serial Data Formats.............................................................................................................. 19

2-2 TAS5508C Audio Processing Feature Sets .................................................................................. 21

2-3 Contents of One 20-Byte Biquad Filter Register (Default = All-Pass)..................................................... 29

2-4 Bass and Treble Filter Selections.............................................................................................. 30

2-5 Linear Gain Step Size ........................................................................................................... 30

2-6 Default Loudness Compensation Parameters................................................................................ 32

2-7 Loudness Function Parameters ................................................................................................ 33

2-8 DRC Recommended Changes From TAS5508C Defaults ................................................................. 34

3-1 Device Outputs During Reset................................................................................................... 43

3-2 Values Set During Reset ........................................................................................................ 44

3-3 Device Outputs During Power Down .......................................................................................... 45

3-4 Device Outputs During Back-End Error ....................................................................................... 46

3-5 Description of the Channel Configuration Registers (0x05 to 0x0C) ...................................................... 47

3-6 Recommended TAS5508C Configurations for Texas Instruments Power Stages....................................... 48

3-7 Audio System Configuration (General Control Register 0xE0)............................................................. 49

3-8 Volume Ramp Rates in ms ..................................................................................................... 50

3-9 Interchannel Delay Default Values............................................................................................. 50

7-1 Clock Control Register Format ................................................................................................. 73

7-2 General Status Register Format................................................................................................ 73

7-3 Error Status Register Format ................................................................................................... 74

7-4 System Control Register 1 Format............................................................................................. 74

7-5 System Control Register 2 Format............................................................................................. 74

7-6 Channel Configuration Control Register Format ............................................................................. 75

7-7 Headphone Configuration Control Register Format ......................................................................... 75

7-8 Serial Data Interface Control Register Format ............................................................................... 75

7-9 Soft Mute Register Format...................................................................................................... 76

7-10 Automute Control Register Format............................................................................................. 77

7-11 Automute PWM Threshold and Back-End Reset Period Register Format................................................ 78

7-12 Modulation Index Limit Register Format ...................................................................................... 79

7-13 Interchannel Delay Register Format ........................................................................................... 79

7-14 Channel Offset Register Format................................................................................................ 79

7-15 Bank-Switching Command Register Format.................................................................................. 80

7-16 Channel 1–8 Input Mixer Register Format.................................................................................... 81

7-17 Bass Management Register Format ........................................................................................... 84

7-18 Biquad Filter Register Format .................................................................................................. 84

7-19 Contents of One 20-Byte Biquad Filter Register (Default = All-Pass)..................................................... 85

7-20 Channel 1–8 Bass and Treble Bypass Register Format.................................................................... 85

7-21 Loudness Register Format...................................................................................................... 85

7-22 Channel 1–7 DCR1 Control Register Format................................................................................. 86

7-23 Channel-8 DRC2 Control Register Format ................................................................................... 87

7-24 DRC1 Data Register Format.................................................................................................... 87

7-25 DRC2 Data Register Format.................................................................................................... 88

7-26 DRC Bypass Register Format .................................................................................................. 88

7-27 Output Mixer Register Format (Upper 4 Bytes) .............................................................................. 89

7-28 Output Mixer Register Format (Lower 4 Bytes) .............................................................................. 89

7-29 Output Mixer Register Format (Upper 4 Bytes) .............................................................................. 90

7-30 Output Mixer Register Format (Middle 4 Bytes).............................................................................. 90

TAS5508C

SLES257–SEPTEMBER 2010

7-31 Output Mixer Register Format (Lower 4 Bytes) .............................................................................. 90

7-32 Volume Biquad Register Format (Default = All-Pass)....................................................................... 91

7-33 Volume Gain Update Rate (Slew Rate) ....................................................................................... 92

7-34 Treble and Bass Gain Step Size (Slew Rate)................................................................................ 92

7-35 Volume Register Format ........................................................................................................ 92

7-36 Master and Individual Volume Controls ....................................................................................... 93

7-37 Channel 8 (Subwoofer).......................................................................................................... 94

7-38 Channels 6 and 5 (Right and Left Lineout in 6-Channel Configuration; Right and Left Surround in 8-Channel

Configuration)..................................................................................................................... 94

7-39 Channels 4 and 3 (Right and Left Rear) ...................................................................................... 94

7-40 Channels 7, 2, and 1 (Center, Right Front, and Left Front)................................................................. 95

7-41 Bass Filter Index Register Format ............................................................................................. 95

7-42 Bass Filter Indexes............................................................................................................... 95

7-43 Channel 8 (Subwoofer).......................................................................................................... 96

7-44 Channels 6 and 5 (Right and Left Lineout in 6-Channel Configuration; Right and Left Surround in 8-Channel

Configuration)..................................................................................................................... 96

7-45 Channels 4 and 3 (Right and Left Rear) ...................................................................................... 96

7-46 Channels 7, 2, and 1 (Center, Right Front, and Left Front)................................................................. 96

7-47 Treble Filter Index Register Format............................................................................................ 97

7-48 Treble Filter Indexes............................................................................................................. 97

7-49 AM Mode Register Format ...................................................................................................... 97

7-50 AM Tuned Frequency Register in BCD Mode (Lower 2 Bytes of 0xDE).................................................. 98

7-51 AM Tuned Frequency Register in Binary Mode (Lower 2 Bytes of 0xDE)................................................ 98

7-52 PSVC Range Register Format ................................................................................................. 99

7-53 General Control Register Format .............................................................................................. 99

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TAS5508C

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8-Channel Digital Audio PWM Processor

Check for Samples: TAS5508C

1 Introduction PWM

1.1 Features

1234

• General Features

– Automated Operation With an Easy-to-Use

Control Interface – I2C Serial-Control Slave Interface – Integrated AM Interference-Avoidance

Circuitry – Single, 3.3-V Power Supply – 64-Pin TQFP Package – 5-V Tolerant Inputs

• Audio Input/Output – Automatic Master Clock Rate and Data

Sample Rate Detection – Eight Serial Audio Input Channels – Eight PWM Audio Output Channels

Configurable as Six Channels With Stereo

Lineout or Eight Channels – Line Output Is a PWM Output to Drive an

External Differential-Input Operational

Amplifier – Headphone PWM Output to Drive an External

Differential Amplifier Like the TPA112 – PWM Outputs Support Single-Ended and

Bridge-Tied Loads – 32-, 38-, 44.1-, 48-, 88.2-, 96-, 176.4-, and

192-kHz Sampling Rates – Data Formats: 16-, 20-, or 24-Bit

Left-Justified, I2S, or Right-Justified Input

Data – 64-Fs Bit-Clock Rate – 128-, 192-, 256-, 384-, 512-, and 768-Fs

Master Clock Rates (Up to a Maximum of

50 MHz)

• Audio Processing – 48-Bit Processing Architecture With 76 Bits

of Precision for Most Audio Processing Features

– Volume Control Range 36 dB to –127 dB

• Master Volume Control Range of 18 dB to –100 dB

• Eight Individual Channel Volume Control Ranges of 18 dB to –127 dB

– Programmable Soft Volume and Mute

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PurePath Digital is a trademark of Texas Instruments. 3Matlab is a trademark of Math Works, Inc. 4All other trademarks are the property of their respective owners.

SLES257–SEPTEMBER 2010

Update Rates

– Four Bass and Treble Tone Controls with

±18-dB Range, Selectable Corner Frequencies, and Second-Order Slopes

• L, R, and C

• LS, RS

• LR, RR

• Sub – Configurable Loudness Compensation – Two Dynamic Range Compressors With Two

Thresholds, Two Offsets, and Three Slopes – Seven Biquads Per Channel – Full 8×8 Input Crossbar Mixer. Each

Signal-Processing Channel Input Can Be

Any Ratio of the Eight Input Channels. – 8×2 Output Mixer – Channels 1–6. Each

Output Can Be Any Ratio of Any Two

Signal-Processed Channels. – 8×3 Output Mixer – Channels 7 and 8. Each

Output Can Be Any Ratio of Any Three

Signal-Processed Channels. – Three Coefficient Sets Stored on the Device

Can Be Selected Manually or Automatically

(Based on Specific Data Rates). – DC Blocking Filters – Able to Support a Variety of Bass

Management Algorithms

• PWM Processing – 32-Bit Processing PWM Architecture With 40

Bits of Precision

– 8× Oversampling With Fifth-Order Noise

Shaping at 32 kHz–48 kHz, 4× Oversampling at 88.2 kHz and 96 kHz, and 2× Oversampling

at 176.4 kHz and 192 kHz – >102-dB Dynamic Range – THD+N < 0.1% – 20-Hz–20-kHz, Flat Noise Floor for 44.1-, 48-,

88.2-, 96-, 176.4-, and 192-kHz Data Rates

– Digital De-Emphasis for 32-, 44.1-, and

48-kHz Data Rates – Flexible Automute Logic With Programmable

Threshold and Duration for Noise-Free

TAS5508C

SLES257–SEPTEMBER 2010

Operation Support for Enhanced Dynamic Range in

– Intelligent AM Interference-Avoidance

High-Performance Applications

System Provides Clear AM Reception – Adjustable Modulation Limit

– Power-Supply Volume Control (PSVC)

1.2 Overview

The TAS5508C is an 8-channel digital pulse-width modulator (PWM) that provides both advanced performance and a high level of system integration. The TAS5508C is designed to interface seamlessly with most audio digital signal processors. The TAS5508C automatically adjusts control configurations in response to clock and data rate changes and idle conditions. This enables the TAS5508C to provide an easy-to-use control interface with relaxed timing requirements.

The TAS5508C can drive eight channels of H-bridge power stages. Texas Instruments H-bridge parts TAS5111, TAS5112, or TAS5182 with FETs are designed to work seamlessly with the TAS5508C. The TAS5508C supports both single-ended or bridge-tied load configurations. The TAS5508C also provides a high-performance, differential output to drive an external, differential-input, analog headphone amplifier (such as the TPA112).

The TAS5508C uses AD modulation operating at a 384-kHz switching rate for 48-, 96-, and 192-kHz data. The 8× oversampling combined with the fifth-order noise shaper provides a broad, flat noise floor and excellent dynamic range from 20 Hz to 20 kHz.

The TAS5508C is a clocked slave-only device. The TAS5508C receives MCLK, SCLK, and LRCLK from other system components. The TAS5508C accepts master clock rates of 128, 192, 256, 384, 512, and 768 Fs. The TAS5508C accepts a 64-Fs bit clock.

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The TAS5508C allows for extending the dynamic range by providing a power-supply volume control (PSVC) output signal.

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PWM_HPP and MR

PWM_HPP and ML

MCLK

XTL_OUT

XTL_IN

PLL_FLTM

PLL_FLTP

OSC CAP

SCLK

LRCLK

SDIN1

SDIN2

SDIN3

SDIN4

SDA

SCL

RESET

PDN

MUTE

HP_SEL

BKND_ERR

PWM Section

PWM AP and AM7 Center

PWM AP and AM4 R Rear

PWM AP and AM3 L Rear

PWM AP and AM8

Subwoofer

PWM AP and AM1 L Front

PWM AP and AM2 R Front

Power Supply

PWM AP and AM5 L Surround

PWM L Lineout

PWM AP and AM6 R Surround

PWM R Lineout

Digital Audio Processor

VALID

Device

Control

4 2

Det

PSVC

Volume

Control

Clock, PLL, and Serial Data I/F

Serial

Control

I/F

VR_PLL

AVDD_PLL

AVSS_PLL

AVDD_REF

VBGAP

VRA_PLL

VRD_PLL

DVDD

DVSS

AVDD

System Control

DAP Control PWM Control

8 × 8 Crossbar Mixer

Biquads

Block

Emph

SRC NS PWM

Det

Biquads

DRC

Loud

Comp

Soft

Tone

Block

Emph

SRC NS PWM

8 × 2 Crossbar Mixer

Det

Biquads

DRC

Loud

Comp

Soft

Tone

Block

Emph

SRC NS PWM

Det

Biquads

DRC

Loud

Comp

Soft

Tone

Block

Emph

SRC NS PWM

Det

Biquads

DRC

Loud

Comp

Soft

Tone

Block

Emph

SRC NS PWM

Det

Biquads

DRC

Loud

Comp

Soft

Tone

Block

Emph

SRC NS PWM

Det

Biquads

DRC

Loud

Comp

Soft

Tone

Block

Emph

SRC NS PWM

Det

Biquads

DRC

Loud

Comp

Soft

Tone

Block

Emph

Interpolate SRC NS PWM

Soft

Tone

DRC

Loud

Comp

Output Control

Interpolate

B0011-01

AVSS

Soft

Vol

Soft

Vol

Soft

Vol

Soft

Vol

Soft

Vol

Soft

Vol

Soft

Vol

Soft

Vol

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Figure 1-1. TAS5508C Functional Structure

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T AS5508C

DVDLoader

PowerSupply

T exasInstruments

DigitalAudioAmplifier

MPEGDecoder

Front-PanelControls

T uner

TAS5508C

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1.3 TAS5508C System Diagrams

Typical applications for the TAS5508C are 6- to 8-channel audio systems such as DVD or AV receivers.

Figure 1-2 shows the basic system diagram of the DVD receiver.

Figure 1-2. Typical TAS5508C Application (DVD Receiver)

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Figure 1-3 shows the recommended channel configuration when using the TAS5508C with the TAS5121

power stage. Note that each channel is normally dedicated to a particular function.

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TAS5508C

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Figure 1-3. Recommended TAS5508C and TAS5121 Channel Configuraton

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TAS5508C

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VR_PWM PWM_P_4 PWM_M_4 PWM_P_3 PWM_M_3 PWM_P_2 PWM_M_2 PWM_P_1 PWM_M_1 VALID DVSS BKND_ERR DVDD DVSS DVSS VR_DIG

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

VRA_PLL

PLL_FLT_RET

PLL_FLTM

PLL_FLTP

AVSS AVSS

VRD_PLL

AVSS_PLL

AVDD_PLL

VBGAP

RESET

HP_SEL

PDN MUTE DVDD

DVSS

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

PAG PACKAGE

(TOP VIEW)

VR_DPLL

OSC_CAP

XTL_OUT

XTL_IN

RESERVED

SDA

SCL

LRCLK

SCLK

SDIN4

SDIN3

SDIN2

SDIN1

PSVC

RESEVED

MCLK

PWM_HPPR

PWM_HPMR

PWM_HPPL

PWM_HPML

PWM_P_6

PWM_M_6

PWM_P_5

PWM_M_5

DVDD_PWM

DVSS_PWM

PWM_P_8

PWM_M_8

PWM_P_7

PWM_M_7

P0010-01

TAS5508C

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2 Description

2.1 Physical Characteristics

2.1.1 Terminal Assignments

SLES257–SEPTEMBER 2010

2.1.2 Ordering Information

0°C to 70°C TAS5508CPAG

PLASTIC 64-PIN PQFP (PN)

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2.1.3 PIN Descriptions

NAME NO.

AVDD_PLL 9 P 3.3-V analog power supply for PLL. This terminal can be connected to the same

AVSS 5, 6 P Analog ground AVSS_PLL 8 P Analog ground for PLL. This terminal should reference the same ground as

BKND_ERR 37 DI Pullup Active-low. A back-end error sequence is generated by applying logic low to this

DVDD 15, 36 P 3.3-V digital power supply DVDD_PWM 54 P 3.3-V digital power supply for PWM DVSS 16, 34, P Digital ground

35, 38 DVSS_PWM 53 P Digital ground for PWM HP_SEL 12 DI 5 V Pullup Headphone in/out selector. When a logic low is applied, the headphone is

LRCLK 26 DI 5 V Serial-audio data left/right clock (sampling-rate clock) MCLK 63 DI 5 V Pulldown MCLK is a 3.3-V master clock input. The input frequency of this clock can range

MUTE 14 DI 5 V Pullup Soft mute of outputs, active-low (muted signal = a logic low, normal operation =

OSC_CAP 18 AO Oscillator capacitor PDN 13 DI 5 V Pullup Power down, active-low. PDN powers down all logic and stops all clocks

PLL_FLT_RET 2 AO PLL external filter return PLL_FLTM 3 AO PLL negative input. Connected to PLL_FLT_RTN via an RC network PLL_FLTP 4 AI PLL positive input. Connected to PLL_FLT_RTN via an RC network PSVC 32 O Power-supply volume control PWM output PWM_HPML 59 DO PWM left-channel headphone (differential –) PWM_HPMR 61 DO PWM right-channel headphone (differential –) PWM_HPPL 60 DO PWM left-channel headphone (differential +) PWM_HPPR 62 DO PWM right-channel headphone (differential +) PWM_M_1 40 DO PWM 1 output (differential –) PWM_M_2 42 DO PWM 2 output (differential –) PWM_M_3 44 DO PWM 3 output (differential –) PWM_M_4 46 DO PWM 4 output (differential –) PWM_M_5 55 DO PWM 5 output (differential –) PWM_M_6 57 DO PWM 6 output (differential –) PWM_M_7 49 DO PWM 7 (lineout L) output (differential –) PWM_M_8 51 DO PWM 8 (lineout R) output (differential –) PWM_P_1 41 DO PWM 1 output (differential +) PWM_P_2 43 DO PWM 2 output (differential +) PWM_P_3 45 DO PWM 3 output (differential +) PWM_P_4 47 DO PWM 4 output (differential +)

TYPE

(1)

5-V

TOLERANT

TERMINATION

(2)

power source used to drive power terminal DVDD, but to achieve low PLL jitter, this terminal should be bypassed to AVSS_PLL with a 0.1-mF low-ESR capacitor.

terminal DVSS, but to achieve low PLL jitter, ground noise at this terminal must be minimized. The availability of the AVSS terminal allows a designer to use optimizing techniques such as star ground connections, separate ground planes, or other quiet ground-distribution techniques to achieve a quiet ground reference at this terminal.

terminal. The BKND_ERR results in no change to any system parameters, with all H-bridge drive signals going to a hard-mute (M) state.

selected (speakers are off). When a logic high is applied, speakers are selected (headphone is off).

from 4 MHz to 50 MHz.

a logic high). The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp to previous volume.

whenever a logic low is applied. The internal parameters are preserved through a power-down cycle, as long as RESET is not active. The duration for system recovery from power down is 100 ms.

DESCRIPTION

(1) Type: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output (2) All pullups are 200-mA weak pullups and all pulldowns are 200-mA weak pulldowns. The pullups and pulldowns are included to ensure

proper input logic levels if the terminals are left unconnected (pullups => logic-1 input; pulldowns => logic-0 input). Devices that drive inputs with pullups must be able to sink 200 mA, while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be able to source 200 mA, while maintaining a logic-1 drive level.

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NAME NO.

PWM_P_5 56 DO PWM 5 output (differential +) PWM_P_6 58 DO PWM 6 output (differential +) PWM_P_7 50 DO PWM 7 (lineout L) output (differential +) PWM_P_8 52 DO PWM 8 (lineout R) output (differential +) RESERVED 21, 22, Connect to digital ground

23, 64 RESET 11 DI 5 V Pullup System reset input, active-low. A system reset is generated by applying a logic

SCL 25 DI 5 V SCLK 27 DI 5 V Serial-audio data clock (shift clock) input

SDA 24 DIO 5 V SDIN1 31 DI 5 V Pulldown Serial-audio data input 1 is one of the serial-data input ports. SDIN1 supports

SDIN2 30 DI 5 V Pulldown Serial-audio data input 2 is one of the serial-data input ports. SDIN2 supports

SDIN3 29 DI 5 V Pulldown Serial-audio data input 3 is one of the serial-data input ports. SDIN3 supports

SDIN4 28 DI 5 V Pulldown Serial-audio data input 4 is one of the serial-data input ports. SDIN4 supports

VALID 39 DO Output indicating validity of PWM outputs, active-high VBGAP 10 P Band-gap voltage reference. A pinout of the internally regulated 1.2-V reference.

VR_DIG 33 P Voltage reference for 1.8-V digital core supply. A pinout of the internally

VR_DPLL 17 P Voltage reference for 1.8-V digital PLL supply. A pinout of the internally

VR_PWM 48 P Voltage reference for 1.8-V digital PWM core supply. A pinout of the internally

VRA_PLL 1 P Voltage reference for 1.8-V PLL analog supply. A pinout of the internally

VRD_PLL 7 P Voltage reference for 1.8-V PLL digital supply. A pinout of the internally

XTL_IN 20 AI XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They

XTL_OUT 19 AO XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They

TYPE

(1)

5-V

TOLERANT

TERMINATION

(2)

low to this terminal. RESET is an asynchronous control signal that restores the TAS5508C to its default conditions, sets the valid output low, and places the PWM in the hard mute (M) state. Master volume is immediately set to full attenuation. On the release of RESET, if PDN is high, the system performs a 4to 5-ms device initialization and sets the volume at mute.

I2C serial-control clock input/output

I2C serial-control data-interface input/output

four discrete (stereo) data formats and is capable of inputting data at 64 Fs.

Typically has a 1-nF low-ESR capacitor between VBGAP and AVSS_PLL. This terminal must not be used to power external devices.

regulated 1.8-V power used by digital core logic. A 4.7-mF low-ESR capacitor should be connected between this terminal and DVSS. This terminal must not be used to power external devices.

regulated 1.8-V power used by digital PLL logic. A 0.1-mF low-ESR capacitor should be connected between this terminal and DVSS_CORE. This terminal must not be used to power external devices.

regulated 1.8-V power used by digital PWM core logic. A 0.1-mF low-ESR

(3)

capacitor terminal must not be used to power external devices.

regulated 1.8-V power used by PLL logic. A 0.1-mF low-ESR capacitor be connected between this terminal and AVSS_PLL. This terminal must not be used to power external devices.

provide a reference clock for the TAS5508C via use of an external fundamental-mode crystal. XTL_IN is the 1.8-V input port for the oscillator circuit. A 13.5-MHz crystal (HCM49) is recommended.

provide a reference clock for the TAS5508C via use of an external fundamental-mode crystal. XTL_OUT is the 1.8-V output drive to the crystal. A

13.5-MHz crystal (HCM49) is recommended.

should be connected between this terminal and DVSS_PWM. This

DESCRIPTION

SLES257–SEPTEMBER 2010

(3)

should

(3)

should

(3) If desired, low-ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling

capacitors of equal value provides an extended high-frequency supply decoupling. This approach avoids the potential of producing parallel resonance circuits that have been observed when paralleling capacitors of different values.

(3)

2.2 TAS5508C Functional Description

Figure 2-1 shows the TAS5508C functional structure. The following sections describe the TAS5508C

functional blocks:

• Power supply

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TAS5508C

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• Clock, PLL, and serial data interface

• I2C serial-control interface

• Device control

• Digital audio processor (DAP)

2.2.1 Power Supply

The power-supply section contains supply regulators that provide analog and digital regulated power for various sections of the TAS5508C. The analog supply supports the analog PLL, whereas digital supplies support the digital PLL, the digital audio processor (DAP), the pulse-width modulator (PWM), and the output control (reclocker). The regulators can also be turned off when terminals RESET and PDN are both low.

2.2.2 Clock, PLL, and Serial Data Interface

The TAS5508C is a clocked slave-only device that requires the use of an external 13.5-MHz crystal. It accepts MCLK, SCLK, and LRCLK as inputs only.

The TAS5508C uses the external crystal to provide a time base for:

• Continuous data and clock error detection and management

• Automatic data-rate detection and configuration

• Automatic MCLK-rate detection and configuration (automatic bank switching)

• Supporting I2C operation/communication while MCLK is absent The TAS5508C automatically handles clock errors, data-rate changes, and master-clock frequency

changes without requiring intervention from an external system controller. This feature significantly reduces system complexity and design.

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2.2.2.1 Serial Audio Interface

The TAS5508C operates as a slave-only/receive-only serial data interface in all modes. The TAS5508C has four PCM serial data interfaces to permit eight channels of digital data to be received though the SDIN1, SDIN2, SDIN3, and SDIN4 inputs. The serial audio data is in MSB-first, 2s-complement format.

The serial data input interface of the TAS5508C can be configured in right-justified, I2S, or left-justified modes. The serial data interface format is specified using the I2C data-interface control register. The supported formats and word lengths are shown in Table 2-1.

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RECEIVE SERIAL DATA FORMAT WORD LENGTH

Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5508C accepts 16-, 20-, or 24-bit serial data at 32, 38, 44.1, 48, 88.2, 96, 176.4, or 192 kHz in left-justified, I2S, or right-justified format. Data is input using a 64-Fs SCLK clock and an MCLK rate of 128, 192, 256, 384, 512, or 768 Fs, up to a maximum of 50 MHz. The clock speed and serial data format are I2C configurable.

2.2.3 I2C Serial-Control Interface

The TAS5508C has an I2C serial-control slave interface (address 0x36) to receive commands from a system controller. The serial-control interface supports both normal-speed (100 kHz) and high-speed (400 kHz) operations without wait states. Because the TAS5508C has a crystal time base, this interface operates even when MCLK is absent.

SLES257–SEPTEMBER 2010

Table 2-1. Serial Data Formats

Right-justified 16 Right-justified 20 Right-justified 24

I2S 16 I2S 20

I2S 24 Left-justified 16 Left-justified 20 Left-justified 24

The serial control interface supports both single-byte and multiple-byte read/write operations for status registers and the general control registers associated with the PWM. However, for the DAP data-processing registers, the serial control interface also supports multiple-byte (4-byte) write operations.

The I2C supports a special mode which permits I2C write operations to be broken up into multiple data-write operations that are multiples of 4 data bytes. These are 6-byte, 10-byte, 14-byte, 18-byte, etc., write operations that are composed of a device address, read/write bit, subaddress, and any multiple of 4 bytes of data. This permits the system to incrementally write large register values without blocking other I2C transactions. In order to use this feature, the first block of data is written to the target I2C address, and each subsequent block of data is written to a special append register (0xFE) until all the data is written and a stop bit is sent. An incremental read operation is not supported.

2.2.4 Device Control

The TAS5508C control section provides the control and sequencing for the TAS5508C. The device control provides both high- and low-level control for the serial control interface, clock and serial data interfaces, digital audio processor, and pulse-width modulator sections.

2.2.5 Digital Audio Processor (DAP)

The DAP arithmetic unit is used to implement all audio-processing functions: soft volume, loudness compensation, bass and treble processing, dynamic range control, channel filtering, input and output mixing. Figure 2-3 shows the TAS5508C DAP architecture.

The DAP accepts 24-bit data from the serial data interface and outputs 32-bit data to the PWM section. The DAP supports two configurations, one for 32-kHz to 96-kHz data and one for 176.4-kHz to 192-kHz data.

2.2.5.1 TAS5508C Audio-Processing Configurations

The 32-kHz to 96-kHz configuration supports eight channels of data processing that can be configured either as eight channels, or as six channels with two channels for separate stereo line outputs.

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The 176.4-kHz to 192-kHz configuration supports three channels of signal processing with five channels passed though (or derived from the three processed channels).

To support efficiently the processing requirements of both multichannel 32-kHz to 96-kHz data and the 2-channel 176.4-kHz and 192-kHz data, the TAS5508C has separate audio-processing features for 32-kHz to 96-kHz data rates and for 176.4 kHz and 192 kHz. See Table 2-2 for a summary of TAS5508C processing feature sets.

2.2.5.2 TAS5508C Audio Signal-Processing Functions

The DAP provides 10 primary signal-processing functions:

1. The data-processing input has a full 8×8 input crossbar mixer. This enables each input to be any ratio of the eight input channels.

2. Two I2C programmable threshold detectors in each channel support automute.

3. Seven biquads per channel

4. Four soft bass and treble tone controls with ±18-dB range, programmable corner frequencies, and second-order slopes. In 8-channel mode, bass and treble controls are normally configured as follows:

– Bass and treble 1: Channel 1 (left), channel 2 (right), and channel 7 (center) – Bass and treble 2: Channel 3 (left surround) and channel 4 (right surround) – Bass and treble 3: Channel 5 (left back surround) and channel 6 (right back surround) – Bass and treble 4: Channel 8 (subwoofer)

5. Individual channel and master volume controls. Each control provides an adjustment range of 18 dB to –127 dB. This permits a total volume device control range of 36 dB to –127 dB plus mute. The master volume control can be configured to control six or eight channels. The DAP soft volume and mute update interval is I2C programmable. The update is performed at a fixed rate regardless of the sample rate.

6. Programmable loudness compensation that is controlled via the combination of the master and individual volume settings.

7. Two dual-threshold dual-rate dynamic range compressors (DRCs). The volume gain values provided are used as input parameters using the maximum RMS (master volume × individual channel volume).

8. 8×2 output mixer (channels 1–6). Each output can be any ratio of any two signal-processed channels.

9. 8×3 output mixer (channels 7 and 8). Each output can be any ratio of any three signal-processed channels.

10. The DAP maintains three sets of coefficient banks that are used to maintain separate sets of sample-rate-dependent parameters for the biquad, tone controls, loudness, and DRC in RAM. These can be set to be automatically selected for one or more data sample rates or can be manually selected under I2C program control. This feature enables coefficients for different sample rates to be stored in the TAS5508C and then selected when needed.

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Table 2-2. TAS5508C Audio Processing Feature Sets

FEATURE

Signal-processing channels 8 6 + 2 3 Pass-through channels N/A 5 Master volume 1 for 8 channels 1 for 6 channels 1 for 3 channels Individual channel volume

controls

Four bass and treble tone controls Four bass and treble tone controls with ±18-dB range, programmable with ±18-dB range, programmable

Bass and treble tone order slopes order slopes controls L, R, and C (Ch1, 2, and 7) L, R, and C (Ch1, 2, and 7)

Biquads 56 21 Dynamic range DRC1 for seven satellites and DRC1 for five satellites and DRC2 DRC1 for two satellites and

compressors DRC2 for sub for sub (Ch5 and 6 uncompressed) DRC2 for sub

Input/output mapping/ mixing

DC-blocking filters (implemented in PWM Eight channels section)

Digital de-emphasis (implemented in PWM N/A section)

Loudness Eight channels Six channels Three channels Number of coefficient sets

stored

corner frequencies, and second- corner frequencies, and second-

LS, RS (Ch3 and 4) LS, RS (Ch3 and 4) LBS, RBS (Ch5 and 6) Sub (Ch8) Sub (Ch8) Line L and R (Ch5 and 6)

Each of the eight signal-processing channel inputs can be any ratio of the be any ratio of the eight input eight input channels. channels. Each of the eight outputs can be any ratio of any two processed channels. Each of the eight outputs can be

Eight channels for 32 kHz, Six channels for 32 kHz, 44.1 kHz,

44.1 kHz, and 48 kHz and 48 kHz

32 kHz–96 kHz 32 kHz–96 kHz 176.4- and 192-kHz

8-CHANNEL FEATURE SET 6 + 2 LINEOUT FEATURE SET FEATURE SET

8 3

Two bass and treble tone controls with ±18-dB range, programmable corner frequencies, and second-order slopes L and R (Ch1 and 2) Sub (Ch8)

Each of the three signalprocessing channels or the five pass-though channel inputs can

any ratio of any of the three processed channels or five bypass channels.

Three additional coefficient sets can be stored in memory.

2.3 TAS5508C DAP Architecture

2.3.1 TAS5508C DAP Architecture Diagrams

Figure 2-1 shows the TAS5508C DAP architecture for Fs = 96 kHz. Note the TAS5508C bass

management architecture shown in channels 1, 2, 7, and 8. Note that the I2C registers are shown to help the designer configure the TAS5508C.

Figure 2-2 shows the TAS5508C architecture for Fs = 176.4 kHz or Fs = 192 kHz. Note that only channels

1, 2, and 8 contain all the features. Channels 3–7 are pass-through except for master volume control.

Figure 2-3 shows TAS5508C detailed channel processing. The output mixer is 8×2 for channels 1–6 and

8×3 for channels 7 and 8.

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Coeff = 0 (lin), (I2C 0x4C)

Coeff = 1 (lin)

(I2C 0x4D)

7 DAP 1

(0x51−

0x57)

SDIN1-L (L)

(1)

SDIN1-R (R)

SDIN2-L (LS)

SDIN2-R (RS)

SDIN3-L (LBS)

SDIN3-R (RBS)

SDIN4-L (C)

SDIN4-R (LFE)

A B C D E F G H

IP Mixer 1 (I2C 0x41)

8 × 8

Crossbar

Input Mixer

Master Vol

(0xD9)

DAP 1

Volume

(0xD1)

Max Vol

Bass and

Treble 1 (0xDA−

0xDD)

Loud-

ness

(0x91−

0x95)

OP Mixer 1

(I2C 0xAA)

8 × 2 Output

Mixer

L to PWM1

DRC1

(0x96−

0x9C)

7 DAP 2

(0x58−

0x5E)

SDIN1-L (L)

SDIN1-R (R)

(1)

SDIN2-L (LS)

SDIN2-R (RS)

SDIN3-L (LBS)

SDIN3-R (RBS)

SDIN4-L (C)

SDIN4-R (LFE)

A B C D E F G H

IP Mixer 2 (I2C 0x42)

8 × 8

Crossbar

Input Mixer

Master Vol

(0xD9)

DAP 2

Volume

(0xD2)

Max Vol

Bass and

Treble 1 (0xDA−

0xDD)

Loud-

ness

(0x91−

0x95)

OP Mixer 2

(I2C 0xAB)

8 × 2 Output

Mixer

R to PWM2

DRC1

(0x96−

0x9C)

7 DAP 3

(0x5F−

0x65)

SDIN1-L (L)

SDIN1-R (R)

SDIN2-L (LS)

(1)

SDIN2-R (RS)

SDIN3-L (LBS)

SDIN3-R (RBS)

SDIN4-L (C)

SDIN4-R (LFE)

A B C D E F G H

IP Mixer 3 (I2C 0x43)

8 × 8

Crossbar

Input Mixer

Master Vol

(0xD9)

DAP 3

Volume

(0xD3)

Max Vol

Bass and

Treble 2 (0xDA−

0xDD)

Loud-

ness

(0x91−

0x95)

OP Mixer 3

(I2C 0xAC)

8 × 2 Output

Mixer

LS to PWM3

DRC1

(0x96−

0x9C)

7 DAP 4

(0x66−

0x6C)

SDIN1-L (L)

SDIN1-R (R)

SDIN2-L (LS)

SDIN2-R (RS)

(1)

SDIN3-L (LBS)

SDIN3-R (RBS)

SDIN4-L (C)

SDIN4-R (LFE)

A B C D E F G H

IP Mixer 4 (I2C 0x44)

8 × 8

Crossbar

Input Mixer

Master Vol

(0xD9)

DAP 4

Volume

(0xD4)

Max Vol

Bass and

Treble 2 (0xDA−

0xDD)

Loud-

ness

(0x91−

0x95)

OP Mixer 4

(I2C 0xAD)

8 × 2 Output

Mixer

RS to PWM4

DRC1

(0x96−

0x9C)

7 DAP 5

(0x6D−

0x73)

SDIN1-L (L)

SDIN1-R (R)

SDIN2-L (LS)

SDIN2-R (RS)

SDIN3-L (LBS)

(1)

SDIN3-R (RBS)

SDIN4-L (C)

SDIN4-R (LFE)

A B C D E F G H

IP Mixer 5 (I2C 0x45)

8 × 8

Crossbar

Input Mixer

Master Vol

(0xD9)

DAP 5

Volume

(0xD5)

Max Vol

Bass and

Treble 3 (0xDA−

0xDD)

Loud-

ness

(0x91−

0x95)

OP Mixer 5

(I2C 0xAE)

8 × 2 Output

Mixer

LBS to PWM5

DRC1

(0x96−

0x9C)

7 DAP 6

(0x74−

0x7A)

SDIN1-L (L)

SDIN1-R (R)

SDIN2-L (LS)

SDIN2-R (RS)

SDIN3-L (LBS)

SDIN3-R (RBS)

(1)

SDIN4-L (C)

SDIN4-R (LFE)

A B C D E F G H

IP Mixer 6 (I2C 0x46)

8 × 8

Crossbar

Input Mixer

Master Vol

(0xD9)

DAP 6

Volume

(0xD6)

Max Vol

Bass and

Treble 3 (0xDA−

0xDD)

Loud-

ness

(0x91−

0x95)

OP Mixer 6

(I2C 0xAF)

8 × 2 Output

Mixer

RBS to PWM6

DRC1

(0x96−

0x9C)

5 DAP 7

(0x7D−

0x81)

SDIN1-L (L)

SDIN1-R (R)

SDIN2-L (LS)

SDIN2-R (RS)

SDIN3-L (LBS)

SDIN3-R (RBS)

SDIN4-L (C)

(1)

SDIN4-R (LFE)

A B C D E F G H

IP Mixer 7 (I2C 0x47)

8 × 8

Crossbar

Input Mixer

Master Vol

(0xD9)

DAP 7

Volume

(0xD7)

Max Vol

Bass and

Treble 1 (0xDA−

0xDD)

Loud-

ness

(0x91−

0x95)

OP Mixer 7

(I2C 0xB0)

8 × 3 Output

Mixer

C to PWM7

DRC1

(0x96−

0x9C)

5 DAP 8

(0x84−

0x88)

SDIN1-L (L)

SDIN1-R (R)

SDIN2-L (LS)

SDIN2-R (RS)

SDIN3-L (LBS)

SDIN3-R (RBS)

SDIN4-L (C)

SDIN4-R (LFE)

(1)

A B C D E F G H

IP Mixer 8 (I2C 0x48)

8 × 8

Crossbar

Input Mixer

Master Vol

(0xD9)

DAP 8

Volume

(0xD8)

Max Vol

Bass and

Treble 4 (0xDA−

0xDD)

Loud-

ness

(0x91−

0x95)

OP Mixer 8

(I2C 0xB1)

8 × 3 Output

Mixer

Sub to PWM8

DRC2

(0x9D−

0xA1)

2 DAP 8

(0x82−

0x83)

B0014-01

Coeff = 0 (lin), (I2C 0x4F)

Coeff = 1 (lin)

(I2C 0x50)

Coeff = 0 (lin), (I2C 0x49)

Coeff = 0 (lin) (I2C 0x4A)

2 DAP 7

(0x7B−

0x7C)

Coeff = 0 (lin), (I2C 0x4B)

Coeff = 0 (lin), (I2C 0x4E)

TAS5508C

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(1) Default inputs

Figure 2-1. TAS5508C DAP Architecture With I2C Registers (Fs ≤ 96 kHz)

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B0015-03

SDIN1-L (L)

(1)

SDIN1-L (L)

SDIN1-R (R)

(1)

SDIN1-R (R)

SDIN2-L (LS)

(1)

SDIN2-L (LS)

SDIN2-R (RS)

(1)

SDIN2-R (RS)

SDIN3-L (LBS)

(1)

SDIN3-L (LBS)

SDIN3-R (RBS)

(1)

SDIN3-R (RBS)

SDIN4-L (C)

(1)

SDIN4-L (C)

SDIN4-R (LFE)

(1)

Max Vol

IP Mixer 1

(I C 0x41)

8 8

Crossbar

Input Mixer

IP Mixer 2

(I C 0x42)

8 8

Crossbar

Input Mixer

IP Mixer 3

(I C 0x43)

8 8

Crossbar

Input Mixer

IP Mixer 4

(I C 0x44)

8 8

Crossbar

Input Mixer

IP Mixer 5

(I C 0x45)

8 8

Crossbar

Input Mixer

IP Mixer 6

(I C 0x46)

8 8

Crossbar

Input Mixer

IP Mixer 7

(I C 0x47)

8 8

Crossbar

Input Mixer

IP Mixer 8

(I C 0x48)

8 8

Crossbar

Input Mixer

OP Mixer 1

(I C 0xAA)

8 2

Output Mixer

OP Mixer 2

(I C 0xAB)

8 2

Output Mixer

OP Mixer 3

(I C 0xAC)

8 2

Output Mixer

OP Mixer 4

(I C 0xAD)

8 2

Output Mixer

OP Mixer 5

(I C 0xAE)

8 2

Output Mixer

OP Mixer 6

(I C 0xAF)

8 2

Output Mixer

OP Mixer 7

(I C 0xB0)

8 3

Output Mixer

OP Mixer 8

(I C 0xB1)

8 3

Output Mixer

Master Vol

(0xD9)

Master Vol

(0xD9)

Master Vol

(0xD9)

Master Vol

(0xD9)

Master Vol

(0xD9)

Master Vol

(0xD9)

Master Vol

(0xD9)

Master Vol

(0xD9)

4BQ

(0x51–

0x54)

4BQ

(0x58–

0x5B)

3BQ

(0x5F–

0x61)

3BQ

(0x66–

0x68)

3BQ

(0x7B–

0x7D)

4BQ

(0x82–

0x85)

Loud-

ness

(0x91–

0x95)

Loud-

ness

(0x91–

0x95)

Loud-

ness

(0x91–

0x95)

DRC1

(0x96–

0x9C)

DRC1

(0x96–

0x9C)

DRC1

(0x96–

0x9C)

DRC1

(0x96–

0x9C)

DRC2

(0x9D–

0xA1)

DRC1

(0x96–

0x9C)

DAP 1

Volume

(0xD1)

DAP 2

Volume

(0xD2)

DAP 3

Volume

(0xD3)

DAP 4

Volume

(0xD4)

DAP 5

Volume

(0xD5)

DAP 6

Volume

(0xD6)

DAP 7

Volume

(0xD7)

DAP 8

Volume

(0xD8)

L to PWM1

R to PWM2

LS to PWM3

RS to PWM4

LBS to PWM5

RBS to PWM6

C to PWM7

Sub to PWM8

Bass Treble 1

(0xDA–

0xDD)

and

Bass Treble 1

(0xDA–

0xDD)

and

Bass Treble 4

(0xDA–

0xDD)

and

TAS5508C

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(1) Default inputs

Figure 2-2. TAS5508C Architecture With I2C Registers (Fs = 176.4 kHz or Fs = 192 kHz)

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Biquads

Series

Bass

and

Treble

Loudness

DRC

Input Mixer

1 Other Channel Output From 7 Available

32-Bit Trunc

PWM

Proc

A_to_ipmix

B_to_ipmix

SDIN1

C_to_ipmix

D_to_ipmix

SDIN2

Left

Right

Channel Volume

Bass and Treble

Bypass

Bass

and

Treble

Inline

Pre-

Volume

Post-

Volume

Output

Gain

Output Mixer Sums Any Two Channels

PWM Output

C D

Left

Right

DRC

Bypass

DRC

Inline

E_to_ipmix

F_to_ipmix

SDIN3

G_to_ipmix

H_to_ipmix

SDIN4

Left

Right

G H

Left

Right

B0016-01

Master

Volume

Max

Volume

TAS5508C

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Figure 2-3. TAS5508C Detailed Channel Processing

2.3.2 I2C Coefficient Number Formats

The architecture of the TAS5508C is contained in ROM resources within the TAS5508C and cannot be altered. However, mixer gain, level offset, and filter tap coefficients, which can be entered via the I2C bus interface, provide a user with the flexibility to set the TAS5508C to a configuration that achieves system-level goals.

The firmware is executed in a 48-bit, signed, fixed-point arithmetic machine. The most significant bit of the 48-bit data path is a sign bit, and the 47 lower bits are data bits. Mixer gain operations are implemented by multiplying a 48-bit, signed data value by a 28-bit, signed gain coefficient. The 76-bit, signed output product is then truncated to a signed, 48-bit number. Level offset operations are implemented by adding a 48-bit, signed offset coefficient to a 48-bit, signed data value. In most cases, if the addition results in overflowing the 48-bit, signed number format, saturation logic is used. This means that if the summation results in a positive number that is greater than 0x7FFF FFFF FFFF (the spaces are used to ease the reading of the hexadecimal number), the number is set to 0x7FFF FFFF FFFF. If the summation results in a negative number that is less than 0x80000000 0000, the number is set to 0x8000 0000 0000.

2.3.2.1 28-Bit 5.23 Number Format

All mixer gain coefficients are 28-bit coefficients using a 5.23 number format. Numbers formatted as 5.23 numbers have 5 bits to the left of the binary point and 23 bits to the right of the binary point. This is shown in Figure 2-4.

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−23

Bit

S_xxxx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx

2−4 Bit

2−1 Bit

20 Bit

Sign Bit

23 Bit

M0007-01

(1 or 0) y 23 + (1 or 0) y 22 + … + (1 or 0) y 20 + (1 or 0) y 2−1 + … + (1 or 0) y 2−4 + … + (1 or 0) y 2

−23

23 Bit 22 Bit 20 Bit 2−1 Bit 2−4 Bit 2

−23

Bit

M0008-01

Coefficient

Digit 8

u u S x x x

Coefficient

Digit 7

x x x

Coefficient

Digit 6

x x x

Coefficient

Digit 5

x x x

Coefficient

Digit 4

x x x

Coefficient

Digit 3

x x x

Coefficient

Digit 2

x x x

Coefficient

Digit 1

Fraction

Digit 5

Sign

Bit

Fraction

Digit 6

Fraction

Digit 4

Fraction

Digit 3

Fraction

Digit 2

Fraction

Digit 1

Integer

Digit 1

u = unused or don’t care bits Digit = hexadecimal digit

M0009-01

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The decimal value of a 5.23 format number can be found by following the weighting shown in Figure 2-5. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number. In this case, every bit must be inverted, a 1 added to the result, and then the weighting shown in Figure 2-5 applied to obtain the magnitude of the negative number.

SLES257–SEPTEMBER 2010

Figure 2-4. 5.23 Format

Figure 2-5. Conversion Weighting Factors—5.23 Format to Floating Point

Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit number (4-byte or 8-digit hexadecimal number) is shown in Figure 2-6.

Figure 2-6. Alignment of 5.23 Coefficient in 32-Bit I2C Word

As Figure 2-6 shows, the hexadecimal (hex) value of the integer part of the gain coefficient cannot be

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−23

Bit

S_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx

20 Bit

216 Bit

222 Bit

Sign Bit

223 Bit

2−1 Bit

−10

Bit

M0007-02

(1 or 0) y 223 + (1 or 0) y 222 + … + (1 or 0) y 20 + (1 or 0) y 2−1 + … + (1 or 0) y 2

−23

223 Bit 222 Bit 20 Bit 2−1 Bit 2

−23

Bit

M0008-02

TAS5508C

SLES257–SEPTEMBER 2010

concatenated with the hex value of the fractional part of the gain coefficient to form the 32-bit I2C coefficient. The reason is that the 28-bit coefficient contains 5 bits of integer, and thus the integer part of the coefficient occupies all of one hex digit and the most significant bit of the second hex digit. In the same way, the fractional part occupies the lower three bits of the second hex digit, and then occupies the other five hex digits (with the eighth digit being the zero-valued most significant hex digit).

2.3.2.2 48-Bit 25.23 Number Format

All level adjustment and threshold coefficients are 48-bit coefficients using a 25.23 number format. Numbers formatted as 25.23 numbers have 25 bits to the left of the decimal point and 23 bits to the right of the decimal point. This is shown in Figure 2-7.

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Figure 2-7. 25.23 Format

Figure 2-8 shows the derivation of the decimal value of a 48-bit 25.23 format number.

Figure 2-8. Alignment of 5.23 Coefficient in 32-Bit I2C Word

Two 32-bit words must be sent over the I2C bus to download a level or threshold coefficient into the TAS5508C. The alignment of the 48-bit, 25.23 formatted coefficient in the 8-byte (two 32-bit words) I2C word is shown in Figure 2-9.

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Coefficient

Digit 16

u u u u u u

Coefficient

Digit 15

u u u

Coefficient

Digit 14

u u u

Coefficient

Digit 13

x x x

Coefficient

Digit 12

x x x

Coefficient

Digit 11

x x x

Coefficient

Digit 10

x x x

Coefficient

Digit 9

Word 1 (MostSignificant Word)

Integer

Digit 3

Integer

Digit 4

(Bits 211 − 29)

Integer

Digit 2

Integer

Digit 1

Sign

Bit

Coefficient

Digit 8

x x x x x x

Coefficient

Digit 7

x x x

Coefficient

Digit 6

x x x

Coefficient

Digit 5

x x x

Coefficient

Digit 4

x x x

Coefficient

Digit 3

x x x

Coefficient

Digit 2

x x x

Coefficient

Digit 1

Word 2 (LeastSignificant Word)

Fraction

Digit 5

Integer

Digit 4

(Bit 28)

Fraction

Digit 6

Fraction

Digit 4

Fraction

Digit 3

Fraction

Digit 2

Fraction

Digit 1

Integer

Digit 6

Integer

Digit 5

u = unused or don’t care bits Digit = hexadecimal digit

M0009-02

TAS5508C

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2.3.2.3 TAS5508C Audio Processing

Figure 2-9. Alignment of 25.23 Coefficient in Two 32-Bit I2C Words

The TAS5508C digital audio processing is designed so that noise produced by filter operations is maintained below the smallest signal amplitude of interest, as shown in Figure 2-10. The TAS5508C achieves this low noise level by increasing the precision of the signal representation substantially above the number of bits that are absolutely necessary to represent the input signal.

Similarly, the TAS5508C carries additional precision in the form of overflow bits to permit the value of intermediate calculations to exceed the input precision without clipping. The TAS5508C advanced digital audio processor achieves both of these important performance capabilities by using a high-performance digital audio processing architecture with a 48-bit data path, 28-bit filter coefficients, and a 76-bit accumulator.

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Noise Floor With No Additional Precision

Maximum Signal Amplitude

Ideal Input Possible Outputs Desired Output

Filter Operation

Signal

Bits

Input

Overflow

Reduced

SNR

Signal

Output

Noise Floor as a Result of Additional Precision

Signal

Bits

Output

Values Retained by Overflow Bits

M0010-01

Gain Coefficient

SDIN1-L

Gain Coefficient

SUM

Gain Coefficient

M0011-01

SDIN1-R

SDIN4-R

TAS5508C

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2.4 Input Crossbar Mixer

The TAS5508C has a full 8×8 input crossbar mixer. This mixer permits each signal processing channel input to be any ratio of any of the eight input channels, as shown in Figure 2-11. The control parameters for the input crossbar mixer are programmable via the I2C interface. See the Input Mixer Registers (0x41–0x48, Channels 1–8), Section 7.16, for more information.

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Figure 2-10. TAS5508C Digital Audio Processing

2.5 Biquad Filters

For 32-kHz to 96-kHz data, the TAS5508C provides 56 biquads across the eight channels (seven per channel).

For 176.4-kHz and 192-kHz data, the TAS5508C has 21 biquads across the three channels (seven per channel). All of the biquad filters are second-order direct form I structure.

Figure 2-11. Input Crossbar Mixer

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48 76 48

48 76

76 48

M0012-01

–1

Magnitude Truncation

–1

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The direct form I structure provides a separate delay element and mixer (gain coefficient) for each node in the biquad filter. Each mixer output is a signed 76-bit product of a signed 48-bit data sample (25.23 format number) and a signed 28-bit coefficient (5.23 format number), as shown in Figure 2-12. The 76-bit ALU in the TAS5508C allows the 76-bit resolution to be retained when summing the mixer outputs (filter products).

The five 28-bit coefficients for the each of the 56 biquads are programmable via the I2C interface. See

Table 2-3.

SLES257–SEPTEMBER 2010

Figure 2-12. Biquad Filter Structure

All five coefficients for one biquad filter structure are written to one I2C register containing 20 bytes (or five 32-bit words). The structure is the same for all biquads in the TAS5508C. Registers 0x51–0x88 show all the biquads in the TAS5508C. Note that u[31:28] bits are unused and default to 0x0.

Table 2-3. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass)

DESCRIPTION REGISTER FIELD CONTENTS

b0coefficient u[31:28], b0[27:24], b0[23:16], b0[15:8], b0[7:0] 1.0 0x00, 0x80, 0x00, 0x00 b1coefficient u[31:28], b1[27:24], b1[23:16], b1[15:8], b1[7:0] 0.0 0x00, 0x00, 0x00, 0x00 b2coefficient u[31:28], b2[27:24], b2[23:16], b2[15:8], b2[7:0] 0.0 0x00, 0x00, 0x00, 0x00 a1coefficient u[31:28], a1[27:24], a1[23:16], a1[15:8], a1[7:0] 0.0 0x00, 0x00, 0x00, 0x00 a2coefficient u[31:28], a2[27:24], a2[23:16], a2[15:8], a2[7:0] 0.0 0x00, 0x00, 0x00, 0x00

2.6 Bass and Treble Controls

From 32-kHz to 96-kHz data, the TAS5508C has four bass and treble tone controls. Each control has a ±18-dB control range with selectable corner frequencies and second-order slopes. These controls operate four channel groups:

• L, R, and C (channels 1, 2, and 7)

• LS, RS (channels 3 and 4)

• LBS, RBS (alternatively called L and R lineout) (channels 5 and 6)

• Sub (channel 8) For 176.4-kHz and 192-kHz data, the TAS5508C has two bass and treble tone controls. Each control has

a ±18-dB I2C control range with selectable corner frequencies and second-order slopes. These controls operate two channel groups:

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INITIALIZATION GAIN COEFFICIENT VALUE

DECIMAL HEX

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• L and R

• Sub The bass and treble filters use a soft update rate that does not produce artifacts during adjustment.

Table 2-4. Bass and Treble Filter Selections

(kHz)

32 42 917 83 1833 125 3000 146 3667 167 4333 38 49 1088 99 2177 148 3562 173 4354 198 5146

44.1 57 1263 115 2527 172 4134 201 5053 230 5972 48 63 1375 125 2750 188 4500 219 5500 250 6500

88.2 115 2527 230 5053 345 8269 402 10106 459 11944 96 125 2750 250 5500 375 9000 438 11000 500 13000

176.4 230 5053 459 10106 689 16538 804 20213 919 23888 192 250 5500 500 11000 750 18000 875 22000 1000 26000

FILTER SET 1 FILTER SET 2 FILTER SET 3 FILTER SET 4 FILTER SET 5

BASS TREBLE BASS TREBLE BASS TREBLE BASS TREBLE BASS TREBLE

3-dB CORNER FREQUENCIES

The I2C registers that control bass and treble are:

• Bass and treble bypass register (0x89–0x90, channels 1–8)

• Bass and treble slew rates (0xD0)

• Bass filter sets 1–5 (0xDA)

• Bass filter index (0xDB)

• Treble filter sets 1–5 (0xDC)

• Treble filter index (0xDD)

2.7 Volume, Automute, and Mute

The TAS5508C provides individual channel and master volume controls. Each control provides an adjustment range of 18 dB to –100 dB in 0.25-dB increments. This permits a total volume device control range of 36 dB to –100 dB plus mute. The master volume control can be configured to control six or eight channels.

The TAS5508C has a master soft mute control that can be enabled by a terminal or I2C command. The device also has individual channel soft mute controls that are enabled via I2C.

The soft volume and mute update rates are programmable. The soft adjustments are performed using a soft-gain linear update with an I2C-programmable linear step size at a fixed temporal rate. The linear soft-gain step size can be varied from 0.5 to 0.003906. Table 2-5 lists the linear gain step sizes.

Table 2-5. Linear Gain Step Size

STEP SIZE (GAIN) 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.007813 0.003906

Time to go from 36.124 db to –127 dB in ms 10.67 21.33 42.67 85.34 170.67 340.35 682.70 1365.4 Time to go from 18.062 db to –127 dB in ms 1.33 2.67 5.33 10.67 21.33 42.67 85.33 170.67 Time to go from 0 db to –127 dB in ms 0.17 0.33 0.67 1.33 2.67 5.33 10.67 21.33

2.8 Automute and Mute

The TAS5508C has individual channel automute controls that are enabled via the I2C interface. Two separate detectors can trigger the automute:

• Input automute: All channels are muted when all 8 inputs to the TAS5508C are less in magnitude than the input threshold value for a programmable amount of time.

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+ 77 hidden pages

Texas instruments TAS5508C Data Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction PWM

1.1 Features

1.2 Overview

1.3 TAS5508C System Diagrams

2 Description

2.1 Physical Characteristics

2.1.1 Terminal Assignments

2.1.2 Ordering Information

2.1.3 PIN Descriptions

2.2 TAS5508C Functional Description

2.2.1 Power Supply

2.2.2 Clock, PLL, and Serial Data Interface

2.2.2.1 Serial Audio Interface

2.2.3 I2C Serial-Control Interface

2.2.4 Device Control

2.2.5 Digital Audio Processor (DAP)

2.2.5.1 TAS5508C Audio-Processing Configurations

2.2.5.2 TAS5508C Audio Signal-Processing Functions

2.3 TAS5508C DAP Architecture

2.3.1 TAS5508C DAP Architecture Diagrams

2.3.2 I2C Coefficient Number Formats

2.3.2.1 28-Bit 5.23 Number Format

2.3.2.2 48-Bit 25.23 Number Format

2.3.2.3 TAS5508C Audio Processing

2.4 Input Crossbar Mixer

2.5 Biquad Filters

2.6 Bass and Treble Controls

2.7 Volume, Automute, and Mute

2.8 Automute and Mute