PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
192-kHz Sampling Rates
– Data Formats: 16-, 20-, or 24-Bit
Left-Justified, I2S, or Right-Justified Input
Data
– 64-Fs Bit-Clock Rate
– 128-, 192-, 256-, 384-, 512-, and 768-Fs
Master Clock Rates (Up to a Maximum of
50 MHz)
• Audio Processing
– 48-Bit Processing Architecture With 76 Bits
of Precision for Most Audio Processing
Features
– Volume Control Range 36 dB to –127 dB
•Master Volume Control Range of 18 dB to
–100 dB
•Eight Individual Channel Volume Control
Ranges of 18 dB to –127 dB
– Programmable Soft Volume and Mute
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PurePath Digital is a trademark of Texas Instruments.
3Matlab is a trademark of Math Works, Inc.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SLES257–SEPTEMBER 2010
Update Rates
– Four Bass and Treble Tone Controls with
±18-dB Range, Selectable Corner
Frequencies, and Second-Order Slopes
•L, R, and C
•LS, RS
•LR, RR
•Sub
– Configurable Loudness Compensation
– Two Dynamic Range Compressors With Two
Thresholds, Two Offsets, and Three Slopes
– Seven Biquads Per Channel
– Full 8×8 Input Crossbar Mixer. Each
Signal-Processing Channel Input Can Be
Any Ratio of the Eight Input Channels.
– 8×2 Output Mixer – Channels 1–6. Each
Output Can Be Any Ratio of Any Two
Signal-Processed Channels.
– 8×3 Output Mixer – Channels 7 and 8. Each
Output Can Be Any Ratio of Any Three
Signal-Processed Channels.
– Three Coefficient Sets Stored on the Device
Can Be Selected Manually or Automatically
(Based on Specific Data Rates).
– DC Blocking Filters
– Able to Support a Variety of Bass
Management Algorithms
• PWM Processing
– 32-Bit Processing PWM Architecture With 40
Bits of Precision
– 8× Oversampling With Fifth-Order Noise
Shaping at 32 kHz–48 kHz, 4× Oversampling
at 88.2 kHz and 96 kHz, and 2× Oversampling
at 176.4 kHz and 192 kHz
– >102-dB Dynamic Range
– THD+N < 0.1%
– 20-Hz–20-kHz, Flat Noise Floor for 44.1-, 48-,
88.2-, 96-, 176.4-, and 192-kHz Data Rates
– Digital De-Emphasis for 32-, 44.1-, and
48-kHz Data Rates
– Flexible Automute Logic With Programmable
System Provides Clear AM Reception– Adjustable Modulation Limit
– Power-Supply Volume Control (PSVC)
1.2Overview
The TAS5508C is an 8-channel digital pulse-width modulator (PWM) that provides both advanced
performance and a high level of system integration. The TAS5508C is designed to interface seamlessly
with most audio digital signal processors. The TAS5508C automatically adjusts control configurations in
response to clock and data rate changes and idle conditions. This enables the TAS5508C to provide an
easy-to-use control interface with relaxed timing requirements.
The TAS5508C can drive eight channels of H-bridge power stages. Texas Instruments H-bridge parts
TAS5111, TAS5112, or TAS5182 with FETs are designed to work seamlessly with the TAS5508C. The
TAS5508C supports both single-ended or bridge-tied load configurations. The TAS5508C also provides a
high-performance, differential output to drive an external, differential-input, analog headphone amplifier
(such as the TPA112).
The TAS5508C uses AD modulation operating at a 384-kHz switching rate for 48-, 96-, and 192-kHz data.
The 8× oversampling combined with the fifth-order noise shaper provides a broad, flat noise floor and
excellent dynamic range from 20 Hz to 20 kHz.
The TAS5508C is a clocked slave-only device. The TAS5508C receives MCLK, SCLK, and LRCLK from
other system components. The TAS5508C accepts master clock rates of 128, 192, 256, 384, 512, and
768 Fs. The TAS5508C accepts a 64-Fs bit clock.
www.ti.com
The TAS5508C allows for extending the dynamic range by providing a power-supply volume control
(PSVC) output signal.
AVDD_PLL9P3.3-V analog power supply for PLL. This terminal can be connected to the same
AVSS5, 6PAnalog ground
AVSS_PLL8PAnalog ground for PLL. This terminal should reference the same ground as
BKND_ERR37DIPullupActive-low. A back-end error sequence is generated by applying logic low to this
DVDD15, 36P3.3-V digital power supply
DVDD_PWM54P3.3-V digital power supply for PWM
DVSS16, 34,PDigital ground
35, 38
DVSS_PWM53PDigital ground for PWM
HP_SEL12DI5 VPullupHeadphone in/out selector. When a logic low is applied, the headphone is
LRCLK26DI5 VSerial-audio data left/right clock (sampling-rate clock)
MCLK63DI5 VPulldownMCLK is a 3.3-V master clock input. The input frequency of this clock can range
MUTE14DI5 VPullupSoft mute of outputs, active-low (muted signal = a logic low, normal operation =
OSC_CAP18AOOscillator capacitor
PDN13DI5 VPullupPower down, active-low. PDN powers down all logic and stops all clocks
power source used to drive power terminal DVDD, but to achieve low PLL jitter,
this terminal should be bypassed to AVSS_PLL with a 0.1-mF low-ESR
capacitor.
terminal DVSS, but to achieve low PLL jitter, ground noise at this terminal must
be minimized. The availability of the AVSS terminal allows a designer to use
optimizing techniques such as star ground connections, separate ground planes,
or other quiet ground-distribution techniques to achieve a quiet ground reference
at this terminal.
terminal. The BKND_ERR results in no change to any system parameters, with
all H-bridge drive signals going to a hard-mute (M) state.
selected (speakers are off). When a logic high is applied, speakers are selected
(headphone is off).
from 4 MHz to 50 MHz.
a logic high). The mute control provides a noiseless volume ramp to silence.
Releasing mute provides a noiseless ramp to previous volume.
whenever a logic low is applied. The internal parameters are preserved through
a power-down cycle, as long as RESET is not active. The duration for system
recovery from power down is 100 ms.
DESCRIPTION
(1) Type: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) All pullups are 200-mA weak pullups and all pulldowns are 200-mA weak pulldowns. The pullups and pulldowns are included to ensure
proper input logic levels if the terminals are left unconnected (pullups => logic-1 input; pulldowns => logic-0 input). Devices that drive
inputs with pullups must be able to sink 200 mA, while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 200 mA, while maintaining a logic-1 drive level.
23, 64
RESET11DI5 VPullupSystem reset input, active-low. A system reset is generated by applying a logic
SCL25DI5 V
SCLK27DI5 VSerial-audio data clock (shift clock) input
SDA24DIO5 V
SDIN131DI5 VPulldownSerial-audio data input 1 is one of the serial-data input ports. SDIN1 supports
SDIN230DI5 VPulldownSerial-audio data input 2 is one of the serial-data input ports. SDIN2 supports
SDIN329DI5 VPulldownSerial-audio data input 3 is one of the serial-data input ports. SDIN3 supports
SDIN428DI5 VPulldownSerial-audio data input 4 is one of the serial-data input ports. SDIN4 supports
VALID39DOOutput indicating validity of PWM outputs, active-high
VBGAP10PBand-gap voltage reference. A pinout of the internally regulated 1.2-V reference.
VR_DIG33PVoltage reference for 1.8-V digital core supply. A pinout of the internally
VR_DPLL17PVoltage reference for 1.8-V digital PLL supply. A pinout of the internally
VR_PWM48PVoltage reference for 1.8-V digital PWM core supply. A pinout of the internally
VRA_PLL1PVoltage reference for 1.8-V PLL analog supply. A pinout of the internally
VRD_PLL7PVoltage reference for 1.8-V PLL digital supply. A pinout of the internally
XTL_IN20AIXTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They
XTL_OUT19AOXTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They
TYPE
(1)
5-V
TOLERANT
TERMINATION
(2)
low to this terminal. RESET is an asynchronous control signal that restores the
TAS5508C to its default conditions, sets the valid output low, and places the
PWM in the hard mute (M) state. Master volume is immediately set to full
attenuation. On the release of RESET, if PDN is high, the system performs a 4to 5-ms device initialization and sets the volume at mute.
I2C serial-control clock input/output
I2C serial-control data-interface input/output
four discrete (stereo) data formats and is capable of inputting data at 64 Fs.
four discrete (stereo) data formats and is capable of inputting data at 64 Fs.
four discrete (stereo) data formats and is capable of inputting data at 64 Fs.
four discrete (stereo) data formats and is capable of inputting data at 64 Fs.
Typically has a 1-nF low-ESR capacitor between VBGAP and AVSS_PLL. This
terminal must not be used to power external devices.
regulated 1.8-V power used by digital core logic. A 4.7-mF low-ESR capacitor
should be connected between this terminal and DVSS. This terminal must not
be used to power external devices.
regulated 1.8-V power used by digital PLL logic. A 0.1-mF low-ESR capacitor
should be connected between this terminal and DVSS_CORE. This terminal
must not be used to power external devices.
regulated 1.8-V power used by digital PWM core logic. A 0.1-mF low-ESR
(3)
capacitor
terminal must not be used to power external devices.
regulated 1.8-V power used by PLL logic. A 0.1-mF low-ESR capacitor
be connected between this terminal and AVSS_PLL. This terminal must not be
used to power external devices.
regulated 1.8-V power used by PLL logic. A 0.1-mF low-ESR capacitor
be connected between this terminal and AVSS_PLL. This terminal must not be
used to power external devices.
provide a reference clock for the TAS5508C via use of an external
fundamental-mode crystal. XTL_IN is the 1.8-V input port for the oscillator
circuit. A 13.5-MHz crystal (HCM49) is recommended.
provide a reference clock for the TAS5508C via use of an external
fundamental-mode crystal. XTL_OUT is the 1.8-V output drive to the crystal. A
13.5-MHz crystal (HCM49) is recommended.
should be connected between this terminal and DVSS_PWM. This
DESCRIPTION
SLES257–SEPTEMBER 2010
(3)
should
(3)
should
(3) If desired, low-ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling
capacitors of equal value provides an extended high-frequency supply decoupling. This approach avoids the potential of producing
parallel resonance circuits that have been observed when paralleling capacitors of different values.
(3)
(3)
2.2TAS5508C Functional Description
Figure 2-1 shows the TAS5508C functional structure. The following sections describe the TAS5508C
The power-supply section contains supply regulators that provide analog and digital regulated power for
various sections of the TAS5508C. The analog supply supports the analog PLL, whereas digital supplies
support the digital PLL, the digital audio processor (DAP), the pulse-width modulator (PWM), and the
output control (reclocker). The regulators can also be turned off when terminals RESET and PDN are both
low.
2.2.2Clock, PLL, and Serial Data Interface
The TAS5508C is a clocked slave-only device that requires the use of an external 13.5-MHz crystal. It
accepts MCLK, SCLK, and LRCLK as inputs only.
The TAS5508C uses the external crystal to provide a time base for:
•Continuous data and clock error detection and management
•Automatic data-rate detection and configuration
•Automatic MCLK-rate detection and configuration (automatic bank switching)
•Supporting I2C operation/communication while MCLK is absent
The TAS5508C automatically handles clock errors, data-rate changes, and master-clock frequency
changes without requiring intervention from an external system controller. This feature significantly
reduces system complexity and design.
www.ti.com
2.2.2.1Serial Audio Interface
The TAS5508C operates as a slave-only/receive-only serial data interface in all modes. The TAS5508C
has four PCM serial data interfaces to permit eight channels of digital data to be received though the
SDIN1, SDIN2, SDIN3, and SDIN4 inputs. The serial audio data is in MSB-first, 2s-complement format.
The serial data input interface of the TAS5508C can be configured in right-justified, I2S, or left-justified
modes. The serial data interface format is specified using the I2C data-interface control register. The
supported formats and word lengths are shown in Table 2-1.
Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5508C accepts 16-, 20-, or 24-bit
serial data at 32, 38, 44.1, 48, 88.2, 96, 176.4, or 192 kHz in left-justified, I2S, or right-justified format.
Data is input using a 64-Fs SCLK clock and an MCLK rate of 128, 192, 256, 384, 512, or 768 Fs, up to a
maximum of 50 MHz. The clock speed and serial data format are I2C configurable.
2.2.3I2C Serial-Control Interface
The TAS5508C has an I2C serial-control slave interface (address 0x36) to receive commands from a
system controller. The serial-control interface supports both normal-speed (100 kHz) and high-speed (400
kHz) operations without wait states. Because the TAS5508C has a crystal time base, this interface
operates even when MCLK is absent.
The serial control interface supports both single-byte and multiple-byte read/write operations for status
registers and the general control registers associated with the PWM. However, for the DAP
data-processing registers, the serial control interface also supports multiple-byte (4-byte) write operations.
The I2C supports a special mode which permits I2C write operations to be broken up into multiple
data-write operations that are multiples of 4 data bytes. These are 6-byte, 10-byte, 14-byte, 18-byte, etc.,
write operations that are composed of a device address, read/write bit, subaddress, and any multiple of 4
bytes of data. This permits the system to incrementally write large register values without blocking other
I2C transactions. In order to use this feature, the first block of data is written to the target I2C address, and
each subsequent block of data is written to a special append register (0xFE) until all the data is written
and a stop bit is sent. An incremental read operation is not supported.
2.2.4Device Control
The TAS5508C control section provides the control and sequencing for the TAS5508C. The device control
provides both high- and low-level control for the serial control interface, clock and serial data interfaces,
digital audio processor, and pulse-width modulator sections.
2.2.5Digital Audio Processor (DAP)
The DAP arithmetic unit is used to implement all audio-processing functions: soft volume, loudness
compensation, bass and treble processing, dynamic range control, channel filtering, input and output
mixing. Figure 2-3 shows the TAS5508C DAP architecture.
The DAP accepts 24-bit data from the serial data interface and outputs 32-bit data to the PWM section.
The DAP supports two configurations, one for 32-kHz to 96-kHz data and one for 176.4-kHz to 192-kHz
data.
2.2.5.1TAS5508C Audio-Processing Configurations
The 32-kHz to 96-kHz configuration supports eight channels of data processing that can be configured
either as eight channels, or as six channels with two channels for separate stereo line outputs.
The 176.4-kHz to 192-kHz configuration supports three channels of signal processing with five channels
passed though (or derived from the three processed channels).
To support efficiently the processing requirements of both multichannel 32-kHz to 96-kHz data and the
2-channel 176.4-kHz and 192-kHz data, the TAS5508C has separate audio-processing features for
32-kHz to 96-kHz data rates and for 176.4 kHz and 192 kHz. See Table 2-2 for a summary of TAS5508C
processing feature sets.
2.2.5.2TAS5508C Audio Signal-Processing Functions
The DAP provides 10 primary signal-processing functions:
1. The data-processing input has a full 8×8 input crossbar mixer. This enables each input to be any ratio
of the eight input channels.
2. Two I2C programmable threshold detectors in each channel support automute.
3. Seven biquads per channel
4. Four soft bass and treble tone controls with ±18-dB range, programmable corner frequencies, and
second-order slopes. In 8-channel mode, bass and treble controls are normally configured as follows:
– Bass and treble 1: Channel 1 (left), channel 2 (right), and channel 7 (center)
– Bass and treble 2: Channel 3 (left surround) and channel 4 (right surround)
– Bass and treble 3: Channel 5 (left back surround) and channel 6 (right back surround)
– Bass and treble 4: Channel 8 (subwoofer)
5. Individual channel and master volume controls. Each control provides an adjustment range of 18 dB to
–127 dB. This permits a total volume device control range of 36 dB to –127 dB plus mute. The master
volume control can be configured to control six or eight channels. The DAP soft volume and mute
update interval is I2C programmable. The update is performed at a fixed rate regardless of the sample
rate.
6. Programmable loudness compensation that is controlled via the combination of the master and
individual volume settings.
7. Two dual-threshold dual-rate dynamic range compressors (DRCs). The volume gain values provided
are used as input parameters using the maximum RMS (master volume × individual channel volume).
8. 8×2 output mixer (channels 1–6). Each output can be any ratio of any two signal-processed channels.
9. 8×3 output mixer (channels 7 and 8). Each output can be any ratio of any three signal-processed
channels.
10. The DAP maintains three sets of coefficient banks that are used to maintain separate sets of
sample-rate-dependent parameters for the biquad, tone controls, loudness, and DRC in RAM. These
can be set to be automatically selected for one or more data sample rates or can be manually selected
under I2C program control. This feature enables coefficients for different sample rates to be stored in
the TAS5508C and then selected when needed.
Signal-processing channels86 + 23
Pass-through channelsN/A5
Master volume1 for 8 channels1 for 6 channels1 for 3 channels
Individual channel volume
controls
Four bass and treble tone controlsFour bass and treble tone controls
with ±18-dB range, programmablewith ±18-dB range, programmable
Bass and treble toneorder slopesorder slopes
controlsL, R, and C (Ch1, 2, and 7)L, R, and C (Ch1, 2, and 7)
Biquads5621
Dynamic rangeDRC1 for seven satellites andDRC1 for five satellites and DRC2DRC1 for two satellites and
compressorsDRC2 for subfor sub (Ch5 and 6 uncompressed)DRC2 for sub
Input/output mapping/
mixing
DC-blocking filters
(implemented in PWMEight channels
section)
Digital de-emphasis
(implemented in PWMN/A
section)
LoudnessEight channelsSix channelsThree channels
Number of coefficient sets
stored
corner frequencies, and second-corner frequencies, and second-
LS, RS (Ch3 and 4)LS, RS (Ch3 and 4)
LBS, RBS (Ch5 and 6)Sub (Ch8)
Sub (Ch8)Line L and R (Ch5 and 6)
Each of the eight signal-processing channel inputs can be any ratio of thebe any ratio of the eight input
eight input channels.channels.
Each of the eight outputs can be any ratio of any two processed channels. Each of the eight outputs can be
Eight channels for 32 kHz,Six channels for 32 kHz, 44.1 kHz,
44.1 kHz, and 48 kHzand 48 kHz
32 kHz–96 kHz32 kHz–96 kHz176.4- and 192-kHz
8-CHANNEL FEATURE SET6 + 2 LINEOUT FEATURE SETFEATURE SET
83
Two bass and treble tone
controls with ±18-dB range,
programmable corner
frequencies, and second-order
slopes
L and R (Ch1 and 2)
Sub (Ch8)
Each of the three signalprocessing channels or the five
pass-though channel inputs can
any ratio of any of the three
processed channels or five
bypass channels.
Three additional coefficient sets can be stored in memory.
2.3TAS5508C DAP Architecture
2.3.1TAS5508C DAP Architecture Diagrams
Figure 2-1 shows the TAS5508C DAP architecture for Fs = 96 kHz. Note the TAS5508C bass
management architecture shown in channels 1, 2, 7, and 8. Note that the I2C registers are shown to help
the designer configure the TAS5508C.
Figure 2-2 shows the TAS5508C architecture for Fs = 176.4 kHz or Fs = 192 kHz. Note that only channels
1, 2, and 8 contain all the features. Channels 3–7 are pass-through except for master volume control.
Figure 2-3 shows TAS5508C detailed channel processing. The output mixer is 8×2 for channels 1–6 and
The architecture of the TAS5508C is contained in ROM resources within the TAS5508C and cannot be
altered. However, mixer gain, level offset, and filter tap coefficients, which can be entered via the I2C bus
interface, provide a user with the flexibility to set the TAS5508C to a configuration that achieves
system-level goals.
The firmware is executed in a 48-bit, signed, fixed-point arithmetic machine. The most significant bit of the
48-bit data path is a sign bit, and the 47 lower bits are data bits. Mixer gain operations are implemented
by multiplying a 48-bit, signed data value by a 28-bit, signed gain coefficient. The 76-bit, signed output
product is then truncated to a signed, 48-bit number. Level offset operations are implemented by adding a
48-bit, signed offset coefficient to a 48-bit, signed data value. In most cases, if the addition results in
overflowing the 48-bit, signed number format, saturation logic is used. This means that if the summation
results in a positive number that is greater than 0x7FFF FFFF FFFF (the spaces are used to ease the
reading of the hexadecimal number), the number is set to 0x7FFF FFFF FFFF. If the summation results in
a negative number that is less than 0x80000000 0000, the number is set to 0x8000 0000 0000.
2.3.2.128-Bit 5.23 Number Format
All mixer gain coefficients are 28-bit coefficients using a 5.23 number format. Numbers formatted as 5.23
numbers have 5 bits to the left of the binary point and 23 bits to the right of the binary point. This is shown
in Figure 2-4.
(1 or 0) y 23 + (1 or 0) y 22 + … + (1 or 0) y 20 + (1 or 0) y 2−1 + … + (1 or 0) y 2−4 + … + (1 or 0) y 2
−23
23 Bit22 Bit20 Bit2−1 Bit2−4 Bit2
−23
Bit
M0008-01
u
Coefficient
Digit 8
u
u uS x x x
Coefficient
Digit 7
x.
x x x
Coefficient
Digit 6
x
x x x
Coefficient
Digit 5
x
x x x
Coefficient
Digit 4
x
x x x
Coefficient
Digit 3
x
x x x
Coefficient
Digit 2
x
x x x
Coefficient
Digit 1
Fraction
Digit 5
Sign
Bit
0
Fraction
Digit 6
Fraction
Digit 4
Fraction
Digit 3
Fraction
Digit 2
Fraction
Digit 1
Integer
Digit 1
u = unused or don’t care bits
Digit = hexadecimal digit
M0009-01
TAS5508C
www.ti.com
The decimal value of a 5.23 format number can be found by following the weighting shown in Figure 2-5. If
the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the
correct number. If the most significant bit is a logic 1, then the number is a negative number. In this case,
every bit must be inverted, a 1 added to the result, and then the weighting shown in Figure 2-5 applied to
obtain the magnitude of the negative number.
SLES257–SEPTEMBER 2010
Figure 2-4. 5.23 Format
Figure 2-5. Conversion Weighting Factors—5.23 Format to Floating Point
Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the
32-bit number (4-byte or 8-digit hexadecimal number) is shown in Figure 2-6.
Figure 2-6. Alignment of 5.23 Coefficient in 32-Bit I2C Word
As Figure 2-6 shows, the hexadecimal (hex) value of the integer part of the gain coefficient cannot be
(1 or 0) y 223 + (1 or 0) y 222 + … + (1 or 0) y 20 + (1 or 0) y 2−1 + … + (1 or 0) y 2
−23
223 Bit222 Bit20 Bit2−1 Bit2
−23
Bit
M0008-02
TAS5508C
SLES257–SEPTEMBER 2010
concatenated with the hex value of the fractional part of the gain coefficient to form the 32-bit I2C
coefficient. The reason is that the 28-bit coefficient contains 5 bits of integer, and thus the integer part of
the coefficient occupies all of one hex digit and the most significant bit of the second hex digit. In the same
way, the fractional part occupies the lower three bits of the second hex digit, and then occupies the other
five hex digits (with the eighth digit being the zero-valued most significant hex digit).
2.3.2.248-Bit 25.23 Number Format
All level adjustment and threshold coefficients are 48-bit coefficients using a 25.23 number format.
Numbers formatted as 25.23 numbers have 25 bits to the left of the decimal point and 23 bits to the right
of the decimal point. This is shown in Figure 2-7.
www.ti.com
Figure 2-7. 25.23 Format
Figure 2-8 shows the derivation of the decimal value of a 48-bit 25.23 format number.
Figure 2-8. Alignment of 5.23 Coefficient in 32-Bit I2C Word
Two 32-bit words must be sent over the I2C bus to download a level or threshold coefficient into the
TAS5508C. The alignment of the 48-bit, 25.23 formatted coefficient in the 8-byte (two 32-bit words) I2C
word is shown in Figure 2-9.
u = unused or don’t care bits
Digit = hexadecimal digit
M0009-02
TAS5508C
www.ti.com
SLES257–SEPTEMBER 2010
2.3.2.3TAS5508C Audio Processing
Figure 2-9. Alignment of 25.23 Coefficient in Two 32-Bit I2C Words
The TAS5508C digital audio processing is designed so that noise produced by filter operations is
maintained below the smallest signal amplitude of interest, as shown in Figure 2-10. The TAS5508C
achieves this low noise level by increasing the precision of the signal representation substantially above
the number of bits that are absolutely necessary to represent the input signal.
Similarly, the TAS5508C carries additional precision in the form of overflow bits to permit the value of
intermediate calculations to exceed the input precision without clipping. The TAS5508C advanced digital
audio processor achieves both of these important performance capabilities by using a high-performance
digital audio processing architecture with a 48-bit data path, 28-bit filter coefficients, and a 76-bit
accumulator.
The TAS5508C has a full 8×8 input crossbar mixer. This mixer permits each signal processing channel
input to be any ratio of any of the eight input channels, as shown in Figure 2-11. The control parameters
for the input crossbar mixer are programmable via the I2C interface. See the Input Mixer Registers(0x41–0x48, Channels 1–8), Section 7.16, for more information.
www.ti.com
Figure 2-10. TAS5508C Digital Audio Processing
2.5Biquad Filters
For 32-kHz to 96-kHz data, the TAS5508C provides 56 biquads across the eight channels (seven per
channel).
For 176.4-kHz and 192-kHz data, the TAS5508C has 21 biquads across the three channels (seven per
channel). All of the biquad filters are second-order direct form I structure.
The direct form I structure provides a separate delay element and mixer (gain coefficient) for each node in
the biquad filter. Each mixer output is a signed 76-bit product of a signed 48-bit data sample (25.23 format
number) and a signed 28-bit coefficient (5.23 format number), as shown in Figure 2-12. The 76-bit ALU in
the TAS5508C allows the 76-bit resolution to be retained when summing the mixer outputs (filter
products).
The five 28-bit coefficients for the each of the 56 biquads are programmable via the I2C interface. See
Table 2-3.
SLES257–SEPTEMBER 2010
Figure 2-12. Biquad Filter Structure
All five coefficients for one biquad filter structure are written to one I2C register containing 20 bytes (or five
32-bit words). The structure is the same for all biquads in the TAS5508C. Registers 0x51–0x88 show all
the biquads in the TAS5508C. Note that u[31:28] bits are unused and default to 0x0.
Table 2-3. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass)
From 32-kHz to 96-kHz data, the TAS5508C has four bass and treble tone controls. Each control has a
±18-dB control range with selectable corner frequencies and second-order slopes. These controls operate
four channel groups:
•L, R, and C (channels 1, 2, and 7)
•LS, RS (channels 3 and 4)
•LBS, RBS (alternatively called L and R lineout) (channels 5 and 6)
•Sub (channel 8)
For 176.4-kHz and 192-kHz data, the TAS5508C has two bass and treble tone controls. Each control has
a ±18-dB I2C control range with selectable corner frequencies and second-order slopes. These controls
operate two channel groups:
The I2C registers that control bass and treble are:
•Bass and treble bypass register (0x89–0x90, channels 1–8)
•Bass and treble slew rates (0xD0)
•Bass filter sets 1–5 (0xDA)
•Bass filter index (0xDB)
•Treble filter sets 1–5 (0xDC)
•Treble filter index (0xDD)
2.7Volume, Automute, and Mute
The TAS5508C provides individual channel and master volume controls. Each control provides an
adjustment range of 18 dB to –100 dB in 0.25-dB increments. This permits a total volume device control
range of 36 dB to –100 dB plus mute. The master volume control can be configured to control six or eight
channels.
The TAS5508C has a master soft mute control that can be enabled by a terminal or I2C command. The
device also has individual channel soft mute controls that are enabled via I2C.
The soft volume and mute update rates are programmable. The soft adjustments are performed using a
soft-gain linear update with an I2C-programmable linear step size at a fixed temporal rate. The linear
soft-gain step size can be varied from 0.5 to 0.003906. Table 2-5 lists the linear gain step sizes.
Time to go from 36.124 db to –127 dB in ms10.6721.3342.6785.34170.67340.35682.701365.4
Time to go from 18.062 db to –127 dB in ms1.332.675.3310.6721.3342.6785.33170.67
Time to go from 0 db to –127 dB in ms0.170.330.671.332.675.3310.6721.33
2.8Automute and Mute
The TAS5508C has individual channel automute controls that are enabled via the I2C interface. Two
separate detectors can trigger the automute:
•Input automute: All channels are muted when all 8 inputs to the TAS5508C are less in magnitude than
the input threshold value for a programmable amount of time.
•Output automute: A single channel is muted when the output of the DAP section is less in magnitude
The detection period and thresholds for these two detectors are the same.
This time interval is selectable via I2C to be from 1 ms to 110 ms. The increments of time are 1, 2, 3, 4, 5,
10, 20, 30, 40, 50, 60, 70, 80, 90, 100, and 110 ms. This interval is independent of the sample rate. The
default value is mask programmable.
The input threshold value is an unsigned magnitude that is expressed as a bit position. This value is
adjustable via I2C. The range of the input threshold adjustment is from below the LSB (bit position 0) to
below bit position 12 in a 24-bit input-data word (bit positions 8 to 20 in the DSPE). This range provides an
input threshold that can be adjusted for 12 to 24 bits of data. The default value is mask programmable.
SLES257–SEPTEMBER 2010
than the input threshold value for a programmable amount of time.
Figure 2-13. Automute Threshold
The automute state is exited when the TAS5508C receives one sample that is greater than the output
threshold.
The output threshold can be one of two values:
•Equal to the input threshold
•6 dB (one bit position) greater than the input threshold
The value for the output threshold is selectable via I2C. The default value is mask programmable.
The system latency enables the data value that is above the threshold to be preserved and output.
A mute command initiated by automute, master mute, individual I2C mute, the AM interference mute
sequence, or the bank-switch mute sequence overrides an unmute command or a volume command.
While a mute command is activated, the commanded channels transition to the mute state. When a
channel is unmuted, it goes to the last commanded volume setting that has been received for that
channel.
2.9Loudness Compensation
The loudness compensation function compensates for the Fletcher-Munson loudness curves. The
TAS5508C loudness implementation tracks the volume control setting to provide spectral compensation
for weak low- or high-frequency response at low volume levels. For the volume tracking function, both
linear and logarithmic control laws can be implemented. Any biquad filter response can be used to provide
the desired loudness curve. The control parameters for the loudness control are programmable via the I2C
interface.
The TAS5508C has a single set of loudness controls for the eight channels. In 6-channel mode, loudness
is available to the six speaker outputs and also to the line outputs. The loudness control input uses the
maximum individual master volume (V) to control the loudness that is applied to all channels. In the
192-kHz and 176.4-kHz modes, the loudness function is active only for channels 1, 2, and 8.
Loudness function = f(V) = G ×[2
Loudness function = f(V) = G × [VLG× 2LO] + O
For example, for the default values LG = –0.5, LO = 0, G = 1, and O = 0, then:
Loudness function = 1/SQRT(V), which is the recommended transfer function for loudness. So,
Audio out = (audio in) × V + H(Z) × SQRT(V). Other transfer functions are possible.
Problem: Due to the Fletcher-Munson phenomena, we want to compensate for low-frequency attenuation
near 60 Hz. The TAS5508C provides a loudness transfer function with EQ gain = 6, EQ center frequency
= 60 Hz, and EQ bandwidth = 60 Hz.
Solution: Using Texas Instruments ALE TAS5508C DSP tool, Matlab™, or other signal-processing tool,
develop a loudness function with the parameters listed in Table 2-7.
See Figure 2-15 for the resulting loudness function at different gains.
2.10 Dynamic Range Control (DRC)
DRC provides both compression and expansion capabilities over three separate and definable regions of
audio signal levels. Programmable threshold levels set the boundaries of the three regions. Within each of
the three regions, a distinct compression or expansion transfer function can be established and the slope
of each transfer function is determined by programmable parameters. The offset (boost or cut) at the two
boundaries defining the three regions can also be set by programmable offset coefficients. The DRC
implements the composite transfer function by computing a 5.23-format gain coefficient from each sample
output from the rms estimator. This gain coefficient is then applied to a mixer element, whose other input
is the audio data stream. The mixer output is the DRC-adjusted audio data.
There are two distinct DRC blocks in the TAS5508C. DRC1 services channels 1–7 in the 8-channel mode
and channels 1–4 and 7 in the 6-channel mode. This DRC computes rms estimates of the audio data
streams on all channels that it controls. The estimates are then compared on a sample-by-sample basis
and the larger of the estimates is used to compute the compression/expansion gain coefficient. The gain
coefficient is then applied to the appropriate channel audio streams. DRC2 services only channel 8. This
DRC also computes an rms estimate of the signal level on channel 8 and this estimate is used to compute
the compression/expansion gain coefficient applied to the channel-8 audio stream.
All of the TAS5508C default values for DRC can be used except for the DRC1 decay and DRC2 decay.
Table 2-8 shows the recommended time constants and their hex values. If the user wants to implement
other DRC functions, Texas Instruments recommends using the automatic loudspeaker equalization (ALE)
tool available from Texas Instruments. The ALE tool allows the user to select the DRC transfer function
graphically. It then outputs the TAS5508C hex coefficients for download to the TAS5508C.
Table 2-8. DRC Recommended Changes From TAS5508C Defaults
I2CRECOMMENDED TIMERECOMMENDED
SUBADDRESSCONSTANT (ms)HEX VALUE
0x98DRC1 energy50000 883F0000883F
0x9CDRC1 attack50000883F0000 883F
0x9DDRC2 energy50000883F0000 883F
0xA1DRC2 attack50000883F0000 883F
REGISTER FIELDSDEFAULT HEX
DRC1 (1 – energy)007F 77C0007F 77C0
DRC1 (1 – attack)007F77C0007F77C0
DRC1 decay20001538F0000 00AE
DRC1 (1 – decay)007E AC70007FFF51
DRC2 (1 – energy)007F 77C0007F 77C0
DRC2 (1 – attack)007F77C0007F77C0
DRC2 decay20001538F0000 00AE
DRC2 (1 – decay)007E AC70007FFF51
www.ti.com
Recommended DRC set-up flow if the defaults are used:
•After power up, load the recommended hex value for DRC1 and DRC2 decay and (1 – decay). See
Table 2-8.
•Enable either the pre-volume or post-volume DRC.
Recommended DRC set-up flow if the DRC design uses values different from the defaults:
•After power up, load all DRC coefficients per the DRC design.
•Enable either the pre-volume or post-volume DRC.
Figure 2-16 shows the positioning of the DRC block in the TAS5508C processing flow. As seen, the DRC
input can come either before or after soft volume control and loudness processing.
Figure 2-16. DRC Positioning in TAS5508C Processing Flow
Figure 2-17 illustrates a typical DRC transfer function.
The three regions shown in Figure 2-17 are defined by three sets of programmable coefficients:
•Thresholds T1 and T2 define region boundaries.
•Offsets O1 and O2 define the DRC gain coefficient settings at thresholds T1 and T2, respectively.
•Slopes k0, k1, and k2 define whether compression or expansion is to be performed within a given
SLES257–SEPTEMBER 2010
Figure 2-17. Dynamic Range Compression (DRC) Transfer Function Structure
region. The magnitudes of the slopes define the degree of compression or expansion to be performed.
The three sets of parameters are all defined in logarithmic space and adhere to the following rules:
•The maximum input sample into the DRC is referenced at 0 dB. All values below this maximum value
then have negative values in logarithmic (dB) space.
•The samples input into the DRC are 32-bit words and consist of the upper 32 bits of the 48-bit word
format used by the digital audio processor (DAP). The 48-bit DAP word is derived from the 32-bit serial
data received at the serial-audio receive port by adding 8 bits of headroom above the 32-bit word and
8 bits of computational precision below the 32-bit word. If the audio processing steps between the SAP
input and the DRC input result in no accumulative boost or cut, the DRC operates on the 8 bits of
headroom and the 24 MSBs of the audio sample. Under these conditions, a 0-dB (maximum value)
audio sample (0x7FFF FFFF) is seen at the DRC input as a –48-dB sample (8 bits × –6.02 dB/bit =
–48 dB).
•Thresholds T1 and T2 define, in dB, the boundaries of the three regions of the DRC, as referenced to
the rms value of the data into the DRC. Zero-valued threshold settings reference the maximum-valued
rms input into the DRC and negative-valued thresholds reference all other rms input levels.
Positive-valued thresholds have no physical meaning and are not allowed. In addition, zero-valued
threshold settings are not allowed.
Although the DRC input is limited to 32-bit words, the DRC itself operates using the 48-bit word format of
the DAP. The 32-bit samples input into the DRC are placed in the upper 32 bits of this 48-bit word space.
This means that the threshold settings must be programmed as 48-bit (25.23 format) numbers.
Zero-valued and positive-valued threshold settings are not allowed and cause
unpredictable behavior if used.
•Offsets O1 and O2 define, in dB, the attenuation (cut) or gain (boost) applied by the DRC-derived gain
coefficient at the threshold points T1 and T2, respectively. Positive offsets are defined as cuts, and
thus boost or gain selections are negative numbers. Offsets must be programmed as 48-bit (25.23
format) numbers.
•Slopes k0, k1, and k2 define whether compression or expansion is to be performed within a given
region, and the degree of compression or expansion to be applied. Slopes are programmed as 28-bit
(5.23 format) numbers.
2.10.1 DRC Implementation
The three elements comprising the DRC include: (1) an rms estimator, (2) a compression/expansion
coefficient computation engine, and (3) an attack/decay controller.
•RMS estimator—This DRC element derives an estimate of the rms value of the audio data stream into
the DRC. For the DRC block shared by Ch1 and Ch2, two estimates are computed—an estimate of the
Ch1 audio data stream into the DRC, and an estimate of the Ch2 audio data stream into the DRC. The
outputs of the two estimators are then compared, sample-by-sample, and the larger-valued sample is
forwarded to the compression/expansion coefficient computation engine.
Two programmable parameters, ae and (1 – ae), set the effective time window over which the rms
estimate is made. For the DRC block shared by Ch1 and Ch2, the programmable parameters apply to
both rms estimators. The time window over which the rms estimation is computed can be determined
by:
www.ti.com
•Compression/expansion coefficient computation—This DRC element converts the output of the rms
estimator to a logarithmic number, determines the region where the input resides, and then computes
and outputs the appropriate coefficient to the attack/decay element. Seven programmable parameters,
T1, T2, O1, O2, k0, k1, and k2, define the three compression/expansion regions implemented by this
element.
•Attack/decay control—This DRC element controls the transition time of changes in the coefficient
computed in the compression/expansion coefficient computation element. Four programmable
parameters define the operation of this element. Parameters ad and (1 – ad) set the decay or release
time constant to be used for volume boost (expansion). Parameters aa and (1 – aa) set the attack time
constant to be used for volume cuts. The transition time constants can be determined by:
There are seven programmable parameters assigned to each DRC block: two threshold parameters—T1
and T2, two offset parameters—O1 and O2, and three slope parameters—k0, k1, and k2. The threshold
parameters establish the three regions of the DRC transfer curve, the offsets anchor the transfer curve by
establishing known gain settings at the threshold levels, and the slope parameters define whether a given
region is a compression or an expansion region
The audio input stream into the DRC must pass through DRC-dedicated programmable input mixers.
These mixers are provided to scale the 32-bit input into the DRC to account for the positioning of the
audio data in the 48-bit DAP word and the net gain or attenuation in signal level between the SAP input
and the DRC. The selection of threshold values must take the gain (attenuation) of these mixers into
account. The DRC implementation examples that follow illustrate the effect these mixers have on
establishing the threshold settings.
T2 establishes the boundary between the high-volume region and the mid-volume region. T1 establishes
the boundary between the mid-volume region and the low-volume region. Both thresholds are set in
logarithmic space, and which region is active for any given rms estimator output sample is determined by
the logarithmic value of the sample.
Threshold T2 serves as the fulcrum or pivot point in the DRC transfer function. O2 defines the boost
(> 0 dB) or cut (< 0 dB) implemented by the DRC-derived gain coefficient for an rms input level of T2. If
O2 = 0 dB, the value of the derived gain coefficient is 1 (0x0080 0000 in 5.23 format). k2 is the slope of
the DRC transfer function for rms input levels above T2, and k1 is the slope of the DRC transfer function
for rms input levels below T2 (and above T1). The labeling of T2 as the fulcrum stems from the fact that
there cannot be a discontinuity in the transfer function at T2. The user can, however, set the DRC
parameters to realize a discontinuity in the transfer function at the boundary defined by T1. If no
discontinuity is desired at T1, the value for the offset term O1 must obey the following equation.
T1 and T2 are the threshold settings in dB, k1 is the slope for region 1, and O2 is the offset in dB at T2. If
the user chooses to select a value of O1 that does not obey the above equation, a discontinuity at T1 is
realized.
Decreasing in volume from T2, the slope k1 remains in effect until the input level T1 is reached. If, at this
input level, the offset of the transfer function curve from the 1 : 1 transfer curve does not equal O1, there
is a discontinuity at this input level as the transfer function is snapped to the offset called for by O1. If no
discontinuity is wanted, O1 and/or k1 must be adjusted so that the value of the transfer curve at input level
T1 is offset from the 1 : 1 transfer curve by the value O1. The examples that follow illustrate both
continuous and discontinuous transfer curves at T1.
Decreasing in volume from T1, starting at offset level O1, slope k0 defines the compression/expansion
activity in the lower region of the DRC transfer curve.
SLES257–SEPTEMBER 2010
2.10.2.1 Threshold Parameter Computation
For thresholds,
T
dB
= –6.0206T
INPUT
= –6.0206T
If, for example, it is desired to set T1 = –64 dB, then the subaddress entry required to set T1 to –64 dB is:
T1 is entered as a 48-bit number in 25.23 format. Therefore:
T1 = 10.63= 0 1010.1010 0001 0100 0111 1010111
= 0x0000 0550 A3D7 in 25.23 format
2.10.2.2 Offset Parameter Computation
The offsets set the boost or cut applied by the DRC-derived gain coefficient at the threshold point. An
equivalent statement is that offsets represent the departure of the actual transfer function from a 1 : 1
transfer at the threshold point. Offsets are 25.23-formatted 48-bit logarithmic numbers. They are computed
by the following equation.
Gains or boosts are represented as negative numbers; cuts or attenuations are represented as positive
numbers. For example, to achieve a boost of 21 dB at threshold T1, the I2C coefficient value entered for
O1 must be:
+ 0.1000_0011_0001_1101_0100
+ 0x00000041886A in 25.23 format
k +
1
n
* 1
k +
1
n
* 1
0.5 : 1 compression å k +
1
0.5
* 1 + 1
1 : 2 expansion å k + 2 * 1 + 1
Compression equation: k + *4 +
1
n
*1 å n + *
1
3
å *0.3333 : 1 compression
Expansion equation: k + *4 + n * 1 å n + *3 å 1 : *3 expansion
TAS5508C
SLES257–SEPTEMBER 2010
2.10.2.3 Slope Parameter Computation
In developing the equations used to determine the subaddress of the input value required to realize a
given compression or expansion within a given region of the DRC, the following convention is adopted.
DRC transfer = Input increase : Output increase
If the DRC realizes an output increase of n dB for every dB increase in the rms value of the audio into the
DRC, a 1 : n expansion is being performed. If the DRC realizes a 1-dB increase in output level for every
n-dB increase in the rms value of the audio into the DRC, an n : 1 compression is being performed.
k = n – 1
For n : 1 compression, the slope k can be found by:
In both expansion (1 : n) and compression (n : 1), n is implied to be greater than 1. Thus, for expansion:
k = n – 1 means k > 0 for n > 1. Likewise, for compression,means –1 < k < 0 for n > 1. Thus, it
appears that k must always lie in the range k > –1.
www.ti.com
The DRC imposes no such restriction and k can be programmed to values as negative as –15.999. To
determine what results when such values of k are entered, it is first helpful to note that the compression
and expansion equations for k are actually the same equation. For example, a 1 : 2 expansion is also a
0.5 : 1 compression.
As can be seen, the same value for k is obtained either way. The ability to choose values of k less than –1
allows the DRC to implement negative-slope transfer curves within a given region. Negative-slope transfer
curves are usually not associated with compression and expansion operations, but the definition of these
operations can be expanded to include negative-slope transfer functions. For example, if k = –4
With k = –4, the output decreases 3 dB for every 1 dB increase in the rms value of the audio into the
DRC. As the input increases in volume, the output decreases in volume.
2.11 Output Mixer
The TAS5508C provides an 8×2 output mixer for channels 1, 2, 3, 4, 5, and 6. For channels 7 and 8, the
TAS5508C provides an 8×3 output mixer. These mixers allow each output to be any ratio of any two (or
three) signal-processed channels. The control parameters for the output crossbar mixer are programmable
via the I2C interface.
The TAS5508C has eight channels of high-performance digital PWM modulators that are designed to
drive switching output stages (back ends) in both single-ended (SE) and H-bridge (bridge-tied load)
configurations. The TAS5508C device uses noise-shaping and sophisticated, error-correction algorithms
to achieve high power efficiency and high-performance digital audio reproduction. The TAS5508C uses an
AD1 PWM modulation scheme combined with a fifth-order noise shaper to provide a 102-dB SNR from
20 Hz to 20 kHz.
Submit Documentation Feedback
Product Folder Link(s): TAS5508C
The PWM section accepts 32-bit PCM data from the DAP and outputs eight PWM audio output channels
configurable as either:
•Six channels to drive power stages and two channels to drive a differential-input active filter to provide
a separately controllable stereo lineout
•Eight channels to drive power stages
The TAS5508C PWM section output supports both single-ended and bridge-tied loads.
The PWM section provides a headphone PWM output to drive an external differential amplifier like the
TPA112. The headphone circuit uses the PWM modulator for channels 1 and 2. The headphone does not
operate while the six or eight back-end drive channels are operating. The headphone is enabled via a
headphone-select terminal or I2C command.
The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter
cutoff frequency is less than 1 Hz.
The PWM section has individual channel de-emphasis filters for 32, 44.1, and 48 kHz that can be enabled
and disabled.
The PWM section also contains the power-supply volume control (PSVC) PWM.
The interpolator, noise shaper, and PWM sections provide a PWM output with the following features:
•Up to 8× oversampling
– 8× at FS= 44.1 kHz, 48 kHz, 32 kHz, 38 kHz
– 4× at FS= 88.2 kHz, 96 kHz
– 2× at FS= 176.4 kHz, 192 kHz
•Fifth-order noise shaping
•100-dB dynamic range 0–20 kHz (TAS5508C + TAS5111 system measured at speaker terminals)
•THD < 0.01%
•Adjustable maximum modulation limit of 93.8% to 99.2%
•3.3-V digital signal
2.12.1 DC Blocking (High-Pass Enable/Disable)
Each input channel incorporates a first-order, digital, high-pass filter to block potential dc components. The
filter –3-dB point is approximately 0.89-Hz at the 44.1-kHz sampling rate. The high-pass filter can be
enabled and disabled via the I2C interface.
2.12.2 De-Emphasis Filter
For audio sources that have been pre-emphasized, a precision 50-ms/15-ms de-emphasis filter is provided
to support the sampling rates of 32 kHz, 44.1 kHz, and 48 kHz. Figure 2-19 shows a graph of the
de-emphasis filtering characteristics. De-emphasis is set using two bits in the system control register.
The TAS5508C supports volume control both by conventional digital gain/attenuation and by a
combination of digital and analog gain/attenuation. Varying the H-bridge power-supply voltage performs
the analog volume control function. The benefits of using power-supply volume control (PSVC) are
reduced idle channel noise, improved signal resolution at low volumes, increased dynamic range, and
reduced radio frequency emissions at reduced power levels. The PSVC is enabled via I2C. When enabled,
the PSCV provides a PWM output that is filtered to provide a reference voltage for the power supply. The
power-supply adjustment range can be set for –12.04, –18.06, or –24.08 dB, to accommodate a range of
variable power-supply designs.
Figure 2-20 and Figure 2-21 show how power-supply and digital gains can be used together.
The volume biquad (0xCF) can be used to implement a low-pass filter in the digital volume control to
match the PSVC volume transfer function.
Submit Documentation Feedback
Product Folder Link(s): TAS5508C
−60
−50
−40
−30
−20
−10
0
10
20
30
−80−70−60−50−40−30−20−100102030
Desired Gain − dB
Digital and Power-Supply Gain − dB
Digital Gain
Power-Supply Gain
G002
G003
Desired Gain − Linear
Digital and Power-Supply Gain − dB
Digital Gain
Power-Supply Gain
0.000010.1100
0.0001
0.01
10
100
1
0.001
0.1
1
100.00010.0010.01
TAS5508C
www.ti.com
SLES257–SEPTEMBER 2010
Figure 2-20. Power-Supply and Digital Gains (Log Space)
Figure 2-21. Power-Supply and Digital Gains (Linear Space)
2.12.4 AM Interference Avoidance
Digital amplifiers can degrade AM reception as a result of their RF emissions. Texas Instruments' patented
AM interference-avoidance circuit provides a flexible system solution for a wide variety of digital audio
architectures. During AM reception, the TAS5508C adjusts the radiated emissions to provide an
emission-clear zone for the tuned AM frequency. The inputs to the TAS5508C for this operation are the
tuned AM frequency, the IF frequency, and the sample rate. The sample rate is automatically detected.
The TAS5508C provides control and status information from both the I2C registers and device pins.
This section describes some of these controls and status functions. The I2C summary and detailed
register descriptions are contained in Section 6 and Section 7.
3.1I2C Status Registers
The TAS5508C has two status registers that provide general device information. These are the general
status register 0 (0x01) and the error status register (0x02).
3.1.1General Status Register (0x01)
•Device identification code
•Clip indicator – The TAS5508C has a clipping indicator. Writing to the register clears the indicator.
•Bank switching is busy.
3.1.2Error Status Register (0x02)
•No internal errors (the valid signal is high)
•A clock error has occurred – These are sticky bits that are cleared by writing to the register.
– LRCLK error – when the number of MCLKs per LRCLK is incorrect
– SCLK error – when the number of SCLKS per LRCLK is incorrect
– Frame slip – when the number of MCLKs per LRCLK changes by more than 10 MCLK cycles
– PLL phase-lock error
•This error status register is normally used for system development only.
SLES257–SEPTEMBER 2010
3.2TAS5508C Pin Controls
The TAS5508C provide a number of terminal controls to manage the device operation. These controls
are:
•RESET
•PDN
•BKND_ERR
•HP_SEL
•MUTE
3.2.1Reset (RESET)
The TAS5508C is placed in the reset mode either by the power-up reset circuitry when power is applied,
or by setting the RESET terminal low.
RESET is an asynchronous control signal that restores the TAS5508C to the hard mute state (M). Master
volume is immediately set to full attenuation (there is no ramp down). Reset initiates the device reset
without an MCLK input. As long as the RESET terminal is held low, the device is in the reset state. During
reset, all I2C and serial data bus operations are ignored.
Table 3-1 shows the device output signals while RESET is active.
Because RESET is an asynchronous signal, clicks and pops produced during the application (the leading
edge) of RESET cannot be avoided. However, the transition from the hard mute state (M) to the
operational state is performed using a quiet start-up sequence to minimize noise. This control uses the
PWM reset and unmute sequence to shut down and start up the PWM. A detailed description of these
sequences is contained in the PWM section. If a completely quiet reset or power-down sequence is
desired, MUTE should be applied before applying RESET.
The rising edge of the reset pulse begins device initialization before the transition to the operational mode.
During device initialization, all controls are reset to their initial states. Table 3-2 shows the default control
settings following a reset.
Clock registerNot valid
High passDisabled
Unmute from clock errorHard unmute
PSVC Hi-ZDisabled
Post DAP detection automuteEnabled
Eight Ch PreDAP detection automuteEnabled
De-emphasisDe-emphasis disabled
Channel configuration controlConfigured for the default setting
Headphone configuration controlConfigured for the default setting
Serial data interface formatI2S 24 bit
Individual channel muteNo channels are muted
Automute delay5 ms
Automute threshold 1< 8 bits
Automute threshold 2Same as automute threshold 1
Modulation limitMaximum modulation limit of 97.7%
Six- (or eight – low) channel configurationEight channels
Slew rate limitDisengaged for all channels
Interchannel delay–32, 0, –16, 16, –24, 8, –8, –24
Shutdown PWM on errorEnabled
Volume and mute update rateVolume ramp 85 ms
Treble and bass slew rateUpdate every 1.31 ms
Bank switchingManual bank selection is enabled
Auto bank switching mapAll channels use bank 1
Biquad coefficients (5508)Set to all pass
Input mixer coefficientsInput N -> Channel N, no attenuation
Output mixer coefficientsChannel N -> Output N, no attenuation
Subwoofer sum into Ch1 and Ch2 (5508)Gain of 0
Ch1 and Ch2 sum in subwoofer (5508)Gain of 0
Bass and treble bypassGain of 1
Bass and treble inlineGain of 0
DRC bypass (5508)Gain of 1
DRC inline (5508)Gain of 0
DRC (5508)DRC disabled, default values
www.ti.com
Table 3-1. Device Outputs During Reset (continued)
After the initialization time, the TAS5508C starts the transition to the operational state with the master
volume set at mute.
Because the TAS5508C has an external crystal time base, following the release of RESET, the
TAS5508C sets the MCLK and data rates and performs the initialization sequences. The PWM outputs
are held at a mute state until the master volume is set to a value other than mute via I2C.
SLES257–SEPTEMBER 2010
Table 3-2. Values Set During Reset (continued)
CONTROLSETTING
Master volumeMute
Individual channel volumes0 dB
All bass and treble Indexes0x12 neutral
Treble filter setsFilter set 3
Bass filter setsFilter set 3
Loudness (5508)Loudness disabled, default values
AM interference enableDisabled
AM interference IF455
AM interference select sequence1
Tuned frequency and mode0000, BCD
Subwoofer PSVC controlEnabled
PSVC and PSVC rangeDisabled/0 dB
3.2.2Power Down (PDN)
The TAS5508C can be placed into the power-down mode by holding the PDN terminal low. When the
power-down mode is entered, both the PLL and the oscillator are shut down. Volume is immediately set to
full attenuation (there is no ramp down). This control uses the PWM mute sequence that provides a low
click and pop transition to the hard mute state (M). A detailed description of the PWM mute sequence is
contained in the PWM section.
Power down is an asynchronous operation that does not require MCLK to go into the power-down state.
To initiate the power-up sequence requires MCLK to be operational and the TAS5508C to receive 5
MCLKs prior to the release of PDN.
As long as the PDN terminal is held low, the device is in the power-down state with the PWM outputs in a
hard mute (M) state. During power down, all I2C and serial data bus operations are ignored. Table 3-3
shows the device output signals while PDN is active.
Following the application of PDN, the TAS5508C does not perform a quiet shutdown to prevent clicks and
pops produced during the application (the leading edge) of this command. The application of PDN
immediately performs a PWM stop. A quiet stop sequence can be performed by first applying MUTE
before PDN.
When PDN is released, the system goes to the end state specified by MUTE and BKND_ERR pins and
the I2C register settings.
The crystal time base allows the TAS5508C to determine the CLK rates. Once these rates are
determined, the TAS5508C unmutes the audio.
3.2.3Back-End Error (BKND_ERR)
Back-end error is used to provide error management for back-end error conditions. Back-end error is a
level-sensitive signal. Back-end error can be initiated by bringing the BKND_ERR terminal low for a
minimum 5 MCLK cycles. When BKND_ERR is brought low, the PWM sets either six or eight channels
into the PWM back-end error state. This state is described in Section 2.12. Once the back-end error
sequence is initiated, a delay of 5 ms is performed before the system starts the output re-initialization
sequence. After the initialization time, the TAS5508C begins normal operation. Back-end error does not
affect other PWM modulator operations.
The number of channels that are affected by the BKND_ERR signal depends on the 6-channel
configuration signal. If the I2C setting 6-channel configuration is false, the TAS5508C places all eight
PWM outputs in the PWM back-end error state, while not affecting any other internal settings or
operations. If the I2Csetting six configuration is true, the TAS5508C brings the PWM outputs 1–6 to a
back-end error state, while not affecting any other internal settings or operations. Table 3-4 shows the
device output signal states during back-end error.
Table 3-4. Device Outputs During Back-End Error
SIGNALSIGNAL STATE
ValidLow
PWM P-outputsM-state – low
PWM M-outputsM-state – low
HPPWM P-outputsM-state – low
HPPWM M-outputsM-state – low
SDASignal input (not driven)
www.ti.com
3.2.4Speaker/Headphone Selector (HP_SEL)
The HP_SEL terminal enables the headphone output or the speaker outputs. The headphone output
receives the processed data output from DAP and PWM channels 1 and 2.
In 6-channel configuration, this feature does not affect the two lineout channels.
When low, the headphone output is enabled. In this mode, the speaker outputs are disabled. When high,
the speaker outputs are enabled and the headphone is disabled.
Changes in the pin logic level result in a state change sequence using soft mute to the hard mute (M)
state for both speaker and headphone followed by a soft unmute.
When HP_SEL is low, the configuration of channels 1 and 2 is defined by the headphone configuration
register. When HP_SEL is high, the channel-1 and -2 configuration registers define the configuration of
channels 1 and 2.
3.2.5Mute (MUTE)
The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp
to previous volume. The TAS5508C has both master and individual channel mute commands. A terminal
is also provided for the master mute. The active-low master mute I2C register and the MUTE terminal are
logically ORed together. If either is set to low, a mute on all channels is performed. The master mute
command operates on all channels regardless of whether the system is in the 6- or 8-channel
configuration.
When MUTE is invoked, the PWM output stops switching and then goes to an idle state.
The master mute terminal is used to support a variety of other operations in the TAS5508C, such as
setting the interchannel delay, the biquad coefficients, the serial interface format, and the clock rates. A
mute command by the master mute terminal, individual I2C mute, the AM interference mute sequence, the
bank switch mute sequence, or automute overrides an unmute command or a volume command. While a
mute is active, the commanded channels are placed in a mute state. When a channel is unmuted, it goes
to the last commanded volume setting that has been received for that channel.
3.3Device Configuration Controls
The TAS5508C provides a number of system configuration controls that are set at initialization and
following a reset.
•Channel configuration
•Headphone configuration
•Audio system configurations
•Recovery from clock error
•Power-supply volume-control enable
•Volume and mute update rate
•Modulation index limit
•Interchannel delay
•Master clock and data rate controls
•Bank controls
SLES257–SEPTEMBER 2010
3.3.1Channel Configuration Registers
For the TAS5508C to have full control of the power stages, registers 0x05 to 0x0C must be programmed
to reflect the proper power stage and how each one should be controlled. There are eight channel
configuration registers, one for each channel.
The primary reason for using these registers is that different power stages require different handling
during start-up, mute/unmute, shutdown, and error recovery. The TAS5508C must select the sequence
that gives the best click and pop performance and ensures that the bootstrap capacitor is charged
correctly during start-up. This sequence depends on which power stage is present at the TAS5508C
output.
Table 3-5. Description of the Channel Configuration Registers (0x05 to 0x0C)
BITDESCRIPTION
D7Enable/disable error recovery sequence. In case the BKND_RECOVERY pin is pulled low, this register determines if this
channel is to follow the error recovery sequence or to continue with no interruption.
D6Determines if the power stage needs the TAS5508C VALID pin to go low to reset the power stage. Some power stages can be
reset by a combination of PWM signals. For these devices, it is recommended to set this bit low, because the VALID pin is
shared for power stages. This provides better control of each power stage.
D5Determines if the power stage needs the TAS5508C VALID pin to go low to mute the power stage. Some power stages can be
muted by a combination of PWM signals. For these devices, it is recommended to set this bit low, because the VALID pin is
shared for power stages. This provides better control of each power stage.
D4Inverts the PWM output. Inverting the PWM output can be an advantage if the power stage input pin is opposite the TAS5508C
PWM pinout. This makes routing on the PCB easier. To keep the phase of the output, the speaker terminals must also be
inverted.
D3The power stage TAS5182 has a special PWM input. To ensure that the TAS5508C has full control in all occasions, the PWM
output must be remapped.
D2Can be used to handle click and pop for some applications.
D1This bit is normally used together with D2. For some power stages, both PWM signals must be high to get the desired operation
of both speaker outputs to be low. This bit sets the PWM outputs high-high during mute.
D0Not used
Table 3-6 lists the optimal setting for each output-stage configuration. Note that the default value is
applicable in all configurations except the TAS5182 SE/BTL configuration.
Table 3-6. Recommended TAS5508C Configurations for Texas Instruments Power Stages
DEVICEERROR RECOVERYCONFIGURATIOND7D6D5D4D3D2D1D0
TAS5111
RES
(default)
AUT
RES
TAS5112
AUT
TAS5182RES
BTL11100000
SE11100000
BTL01100000
SE01100000
BTL11000000
SE11000000
BTL01000000
SE01000000
BTL11101000
SE11101000
RES: To recover from a shutdown, the output stage requires VALID to go low.
AUT: The power stage can auto-recover from a shutdown.
BTL: Bridge-tied load configuration
SE: Single-ended configuration
www.ti.com
3.3.2Headphone Configuration Registers
The headphone configuration controls are identical to the speaker configuration controls. The headphone
configuration control settings are used in place of the speaker configuration control settings for channels 1
and 2 when the headphones are selected. However, only one configuration setting for headphones is
used, and that is the default setting.
3.3.3Audio System Configurations
The TAS5508C can be configured to comply with various audio systems: 5.1-channel system, 6-channel
system, 7.1-channel system, and 8-channel system.
The audio system configuration is set in the general control register (0xE0). Bits D31–D4 must be zero
and D0 is don't care.
D3Determines if SUB is to be controlled by PSVC
D2Enables/disables power-supply volume control
D1Sets number of speakers in the system, including possible line outputs
D3–D1 must be configured for the audio system in the application, as shown in Table 3-7.
Table 3-7. Audio System Configuration (General Control Register 0xE0)
Audio SystemD31–D4D3D2D1D0
6 channels or 5.1 not using PSVC0001X
6 channels using PSVC0011X
5.1 system using PSVC0111X
8 channels or 7.1 not using PSVC (default)0000X
8 channels using PSVC0010X
7.1 system using PSVC0110X
3.3.3.1Using Line Outputs in 6-Channel Configurations
The audio system can be configured for a 6-channel configuration (with 2 lineouts) by writing a 1 to bit D1
of register 0xE0 (general control register). In this configuration, channel-5 and -6 processing are exactly
the same as the other channels, except that the master volume has no effect.
Note that in 6-channel configuration, channels 5 and 6 are unaffected by back-end error (BKND_ERR
goes low).
To use channels 5 and 6 as unprocessed lineouts, the following setup should be done:
•Channel-5 volume and channel-6 volume should be set for a constant output such as 0 dB.
•Bass and treble for channels 5 and 6 can be used if desired.
•DRC1 should be bypassed for channels 5 and 6.
•If enabled, the loudness function shapes the response of channels 5 and 6. However, the amplitude of
5 and 6 is not used in determining the loudness response.
•If a down mix is desired on channels 5 and 6 as lineout, the down mixing can be performed using the
channel-5 and channel-6 input mixers.
•The operation of the channel-5 and -6 biquads is unaffected by the 6-/8-channel configuration setting.
SLES257–SEPTEMBER 2010
3.3.4Recovery from Clock Error
The TAS5508C can be set either to perform a volume ramp up during the recovery sequence of a clock
error or simply to come up in the last state (or desired state if a volume or tone update was in progress).
This feature is enabled via I2C system control register 0x03.
3.3.5Power-Supply Volume-Control Enable
The power-supply volume control (PSVC) can be enabled and disabled via I2C register 0xE0. The
subwoofer PWM output can be configured to be controlled by the PSVC or digitally attenuated when
PSVC is enabled (for powered subwoofer configurations). Note that PSVC cannot be simultaneously
enabled along with unmute outputs after clock error feature.
3.3.6Volume and Mute Update Rate
The TAS5508C has fixed soft volume and mute ramp durations. The ramps are linear. The soft volume
and mute ramp rates are adjustable by programming the I2C register 0xD0 for the appropriate number of
steps to be 512, 1024, or 2048. The update is performed at a fixed rate regardless of the sample rate.
•In normal speed, the update rate is 1 step every 4/Fs seconds.
•In double speed, the update is 1 step every 8/Fs seconds.
•In quad speed, the update is 1 step every 16/Fs seconds.
Because of processor loading, the update rate can increase for some increments by 1/Fs to 3/Fs.
However, the variance of the total time to go from 18 dB to mute is less than 25%.
51246.44 ms42.67 ms
102492.88 ms85.33 ms
2048185.76 ms170.67 ms
3.3.7Modulation Index Limit
PWM modulation is a linear function of the audio signal. When the audio signal is 0, the PWM modulation
is 50%. When the audio signal increases toward full scale, the PWM modulation increases toward 100%.
For negative signals, the PWM modulations fall below 50% toward 0%.
However, there is a limit to the maximum modulation possible. During the offtime period, the power stage
connected to the TAS5508C output needs to get ready for the next ontime period. The maximum possible
modulation is then set by the power stage requirements. All Texas Instruments power stages need
maximum modulation to be 97.7%. This is also the default setting of the TAS5508C. Default settings can
be changed in the modulation index register (0x16).
Note that no change should be made to this register when using Texas Instruments power stages.
3.3.8Interchannel Delay
An 8-bit value can be programmed into each of the eight PWM interchannel delay registers to add a delay
per channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock,
DCLK. The default values are shown in Table 3-9.
This delay is generated in the PWM and can be changed at any time through the serial-control interface
I2C registers 0x1B–0x22. The absolute offset for channel 1 is set in I2C subaddress 0x23.
If used correctly, setting the PWM channel delay can optimize the performance of a
PurePath Digital™ amplifier system . The setting is based on both the type of back-end
power device that is used and the layout. These values are set during initialization using the
I2C serial interface. Unless otherwise noted, use the default values given in Table 3-9.
3.4Master Clock and Serial Data Rate Controls
The TAS5508C functions only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK
(left/right clock) signals that control the flow of data on the four serial data interfaces. The 13.5-MHz
external crystal allows the TAS5508C to detect MCLK and the data rate automatically.
The MCLK frequency can be 64 × Fs, 128 × Fs, 196 × Fs, 256 × Fs, 384 × Fs, 512 × Fs, or 768 × Fs.
The TAS5508C operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK.
However, there is no constraint as to the phase relationship of these signals. The TAS5508C accepts a
64 × Fs SCLK rate and a 1 × Fs LRCLK.
If the phase of SCLK or LRCLK drifts more than ±10 MCLK cycles since the last reset, the TAS5508C
senses a clock error and resynchronizes the clock timing.
The clock and serial data interface have several control parameters:
•MCLK ratio (64 Fs, 128 Fs, 196 Fs, 256 Fs, 384 Fs, 512 Fs, or 768 Fs) – I2C parameter
•AM mode enable/disable – I2C parameter
During AM interference avoidance, the clock control circuitry uses three other configuration inputs:
•Tuned AM frequency (for AM interference avoidance) (550 - 1750 kHz) – I2C parameter
•Frequency set select (1–4) – I2C parameter
•Sample rate – I2C parameter or auto-detected
3.4.1PLL Operation
The TAS5508C uses two internal clocks generated by two internal phase-locked loops (PLLs), the digital
PLL (DPLL) and the analog PLL (APLL). The APLL provides the reference clock for the PWM. The DPLL
provides the reference clock for the digital audio processor and the control logic.
SLES257–SEPTEMBER 2010
The master clock MCLK input provides the input reference clock for the APLL. The external 13.5-MHz
crystal provides the input reference clock for the DPLL. The crystal provides a time base to support a
number of operations, including the detection of the MCLK ratio, the data rate, and clock error conditions.
The crystal time base provides a constant rate for all controls and signal timing.
Even if MCLK is not present, the TAS5508C can receive and store I2C commands and provide status.
3.5Bank Controls
The TAS5508C permits the user to specify and assign sample-rate-dependent parameters for biquad,
loudness, DRC, and tone in one of three banks that can be manually selected or selected automatically
based on the data sampling rate. Each bank can be enabled for one or more specific sample rates via I2C
bank control register 0x40. Each bank set holds the following values:
•Coefficients for seven biquads (7 × 5 = 35 coefficients) for each of the eight channels (registers
0x51–0x88)
•Coefficients for one loudness biquad (register 0x95)
•DRC1 energy and (1 – energy) values (register 0x98)
The default selection for bank control is manual bank with bank 1 selected. Note that if bank switching is
used, bank 2 and bank 3 must be programmed on power up, because the default values are all zeroes. If
bank switching is used and bank 2 and bank 3 are not programmed correctly, then the output of the
TAS5508C could be muted when switching to those banks.
The three bank selection bits of the bank control register allow the appropriate bank to be manually
selected (000 = bank 1, 001 = bank 2, 010 = bank 3). In the manual mode, when a write occurs to the
biquad, DRC, or loudness coefficients, the currently selected bank is updated. If audio data is streaming to
the TAS5508C during a manual bank selection, the TAS5508C first performs a mute sequence, then
performs the bank switch, and finally restores the volume using an unmute sequence.
A mute command initiated by the bank-switch mute sequence overrides an unmute command or a volume
command. While a mute is active, the commanded channels are muted. When a channel is unmuted, the
volume level goes to the last commanded volume setting that has been received for that channel.
If MCLK or SCLK is stopped, the TAS5508C performs a bank-switch operation. If the clocks start up once
the manual bank-switch command has been received, the bank-switch operation is performed during the
5-ms, silent-start sequence.
3.5.2Automatic Bank Selection
To enable automatic bank selection, a value of 3 is written into the bank selection bits of the bank control
register. Banks are associated with one or more sample rates by writing values into the bank 1 or bank 2
data-rate selection registers. The automatic bank selection is performed when a frequency change is
detected according to the following scheme:
1. The system scans bank-1 data-rate associations to see if bank 1 is assigned for that data rate.
2. If bank 1 is assigned, then the bank-1 coefficients are loaded.
3. If bank 1 is not assigned, the system scans bank 2 to see if bank 2 is assigned for that data rate.
4. If bank 2 is assigned, the bank 2 coefficients are loaded.
5. If bank 2 is not assigned, the system loads the bank 3 coefficients.
www.ti.com
The default is that all frequencies are enabled for bank 1. This default is expressed as a value of all 1s in
the bank-1 auto-selection byte and all 0s in the bank-2 auto-selection byte.
3.5.2.1Coefficient Write Operations While Automatic Bank Switch Is Enabled
In automatic mode, if a write occurs to the tone, EQ, DRC, or loudness coefficients, the bank that is
written to is the current bank.
3.5.3Bank Set
Bank set is used to provide a secure way to update the bank coefficients in both the manual and
automatic switching modes without causing a bank switch to occur. Bank-set mode does not alter the
current bank register mapping. It simply enables any bank coefficients to be updated while inhibiting any
bank switches from taking place. In manual mode, this enables the coefficients to be set without switching
banks. In automatic mode, this prevents a clock error or data rate change from corrupting a bank
coefficient write.
To update the coefficients of a bank, a value of 4, 5, or 6 is written into in the bank selection-bits of the
bank control register. This enables the tone, EQ, DRC, and loudness coefficient values of bank 1, 2, or 3,
respectively, to be updated.
Once the coefficients of the bank have been updated, the bank-selection bits are then returned to the
desired manual or automatic bank-selection mode.
3.5.4Bank-Switch Timeline
After a bank switch is initiated (manual or automatic), no I2C writes to the TAS5508C should occur before
a minimum of 186 ms. This value is determined by the volume ramp rates for a particular sample rate.
Problem: The audio unit containing a TAS5508C needs to handle different audio formats with different
sample rates. Format #1 requires Fs = 32 kHz, format #2 requires Fs = 44.1 kHz, and format #3 requires
Fs = 48 kHz. The sample-rate-dependent parameters in the TAS5508C require different coefficients and
data depending on the sample rate.
Strategy: Use the TAS5508C bank-switching feature to allow for managing and switching three banks
associated with the three sample rates, 32 kHz (bank 1), 44.1 kHz (bank 2), and 48 kHz (bank 3).
One possible algorithm is to generate, load, and automatically manage bank switching for this problem:
1. Generate bank-related coefficients for sample rates of 32 kHz, 44.1 kHz, and 48 kHz, and include the
same in the microprocessor-based TAS5508C I2C firmware.
2. On TAS5508C power up or reset, the microprocessor runs the following TAS5508C initialization code:
(a) Update bank 1 (write 0x00048040 to register 0x40).
(b) Write bank-related I2C registers with appropriate values for bank 1.
(c) Write bank 2 (write 0x0005 8040 to register 0x40).
(d) Load bank-related I2C registers with appropriate values for bank 2.
(e) Write bank 3 (write 0x00068040 to register 0x40).
(f) Load bank-related I2C registers with appropriate values for bank 3.
(g) Select automatic bank switching (write 0x0003 8040 to register 0x40).
3. When the audio media changes, the TAS5508C automatically detects the incoming sample rate and
automatically switches to the appropriate bank.
SLES257–SEPTEMBER 2010
In this example, any sample rates other than 32 kHz and 44.1 kHz use bank 3. If other sample rates are
used, then the banks must be set up differently.
3.5.6Bank-Switching Example 2
Problem: The audio system uses all of the sample rates supported by the TAS5508C. How can the
automatic bank switching be set up to handle this situation?
Strategy: Use the TAS5508C bank-switching feature to allow for managing and switching three banks
associated with sample rates as follows:
•Bank 1: Coefficients for 32 kHz, 38 kHz, 44.1 kHz, and 48 kHz
•Bank 2: Coefficients for 88.2kHz and 96 kHz
•Bank 3: Coefficients for 176.4 kHz and 192 kHz
One possible algorithm is to generate, load, and automatically manage bank switching for this problem:
1. Generate bank-related coefficients for sample rates 48 kHz (bank 1), 96 kHz (bank 2), and 192 kHz
(bank 3) and include the same in the microprocessor-based TAS5508C I2C firmware.
2. On TAS5508C power up or reset, the microprocessor runs the following TAS5508C initialization code:
(a) Update bank 1 (write 0x0004F00C to register 0x40).
(b) Write bank-related I2C registers with appropriate values for bank 1.
(c) Write bank 2 (write 0x0005 F00C to register 0x40).
(d) Load bank-related I2C registers with appropriate values for bank 2.
(e) Write bank 3 (write 0x0006F00C to register 0x40).
(f) Load bank-related I2C registers with appropriate values for bank 3.
(g) Select automatic bank switching (write 0x0003 F00C to register 0x40).
3. When the audio media changes, the TAS5508C automatically detects the incoming sample rate and
automatically switches to the appropriate bank.
Supply voltage, DVDD and DVD_PWM–0.3 V to 3.6 V
Supply voltage, AVDD_PLL–0.3 V to 3.6 V
3.3-V digital input–0.5 V to DVDD + 0.5 V
Input voltage5 V tolerant
1.8 V LVCMOS
I
IK
I
OK
T
A
T
stg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
(2) 5-V tolerant inputs are RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL.
(3) VRA_PLL, VRD_PLL, VR_DPLL, VR_DIG, VR_PWM
(4) VREF is a 1.8-V supply derived from regulators internal to the TAS5508C chip. VREF is on terminals VRA_PLL, VRD_PLL, VR_DPLL,
Input clamp current (VI< 0 or VI> 1.8 V±20 mA
Output clamp current (VO< 0 or VO> 1.8 V)±20 mA
Operating free-air temperature0°C to 70°C
Storage temperature range–65°C to 150°C
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VR_DIG, and VR_PWM. These terminals are provided to permit use of external filter capacitors, but should not be used to source power
to external devices.
Timing characteristics for I2C interface signals over recommended operating conditions
PARAMETERTEST CONDITIONSMINMAXUNIT
f
t
t
t
t
t
t
t
t
t
t
C
SCL
w(H)
w(L)
r
f
su1
h1
(buf)
su2
h2
su3
L
Frequency, SCLNo wait states400kHz
Pulse duration, SCL high0.6ms
Pulse duration, SCL low1.3ms
Rise time, SCL and SDA300ns
Fall time, SCL and SDA300ns
Setup time, SDA to SCL100ns
Hold time, SCL to SDA0ns
Bus free time between stop and start condition1.3ms
Setup time, SCL to start condition0.6ms
Hold time, start condition to SCL0.6ms
Setup time, SCL to stop condition0.6ms
Load capacitance for each bus line400pF
Control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMINMAXUNIT
Maximum attenuation before mute–127dB
Maximum gainIndividual volume, master volume18dB
Maximum volume before the onset of clipping0-dB input, any modulation limit0dB
PSVC rangePSVC enabled12, 18, or 24dB
PSVC rateFs
PSVC modulationSingle sided
PSVC quantization2048Steps
PSVC PWM modulation limitsPSVC range = 24 dBdB
Individual volume, master volume, or a
combination of both
6%95%
(120 : 2048)(1944 : 2048)
4.8Serial Audio Interface Control and Timing
4.8.1I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 64 × Fs is
used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the
first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS5508C masks unused trailing data bit positions.
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 64
× Fs is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles.
The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5508C masks unused
trailing data bit positions.
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
64 × Fs is used to clock in the data. The first bit of data appears on the data lines eight bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5508C
masks unused leading data bit positions.
The TAS5508C has a bidirectional I2C interface that is compatible with the Inter-IC (I2C) bus protocol and
supports both 100-kbps and 400-kbps data transfer rates for single- and multiple-byte write and read
operations. This is a slave-only device that does not support a multimaster bus environment or wait state
insertion. The control interface is used to program the registers of the device and to read device status.
The TAS5508C supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus
operation (400 kHz maximum). The TAS5508C performs all I2C operations without I2C wait cycles.
5.1General I2C Operation
The I2C bus employs two signals—SDA (data) and SCL (clock)—to communicate between integrated
circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data can be
transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte
transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer
operation begins with the master device driving a start condition on the bus and ends with the master
device driving a stop condition on the bus. The bus uses transitions on SDA while the clock is high to
indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high
transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period.
These conditions are shown in Figure 5-1. The master generates the 7-bit slave address and the
read/write (R/W) bit to open communication with another device and then wait for an acknowledge
condition. The TAS5508C holds SDA low during the acknowledge clock period to indicate an
acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is
addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same
signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for
the SDA and SCL signals to set the high level for the bus.
SLES257–SEPTEMBER 2010
Figure 5-1. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When
the last word transfers, the master generates a stop condition to release the bus. A generic data transfer
sequence is shown in Figure 5-1.
The 7-bit address for the TAS5508C is 0011011.
5.2Single- and Multiple-Byte Transfers
The serial-control interface supports both single-byte and multiple-byte read/write operations for status
registers and the general control registers associated with the PWM. However, for the DAP data
processing registers, the serial-control interface supports only multiple-byte (four-byte) read/write
operations.
During multiple-byte read operations, the TAS5508C responds with data, a byte at a time, starting at the
subaddress assigned, as long as the master device continues to respond with acknowledges. If a
particular subaddress does not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the TAS5508C compares the number of bytes transmitted to the
number of bytes that are required for each specific subaddress. If a write command is received for a
biquad subaddress, the TAS5508C expects to receive five 32-bit words. If fewer than five 32-bit data
words have been received when a stop command (or another start command) is received, the data
received is discarded. Similarly, if a write command is received for a mixer coefficient, the TAS5508C
expects to receive one 32-bit word.
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The
TAS5508C also supports sequential I2C addressing. For write transactions, if a subaddress is issued
followed by data for that subaddress and the 15 subaddresses that follow, a sequential I2C write
transaction has taken place, and the data for all 16 subaddresses is successfully received by the
TAS5508C. For I2C sequential write transactions, the subaddress then serves as the start address and the
amount of data subsequently transmitted, before a stop or start is transmitted, determines how many
subaddresses are written. As is true for random addressing, sequential addressing requires that a
complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data
for the last subaddress is discarded. However, all other data written is accepted; only the incomplete data
is discarded.
5.3Single-Byte Write
As shown in Figure 5-2, a single-byte, data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the
direction of the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct
I2C device address and the read/write bit, the TAS5508C device responds with an acknowledge bit. Next,
the master transmits the address byte or bytes corresponding to the TAS5508C internal memory address
being accessed. After receiving the address byte, the TAS5508C again responds with an acknowledge bit.
Next, the master device transmits the data byte to be written to the memory address being accessed. After
receiving the data byte, the TAS5508C again responds with an acknowledge bit. Finally, the master
device transmits a stop condition to complete the single-byte, data-write transfer.
www.ti.com
Figure 5-2. Single-Byte Write Transfer
5.4Multiple-Byte Write
A multiple-byte, data-write transfer is identical to a single-byte, data-write transfer except that multiple data
bytes are transmitted by the master device to TAS5508C, as shown in Figure 5-3. After receiving each
data byte, the TAS5508C responds with an acknowledge bit.
The I2C supports a special mode which permits I2C write operations to be broken up into multiple data
write operations that are multiples of four data bytes. These are 6-byte, 10-byte, 14-byte, 18-byte, etc.,
write operations that are composed of a device address, read/write bit, subaddress, and any multiple of
four bytes of data. This permits the system to write large register values incrementally without blocking
other I2C transactions.
This feature is enabled by the append subaddress function in the TAS5508C. This function enables the
TAS5508C to append four bytes of data to a register that was opened by a previous I2C register write
operation but has not received its complete number of data bytes. Because the length of the long registers
is a multiple of four bytes, using four-byte transfers has only an integral number of append operations.
When the correct number of bytes has been received, the TAS5508C starts processing the data.
The procedure to perform an incremental multibyte-write operation is as follows:
1. Start a normal I2C write operation by sending the device address, write bit, register subaddress, and
the first four bytes of the data to be written. At the end of that sequence, send a stop condition. At this
point, the register has been opened and accepts the remaining data that is sent by writing four-byte
blocks of data to the append subaddress (0xFE).
2. At a later time, one or more append data transfers are performed to incrementally transfer the
remaining number of bytes in sequential order to complete the register write operation. Each of these
append operations is composed of the device address, write bit, append subaddress (0xFE), and four
bytes of data followed by a stop condition.
3. The operation is terminated due to an error condition, and the data is flushed:
(a) If a new subaddress is written to the TAS5508C before the correct number of bytes are written.
(b) If more or fewer than four bytes are data written at the beginning or during any of the append
operations.
(c) If a read bit is sent.
SLES257–SEPTEMBER 2010
5.6Single-Byte Read
As shown in Figure 5-4, a single-byte, data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write
and then a read are actually performed. Initially, a write is performed to transfer the address byte or bytes
of the internal memory address to be read. As a result, the read/write bit is a 0. After receiving the
TAS5508C address and the read/write bit, the TAS5508C responds with an acknowledge bit. In addition,
after sending the internal memory address byte or bytes, the master device transmits another start
condition followed by the TAS5508C address and the read/write bit again. This time the read/write bit is a
1, indicating a read transfer. After receiving the TAS5508C and the read/write bit the TAS5508C again
responds with an acknowledge bit. Next, the TAS5508C transmits the data byte from the memory address
being read. After receiving the data byte, the master device transmits a not acknowledge followed by a
stop condition to complete the single-byte, data-read transfer.
A multiple-byte, data-read transfer is identical to a single-byte, data-read transfer except that multiple data
bytes are transmitted by the TAS5508C to the master device, as shown in Figure 5-5. Except for the last
data byte, the master device responds with an acknowledge bit after receiving each data byte.
0x51–0x8820/reg.Biquad filter registerCh1–Ch8 biquad filter coefficientsAll biquads = All pass for all channels
0x89–0x908Bass and treble bypassBypass bass and treble for Ch1–Ch8Bassand treble bypassed for all channels
0xAA8sel op1–8 and mix to PWM1 Select 0 to 2 of eight channels toMix channels to PWM1
0xAB8sel op1–8 and mix to PWM2 Select 0 to 2 of eight channels toMix channels to PWM2
0xAC8sel op1–8 and mix to PWM3 Select 0 to 2 of eight channels toMix channels to PWM3
0xAD8sel op1–8 and mix to PWM4 Select 0 to 2 of eight channels toMix channels to PWM4
0xAE8sel op1–8 and mix to PWM5 Select 0 to 2 of eight channels toMix channels to PWM5
0xAF8sel op1–8 and mix to PWM6 Select 0 to 2 of eight channels toMix channels to PWM6
0xB012sel op1–8 and mix to PWM7 Select 0 to 3 of eight channels toMix channels to PWM7
0xB112sel op1–8 and mix to PWM8 Select 0 to 3 of eight channels toMix channels to PWM8
0xB2–0xCEReserved
0xCF20Volume biquadVolume biquadAll pass
0xD04Volume, treble, and bassu [31:24], u [23:16], u [15:12]0x00, 0x00, 0x02, 0x3F
0xD14Ch1 volumeCh1 volume0 dB
0xD24Ch2 volumeCh2 volume0 dB
0xD34Ch3 volumeCh3 volume0 dB
0xD44Ch4 volumeCh4 volume0 dB
0xD54Ch5 volumeCh5 volume0 dB
0xD64Ch6 volumeCh6 volume0 dB
0xD74Ch7 volumeCh7 volume0 dB
0xD84Ch8 volumeCh8 volume0 dB
TOTAL
BYTES
REGISTER FIELDSDESCRIPTION OF CONTENTSDEFAULT STATE
0xDA4Bass filter set registerBass filter set (all channels)Filter set 3
0xDB4Bass filter index registerBass filter level (all channels)0 dB
0xDC4Treble filter set registerTreble filter set (all channels)Filter set 3
0xDD4Treble filter index registerTreble filter level (all channels)0 dB
0xDE4AM mode registerSet up AM mode for AM-interferenceAM mode disabled
0xDF4PSVC range registerSet PSVC control range12-dB control range
0xE04General control register6- or 8-channel configuration, PSVC8-channel configuration
Unless otherwise noted, the I2C register default values are in bold font.
Note that u indicates unused bits.
7.1Clock Control Register (0x00)
Bit D1 is Don't Care.
Table 7-1. Clock Control Register Format
D7D6D5D4D3D2D1D0FUNCTION
000––––32-kHz data rate
001––––38-kHz data rate
010––––44.1-kHz data rate
011––––48-kHz data rate
100––––88.2-kHz data rate
101––––96-kHz data rate
110––––176.4-kHz data rate
111––––192-kHz data rate
–––000MCLK frequency = 64
–––001MCLK frequency = 128
–––010MCLK frequency = 192
–––011MCLK frequency = 256
–––100MCLK frequency = 384
–––101MCLK frequency = 512
–––110MCLK frequency = 768
–––111Reserved
––––––1Clock register is valid (read-only)
Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software
must clear the register (write zeroes) and then read them to determine if there are any persistent errors.
Table 7-6. Channel Configuration Control Register Format
D7D6D5D4D3D2D1D0FUNCTION
0––––––Disable back-end reset sequence for a channel – BEErrorRecEn
1––––––Enable back-end reset sequence for a channel
–0–––––Valid does not have to be low for this channel to be reset BEValidRst
–1–––––Valid must be low for this channel to be reset
––0––––Valid does not have to be low for this channel to be muted BEValidMute
––1––––Valid must be low for this channel to be muted
–––0–––Normal BEPolarity
–––1–––Switches PWM+ and PWM– and inverts audio signal
––––0––Do not remap output to comply with 5182 interface
––––1––Remap output to comply with 5182 interface
–––––0–Do not go to low-low in mute – BELowMute
–––––1–Go to low-low in mute
––––––0Do not remap Hi-Z state to low-low state – BE5111BsMute
––––––1Remap Hi-Z state to low-low state
7.7Headphone Configuration Control Register (0x0D)
Bit D0 is Don't Care.
Table 7-7. Headphone Configuration Control Register Format
D7D6D5D4D3D2D1D0FUNCTION
0––––––Disable back-end reset sequence for a channel – BEErrorRecEn
1––––––Enable back-end reset sequence for a channel
–0–––––Valid does not have to be low for this channel to be reset
–1–––––Valid must be low for this channel to be reset
––0––––Valid does not have to be low for this channel to be muted
––1––––Valid must be low for this channel to be muted
–––0–––Normal BEPolarity
–––1–––Switches PWM+ and PWM– and inverts audio signal
––––0––Do not remap output to comply with 5182 interface
––––1––Remap output to comply with 5182 interface
–––––0–Do not go to low-low in mute – BELowMute
–––––1–Go to low-low in mute
––––––0Do not remap Hi-Z state to low-low state – BE5111BsMute
––––––1Remap Hi-Z state to low-low state
BEValidRst
BEValidMute
7.8Serial Data Interface Control Register (0x0E)
Nine serial modes can be programmed via the I2C interface.
Table 7-8. Serial Data Interface Control Register Format
––––0000Set input automute and PWM automute delay to 1 ms
––––0001Set input automute and PWM automute delay to 2 ms
––––0010Set input automute and PWM automute delay to 3 ms
––––0011Set input automute and PWM automute delay to 4 ms
––––0100Set input automute and PWM automute delay to 5 ms
––––0101Set input automute and PWM automute delay to 10 ms
––––0110Set input automute and PWM automute delay to 20 ms
––––0111Set input automute and PWM automute delay to 30 ms
––––1000Set input automute and PWM automute delay to 40 ms
––––1001Set input automute and PWM automute delay to 50 ms
––––1010Set input automute and PWM automute delay to 60 ms
––––1011Set input automute and PWM automute delay to 70ms
––––1100Set input automute and PWM automute delay to 80 ms
––––1101Set input automute and PWM automute delay to 90 ms
––––1110Set input automute and PWM automute delay to 100 ms
––––1111Set input automute and PWM automute delay to 110 ms
0000–––
0001––––
0010––––Set input automute threshold less than bit 2
0011––––Set input automute threshold less than bit 3
0100––––Set input automute threshold less than bit 4
0101––––Set input automute threshold less than bit 5
0110––––Set input automute threshold less than bit 6
0111––––Set input automute threshold less than bit 7
1000––––Set input automute threshold less than bit 8
1001––––Set input automute threshold less than bit 9
1010––––Set input automute threshold less than bit 10
1011––––Set input automute threshold less than bit 11
1100––––Set input automute threshold less than bit 12
1101––––Set input automute threshold less than bit 13
1110––––Set input automute threshold less than bit 14
1111––––Set input automute threshold less than bit 15
Set input automute threshold less than bit 1 (zero input signal), lowest
automute threshold.
7.11 Automute PWM Threshold and Back-End Reset Period Register (0x15)
Table 7-11. Automute PWM Threshold and Back-End Reset Period Register Format
D7D6D5D4D3D2D1D0FUNCTION
0000––––Set PWM automute threshold equal to input automute threshold
0001––––Set PWM automute threshold 1 bit more than input automute threshold
0010––––Set PWM automute threshold 2 bits more than input automute threshold
0011––––Set PWM automute threshold 3 bits more than input automute threshold
0100––––Set PWM automute threshold 4 bits more than input automute threshold
0101––––Set PWM automute threshold 5 bits more than input automute threshold
0110––––Set PWM automute threshold 6 bits more than input automute threshold
0111––––Set PWM automute threshold 7 bits more than input automute threshold
1000––––Set PWM automute threshold equal to input automute threshold
1001––––Set PWM automute threshold 1 bit less than input automute threshold
1010––––Set PWM automute threshold 2 bits less than input automute threshold
1011––––Set PWM automute threshold 3 bits less than input automute threshold
1100––––Set PWM automute threshold 4 bits less than input automute threshold
1101––––Set PWM automute threshold 5 bits less than input automute threshold
1110––––Set PWM automute threshold 6 bits less than input automute threshold
1111––––Set PWM automute threshold 7 bits less than input automute threshold
––––0000Set back-end reset period < 1 ms
––––0001Set back-end reset period 1 ms
––––0010Set back-end reset period 2 ms
––––0011Set back-end reset period 3 ms
––––0100Set back-end reset period 4 ms
––––0101Set back-end reset period 5 ms
––––0110Set back-end reset period 6 ms
––––0111Set back-end reset period 7 ms
––––1000Set back-end reset period 8 ms
––––1001Set back-end reset period 9 ms
––––1010Set back-end reset period 10 ms
––––1011Set back-end reset period 10 ms
––––11XXSet back-end reset period 10 ms
100000Default value for channel 1 = –32
000000Default value for channel 2 = 0
110000Default value for channel 3 = –16
010000Default value for channel 4 = 16
101000Default value for channel 5 = –24
001000Default value for channel 6 = 8
111000Default value for channel 7 = –8
011000Default value for channel 8 = 24
7.14 Channel Offset Register (0x23)
The channel offset register is mapped into 0x23.
Table 7-14. Channel Offset Register Format
D7D6D5D4D3D2D1D0Function
00000000Minimum absolute offset, 0 DCLK cycles, default for channel 1
Table 7-15. Bank-Switching Command Register Format
D31D30D29D28D27D26D25D24FUNCTION
Unused bits
D23D22D21D20D19D18D17D16FUNCTION
–000Manual selection bank 1
–001Manual selection bank 2
–010Manual selection bank 3
–011Automatic bank selection
–100Update the values in bank 1
–101Update the values in bank 2
–110Update the values in bank 3
–111Update only the bank map
0xxxUpdate the bank map using values in D15–D0
1xxxDo not update the bank map using values in D15–D0
D15D14D13D12D11D10D9D8FUNCTION
1–––––––32-kHz data rate—use bank 1
–1––––––38-kHz data rate—use bank 1
––1–––––44.1-kHz data rate—use bank 1
–––1––––48-kHz data rate—use bank 1
––––1–––88.2-kHz data rate—use bank 1
–––––1––96-kHz data rate—use bank 1
––––––1–176.4-kHz data rate—use bank 1
–––––––1192-kHz data rate—use bank 1
11111111Default
www.ti.com
D7D6D5D4D3D2D1D0FUNCTION
1–––––––32-kHz data rate—use bank 2
–1––––––38-kHz data rate—use bank 2
––1–––––44.1-kHz data rate—use bank 2
–––1––––48-kHz data rate—use bank 2
––––1–––88.2-kHz data rate—use bank 2
–––––1––96-kHz data rate—use bank 2
––––––1–176.4-kHz data rate—use bank 2
–––––––1192-kHz data rate—use bank 2
Input mixers 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
and 0x48, respectively.
Each gain coefficient is in 28-bit (5.23) format so 0x80 0000 is a gain of 1. Each gain coefficient is written
as a 32-bit word with the upper four bits not used. For 8-gain coefficients, the total is 32 bytes.
Bold indicates the one channel that is passed through the mixer.
Registers 0x49–0x50 provide configuration control for bass mangement.
Each gain coefficient is in 28-bit (5.23) format so 0x80 0000 is a gain of 1. Each gain coefficient is written
as a 32-bit word with the upper four bits not used.
0x51–0x5720/reg.Ch1_bq[1:7]Ch1 biquads 1–7. See Table 7-19 for bit definition.See Table 7-19
0x58–0x5E20/reg. Ch2_bq[1:7]Ch2 biquads 1–7. See Table 7-19 for bit definition.See Table 7-19
0x5F–0x6520/reg. Ch3_bq[1:7]Ch3 biquads 1–7. See Table 7-19 for bit definition.See Table 7-19
0x66–0x6C20/reg.Ch4_bq[1:7]Ch4 biquads 1–7. See Table 7-19 for bit definition.See Table 7-19
0x6D–0x7320/reg.Ch5_bq[1:7]Ch5 biquads 1–7. See Table 7-19 for bit definition.See Table 7-19
0x74–0x7A20/reg. Ch6_bq[1:7]Ch6 biquads 1–7. See Table 7-19 for bit definition.See Table 7-19
0x7B–0x8120/reg. Ch7_bq[1:7]Ch7 biquads 1–7. See Table 7-19 for bit definition.See Table 7-19
0x82–0x8820/reg.Ch8_bq[1:7]Ch8 biquads 1–7. See Table 7-19 for bit definition.See Table 7-19
Each gain coefficient is in 28-bit (5.23) format so 0x80 0000 is a gain of 1. Each gain coefficient is written
as a 32-bit word with the upper four bits not used.
Table 7-19. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass)
7.19 Bass and Treble Bypass Register, Channels 1–8 (0x89–0x90)
Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F,
and 0x90, respectively. Eight bytes are written for each channel. Each gain coefficient is in 28-bit (5.23)
format so 0x80 0000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits
not used.
Table 7-20. Channel 1–8 Bass and Treble Bypass Register Format
DRC bypass/inline for channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0xA2, 0xA3, 0xA4,
0xA5, 0xA6, 0xA7, 0xA8, and 0xA9, respectively. Eight bytes are written for each channel. Each gain
coefficient is in 28-bit (5.23) format, so 0x0080 0000 is a gain of 1. Each gain coefficient is written as a
32-bit word with the upper 4 bits not used.
To enable DRC for a given channel (with unity gain), bypass = 0x0000 0000 and inline = 0x0080 0000.
To disable DRC for a given channel, bypass = 0x00800000 and inline = 0x0000 0000.
Table 7-31. Output Mixer Register Format (Lower 4 Bytes) (continued)
D31D30D29D28D27D26D25D24FUNCTION
0100Select channel 5 to output mixer
0101Select channel 6 to output mixer
0110Select channel 7 to output mixer
0111Select channel 8 to output mixer
G27G26G25G24Selected channel gain (upper 4 bits)
D23D22D21D20D19D18D17D16FUNCTION
G23G22G21G20G19G18G17G16Selected channel gain (continued)
D15D14D13D12D11D10D9D8FUNCTION
G15G14G13G12G11G10G9G8Selected channel gain (continued)
D7D6D5D4D3D2D1D0FUNCTION
G7G6G5G4G3G2G1G0Selected channel gain (lower 8 bits)
7.28 Volume Biquad Register (0xCF)
Each gain coefficient is in 28-bit (5.23) format so 0x80 0000 is a gain of 1. Each gain coefficient is written
as a 32-bit word with the upper four bits not used.
SLES257–SEPTEMBER 2010
Table 7-32. Volume Biquad Register Format (Default = All-Pass)
7.29 Volume, Treble, and Bass Slew Rates Register (0xD0)
Table 7-33. Volume Gain Update Rate (Slew Rate)
D31–D10D9D8FUNCTION
000512-step update at 4 Fs, 42.6 ms at 48 kHz
0011024-step update at 4 Fs, 85.3 ms at 48 kHz
0102048-step update at 4 Fs, 170 ms at 48 kHz
0112048-step update at 4 Fs, 170 ms at 48 kHz
Table 7-34. Treble and Bass Gain Step Size (Slew Rate)
D7D6D5D4D3D2D1D0FUNCTION
00000000No operation
00000011
00000100Minimum rate – Updates every 0.083 ms (every LRCLK at 48 kHz)
00100000Updates every 0.67 ms (32 LRCLKs at 48 kHz)
00111111Default rate - Updates every 1.31 ms (63 LRCLKs at 48 kHz). This is the
maximum constant time that can be set for all sample rates.
11111111Maximum rate – Updates every 5.08 ms (every 255 LRCLKs at 48 kHz)
7.30 Volume Registers (0xD1–0xD9)
www.ti.com
Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7,
and 0xD8, respectively. The default volume for all channels is 0 dB.
Master volume is mapped into register 0xD9. The default for the master volume is mute.
Bits D31–D12 are Don't Care.
00012.04-dB control range for PSVC
00118.06-dB control range for PSVC
01024.08-dB control range for PSVC
011Ignore – retain last value
7.37 General Control Register (0xE0)
Bits D31–D4 are zero. Bit D0 is Don't Care.
Table 7-53. General Control Register Format
D31–D4D3D2D1D0FUNCTION
0–08-channel configuration
0–16-channel configuration
00–Power-supply volume control disabled
01–Power-supply volume control enabled
00––Subwoofer part of PSVC
01––Subwoofer separate from PSVC