Texas Instruments TAS5508-5121K8EVM, TAS5121 User Manual

TAS5508−5121K8EVM
Evaluation Module for the TAS5508B 8-Channel Digital Audio PWM Processor and the TAS5121 Digital Amplifier Power Output Stage
User’s Guide
IMPORTANT NOTICE
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
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DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
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Mailing Address: Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright © 2006, Texas Instruments Incorporated
EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:.
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished endproduct fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete in terms of required design, marketing, and/or manufacturingrelated protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/or safety programs, please contact the TI application engineer or visit www.ti.com/esh
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used.
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished endproduct fit for general consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference.
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
.
FCC WARNING
Copyright © 2006, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 0–29.5 V and the output voltage range of 15–20 V for the system supply.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 75°C. The EVM is designed to operate properly with certain components above 75°C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User’s Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments Post Office Box 655303 Dallas, Texas 75265
Copyright © 2006, Texas Instruments Incorporated
About This Manual
This manual describes the operation of the TAS55085121K8EVM evaluation module from Texas Instruments.
How to Use This Manual
This document contains the following chapters:
- Chapter 1 — Overview
- Chapter 2 — System Interfaces
- Chapter 3 — Protection
Preface
Read This First
Information About Cautions and Warnings
This manual may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially cause harm to you
The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully.
.
Read This First
iii
Related Documentation From Texas Instruments
The following table contains a list of data manuals that have detailed descriptions of the integrated circuits used in the design of the TAS55085121K8EVM. The data manuals can be obtained at the URL http://www.ti.com.
Part Number Literature Number
TAS5508B SLES162
TAS5121 SLES086
TLV272 SLOS351
SN74LVC1G00 SCES212
SN74LVC1G08 SCES217
SN74LVC2G08 SCES198
SN74LVC1G14 SCES218
SN74LV123A SCLS393
SN74LVC125A SCAS290
SN74LVC1G126A SCES211
LM317M SLVS297
TPS3801K33 SLVS219
TPS76733 SLVS208
Additional Documentation
TAS55085121K8EVM Application Report (SLEA034A)
PC Configuration Tool for TAS5508B (TAS5508 GUI ver.2.1 or later)
General Application Notes
FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference.
Trademarks
Equibit, PowerPAD, and PurePath Digital are trademarks of Texas Instruments.
iv
Contents
1 Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 TAS55085121K8EVM Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 PCB Key Map 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 System Interfaces 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Power Supply (PSU) Interface (J70, J71, and J73) 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 PSU Control Interface (J72) 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Loudspeaker Connectors (J100 . . . J800) 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Line Out Connectors (J950 and J951) 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Headphone Connector (J900) 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Line Output Select (J50) 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Headphone Select (J32) 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Control Interface (J30) 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Digital Audio Interface (J40) 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Protection 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Short-Circuit Protection and Fault-Reporting Circuitry 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Device Fault Reporting 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
v
Figures
11 Integrated PurePath Digitalt Amplifier System 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 Physical Structure for the TAS55085121K8EVM (Rough Outline) 1-3. . . . . . . . . . . . . . . . . . .
21 Recommended Power-Up Sequence 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22 J71 and J70 Pin Numbers 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23 J73 Pin Numbers 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24 J72 Pin Numbers 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25 J100 . . . J800 Pin Numbers 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26 J950 and J951 Pin Numbers 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27 J900 Pin Numbers 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28 J50 Pin Numbers 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29 J32 Pin Numbers 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
21 Recommended Supply Voltages 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22 J71 Pin Description 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23 J70 Pin Description 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24 J73 Pin Description 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25 J72 Pin Description 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26 J100 . . . J800 Pin Description 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27 J950 and J952 Pin Description 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28 J900 Pin Description 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29 J50 Pin Description 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
210 J32 Pin Description 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
211 J30 Pin Description 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
212 J40 Pin Description 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31 Channel Allocation 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32 TAS5121 Warning/Error Signal Decoding 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
Chapter 1
Overview
The TAS55085121K8EVM PurePath Digital customer evaluation amplifier module demonstrates two audio integrated circuits, TAS5508B and TAS5121, from Texas Instruments (TI).
The TAS5508BPAG is a high-performance 32-bit (24-bit input) multichannel PurePath Digital pulse width modulator (PWM) based on Equibittechnology, with a new fully symmetrical AD modulation scheme. It accepts an input sample rate from 32 kHz to 192 kHz. The device also has digital audio processing (DAP) that provides 48-bit signal processing, advanced performance, and a high level of system integration. The device has interfaces for headphone output and power supply volume control (PSVC).
The TAS5121DKD is a compact, high-power, digital amplifier power stage designed to drive a 4-Ω loudspeaker up to 100 W (10% THD+N). The TAS5121DKD contains integrated gate drivers, four matched and electrically isolated enhancement-mode N-channel power DMOS transistors, and protection/fault-reporting circuitry.
The DKD package has a PowerPAD on the top side for heat transfer through a heatsink. The heatsink in this design is for evaluation purpose only.
This EVM, together with a TI input board, is a complete 8-channel digital audio amplifier system, which includes digital input (S/PDIF), analog inputs, interface to PC, and DAP features, such as digital volume control, input and output mixers, auto mute, equalization, tone controls, loudness, dynamic range compression, and PSVC output. There are configuration options for stereo line level output, stereo headphone output, and power-stage failure protection.
This 7.1 system is designed for home-theater applications, such as A/V receivers, DVD minicomponent systems, home theater in a box (HTIB), DVD receivers, or plasma display panels (PDPs).
Topic Page
1.1 TAS55085121K8EVM Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 PCB Key Map 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview
1-1
TAS55085121K8EVM Features
1.1 TAS55085121K8EVM Features
- 8-channel PurePath Digital evaluation module
- Stereo channel line output
- Stereo headphone output
- Self-contained protection system (short circuit and thermal)
- Standard I
2
S and I2C control connector for TI input board
- Double-sided plated-through PCB layout
Figure 11. Integrated PurePath DigitalE Amplifier System
2 Channel
Headphone Output
6 Channel
Analog Input
PC Interface
Optical
and
Coaxial
S/PDIF Input
Example
Texas Instruments
InputPC Board
Control Interface
I2C Bus
I2S Bus
TAS55085121K8EVM
Module
Power Supply
2 Channel
Rec Line Output
8 Channel
Speaker Output
1-2
1.2 PCB Key Map
The physical structure for the TAS55085121K8EVM is illustrated in Figure 12.
Figure 12. Physical Structure for TAS55085121K8EVM (Rough Outline)
PCB Key Map
Left Line
Output
(J950)
Headphone
Output
(J900)
Right Line
Output
(J951)
Channel 6
Output Stage
Channel 5
Output Stage
Channel 8
Output Stage
Control
Interface (J30)
J700J800J500J600
Channel 7
Output Stage
TAS5508B
PSU
Interface
(J70)
Channel 4
Output Stage
Input Signal
Interface (J40)
Speaker OutputsSpeaker Outputs
Channel 3
Output Stage
J100J200J300J400
Channel 2
Output Stage
PSU
PSU
PSU
Channel 1
Output Stage
(J73)
Interface
(J71)
Interface
(J72)
Control
Regulator
Gate Drive
5V
Regulator
3.3V Regulator
Overview
1-3
1-4
Chapter 2
 
This chapter describes the TAS55085121K8EVM board in regards to power supplies and system interfaces.
Topic Page
2.1 Power Supply (PSU) Interface (J70, J71, and J73) 2-2. . . . . . . . . . . . . . . .
2.2 Loudspeaker Connectors (J100 . . . J800) 2-4. . . . . . . . . . . . . . . . . . . . . . .
2.3 Line Out Connectors (J950 and J951) 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Headphone Connector (J900) 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Line Output Select (J50) 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Headphone Select (J32) 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Control Interface (J30) 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Digital Audio Interface (J40) 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Interfaces
2-1
Power Supply (PSU) Interface (J70, J71, and J73)
2.1 Power Supply (PSU) Interface (J70, J71, and J73)
The TAS55085121K8EVM module must be powered from external power supplies. High-end audio performance requires a stabilized power supply with low ripple voltage and low output impedance.
Note:
The length of the power supply cable must be minimized. Increasing length of PSU cable is equal to increasing the distortion for the amplifier at high output levels and low frequencies.
The maximum output-stage supply voltage depends of the speaker load resistance. Check the recommended maximum supply voltage in the TAS5121 data sheet (SLES086).
Table 21. Recommended Supply Voltages
Description
System power supply 15 – 20 V 0.3 A
Output-stage power supply 0 – 30.5 V 6 A
The rated current corresponds to 2-channel full scale (80 W each), which most likely is adequate for a standard 8-channel amplifier design.
The recommended TAS5121 power-up sequence is shown in Figure 21. For proper TAS5121 operation, the RESET signal should be kept low during power up. RESET
is pulled low during power up for 200 ms by the onboard reset
generator (U73).
Figure 21. Recommended Power-Up Sequence
System power supply
Output stage power supply
RESET
> 1 ms
Voltage Limitations
(4-W load)
Current
Recommendations
Figure 2−2. J71 and J70 Pin Numbers
System Power Supply
(PCB connector top view)
2-2
4
3
2
1
Table 22. J71 Pin Description
Pin No. Net-Name at Schematics Description
1 V-HBRIDGE Output-stage power supply
2 System power supply
3 GND Ground
4
Table 23. J70 Pin Description
(Optional Use to decrease of impedance to reach better performance)
Pin No. Net-Name at Schematics Description
1 V-HBRIDGE Extra output-stage power supply
2 V-HBRIDGE Extra output-stage power supply
3 GND Extra ground
4
Figure 23. J73 Pin Numbers
Power Supply (PSU) Interface (J70, J71, and J73)
GND Ground
GND Extra ground
2
(PCB connector top view)
Table 24. J73 Pin Description
(Optional)
Pin No. Net-Name at Schematics Description
1 V-HBRIDGE Extra output-stage power supply
2 V-HBRIDGE Extra output-stage power supply
2.1.1 PSU Control Interface (J72)
This interface is used for onboard sensing of output supply voltage and for the power supply volume control (PSVC) signal.
Figure 24. J72 Pin Numbers
1
5
4
3
2
1
(PCB connector top view)
System Interfaces
2-3
Loudspeaker Connectors (J100 . . . J800)
Table 25. J72 Pin Description
Pin No. Net-Name at Schematics Description
1 Reserved for future use
2 V-HBRIDGE Sense of output power supply
3 GND Ground
4 RESET
5
PSVC Power-supply volume control signal
2.2 Loudspeaker Connectors (J100 . . . J800)
Both positive and negative speaker outputs are floating and may not be connected to ground (e.g., through an oscilloscope).
Figure 2−5. J100 . . . J800 Pin Numbers
System reset (bidirectional)
2
1
(PCB connector top view)
Table 26. J100 . . . J800 Pin Description
Pin No. Net-Name at Schematics Description
1 OUT1 Speaker negative output
2 OUT2 Speaker positive output
2.3 Line Out Connectors (J950 and J951)
Figure 2−6. J950 and J951 Pin Numbers
2
1
4
(PCB connector top view)
Table 27. J950 and J952 Pin Description
3
2-4
Pin No. Net-Name at Schematics Description
1 GND Ground
2 OUT Line out signal
3 OUT Line out signal
4
OUT Line out signal
2.4 Headphone Connector (J900)
Figure 2−7. J900 Pin Numbers
Headphone Connector (J900)
1
Table 28. J900 Pin Description
Pin No. Net-Name at Schematics Description
1 OUTL Left headphone output
2 GND Ground
3 For future use
4
2.5 Line Output Select (J50)
Figure 28. J50 Pin Numbers
Table 29. J50 Pin Description
Pin No. Description
12 Line outputs enabled
23 Line outputs disabled
2
(PCB connector top view)
OUTR Right headphone output
3
4
2.6 Headphone Select (J32)
Figure 29. J32 Pin Numbers
Table 210.J32 Pin Description
Pin No. Description
12 Headphone enabled
23 Headphone disabled
System Interfaces
2-5
Control Interface (J30)
2.7 Control Interface (J30)
This interface connects the TAS5508−5121K8EVM board to a TI input board.
Table 211. J30 Pin Description
Pin
Net-Name at
No.
Schematics
1 GND Ground
2 PSVCMCPU Power supply volume control from (mC) input board
3 GND Ground
4 RESET System reset (bidirectional). Activate MUTE before RESET for quiet reset.
5 BKNDERR Backend error (or soft reset) provides reduced click and pop reset, without resetting I2C
6 MUTE Ramp volume from any setting to noiseless soft mute. Mute can also be activated by I2C.
7 PDN Power down. The TAS5508B goes to a power-down state when activated.
89RESERVED
10 SDA I2C data clock
11 GND Ground
12 SCL I2C bit clock
1314RESERVED
Description
volume register settings.
15 CONFSEL Configuration select. Channel 5 and 6 speaker outputs active and line outputs inactive
when high. Line outputs active and channel 5 and 6 speaker outputs inactive when low.
16 RESERVED
17 GND Ground
1819RESERVED
20 SD1 Shutdown error reporting for front left, front right, and center channels. Activated if the
TAS5121 has high current or high temperature. See Chapter 3.
21 SD2 Shutdown error reporting for rear left, rear right, surround left, surround right, and
subwoofer channels. Activated if TAS5121 has high current or high temperature. See Chapter 3.
22 OTW Temperature warning. Activated if one or more TAS5121 has reached the temperature
warning level.
23 RESERVED
24 HPSEL Headphone select. Headphone is active when low and inactive when high.
2526GND Ground
27
RESERVED 28 29 30
3132GND Ground
3334+5V 5-V dc power supply (output)
2-6
Digital Audio Interface (J40)
2.8 Digital Audio Interface (J40)
The digital audio interface contains digital audio signal data (I2S), clocks, etc. See the TAS5508B Data Manual (SLES162) for signal timing and details not explained in this document.
Table 212.J40 Pin Description
Pin
Net-Name at
No.
Schematics
1 GND Ground
2 MCLK Master clock input. Low-jitter system clock for PWM generation and reclocking.
3 GND Ground
4 SDIN1 I2S data 1, channel 1 and 2
5 SDIN2 I2S data 2, channel 3 and 4
6 SDIN3 I2S data 3, channel 5 and 6
7 SDIN4 I2S data 4, channel 7 and 8
8 Reserved
9 Reserved
10 GND Ground
11 SCLK I2S bit clock
12 GND Ground
13 LRCLK I2S leftright clock
14 GND Ground
15 Reserved
16 GND Ground
Description
Ground connection from source to the TAS5508B must be a low-impedance connection.
System Interfaces
2-7
2-8
Chapter 3
Protection
This chapter describes the short-circuit protection and fault-reporting circuitry of the TAS5121 device.
Topic Page
3.1 Short-Circuit Protection and Fault-Reporting Circuitry 3-2. . . . . . . . . . .
3.2 Device Fault Reporting 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection
3-1
Short-Circuit Protection and Fault-Reporting Circuitry
3.1 Short-Circuit Protection and Fault-Reporting Circuitry
The TAS5121 is a self-protecting device that provides device fault reporting (including high-temperature protection and short-circuit protection). The TAS5121 is configured in back-end auto-recovery mode and, therefore, resets automatically after all errors (M1, M2, and M3 is set low). This means that the device restarts itself after an error occasion and reports shortly through SD1 and SD2 error signals.
The shutdown report signals are separated into two wires, SD1 covers the primary information channels (front channels and center), where the SD2 surround/line out channels, and subwoofer). Therefore, a microprocessor can react differently on errors depending on primary or secondary channels faults, e.g., lowering the output level or shutting down the secondary channels on continues error reporting from one of those, where the primary channels continue.
covers the secondary information channels (rear channels,
and SD2. SD1
3-2
3.2 Device Fault Reporting
The OTW and SD outputs from the TAS5121 indicate fault conditions. See the TAS5121 data sheet (SLES086) for a description of these pins.
The temperature warning signals at the TAS55085121K8EVM board are wired-OR to one temperature warning signal [OTW connector (J30)].
Device Fault Reporting
– pin 22 in control interface
Shutdown signals are wired-OR into two shutdown signals [SD1 20 and pin 21 in control interface connector (J30)]. See Table 31 for channel allocation.
Table 31. Channel Allocation
Description Terminal Shutdown Signal
Front left J100 SD1
Front right J200 SD1
Rear left J300 SD2
Rear right J400 SD2
Surround left (or line out left) J500 SD2
Surround right (or line out right) J600 SD2
Center J700 SD1
Subwoofer J800 SD2
The shutdown signals, together with the temperature warning signal, give chip state information as described in Table 3−2. Device fault reporting outputs are open-drain outputs.
Table 32. TAS5121 Warning/Error Signal Decoding
OTW SDx Device Condition
0 0 High-temperature error and/or high-current error
0 1 High-temperature warning
1 0 Undervoltage lockout or high-current error
1 1 Normal operation, no errors/warnings
and SD2 – pin
Protection
3-3
3-4
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