Evaluation Module for the TAS5508B 8-Channel
Digital Audio PWM Processor and the TAS5121
Digital Amplifier Power Output Stage
User’s Guide
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as the input and output ranges are maintained. These components include but are not limited
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types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
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that these devices may be very warm to the touch.
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This manual describes the operation of the TAS5508−5121K8EVM evaluation
module from Texas Instruments.
How to Use This Manual
This document contains the following chapters:
- Chapter 1 — Overview
- Chapter 2 — System Interfaces
- Chapter 3 — Protection
Preface
Read This First
Information About Cautions and Warnings
This manual may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
.
Read This First
iii
Related Documentation From Texas Instruments
The following table contains a list of data manuals that have detailed
descriptions of the integrated circuits used in the design of the
TAS5508−5121K8EVM. The data manuals can be obtained at the URL
http://www.ti.com.
Part NumberLiterature Number
TAS5508BSLES162
TAS5121SLES086
TLV272SLOS351
SN74LVC1G00SCES212
SN74LVC1G08SCES217
SN74LVC2G08SCES198
SN74LVC1G14SCES218
SN74LV123ASCLS393
SN74LVC125ASCAS290
SN74LVC1G126ASCES211
LM317MSLVS297
TPS3801K33SLVS219
TPS76733SLVS208
Additional Documentation
TAS5508−5121K8EVM Application Report (SLEA034A)
PC Configuration Tool for TAS5508B (TAS5508 GUI ver.2.1 or later)
General Application Notes
FCC Warning
This equipment is intended for use in a laboratory test environment only. It
generates, uses, and can radiate radio frequency energy and has not been
tested for compliance with the limits of computing devices pursuant to subpart
J of part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.
Trademarks
Equibit, PowerPAD, and PurePath Digital are trademarks of Texas
Instruments.
The TAS5508−5121K8EVM PurePath Digital™ customer evaluation amplifier
module demonstrates two audio integrated circuits, TAS5508B and TAS5121,
from Texas Instruments (TI).
The TAS5508BPAG is a high-performance 32-bit (24-bit input) multichannel
PurePath Digital pulse width modulator (PWM) based on Equibit™ technology,
with a new fully symmetrical AD modulation scheme. It accepts an input
sample rate from 32 kHz to 192 kHz. The device also has digital audio
processing (DAP) that provides 48-bit signal processing, advanced
performance, and a high level of system integration. The device has interfaces
for headphone output and power supply volume control (PSVC).
The TAS5121DKD is a compact, high-power, digital amplifier power stage
designed to drive a 4-Ω loudspeaker up to 100 W (10% THD+N). The
TAS5121DKD contains integrated gate drivers, four matched and electrically
isolated enhancement-mode N-channel power DMOS transistors, and
protection/fault-reporting circuitry.
The DKD package has a PowerPAD™ on the top side for heat transfer through
a heatsink. The heatsink in this design is for evaluation purpose only.
This EVM, together with a TI input board, is a complete 8-channel digital audio
amplifier system, which includes digital input (S/PDIF), analog inputs,
interface to PC, and DAP features, such as digital volume control, input and
output mixers, auto mute, equalization, tone controls, loudness, dynamic
range compression, and PSVC output. There are configuration options for
stereo line level output, stereo headphone output, and power-stage failure
protection.
This 7.1 system is designed for home-theater applications, such as A/V
receivers, DVD minicomponent systems, home theater in a box (HTIB), DVD
receivers, or plasma display panels (PDPs).
2.1Power Supply (PSU) Interface (J70, J71, and J73)
The TAS5508−5121K8EVM module must be powered from external power
supplies. High-end audio performance requires a stabilized power supply with
low ripple voltage and low output impedance.
Note:
The length of the power supply cable must be minimized. Increasing length
of PSU cable is equal to increasing the distortion for the amplifier at high
output levels and low frequencies.
The maximum output-stage supply voltage depends of the speaker load
resistance. Check the recommended maximum supply voltage in the
TAS5121 data sheet (SLES086).
Table 2−1. Recommended Supply Voltages
Description
System power supply15 – 20 V0.3 A
Output-stage power supply0 – 30.5 V6 A
†
The rated current corresponds to 2-channel full scale (80 W each), which most likely is adequate
for a standard 8-channel amplifier design.
The recommended TAS5121 power-up sequence is shown in Figure 2−1. For
proper TAS5121 operation, the RESET signal should be kept low during power
up. RESET
is pulled low during power up for 200 ms by the onboard reset
generator (U73).
Figure 2−1. Recommended Power-Up Sequence
System power supply
Output stage power supply
RESET
> 1 ms
Voltage Limitations
(4-W load)
Current
Recommendations
†
Figure 2−2. J71 and J70 Pin Numbers
System Power Supply
(PCB connector top view)
2-2
4
3
2
1
Table 2−2. J71 Pin Description
Pin No.Net-Name at SchematicsDescription
1V-HBRIDGEOutput-stage power supply
2−System power supply
3GNDGround
4
Table 2−3. J70 Pin Description
(Optional − Use to decrease of impedance to reach better performance)
Pin No.Net-Name at SchematicsDescription
1V-HBRIDGEExtra output-stage power supply
2V-HBRIDGEExtra output-stage power supply
3GNDExtra ground
4
Figure 2−3. J73 Pin Numbers
Power Supply (PSU) Interface (J70, J71, and J73)
GNDGround
GNDExtra ground
2
(PCB connector top view)
Table 2−4. J73 Pin Description
(Optional)
Pin No.Net-Name at SchematicsDescription
1V-HBRIDGEExtra output-stage power supply
2V-HBRIDGEExtra output-stage power supply
2.1.1PSU Control Interface (J72)
This interface is used for onboard sensing of output supply voltage and for the
power supply volume control (PSVC) signal.
Figure 2−4. J72 Pin Numbers
1
5
4
3
2
1
(PCB connector top view)
System Interfaces
2-3
Loudspeaker Connectors (J100 . . . J800)
Table 2−5. J72 Pin Description
Pin No.Net-Name at SchematicsDescription
1—Reserved for future use
2V-HBRIDGESense of output power supply
3GNDGround
4RESET
5
PSVCPower-supply volume control signal
2.2Loudspeaker Connectors (J100 . . . J800)
Both positive and negative speaker outputs are floating and may
not be connected to ground (e.g., through an oscilloscope).
Figure 2−5. J100 . . . J800 Pin Numbers
System reset (bidirectional)
2
1
(PCB connector top view)
Table 2−6. J100 . . . J800 Pin Description
Pin No.Net-Name at SchematicsDescription
1OUT−1Speaker negative output
2OUT−2Speaker positive output
2.3Line Out Connectors (J950 and J951)
Figure 2−6. J950 and J951 Pin Numbers
2
1
4
(PCB connector top view)
Table 2−7. J950 and J952 Pin Description
3
2-4
Pin No.Net-Name at SchematicsDescription
1GNDGround
2OUTLine out signal
3OUTLine out signal
4
OUTLine out signal
2.4Headphone Connector (J900)
Figure 2−7. J900 Pin Numbers
Headphone Connector (J900)
1
Table 2−8. J900 Pin Description
Pin No.Net-Name at SchematicsDescription
1OUT−LLeft headphone output
2GNDGround
3—For future use
4
2.5Line Output Select (J50)
Figure 2−8. J50 Pin Numbers
Table 2−9. J50 Pin Description
Pin No.Description
1−2Line outputs enabled
2−3Line outputs disabled
2
(PCB connector top view)
OUT−RRight headphone output
3
4
2.6Headphone Select (J32)
Figure 2−9. J32 Pin Numbers
Table 2−10.J32 Pin Description
Pin No.Description
1−2Headphone enabled
2−3Headphone disabled
System Interfaces
2-5
Control Interface (J30)
2.7Control Interface (J30)
This interface connects the TAS5508−5121K8EVM board to a TI input board.
Table 2−11. J30 Pin Description
Pin
Net-Name at
No.
Schematics
1GNDGround
2PSVC−MCPU Power supply volume control from (mC) input board
3GNDGround
4RESETSystem reset (bidirectional). Activate MUTE before RESET for quiet reset.
5BKND−ERRBackend error (or soft reset) provides reduced click and pop reset, without resetting I2C
6MUTERamp volume from any setting to noiseless soft mute. Mute can also be activated by I2C.
7PDNPower down. The TAS5508B goes to a power-down state when activated.
89RESERVED
10SDAI2C data clock
11GNDGround
12SCLI2C bit clock
1314RESERVED
Description
volume register settings.
15CONF−SELConfiguration select. Channel 5 and 6 speaker outputs active and line outputs inactive
when high. Line outputs active and channel 5 and 6 speaker outputs inactive when low.
16RESERVED
17GNDGround
1819RESERVED
20SD1Shutdown error reporting for front left, front right, and center channels. Activated if the
TAS5121 has high current or high temperature. See Chapter 3.
21SD2Shutdown error reporting for rear left, rear right, surround left, surround right, and
subwoofer channels. Activated if TAS5121 has high current or high temperature. See
Chapter 3.
22OTWTemperature warning. Activated if one or more TAS5121 has reached the temperature
warning level.
23RESERVED
24HP−SELHeadphone select. Headphone is active when low and inactive when high.
2526GNDGround
27
RESERVED
28
29
30
3132GNDGround
3334+5V5-V dc power supply (output)
2-6
Digital Audio Interface (J40)
2.8Digital Audio Interface (J40)
The digital audio interface contains digital audio signal data (I2S), clocks, etc.
See the TAS5508B Data Manual (SLES162) for signal timing and details not
explained in this document.
Table 2−12.J40 Pin Description
Pin
Net-Name at
No.
Schematics
1GNDGround
2MCLKMaster clock input. Low-jitter system clock for PWM generation and reclocking.
3GNDGround
4SDIN1I2S data 1, channel 1 and 2
5SDIN2I2S data 2, channel 3 and 4
6SDIN3I2S data 3, channel 5 and 6
7SDIN4I2S data 4, channel 7 and 8
8Reserved
9Reserved
10GNDGround
11SCLKI2S bit clock
12GNDGround
13LRCLKI2S left−right clock
14GNDGround
15Reserved
16GNDGround
Description
Ground connection from source to the TAS5508B must be a low-impedance
connection.
System Interfaces
2-7
2-8
Chapter 3
Protection
This chapter describes the short-circuit protection and fault-reporting circuitry
of the TAS5121 device.
Short-Circuit Protection and Fault-Reporting Circuitry
3.1Short-Circuit Protection and Fault-Reporting Circuitry
The TAS5121 is a self-protecting device that provides device fault reporting
(including high-temperature protection and short-circuit protection). The
TAS5121 is configured in back-end auto-recovery mode and, therefore, resets
automatically after all errors (M1, M2, and M3 is set low). This means that the
device restarts itself after an error occasion and reports shortly through SD1
and SD2 error signals.
The shutdown report signals are separated into two wires, SD1
covers the primary information channels (front channels and center), where
the SD2
surround/line out channels, and subwoofer). Therefore, a microprocessor can
react differently on errors depending on primary or secondary channels faults,
e.g., lowering the output level or shutting down the secondary channels on
continues error reporting from one of those, where the primary channels
continue.
covers the secondary information channels (rear channels,
and SD2. SD1
3-2
3.2Device Fault Reporting
The OTW and SD outputs from the TAS5121 indicate fault conditions. See the
TAS5121 data sheet (SLES086) for a description of these pins.
The temperature warning signals at the TAS5508−5121K8EVM board are
wired-OR to one temperature warning signal [OTW
connector (J30)].
Device Fault Reporting
– pin 22 in control interface
Shutdown signals are wired-OR into two shutdown signals [SD1
20 and pin 21 in control interface connector (J30)]. See Table 3−1 for channel
allocation.
Table 3−1. Channel Allocation
DescriptionTerminalShutdown Signal
Front leftJ100SD1
Front rightJ200SD1
Rear leftJ300SD2
Rear rightJ400SD2
Surround left (or line out left)J500SD2
Surround right (or line out right)J600SD2
CenterJ700SD1
SubwooferJ800SD2
The shutdown signals, together with the temperature warning signal, give chip
state information as described in Table 3−2. Device fault reporting outputs are
open-drain outputs.