Datasheet tas5352a Datasheet (Texas Instruments)

TM

0

150

10

20

30

40

50

60

70

80

90

100

110

120

130

140

0 34246 8 10 12 14 16 18 20 22 24 26 28 30 32

T =75°C THD+Nat10%

C

8

Ω

4

Ω

6

Ω

8

Ω

4

Ω

8

Ω

4

Ω

8

Ω

4

Ω

P – OutputPower – W

O

PVDD – SupplyVoltage – V

TAS5352A

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1

FEATURES

23

• Total Power Output (Bridge Tied Load)

........................................................................................................................................................................................... SLES239 – NOVEMBER 2008

– 2 × 125 W at 10% THD+N Into 4 Ω – 2 × 100 W at 10% THD+N Into 6 Ω

• Total Power Output (Single Ended)

– 4 × 45 W at 10% THD+N Into 3 Ω – 4 × 35 W at 10% THD+N Into 4 Ω

• Total Power Output (Parallel Mode)

– 1 × 250 W at 10% THD+N Into 2 Ω – 1 × 195 W at 10% THD+N Into 3 Ω

• >110 dB SNR (A-Weighted With TAS5518 Modulator) PWM signal (PWM activity detector).

• < 0.1% THD+N (1 W, 1 kHz)

• Supports PWM Frame Rates of 192 kHz to

432 kHz

• Resistor-Programmable Current Limit

• Integrated Self-Protection Circuitry, Including:

– Under Voltage Protection – Overtemperature Warning and Error – Overload Protection – Short-Circuit Protection – PWM Activity Detector

• Standalone Protection Recovery

• Power-On Reset (POR) to Eliminate System

Power-Supply Sequencing

• High-Efficiency Power Stage (>90%) With 80-m Ω Output MOSFETs

• Thermally Enhanced 44-Pin HTSSOP Package (DDV)

• Error Reporting, 3.3-V and 5.0-V Compliant

• EMI Compliant When Used With

Recommended System Design

APPLICATIONS

• Mini/Micro Audio System

• DVD Receiver

• Home Theater

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 PurePath Digital, PowerPad are trademarks of Texas Instruments. 3 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

125 W STEREO DIGITAL AMPLIFIER POWER STAGE

DESCRIPTION

The TAS5352A is a high-performance, integrated stereo digital amplifier power stage designed to drive a 4- Ω bridge-tied load (BTL) at up to 125 W per channel with low harmonic distortion, low integrated noise, and low idle current.

The TAS5352A has a complete protection system integrated on-chip, safeguarding the device against a wide range of fault conditions that could damage the system. These protection features are short-circuit protection, over-current protection, under voltage protection, over temperature protection, and a loss of

A power-on-reset (POR) circuit is used to eliminate power-supply sequencing that is required for most power-stage designs.

PurePath Digital™

BTL OUTPUT POWER

vs

SUPPLY VOLTAGE

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

GVDD_B

OTW

NC NC SD

PWM_A

RESET_AB

PWM_B

OC_ADJ

GND AGND VREG

M3 M2 M1

PWM_C

RESET_CD

PWM_D

NC NC

VDD

GVDD_C

DDV PACKAGE

(TOP VIEW)

GVDD_A BST_A NC PVDD_A PVDD_A OUT_A GND_A GND_B OUT_B PVDD_B BST_B BST_C PVDD_C OUT_C GND_C GND_D OUT_D PVDD_D PVDD_D NC BST_D GVDD_D

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23

P0016-02

TAS5352A

SLES239 – NOVEMBER 2008 ...........................................................................................................................................................................................

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

GENERAL INFORMATION

Terminal Assignment

The TAS5352A is available in a thermally enhanced 44-pin HTSSOP PowerPad™ package (DDV) This package contains a thermal pad that is located on the top side of the device for convenient thermal coupling

to the heatsink.

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TAS5352A

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........................................................................................................................................................................................... SLES239 – NOVEMBER 2008

Protection MODE Selection Pins

Protection modes are selected by shorting M1, M2, and M3 to VREG or GND.

MODE PINS

M3 M2 M1

Mode Name PWM Input

0 0 0 BTL mode 1 2N All protection systems enabled 0 0 1 BTL mode 2 2N Latching shutdown on, PWM activity detector and OLP disabled 0 1 0 BTL mode 3 1N All protection systems enabled 0 1 1 PBTL mode 1N / 2N 1 0 0 SE mode 1 1N All protection systems enabled 1 0 1 SE mode 2 1N Latching shutdown on, PWM activity detector and OLP disabled 1 1 0 1 1 1

(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode. (2) PWM_D is used to select between the 1N and 2N interface in PBTL mode (Low = 1N; High = 2N). PWM_D is internally pulled low in

PBTL mode. PWM_A is used as the PWM input in 1N mode and PWM_A and PWM_B are used as inputs for the 2N mode.

(3) PPSC detection system disabled.

Package Heat Dissipation Ratings

(1)

PARAMETER TAS5352ADDV

R

( ° C/W) — 2 BTL or 4 SE channels 1.3

θ JC

R

( ° C/W) — 1 BTL or 2 SE channel(s) 2.6

θ JC

R

( ° C/W) — 1 SE channel 5.0

θ JC

Power Pad area

(2)

(1) JC is junction-to-case, CH is case-to-heatsink. (2) R

is an important consideration. Assume a 2-mil thickness of high performance grease with a thermal conductivity at 2.5W/m-K

θ CH

between the pad area and the heat sink. The R

θ CH

(1)

(2)

All protection systems enabled

Reserved

with this condition is 0.6 ° C/W for the DDV package.

Description

(3)

2

36 mm

(3)

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TAS5352A

SLES239 – NOVEMBER 2008 ...........................................................................................................................................................................................

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

TAS5352A

VDD to AGND – 0.3 V to 13.2 V GVDD_X to AGND – 0.3 V to 13.2 V PVDD_X to GND_X OUT_X to GND_X BST_X to GND_X BST_X to GVDD_X VREG to AGND – 0.3 V to 4.2 V GND_X to GND – 0.3 V to 0.3 V GND_X to AGND – 0.3 V to 0.3 V GND to AGND – 0.3 V to 0.3 V PWM_X, OC_ADJ, M1, M2, M3 to AGND – 0.3 V to 4.2 V RESET_X, SD, OTW to AGND – 0.3 V to 7 V Maximum continuous sink current ( SD, OTW) 9 mA Maximum operating junction temperature range, T Storage temperature – 40 ° C to 125 ° C Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds 260 ° C Minimum pulse duration, low 30 ns

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.

(2)

J

(1)

– 0.3 V to 53 V – 0.3 V to 53 V

– 0.3 V to 66.2 V

– 0.3 V to 53 V

0 ° C to 125 ° C

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ORDERING INFORMATION

T

A

PACKAGE DESCRIPTION

(1)

0 ° C to 70 ° C TAS5352ADDV 44-pin HTSSOP

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com .

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TAS5352A

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........................................................................................................................................................................................... SLES239 – NOVEMBER 2008

Terminal Functions

TERMINAL

NAME DDV NO.

AGND 11 P Analog ground BST_A 43 P Bootstrap pin, A-Side BST_B 34 P Bootstrap pin, B-Side BST_C 33 P Bootstrap pin, C-Side BST_D 24 P Bootstrap pin, D-Side

GND 10 P Ground GND_A 38 P Power ground for half-bridge A GND_B 37 P Power ground for half-bridge B GND_C 30 P Power ground for half-bridge C GND_D 29 P Power ground for half-bridge D

GVDD_A 44 P Gate-drive voltage supply; A-Side GVDD_B 1 P Gate-drive voltage supply; B-Side GVDD_C 22 P Gate-drive voltage supply; C-Side GVDD_D 23 P Gate-drive voltage supply; D-Side

M1 15 I Mode selection pin (LSB) M2 14 I Mode selection pin M3 13 I Mode selection pin (MSB) NC 3, 4, 19, 20, 25, 42 – No connect. Pins may be grounded.

OC_ADJ 9 O Analog overcurrent programming pin

OTW 2 O Overtemperature warning signal, open-drain, active-low OUT_A 39 O Output, half-bridge A OUT_B 36 O Output, half-bridge B OUT_C 31 O Output, half-bridge C OUT_D 28 O Output, half-bridge D

PVDD_A 40, 41 P Power supply input for half-bridge A PVDD_B 35 P Power supply input for half-bridge B PVDD_C 32 P Power supply input for half-bridge C PVDD_D 26, 27 P Power supply input for half-bridge D

PWM_A 6 I PWM Input signal for half-bridge A PWM_B 8 I PWM Input signal for half-bridge B PWM_C 16 I PWM Input signal for half-bridge C

PWM_D 18 I PWM Input signal for half-bridge D RESET_AB 7 I Reset signal for half-bridge A and half-bridge B, active-low RESET_CD 17 I Reset signal for half-bridge C and half-bridge D, active-low

SD 5 O Shutdown signal, open-drain, active-low

VDD 21 P Input power supply

VREG 12 P Internal voltage regulator

(1) I = input, O = output, P = power

FUNCTION

(1)

DESCRIPTION

Product Folder Link(s): TAS5352A

2nd-OrderL-C

OutputFilter

forEach

Half-Bridge

Bootstrap

Capacitors

2-Channel

H-Bridge

BTL Mode

System

Microcontroller

OUT_A

OUT_B

OUT_C

OUT_D

BST_A

BST_B

BST_C

BST_D

RESET_AB RESET_CD

System

Power

Supply

Hardwire

Mode

Control

PVDD

GVDD(12V)/VDD(12V)

GND

Hardwire OCLimit

M1

M3

PVDD Power Supply

Decoupling

34.5V

12V

GND

VAC

PWM_A

PWM_C

PWM_D

PWM_B

VALID

M2

Left-

Channel

Output

Right-

Channel

Output

Input H-Bridge1

Input H-Bridge2

GVDD

VDD

VREG

PowerSupply

Decoupling

4 4 4

Bootstrap

Capacitors

2nd-OrderL-C

OutputFilter

forEach

Half-Bridge

Output

H-Bridge2

Output

H-Bridge1

OTW

SD

TAS5518

B0047-02

PVDD_A,B,C,D

GND_A,B,C,D

GVDD_A,B,C,D

GND

VDD

VREG

AGND

OC_ADJ

I2C

TAS5352A

SLES239 – NOVEMBER 2008 ...........................................................................................................................................................................................

TYPICAL SYSTEM BLOCK DIAGRAM

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Temp.

Sense

M1

M2

RESET_AB

SD

OTW

AGND

OC_ADJ

VREG VREG

VDD

M3

Power

On

Reset

Under-

voltage

Protection

GND

PWM_D OUT_D

GND_D

PVDD_D

BST_D

Timing

Gate

Drive

PWM

Rcv.

Overload

Protection

I

sens e

GVDD_D

RESET_CD

4

Protection

and

I/OLogic

PWM_C OUT_C

GND_C

PVDD_C

BST_C

Timing

Gate

Drive

Ctrl.

PWM

Rcv.

GVDD_C

PWM_B OUT_B

GND_B

PVDD_B

BST_B

Timing

Gate

Drive

Ctrl.

PWM

Rcv.

GVDD_B

PWM_A OUT_A

GND_A

PVDD_A

BST_A

Timing

Gate

Drive

Ctrl.

PWM

Rcv.

GVDD_A

Ctrl.

BTL/PBTL−Configuration

Pulldown Resistor

BTL/PBTL−Configuration

PulldownResistor

BTL/PBTL−Configuration

PulldownResistor

BTL/PBTL−Configuration

PulldownResistor

InternalPullup

ResistorstoVREG

B0034-03

4

TAS5352A

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........................................................................................................................................................................................... SLES239 – NOVEMBER 2008

FUNCTIONAL BLOCK DIAGRAM

Product Folder Link(s): TAS5352A

TAS5352A

SLES239 – NOVEMBER 2008 ...........................................................................................................................................................................................

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RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT

PVDD_X Half-bridge supply voltage 0 34.5 37 V GVDD_X 10.8 12 13.2 V VDD Digital regulator supply voltage 10.8 12 13.2 V

RL(BTL) 3 4 RL(SE) current control), recommended demodulation 2.25 3 Ω RL(PBTL) 1.5 2 L

(BTL) 5 10

Output

L

(SE) Output-filter inductance 5 10 µ H

Output

L

(PBTL) 5 10

Output

f

S

t

LOW

C

PVDD

C

BST

R

OC

R

EXT-PULLUP

T

J

Supply voltage for logic regulators and gate-drive circuitry

Resistive load impedance (no Cycle-by_Cycle filter

Minimum output inductance under short-circuit condition

PWM frame rate 192 384 432 kHz Minimum low-state pulse duration per PWM

Frame, noise shaper enabled

30 nS

PVDD close decoupling capacitors 0.1 µ F Bootstrap capacitor, selected value supports

PWM frame rates from 192 kHz to 432 kHz

33 nF

Over-current programming resistor Resistor tolerance = 5% 22 22 47 k Ω External pull-up resistor to +3.3V to +5.0V for

SD or OTW

3.3 4.7 k Ω

Junction temperature 0 125 ° C

AUDIO SPECIFICATIONS (BTL)

Audio performance is recorded as a chipset consisting of a TAS5518 pwm processor (modulation index limited to 97.7%) and a TAS5352A power stage. PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_x = 34.5 V, GVDD_x = 12 V, RL= 4 Ω , fS= 384 kHz, R C

= 470 nF, unless otherwise noted.

DEM

PARAMETER TEST CONDITIONS UNIT

RL= 4 Ω , 10% THD+N, clipped input signal

P

OMAX

P

O

Maximum Power Output 100

Unclipped Power Output 72

THD+N Total harmonic distortion + noise

V

n

SNR Signal-to-noise ratio

Output integrated noise A-weighted, AES17 filter, Auto mute µ V

(1)

DNR Dynamic range 110 dB DC Offset Output offset voltage +/- 15 mV

P

idle

Power dissipation due to idle losses (IPVDD_X) PO= 0 W, all halfbridges switching

(1) SNR is calculated relative to 0-dBFS input level. (2) Actual system idle losses are affected by core losses of output inductors.

RL= 6 Ω , 10% THD+N, clipped input signal

RL= 8 Ω , 10% THD+N, clipped input signal

RL= 4 Ω , 0 dBFS, unclipped input signal

RL= 6 Ω , 0 dBFS, unclipped input signal

RL= 8 Ω , 0 dBFS, unclipped input signal

0 dBFS; AES17 filter 0.4% 1 W; AES17 filter 0.09%

disabled A-weighted, AES17 filter, Auto mute

disabled A-weighted, input level = – 60 dBFS,

AES17 filter

= 22 k Ω , TC= 75 ° C, Output Filter: L

OC

MIN TYP MAX

(2)

TAS5352A

125

76 W

96

57

50

110 dB

2.6 W

= 10 µ H,

DEM

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TAS5352A

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........................................................................................................................................................................................... SLES239 – NOVEMBER 2008

AUDIO SPECIFICATIONS (Single-Ended Output)

Audio performance is recorded as a chipset consisting of a TAS5086 pwm processor (modulation index limited to 97.7%) and a TAS5352A power stage. PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_x = 34.5 V, GVDD_x = 12 V, RL= 4 Ω , fS= 384 kHz, R C

= 1.0 µ F, unless otherwise noted.

DEM

PARAMETER TEST CONDITIONS UNIT

RL= 3 Ω , 10% THD+N, clipped input

P

OMAX

P

O

Maximum Power Output

Unclipped Power Output

THD+N Total harmonic distortion + noise

V

n

SNR A-weighted, AES17 filter, Auto mute 109 dB

Output integrated noise

Signal-to-noise ratio

(1)

DNR Dynamic range 109 dB P

idle

Power dissipation due to idle losses (IPVDD_X) PO= 0 W, all halfbridges switching

(1) SNR is calculated relative to 0-dBFS input level. (2) Actual system idle losses are affected by core losses of output inductors.

signal RL= 4 Ω , 10% THD+N, clipped input

signal RL= 3 Ω , 0 dBFS, unclipped input

signal RL= 4 Ω , 0 dBFS, unclipped input

signal 0 dBFS; AES17 filter 0.4% 1 W; AES17 filter 0.09% A-weighted, AES17 filter, Auto mute 40 µ V

disabled

disabled A-weighted, input level = – 60 dBFS

AES17 filter

= 22 k Ω , TC= 75 ° C, Output Filter: L

OC

MIN TYP MAX

(2)

TAS5352A

2.6 W

= 20 µ H,

DEM

45

35

25

W

AUDIO SPECIFICATIONS (PBTL)

Audio performance is recorded as a chipset consisting of a TAS5518 pwm processor (modulation index limited to 97.7%) and a TAS5352A power stage. PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_x = 34.5 V, GVDD_x = 12 V, RL= 3 Ω , fS= 384 kHz, R C

= 1 µ F, unless otherwise noted.

DEM

PARAMETER TEST CONDITIONS UNIT

RL= 3 Ω , 10% THD+N, clipped input

P

OMAX

P

O

Maximum Power Output

Unclipped Power Output

THD+N Total harmonic distortion + noise

V

n

SNR A-weighted, AES17 filter, Auto mute 110 dB

Output integrated noise

Signal-to-noise ratio

(1)

DNR Dynamic range 110 dB DC Offset Output offset voltage +/- 15 mV

P

idle

Power dissipation due to idle losses (IPVDD_X) PO= 0 W, all halfbridges switching

(1) SNR is calculated relative to 0-dBFS input level. (2) Actual system idle losses are affected by core losses of output inductors.

signal RL= 2 Ω , 10% THD+N, clipped input

signal RL= 3 Ω , 0 dBFS, unclipped input

signal RL= 2 Ω , 0 dBFS, unclipped input

signal 0 dBFS; AES17 filter 0.4% 1 W; AES17 filter 0.09% A-weighted, AES17 filter, Auto mute 50 µ V

disabled

disabled A-weighted, input level = – 60 dBFS

AES17 filter

= 22 k Ω , TC= 75 ° C, Output Filter: L

OC

MIN TYP MAX

(2)

TAS5352A

195

250

145

190

2.6 W

= 10 µ H,

DEM

W

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TAS5352A

SLES239 – NOVEMBER 2008 ...........................................................................................................................................................................................

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ELECTRICAL CHARACTERISTICS

PVDD_x = 34.5 V, GVDD_X = 12 V, VDD = 12 V, TC(Case temperature) = 25 ° C, fS= 384 kHz, unless otherwise specified.

PARAMETER TEST CONDITIONS UNIT

Internal Voltage Regulator and Current Consumption

VREG VDD = 12 V 3 3.3 3.6 V

IVDD VDD supply current mA

IGVDD_X Gate supply current per half-bridge mA

Voltage regulator, only used as a reference node

Operating, 50% duty cycle 7.2 17 Idle, reset mode 5.5 11 50% duty cycle 8 16 Reset mode 1 1.8 50% duty cycle, with 10 µ H and 470 nF output 19.0 25 mA

IPVDD_X Half-bridge idle current

filter. Reset mode, no switching 525 630 µ A

Output Stage MOSFETs

R

DSon,LS

R

DSon,HS

Drain-to-source resistance, Low Side

Drain-to-source resistance, High Side

TJ= 25 ° C, excludes metalization resistance, 80 89 m Ω

I/O Protection

V

uvp,G

(1)

V

uvp,hyst

BST

uvpF

BST

uvpR

(1)

OTW

OTE

(1)

HYST

(1)

OTE- OTE - OTW differential, temperature OTW

differential

Undervoltage protection limit, GVDD_X

Undervoltage protection limit, 250 mV GVDD_X

Puts device into RESET when BST 5.9 V voltage falls below limit

Brings device out of RESET when 7 V BST voltage rises above limit

Overtemperature warning 115 125 135 ° C Temperature drop needed below

OTW temp. for OTW to be inactive 25 ° C after the OTW event

Overtemperature error threshold 145 155 165 ° C

(1)

delta between OTW and OTE

OLPC Overload protection counter fS= 384 kHz 1.25 ms I

OC

I

OCT

t

ACTIVITY

DETECTOR

I

PD

Overcurrent limit protection 10.9 A Overcurrent response time 150 ns

Time for PWM activity detector to activate when no PWM is present

Output pulldown current of each half-bridge

Resistor — programmable, high-end, R

= 22 k Ω with 1 mS pulse

OC

Lack of transition of any PWM input 13.2 µ S Connected when RESET is active to provide

bootstrap capacitor charge. Not used in SE 3 mA mode.

Static Digital Specifications

V

IH

V

IL

I

Leakage

High-level input voltage 2 V Low-level input voltage 0.8 V

PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3, RESET_AB, RESET_CD

Input leakage current 100 µ A

OTW/SHUTDOWN (SD)

R

INT_PU

V

OH

Internal pullup resistance, OTW to VREG, SD to VREG

High-level output voltage V

Internal pullup resistor 3 3.3 3.6 External pullup of 4.7 k Ω to 5 V 4.5 5

TAS5352A

MIN TYP MAX

9.5 V

30 ° C

20 26 32 k Ω

Product Folder Link(s): TAS5352A

0.005

10

0.01

0.02

0.05

0.1

0.2

0.5

1

2

5

20m 20050m 100m 200m 500m

1 2

5 10 20 50 100

THD+N – TotalHamonic D

isto

rtio

n

– %

P – OutputPower – W

O

T =75°C THD+Nat10%

C

4

W

6

W

8W8W8W8

W

0

150

10

20

30

40

50

60

70

80

90

100

110

120

130

140

0 34246 8 10 12 14 16 18 20 22 24 26 28 30 32

T =75°C THD+Nat10%

C

8

Ω

4

Ω

6

Ω

8

Ω

4

Ω

8

Ω

4

Ω

8

Ω

4

Ω

P – OutputPower – W

O

PVDD – SupplyVoltage – V

0

120

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

95

100

105

110

115

0 34246 8 10 12 14 16 18 20 22 24 26 28 30 32

P

– OutputPower – W

O

PVDD – SupplyVoltage – V

T =75°C

C

4

W

6

W

4W4W4

W

8W8W8W8

W

0

100

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

95

0 28040 80 120 160 200 240

Efficiency – %

2ChannelsOutputPower – W

T =25°C THD+Nat10%

C

8W8W8W4

W

8886

8W8W8W8

W

TAS5352A

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........................................................................................................................................................................................... SLES239 – NOVEMBER 2008

ELECTRICAL CHARACTERISTICS (continued)

PVDD_x = 34.5 V, GVDD_X = 12 V, VDD = 12 V, TC(Case temperature) = 25 ° C, fS= 384 kHz, unless otherwise specified.

PARAMETER TEST CONDITIONS UNIT

V

OL

Low-level output voltage IO= 4 mA 0.2 0.4 V

FANOUT Device fanout OTW, SD No external pullup 30 Devices

TAS5352A

MIN TYP MAX

TYPICAL CHARACTERISTICS, BTL CONFIGURATION

TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER

vs vs

OUTPUT POWER SUPPLY VOLTAGE

UNCLIPPED OUTPUT POWER SYSTEM EFFICIENCY

SUPPLY VOLTAGE OUTPUT POWER

Figure 1. Figure 2.

vs vs

Figure 3. Figure 4.

Product Folder Link(s): TAS5352A

PowerLoss – W

2ChannelsOutputPower – W

0

40

2

4

6

8

10

12

14

16

18

20

22

24

26

28

36

38

0

280

20 40 60

80

100 120 140 160

180

200 220 240 260

34

30

32

T =25°C THD+Nat10%

C

4W4W4W4

W

8W8W8W8

W

8W8W8W6

W

0

160

10

20

30

40

50

60

70

80

90

100

110

120

130

140

150

10 12020 30 40 50 60 70 80 90 100 110

THD+Nat10%

T – CaseTemperature – °C

C

P – OutputPower – W

O

8

W

4

W

8

W

4

W

8

W

4

W

8

W

6

W

8W8W8

W

4

W

f – Frequency – kHz

Noise Amplitude – V

–160

+0

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 22k1k 2k 3k 4k 5k 6k 7k 8k 9k 10k 11k 12k 13k14k 15k 16k 17k 18k 19k 20k 21k

T =75°C V =20.60V SampleRate=48kHz

FFTSize=16384

C

REF

TAS5352A

SLES239 – NOVEMBER 2008 ...........................................................................................................................................................................................

www.ti.com

TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)

SYSTEM POWER LOSS SYSTEM OUTPUT POWER

vs vs

OUTPUT POWER CASE TEMPERATURE

Figure 5. Figure 6.

NOISE AMPLITUDE

vs

FREQUENCY

Figure 7.

Product Folder Link(s): TAS5352A

P

– OutputPower – W

O

PVDD – SupplyVoltage – V

0

60

2.5

5

7.5

10

12.5

15

17.5

20

22.5

25

27.5

30

32.5

35

37.5

40

42.5

45

47.5

50

52.5

55

57.5

0

34

2 4

6 8 10

12 14

16 18 20

22 24

26 28

30 32

T =75°C THD+Nat10%

C

4

W

3

W

P – OutputPower – W

O

THD+N – TotalHamonic Disto

rtion – %

0.005

10

0.01

0.02

0.05

0.1

0.2

0.5

1

2

5

20m 8050m 100m 200m 500m

1 2

5 10 20 50

T =75°C THD+Nat10%

C

4

W

3

W

T – CaseTemperature – °C

C

P

–

OutputPower – W

O

0

60

2.5

5

7.5

10

12.5

15

17.5

20

22.5

25

27.5

30

32.5

35

37.5

40

42.5

45

47.5

50

52.5

55

57.5

10 12020 30 40 50 60 70

80 90

100 110

THD+Nat10%

3

W

4

W

TAS5352A

www.ti.com

........................................................................................................................................................................................... SLES239 – NOVEMBER 2008

TYPICAL CHARACTERISTICS, SE CONFIGURATION

TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER

vs vs

OUTPUT POWER SUPPLY VOLTAGE

Figure 8. Figure 9.

OUTPUT POWER

vs

CASE TEMPERATURE

Figure 10.

Product Folder Link(s): TAS5352A

PVDD – SupplyVoltage – V

P

–

OutputPower

–

W

O

0

300

20

40

60

80

100

120

140

160

180

200

220

240

260

280

0 342 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

T =75°C THD+Nat10%

C

8W8

W

4W2

W

44

W

43

W

THD+N – To

ta

lHamonic Distortion – %

P – OutputPower – W

O

0.005

10

0.01

0.02

0.05

0.1

0.2

0.5

1

2

5

20m 40050m100m 200m 500m 1 2 5 10 20 50 100 200

T =75°C THD+Nat10%

C

4

W

2

W

3

W

8

W

P – OutputPower

– W

O

T – CaseTemperature – °C

C

0

300

20

40

60

80

100

120

140

160

180

200

220

240

260

280

10 12020 30 40 50 60 70 80 90 100 110

4W4W4W3

W

8W8W8W2

W

8W8W8W8

W

8W8W8W4

W

THD+Nat10%

TAS5352A

SLES239 – NOVEMBER 2008 ...........................................................................................................................................................................................

www.ti.com

TYPICAL CHARACTERISTICS, PBTL CONFIGURATION

TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER

vs vs

OUTPUT POWER SUPPLY VOLTAGE

Figure 11. Figure 12.

SYSTEM OUTPUT POWER

vs

CASE TEMPERATURE

Product Folder Link(s): TAS5352A

Figure 13.

GVDD(+12V)

VDD(+12V)

PVDD

GVDD(+12V)

GND

TAS5508/18

PWM1_P

PWM1_M

PWM2_P

PWM2_M

VALID

Microcontroller

I2C

10µH

100nF

50V

10µH

100nF

TAS5352ADDV

GVDD_B

OTW

SD

PWM_A

RESET_AB

PWM_B

OC_ADJ

GND

AGND

VREG

M3

M2

M1

PWM_C

RESET_CD

PWM_D

GVDD_C

GVDD_D

BST_D

PVDD_D

OUT_D

GND_D

GND_C

OUT_C

PVDD_C

BST_C

BST_B

PVDD_B

OUT_B

GND_B

GND_A

VDD

GVDD_A

BST_A

PVDD_A

OUT_A

NC

PVDD_D

PVDD_A

NC

25V

33nF

100nF

50V

100nF

50V

100nF

470nF

100nF

50V

10µH

470µF

50V

470 Fµ

50V

33nF

25V

3.3 W

100nF

0 W

22k

100nF

33nF

25V

100nF

50V

10nF

50V

100nF

470nF

100nF

100nF 50V

33nF

25V

100nF

50V

100nF

10µH

3.3 W

10nF

50V

10nF

50V

3.3 W

1nF 50V

3.3 W

10nF

50V

10nF

50V

3.3 W

3.3

W

10nF

50V

2.2

W

2.2 W

2.2

W

2.2 W

50V

GND

TAS5352A

www.ti.com

........................................................................................................................................................................................... SLES239 – NOVEMBER 2008

APPLICATION INFORMATION

PCB Material Recommendation

FR-4 Glass Epoxy material with 2 oz. (70 µ m) is recommended for use with the TAS5352A. The use of this material can provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB trace inductance.

PVDD Capacitor Recommendation

The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These capacitors should be selected for proper voltage margin and adequate capacitance to support the power requirements. In practice, with a well designed system power supply, 1000 µ F, 50-V will support more applications. The PVDD capacitors should be low ESR type because they are used in a circuit associated with high-speed switching.

Decoupling Capacitor Recommendations

In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this application.

The voltage of the decoupling capacitors should be selected in accordance with good design practices. Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the selection of the 0.1 µ F that is placed on the power supply to each half-bridge. It must withstand the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple current created by high power output. A minimum voltage rating of 50-V is required for use with a 34.5 V power supply.

System Design Recommendations

The following schematics and PCB layouts illustrate "best practices" in the use of the TAS5352A.

Product Folder Link(s): TAS5352A

Figure 14. Typical Differential (2N) BTL Application With AD Modulation Filters

GVDD(+12V)

VDD(+12V)

PVDD

GVDD(+12V)

GND

TAS5508/18

PWM1_P

PWM2_P

VALID

Microcontroller

I2C

10µH

100nF

50V

10µH

100nF

TAS5352ADDV

GVDD_B

OTW

SD

PWM_A

RESET_AB

PWM_B

OC_ADJ

GND

AGND

VREG

M3

M2

M1

PWM_C

RESET_CD

PWM_D

GVDD_C

GVDD_D

BST_D

PVDD_D

OUT_D

GND_D

GND_C

OUT_C

PVDD_C

BST_C

BST_B

PVDD_B

OUT_B

GND_B

GND_A

VDD

GVDD_A

BST_A

PVDD_A

OUT_A

NC

PVDD_D

PVDD_A

NC

25V

33nF

100nF

50V

100nF

50V

100nF

470nF

100nF

50V

10µH

470µF

50V

470 Fµ

50V

33nF

25V

3.3 W

100nF

0 W

22k

100nF

33nF

25V

100nF

50V

10nF

50V

100nF

470nF

100nF

100nF 50V

33nF

25V

100nF

50V

100nF

10µH

3.3 W

10nF

50V

10nF

50V

3.3 W

1nF 50V

3.3 W

10nF

50V

10nF

50V

3.3 W

3.3

W

10nF

50V

2.2

W

2.2 W

2.2

W

2.2 W

50V

GND

TAS5352A

SLES239 – NOVEMBER 2008 ...........................................................................................................................................................................................

www.ti.com

Figure 15. Typical Non-Differential (1N) BTL Application With AD Modulation Filters

Product Folder Link(s): TAS5352A

GVDD(+12V)

VDD(+12V)

PVDD

GVDD(+12V)

PVDD

A

B

C

D

PVDD

B

PVDD

C

PVDD

D

GND

GND GND GND

GND

GND GND

GND

TAS5508/18

PWM1_P

PWM2_P

PWM3_P

PWM4_P

VALID

Microcontroller

I2C

100nF 50V

2

1

100nF100nF

2

1

100nF 50V

2

1

10nF 50V

21

10nF

50V

10nF

50V

2

1

100nF 50V

2

1

3.3R3.3R

1

2

10nF

50V 10nF

50V

21

3.3R3.3R

1

2

10nF 50V

21

0R0R

1 2

10nF

50V 10nF

50V

21

100nF 50V

2

1

3.3R3.3R

1

2

470uF

50V

470uF

50V

1

2

33nF 25V33nF 25V

21

100nF 50V

2

1

470uF

50V

470uF

50V

1

2

3.3R3.3R

1

2

10nF

50V 10nF

50V

21

10k1%10k 1%

1

2

33nF 25V33nF 25V

21

3.3R3.3R

1

2

470uF

50V

470uF

50V

1

2

470uF

50V

470uF

50V

1

2

100nF100nF

21

3.3R3.3R

1

2

10nF

50V

10nF

50V

2

1

470uF

50V

470uF

50V

1

2

22k22k

1 2

100nF 50V

2

1

10k1%10k 1%

1

2

3.3R3.3R

1

2

TAS5352ADDV

GVDD_B

1

OTW

2

SD

5

PWM_A

6

RESET_AB

7

PWM_B

8

OC_ADJ

9

GND

10

AGND

11

VREG

12

M3

13

M2

14

M1

15

PWM_C

16

RESET_CD

17

PWM_D

18

GVDD_C

22

GVDD_D

23

BST_D

24

PVDD_D

27

OUT_D

28

GND_D

29

GND_C

30

OUT_C

31

PVDD_C

32

BST_C

33

BST_B

34

PVDD_B

35

OUT_B

36

GND_B

37

GND_A

38

VDD

21

GVDD_A

44

BST_A

43

PVDD_A

40

OUT_A

39

NC

3

NC

4

NC

19

NC

20

NC

25

PVDD_D

26

PVDD_A

41

NC

42

2.2R2.2R

1

2

20uH20uH

1 2

470uF

50V

470uF

50V

1

2

10k1%10k 1%

1

2

3.3R3.3R

1

2

10k10k

1

2

470uF

50V

470uF

50V

1

2

100nF100nF

2

1

100nF 50V

2

1

100nF 50V

2

1

20uH20uH

1 2

33nF 25V33nF 25V

21

10k10k

1

2

10k10k

1

2

100nF 50V

2

1

100nF100nF

2

1

2.2R2.2R

1

2

1uF1uF

2

1

33nF 25V33nF 25V

21

100nF100nF

2

1

20uH20uH

1 2

1uF1uF

2

1

470uF

50V

470uF

50V

1

2

10k1%10k 1%

1

2

2.2R2.2R

1

2

3.3R3.3R

1

2

20uH20uH

1 2

10k10k

1

2

10nF 50V

21

10k1%10k 1%

1

2

100nF100nF

2

1

1uF1uF

2

1

10k1%10k 1%

1

2

470uF

50V

470uF

50V

1

2

100nF 50V

2

1

10k1%10k 1%

1

2

100nF 50V

2

1

10nF 50V

21

2.2R2.2R

1

2

10nF

50V 10nF

50V

21

1uF1uF

2

1

10k1%10k 1%

1

2

470uF

50V

470uF

50V

1

2

100nF 50V

2

1

3.3R3.3R

1

2

TAS5352A

www.ti.com

........................................................................................................................................................................................... SLES239 – NOVEMBER 2008

Figure 16. Typical SE Application

Product Folder Link(s): TAS5352A

GVDD(+12V)

VDD(+12V)

PVDD

GVDD(+12V)

GND

TAS5508/18

PWM1_P

PWM1_M

VALID

Microcontroller

I2C

10µH

100nF

TAS5352ADDV

GVDD_B

OTW

SD

PWM_A

RESET_AB

PWM_B

OC_ADJ

GND

AGND

VREG

M3

M2

M1

PWM_C

RESET_CD

PWM_D

GVDD_C

GVDD_D

BST_D

PVDD_D

OUT_D

GND_D

GND_C

OUT_C

PVDD_C

BST_C

BST_B

PVDD_B

OUT_B

GND_B

GND_A

VDD

GVDD_A

BST_A

PVDD_A

OUT_A

NC

PVDD_D

PVDD_A

NC

25V

33nF

100nF

50V

100nF

1µF

100nF

50V

10µH

470µF

50V

470 Fµ

50V

33nF

25V

3.3 W

100nF

0 W

22k

100nF

33nF

25V

100nF

50V

10nF

50V

100nF

100nF 50V

33nF

25V

100nF

50V

100nF

10µH

3.3 W

10nF

50V

10nF

50V

3.3 W

1nF 50V

3.3

W

10nF

50V

2.2

W

2.2 W

2.2

W

2.2 W

1R

GVDD(+12V)

VDD(+12V)

PVDD

GVDD(+12V)

GND

TAS5508/18

PWM1_P

PWM1_M

VALID

Microcontroller

I2C

10µH

100nF

TAS5352ADDV

GVDD_B

OTW

SD

PWM_A

RESET_AB

PWM_B

OC_ADJ

GND

AGND

VREG

M3

M2

M1

PWM_C

RESET_CD

PWM_D

GVDD_C

GVDD_D

BST_D

PVDD_D

OUT_D

GND_D

GND_C

OUT_C

PVDD_C

BST_C

BST_B

PVDD_B

OUT_B

GND_B

GND_A

VDD

GVDD_A

BST_A

PVDD_A

OUT_A

NC

PVDD_D

PVDD_A

NC

25V

33nF

100nF

50V

100nF

1µF

100nF

50V

10µH

470µF

50V

470 Fµ

50V

33nF

25V

3.3 W

100nF

0 W

22k

100nF

33nF

25V

100nF

50V

10nF

50V

100nF

100nF 50V

33nF

25V

100nF

50V

100nF

10µH

3.3 W

10nF

50V

10nF

50V

3.3 W

1nF 50V

3.3

W

10nF

50V

2.2

W

2.2 W

2.2

W

2.2 W

1R

50V

TAS5352A

SLES239 – NOVEMBER 2008 ...........................................................................................................................................................................................

www.ti.com

Figure 17. Typical Differential (2N) PBTL Application With AD Modulation Filters

Product Folder Link(s): TAS5352A

Figure 18. Typical Non-Differential (1N) PBTL Application

TAS5352A

www.ti.com

........................................................................................................................................................................................... SLES239 – NOVEMBER 2008

THEORY OF OPERATION

POWER SUPPLIES

To facilitate system design, the TAS5352A needs only a 12 V supply in addition to the (typical) 34.5 V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.

In order to provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the same 12-V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated SEQUENCE pins as possible. In general, inductance between the power supply pins and decoupling capacitors must be avoided. (See reference board documentation for additional information.)

For a properly functioning bootstrap circuit, a small high-impedance state until the gate-drive supply ceramic capacitor must be connected from each voltage (GVDD_X) and VDD voltage are above the bootstrap pin (BST_X) to the power-stage output pin undervoltage protection (UVP) voltage threshold (see (OUT_X). When the power-stage output is low, the the Electrical Characteristics section of this data bootstrap capacitor is charged through an internal sheet). Although not specifically required, it is diode connected between the gate-drive power-- recommended to hold RESET_AB and RESET_CD in supply pin (GVDD_X) and the bootstrap pin. When a low state while powering up the device. This allows the power-stage output is high, the bootstrap an internal circuit to charge the external bootstrap capacitor potential is shifted above the output capacitors by enabling a weak pulldown of the potential and thus provides a suitable voltage supply half-bridge output. for the high-side gate driver. In an application with PWM switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle. In an application running at a reduced switching frequency, generally 192 kHz, the bootstrap capacitor might need to be increased in value.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin. It is recommended to follow the PCB layout of the TAS5352A reference design. For additional information on recommended power supply and required components, see the application diagrams given previously in this data sheet.

The 12 V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the

34.5 V power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5352A is fully protected against erroneous power-stage turnon due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-critical within the specified range (see the Recommended Operating Conditions section of this data sheet).

SYSTEM POWER-UP/POWER-DOWN

Powering Up

The TAS5352A does not require a power-up sequence. The outputs of the H-bridges remain in a

When the TAS5352A is being used with TI PWM modulators such as the TAS5518, no special attention to the state of RESET_AB and RESET_CD is required, provided that the chipset is configured as recommended.

Powering Down

The TAS5352A does not require a power-down sequence. The device remains fully operational as long as the gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical

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Characteristics section of this data sheet). Although signal using the system microcontroller and not specifically required, it is a good practice to hold responding to an overtemperature warning signal by, RESET_AB and RESET_CD low during power down, e.g., turning down the volume to prevent further thus preventing audible artifacts including pops or heating of the device resulting in device shutdown clicks. (OTE).

When the TAS5352A is being used with TI PWM To reduce external component count, an internal modulators such as the TAS5518, no special pullup resistor to 3.3 V is provided on both SD and attention to the state of RESET_AB and RESET_CD OTW outputs. Level compliance for 5-V logic can be is required, provided that the chipset is configured as obtained by adding external pullup resistors to 5 V recommended. (see the Electrical Characteristics section of this data

sheet for further specifications).

Mid Z Sequence Compatibility

The TAS5352A is compatible with the Mid Z sequence of the TAS5086 Modulator. The Mid Z The TAS5352A contains advanced protection circuitry Sequence is a series of pulses that is generated by carefully designed to facilitate system integration and the modulator. This sequence causes the power ease of use, as well as to safeguard the device from stage to slowly enable its outputs as it begins to permanent failure due to a wide range of fault switch. conditions such as short circuits, overload,

By slowly starting the PWM switching, the impulse response created by the onset of switching is reduced. This impulse response is the acoustic artifact that is heard in the output transducers (loudspeakers) and is commonly termed " click " or " pop " .

The low acoustic artifact noise of the TAS5352A will be further decreased when used in conjunction with the TAS5086 modulator with the Mid Z Sequence enabled.

The Mid Z sequence is primarily used for the single-ended output configuration. It facilitates a " softer " PWM output start after the split cap output configuration is charged.

ERROR REPORTING

The SD and OTW pins are both active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device.

Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW goes low when the device junction temperature exceeds 125 ° C (see the following table).

SD OTW DESCRIPTION

0 0 Overtemperature (OTE) or overload (OLP) or

undervoltage (UVP) 0 1 Overload (OLP) or undervoltage (UVP) 1 0 Junction temperature higher than 125 ° C

(overtemperature warning) 1 1 Junction temperature lower than 125 ° C and no

OLP or UVP faults (normal operation)

Note that asserting either RESET_AB or RESET_CD low forces the SD signal high, independent of faults being present. TI recommends monitoring the OTW

DEVICE PROTECTION SYSTEM

overtemperature, and undervoltage. The TAS5352A responds to a fault by immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than overload and over-temperature error ( OTE), the device automatically recovers when the fault condition has been removed, i.e., the supply voltage has increased.

The device will function on errors, as shown in the following table

BTL MODE PBTL MODE SE MODE

Local Local Local

Error Turns Off Error Turns Off Error Turns Off

In In In

A A A B B B C C C D D D

Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge.

Use of TAS5352A in High-Modulation-Index Capable Systems

This device requires at least 30 ns of low time on the output per 384-kHz PWM frame rate in order to keep the bootstrap capacitors charged. As an example, if the modulation index is set to 99.2% in the TAS5508, this setting allows PWM pulse durations down to 10 ns. This signal, which does not meet the 30-ns requirement, is sent to the PWM_X pin and this low-state pulse time does not allow the bootstrap capacitor to stay charged. The TAS5352A device requires limiting the TAS5508 modulation index to

97.7% to keep the bootstrap capacitor charged under all signals and loads.

The TAS5352A contains a bootstrap capacitor under voltage protection circuit (BST_UVP) that monitors the voltage on the bootstrap capacitors. When the

A + B A + B

A + B + C

+ D

C + D C + D

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........................................................................................................................................................................................... SLES239 – NOVEMBER 2008

voltage on the bootstrap capacitors is less than In general, it is recommended to follow closely the required for proper control of the High-Side external component selection and PCB layout as MOSFETs, the device will initiate bootstrap capacitor given in the Application section. recharge sequences until the bootstrap capacitors are properly charged for robust operation. This function may be activated with PWM pulses less than 30 nS.

For added flexibility, the OC threshold is programmable within a limited range using a single

external resistor connected between the OC_ADJ pin Therefore, TI strongly recommends using a TI PWM and AGND. (See the Electrical Characteristics section processor, such as TAS5518, TAS5086 or TAS5508, of this data sheet for information on the correlation with the modulation index set at 97.7% to interface between programming-resistor value and the OC with TAS5352A. threshold.) It should be noted that a properly

functioning overcurrent detector assumes the

Overcurrent (OC) Protection With Current Limiting and Overload Detection

The device has independent, fast-reacting current detectors with programmable trip threshold (OC threshold) on all high-side and low-side power-stage FETs. See the following table for OC-adjust resistor values. The detector outputs are closely monitored by two protection systems. The first protection system controls the power stage in order to prevent the output current from further increasing, i.e., it performs a current-limiting function rather than prematurely shutting down during combinations of high-level music transients and extreme speaker load

presence of a properly designed demodulation filter at

the power-stage output. It is required to follow certain

guidelines when selecting the OC threshold and an

appropriate demodulation inductor:

OC-Adjust Resistor Values Max. Current Before OC Occurs

(k Ω ) (A), TC= 75 ° C

22 10.9 33 9.1 47 7.1

The reported max peak current in the table above is

measured with continuous current in 1 Ω , one

channel active and the other one muted. impedance drops. If the high-current situation

persists, i.e., the power stage is being overloaded, a

Pin-To-Pin Short Circuit Protection (PPSC)

second protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state. Current limiting and overload protection are independent for half-bridges A and B and, respectively, C and D. That is, if the bridge-tied load between half-bridges A and B causes an overload fault, only half-bridges A and B are shut down.

• For the lowest-cost bill of materials in terms of

component selection, the OC threshold measure should be limited, considering the power output requirement and minimum load impedance. Higher-impedance loads require a lower OC threshold.

• The demodulation-filter inductor must retain at

least 5 µ H of inductance at twice the OC threshold setting.

Unfortunately, most inductors have decreasing inductance with increasing temperature and increasing current (saturation). To some degree, an increase in temperature naturally occurs when operating at high output currents, due to core losses and the dc resistance of the inductor ' s copper winding. A thorough analysis of inductor saturation and thermal properties is strongly recommended.

The PPSC detection system protects the device from

permanent damage in the case that a power output

pin (OUT_X) is shorted to GND_X or PVDD_X. For

comparison the OC protection system detects an over

current after the demodulation filter where PPSC

detects shorts directly at the pin before the filter.

PPSC detection is performed at startup i.e. when

VDD is supplied, consequently a short to either

GND_X or PVDD_X after system startup will not

activate the PPSC detection system. When PPSC

detection is activated by a short on the output, all half

bridges are kept in a Hi-Z state until the short is

removed, the device then continues the startup

sequence and starts switching. The detection is

controlled globally by a two step sequence. The first

step ensures that there are no shorts from OUT_X to

GND_X, the second step tests that there are no

shorts from OUT_X to PVDD_X. The total duration of

this process is roughly proportional to the capacitance

of the output LC filter. The typical duration is < 15

ms/ µ F. While the PPSC detection is in progress, SD

is kept low, and the device will not react to changes

applied to the RESET pins. If no shorts are present

the PPSC detection passes, and SD is released. A

device reset will not start a new PPSC detection.

PPSC detection is enabled in BTL and PBTL output Setting the OC threshold too low might cause issues

such as lack of enough output power and/or unexpected shutdowns due to too-sensitive overload detection.

configurations, the detection is not performed in SE

mode. To make sure not to trip the PPSC detection

system it is recommended not to insert resistive load

to GND_X or PVDD_X.

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Overtemperature Protection

The TAS5352A has a two-level temperature-protection system that asserts an active-low warning signal ( OTW) when the device junction temperature exceeds 125 ° C (typical) and, if the device junction temperature exceeds 155 ° C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, either RESET_AB or RESET_CD must be asserted. Thereafter, the device resumes normal operation.

Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5352A fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics Table. Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and SD being asserted low. The device automatically resumes operation when all supply voltages have increased above the UVP threshold.

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DEVICE RESET

Two reset pins are provided for independent control

of half-bridges A/B and C/D. When RESET_AB is

asserted low, all four power-stage FETs in half--

bridges A and B are forced into a high-impedance

(Hi-Z) state. Likewise, asserting RESET_CD low

forces all four power-stage FETs in half-bridges C

and D into a high-impedance state. Thus, both reset

pins are well suited for hard-muting the power stage if

needed.

In BTL modes, to accommodate bootstrap charging

prior to switching start, asserting the reset inputs low

enables weak pulldown of the half-bridge outputs. In

the SE mode, the weak pulldowns are not enabled,

and it is therefore recommended to ensure bootstrap

capacitor charging by providing a low pulse on the

PWM inputs when reset is asserted high.

Asserting either reset input low removes any fault

information to be signaled on the SD output, i.e., SD

is forced high.

A rising-edge transition on either reset input allows

the device to resume operation after an overload

fault. To ensure thermal reliability, the rising edge of

reset must occur no sooner than 4 ms after the falling

edge of SD.

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PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

TAS5352ADDVR HTSSOP DDV 44 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1

Type

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TAS5352ADDVR HTSSOP DDV 44 2000 367.0 367.0 45.0

Pack Materials-Page 2

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Datasheet tas5352a Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

DESCRIPTION

GENERAL INFORMATION

Terminal Assignment

Protection MODE Selection Pins

Package Heat Dissipation Ratings

ABSOLUTE MAXIMUM RATINGS

Terminal Functions

TYPICAL SYSTEM BLOCK DIAGRAM

FUNCTIONAL BLOCK DIAGRAM

RECOMMENDED OPERATING CONDITIONS

AUDIO SPECIFICATIONS (BTL)

AUDIO SPECIFICATIONS (Single-Ended Output)

AUDIO SPECIFICATIONS (PBTL)

ELECTRICAL CHARACTERISTICS

TYPICAL CHARACTERISTICS, BTL CONFIGURATION

TYPICAL CHARACTERISTICS, SE CONFIGURATION

TYPICAL CHARACTERISTICS, PBTL CONFIGURATION

APPLICATION INFORMATION

PCB Material Recommendation

PVDD Capacitor Recommendation

Decoupling Capacitor Recommendations

System Design Recommendations

THEORY OF OPERATION

POWER SUPPLIES

Powering Up

Powering Down

Mid Z Sequence Compatibility

ERROR REPORTING

DEVICE PROTECTION SYSTEM

Use of TAS5352A in High-Modulation-Index Capable Systems

Overcurrent (OC) Protection With Current Limiting and Overload Detection

Pin-To-Pin Short Circuit Protection (PPSC)

Overtemperature Protection

Undervoltage Protection (UVP) and Power-On Reset (POR)

DEVICE RESET