TEXAS INSTRUMENTS TAS5342 Technical data

0 302 4 6 8 10 12 14 16 18 20 22 24 26 28

Ω

T =75°C THD+Nat10%

P Output Po

wer

– –

PVDD – SupplyVoltage – V

130

100

105

110

115

120

125

TAS5342

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FEATURES

• Total Power Output (Bridge Tied Load) – 2 × 100 W at 10% THD+N Into 4 Ω – 2 × 80 W at 10% THD+N Into 6 Ω – 2 × 65 W at 10% THD+N Into 8 Ω

• Total Power Output (Single Ended) – 4 × 40 W at 10% THD+N Into 3 Ω – 4 × 30 W at 10% THD+N Into 4 Ω

• Total Power Output (Parallel Mode) – 1 × 200 W at 10% THD+N Into 2 Ω – 1 × 160 W at 10% THD+N Into 3 Ω

• >110 dB SNR (A-Weighted With TAS5518 Modulator)

• <0.1% THD+N (1 W, 1 kHz)

• Supports PWM Frame Rates of 192 kHz to

432 kHz

• Resistor-Programmable Current Limit

• Integrated Self-Protection Circuitry, Including:

– Under Voltage Protection – Overtemperature Warning and Error – Overload Protection – Short-Circuit Protection – PWM Activity Detector

• Standalone Protection Recovery

• Power-On Reset (POR) to Eliminate System

Power-Supply Sequencing

• High-Efficiency Power Stage (>90%) With 80-m Ω Output MOSFETs

• Thermally Enhanced Package 44-Pin HTSSOP (DDV)

• Error Reporting, 3.3-V and 5.0-V Compliant

• EMI Compliant When Used With

Recommended System Design

APPLICATIONS

• Mini/Micro Audio System

• DVD Receiver

• Home Theater

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 PurePath Digital, PowerPad are trademarks of Texas Instruments. 3 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

100 W STEREO DIGITAL AMPLIFIER POWER STAGE

DESCRIPTION

The TAS5342 is a high-performance, integrated stereo digital amplifier power stage designed to drive a 4- Ω bridge-tied load (BTL) at up to 100 W per channel with low harmonic distortion, low integrated noise, and low idle current.

The TAS5342 has a complete protection system integrated on-chip, safeguarding the device against a wide range of fault conditions that could damage the system. These protection features are short-circuit protection, over-current protection, under voltage protection, over temperature protection, and a loss of PWM signal (PWM activity detector).

A power-on-reset (POR) circuit is used to eliminate power-supply sequencing that is required for most power-stage designs.

PurePath Digital™

SLAS557B – SEPTEMBER 2007 – REVISED OCTOBER 2007

BTL OUTPUT POWER

SUPPLY VOLTAGE

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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

GVDD_B

OTW

NC NC SD

PWM_A

RESET_AB

PWM_B

OC_ADJ

GND AGND VREG

M3 M2 M1

PWM_C

RESET_CD

PWM_D

NC NC

VDD

GVDD_C

DDV PACKAGE

(TOP VIEW)

GVDD_A BST_A NC PVDD_A PVDD_A OUT_A GND_A GND_B OUT_B PVDD_B BST_B BST_C PVDD_C OUT_C GND_C GND_D OUT_D PVDD_D PVDD_D NC BST_D GVDD_D

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23

P0016-02

TAS5342

SLAS557B – SEPTEMBER 2007 – REVISED OCTOBER 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

GENERAL INFORMATION

Terminal Assignment

The TAS5342 is available in a thermally enhanced package 44-pin HTSSOP PowerPad™ package (DDV) This package contains a thermal pad that is located on the top side of the device for convenient thermal coupling

to the heatsink.

Product Folder Link(s): TAS5342

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TAS5342

SLAS557B – SEPTEMBER 2007 – REVISED OCTOBER 2007

Protection MODE Selection Pins

Protection modes are selected by shorting M1, M2, and M3 to VREG or GND.

MODE PINS

M3 M2 M1

Mode Name PWM Input

0 0 0 BTL mode 1 2N All protection systems enabled 0 0 1 BTL mode 2 2N Latching shudown on, PWM activity detector and OLP disabled 0 1 0 BTL mode 3 1N All protection systems enabled 0 1 1 PBTL mode 1N / 2N 1 0 0 SE mode 1 1N All protection systems enabled 1 0 1 SE mode 2 1N Latching shudown on, PWM activity detector and OLP disabled 1 1 0 1 1 1

(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode. (2) PWM_D is used to select between the 1N and 2N interface in PBTL mode (Low = 1N; High = 2N). PWM_D is internally pulled low in

PBTL mode. PWM_A is used as the PWM input in 1N mode and PWM_A and PWM_B are used as inputs for the 2N mode.

(3) PPSC detection system disabled.

(1)

(2)

Description

All protection systems enabled

(3)

Reserved

(3)

Package Heat Dissipation Ratings

PARAMETER TAS5342DDV

( ° C/W) — 2 BTL or 4 SE channels 1.3

θ JC

( ° C/W) — 1 BTL or 2 SE channel(s) 2.6

θ JC

( ° C/W) — 1 SE channel 5.0

θ JC

Power Pad area

(1) JC is junction-to-case, CH is case-to-heatsink. (2) R

is an important consideration. Assume a 2-mil thickness of high performance grease with a thermal conductivity at 2.5W/m-K

θ CH

between the pad area and the heat sink. The R

(1)

(2)

with this condition is 0.6 ° C/W for the DDV package.

θ CH

36 mm

Product Folder Link(s): TAS5342

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TAS5342

SLAS557B – SEPTEMBER 2007 – REVISED OCTOBER 2007

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

VDD to AGND – 0.3 V to 13.2 V GVDD_X to AGND – 0.3 V to 13.2 V PVDD_X to GND_X OUT_X to GND_X BST_X to GND_X BST_X to GVDD_X VREG to AGND – 0.3 V to 4.2 V GND_X to GND – 0.3 V to 0.3 V GND_X to AGND – 0.3 V to 0.3 V GND to AGND – 0.3 V to 0.3 V PWM_X, OC_ADJ, M1, M2, M3 to AGND – 0.3 V to 4.2 V RESET_X, SD, OTW to AGND – 0.3 V to 7 V Maximum continuous sink current ( SD, OTW) 9 mA Maximum operating junction temperature range, T Storage temperature – 40 ° C to 125 ° C Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds 260 ° C Minimum pulse duration, low 30 ns

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.

(2)

(1)

TAS5342

– 0.3 V to 53 V – 0.3 V to 53 V

– 0.3 V to 66.2 V

– 0.3 V to 53 V

0 ° C to 125 ° C

ORDERING INFORMATION

PACKAGE

(1)

DESCRIPTION

0 ° C to 70 ° C TAS5342DDV 44-pin HTSSOP

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com .

Product Folder Link(s): TAS5342

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SLAS557B – SEPTEMBER 2007 – REVISED OCTOBER 2007

Terminal Functions

TERMINAL

NAME DDV NO.

AGND 11 P Analog ground BST_A 43 P Bootstrap pin, A-Side BST_B 34 P Bootstrap pin, B-Side BST_C 33 P Bootstrap pin, C-Side BST_D 24 P Bootstrap pin, D-Side

GND 10 P Ground GND_A 38 P Power ground for half-bridge A GND_B 37 P Power ground for half-bridge B GND_C 30 P Power ground for half-bridge C GND_D 29 P Power ground for half-bridge D

GVDD_A 44 P Gate-drive voltage supply; A-Side GVDD_B 1 P Gate-drive voltage supply; B-Side GVDD_C 22 P Gate-drive voltage supply; C-Side GVDD_D 23 P Gate-drive voltage supply; D-Side

M1 15 I Mode selection pin (LSB) M2 14 I Mode selection pin M3 13 I Mode selection pin (MSB) NC 3, 4, 19, 20, 25, 42 – No connect. Pins may be grounded.

OC_ADJ 9 O Analog overcurrent programming pin

OTW 2 O Overtemperature warning signal, open-drain, active-low OUT_A 39 O Output, half-bridge A OUT_B 36 O Output, half-bridge B OUT_C 31 O Output, half-bridge C OUT_D 28 O Output, half-bridge D

PVDD_A 40, 41 P Power supply input for half-bridge A PVDD_B 35 P Power supply input for half-bridge B PVDD_C 32 P Power supply input for half-bridge C PVDD_D 26, 27 P Power supply input for half-bridge D

PWM_A 6 I PWM Input signal for half-bridge A PWM_B 8 I PWM Input signal for half-bridge B PWM_C 16 I PWM Input signal for half-bridge C

PWM_D 18 I PWM Input signal for half-bridge D RESET_AB 7 I Reset signal for half-bridge A and half-bridge B, active-low RESET_CD 17 I Reset signal for half-bridge C and half-bridge D, active-low

SD 5 O Shutdown signal, open-drain, active-low

VDD 21 P Input power supply

VREG 12 P Internal voltage regulator

(1) I = input, O = output, P = power

FUNCTION

(1)

DESCRIPTION

TAS5342

Product Folder Link(s): TAS5342

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2nd-OrderL-C

OutputFilter

forEach

Half-Bridge

Bootstrap

Capacitors

2-Channel

H-Bridge

BTL Mode

System

Microcontroller

OUT_A

OUT_B

OUT_C

OUT_D

BST_A

BST_B

BST_C

BST_D

RESET_AB RESET_CD

System

Power

Supply

Hardwire

Mode

Control

PVDD

GVDD(12V)/VDD(12V)

GND

Hardwire OCLimit

PVDD Power Supply

Decoupling

31.5V

12V

GND

VAC

PWM_A

PWM_C

PWM_D

PWM_B

VALID

Left-

Channel

Output

Right-

Channel

Output

Input H-Bridge1

Input H-Bridge2

GVDD

VDD

VREG

PowerSupply

Decoupling

4 4 4

Bootstrap

Capacitors

2nd-OrderL-C

OutputFilter

forEach

Half-Bridge

Output

H-Bridge2

Output

H-Bridge1

OTW

TAS5518

B0047-02

PVDD_A,B,C,D

GND_A,B,C,D

GVDD_A,B,C,D

GND

VDD

VREG

AGND

OC_ADJ

I2C

TAS5342

SLAS557B – SEPTEMBER 2007 – REVISED OCTOBER 2007

TYPICAL SYSTEM BLOCK DIAGRAM

Product Folder Link(s): TAS5342

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FUNCTIONAL BLOCK DIAGRAM

Temp. Sense

RESET_AB

OTW

AGND

OC_ADJ

VREG VREG

VDD

Power

Reset

Under-

voltage

Protection

GND

PWM_D OUT_D

GND_D

PVDD_D

BST_D

Timing

Gate

Drive

PWM

Rcv.

Overload

Protection

sens e

GVDD_D

RESET_CD

Protection

and

I/OLogic

PWM_C OUT_C

GND_C

PVDD_C

BST_C

Timing

Gate

Drive

Ctrl.

PWM

Rcv.

GVDD_C

PWM_B OUT_B

GND_B

PVDD_B

BST_B

Timing

Gate

Drive

Ctrl.

PWM

Rcv.

GVDD_B

PWM_A OUT_A

GND_A

PVDD_A

BST_A

Timing

Gate

Drive

Ctrl.

PWM

Rcv.

GVDD_A

Ctrl.

BTL/PBTL−Configuration

Pulldown Resistor

BTL/PBTL−Configuration

PulldownResistor

BTL/PBTL−Configuration

PulldownResistor

BTL/PBTL−Configuration

PulldownResistor

InternalPullup

ResistorstoVREG

B0034-03

TAS5342

SLAS557B – SEPTEMBER 2007 – REVISED OCTOBER 2007

Product Folder Link(s): TAS5342

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TAS5342

SLAS557B – SEPTEMBER 2007 – REVISED OCTOBER 2007

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT

PVDD_X Half-bridge supply voltage 0 31.5 34 V GVDD_X 10.8 12 13.2 V VDD Digital regulator supply voltage 10.8 12 13.2 V

RL(BTL) 3 4 RL(SE) current control), recommended demodulation 2.25 3 Ω RL(PBTL) 1.5 2 L

(BTL) 5 10

Output

(SE) Output-filter inductance 5 10 μ H

Output

(PBTL) 5 10

Output

LOW

PVDD

BST

EXT-PULLUP

Supply voltage for logic regulators and gate-drive circuitry

Resistive load impedance (no Cycle-by_Cycle filter

Minimum output inductance under short-circuit condition

PWM frame rate 192 384 432 kHz Minimum low-state pulse duration per PWM

Frame, noise shaper enabled

30 nS

PVDD close decoupling capacitors 0.1 μ F Bootstrap capacitor, selected value supports

PWM frame rates from 192 kHz to 432 kHz

33 nF

Over-current programming resistor Resistor tolerance = 5% 27 27 47 k Ω External pull-up resistor to +3.3V to +5.0V for

SD or OTW

3.3 4.7 k Ω

Junction temperature 0 125 ° C

AUDIO SPECIFICATIONS (BTL)

Audio performance is recorded as a chipset consisting of a TAS5518 pwm processor (modulation index limited to 97.7%) and a TAS5342 power stage. PCB and system configuraton are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_x = 31.5 V, GVDD_x = 12 V, RL= 4 Ω , fS= 384 kHz, R C

= 470 nF, unless otherwise noted.

DEM

PARAMETER TEST CONDITIONS UNIT

RL= 4 Ω , 10% THD+N, clipped input signal

OMAX

Maximum Power Output 80

Unclipped Power Output 64

THD+N Total harmonic distortion + noise

SNR Signal-to-noise ratio

Output integrated noise A-weighted, AES17 filter, Auto mute μ V

(1)

DNR Dynamic range 110 dB DC Offset Output offset voltage +/- 15 mV

idle

Power dissipation due to idle losses (IPVDD_X) PO= 0 W, all halfbridges switching

(1) SNR is calculated relative to 0-dBFS input level. (2) Actual system idle losses are affected by core losses of output inductors.

RL= 6 Ω , 10% THD+N, clipped input signal

RL= 8 Ω , 10% THD+N, clipped input signal

RL= 4 Ω , 0 dBFS, unclipped input signal

RL= 6 Ω , 0 dBFS, unclipped input signal

RL= 8 Ω , 0 dBFS, unclipped input signal

0 dBFS; AES17 filter 0.2% 1 W; AES17 filter 0.09%

disabled A-weighted, AES17 filter, Auto mute

disabled A-weighted, input level = – 60 dBFS,

AES17 filter

= 27 k Ω , TC= 75 ° C, Output Filter: L

MIN TYP MAX

(2)

DEM

TAS5342

100

65 W

110 dB

2 W

= 10 μ H,

Product Folder Link(s): TAS5342

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TAS5342

SLAS557B – SEPTEMBER 2007 – REVISED OCTOBER 2007

AUDIO SPECIFICATIONS (Single-Ended Output)

Audio performance is recorded as a chipset consisting of a TAS5086 pwm processor (modulation index limited to 97.7%) and a TAS5342 power stage. PCB and system configuraton are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_x = 31.5 V, GVDD_x = 12 V, RL= 4 Ω , fS= 384 kHz, R C

= 1.0 μ F, unless otherwise noted.

DEM

PARAMETER TEST CONDITIONS UNIT

RL= 3 Ω , 10% THD+N, clipped input

OMAX

Maximum Power Output

Unclipped Power Output

THD+N Total harmonic distortion + noise

SNR A-weighted, AES17 filter, Auto mute 109 dB

Output integrated noise

Signal-to-noise ratio

(1)

DNR Dynamic range 109 dB P

idle

Power dissipation due to idle losses (IPVDD_X)

(1) SNR is calculated relative to 0-dBFS input level. (2) Actual system idle losses are affected by core losses of output inductors.

signal RL= 4 Ω , 10% THD+N, clipped input

signal RL= 3 Ω , 0 dBFS, unclipped input

signal RL= 4 Ω , 0 dBFS, unclipped input

signal 0 dBFS; AES17 filter 0.2% 1 W; AES17 filter 0.09% A-weighted, AES17 filter, Auto mute 35 μ V

disabled

disabled A-weighted, input level = – 60 dBFS

AES17 filter PO= 0 W, all half bridges 2 W

switching

= 27 k Ω , TC= 75 ° C, Output Filter: L

(2)

TAS5342

MIN TYP MAX

= 20 μ H,

DEM

AUDIO SPECIFICATIONS (PBTL)

Audio performance is recorded as a chipset consisting of a TAS5518 pwm processor (modulation index limited to 97.7%) and a TAS5342 power stage. PCB and system configuraton are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_x = 31.5 V, GVDD_x = 12 V, RL= 3 Ω , fS= 384 kHz, R = 1.0 uF, unless otherwise noted.

PARAMETER TEST CONDITIONS UNIT

RL= 2 Ω , 10% THD+N, clipped input

OMAX

Maximum Power Output

Unclipped Power Output

THD+N Total harmonic distortion + noise

SNR A-weighted, AES17 filter, Auto mute 110 dB

Output integrated noise

Signal-to-noise ratio

(1)

DNR Dynamic range 110 dB DC Offset Outuput offset voltage +/- 15 mV

signal RL= 3 Ω , 10% THD+N, clipped input

signal RL= 2 Ω , 0 dBFS, unclipped input

signal RL= 3 Ω , 0 dBFS, unclipped input

signal 0 dBFS; AES17 filter 0.2% 1 W; AES17 filter 0.09% A-weighted, AES17 filter, Auto mute 45 μ V

disabled

disabled A-weighted, input level = – 60 dBFS

AES17 filter

= 27 k Ω , TC= 75 ° C, Output Filter: L

TAS5342

MIN TYP MAX

200

160

150

120

DEM

= 10 μ H, C

DEM

(1) SNR is calculated relative to 0-dBFS input level.

Product Folder Link(s): TAS5342

+ 20 hidden pages

TEXAS INSTRUMENTS TAS5342 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

DESCRIPTION

GENERAL INFORMATION

Terminal Assignment

Protection MODE Selection Pins

Package Heat Dissipation Ratings

ABSOLUTE MAXIMUM RATINGS

Terminal Functions

TYPICAL SYSTEM BLOCK DIAGRAM

FUNCTIONAL BLOCK DIAGRAM

RECOMMENDED OPERATING CONDITIONS

AUDIO SPECIFICATIONS (BTL)

AUDIO SPECIFICATIONS (Single-Ended Output)

AUDIO SPECIFICATIONS (PBTL)