TAS5186
TM
TAS5186
www.ti.com |
SLES136 –MAY 2005 |
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6-Channel, 210-W, Digital-Amplifier Power Stage
FEATURES
∙Total Output Power @ 10% THD+N
–5×30 W @ 6Ω + 1×60 W @ 3Ω
∙105-dB SNR (A-Weighted)
∙< 0.05% THD+N @ 1 W
∙Power Stage Efficiency > 90% Into Recommended Loads (SE)
∙Integrated Self-Protection Circuits
–Undervoltage
–Overtemperature
–Overload
–Short Circuit
∙Integrated Active-Bias Control to Avoid DC Pop
∙Thermally Enhanced 44-pin HTSSOP Package
∙EMI-Compliant When Used With Recommended System Design
APPLICATIONS
∙DVD Receiver
∙Home Theater in a Box
DESCRIPTION
The TAS5186 is a high-performance, six-channel, digital-amplifier power stage with an improved protection system. The TAS5186 is capable of driving a 6-Ω, single-ended load up to 30 W per each front/satellite channel and a 3-Ω, single-ended subwoofer greater than 60 W at 10% THD+N performance.
A low-cost, high-fidelity audio system can be built using a TI chipset comprising a modulator (e.g., TAS5086) and the TAS5186. This device does not require power-up sequencing because of the internal power-on reset.
The TAS5186 requires only simple passive demodulation filters on its outputs to deliver high-quality, high-efficiency audio amplification. The efficiency of the TAS5186 is greater than 90% when driving 6-Ω satellites and a 3-Ω subwoofer speaker.
The TAS5186 has an innovative protection system integrated on-chip, safeguarding the device against a wide range of fault conditions that could damage the system. These safeguards are short-circuit protection, overload protection, undervoltage protection, and overtemperature protection. The TAS5186 has a new proprietary current-limiting circuit that reduces the possibility of device shutdown during high-level music transients. A new programmable overcurrent detector allows the use of lower-cost inductors in the demodulation output filter.
TOTAL HARMONIC DISTORTION + NOISE vs
OUTPUT POWER
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20 |
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– % |
10 |
PVDD = 40 V |
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TC = 75°C |
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+ Noise |
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Distortion |
1 |
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6 |
Ω Satellite |
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Harmonic |
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0.1 |
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– Total |
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THD+N |
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3 Ω Subwoofer |
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0.01 |
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1 |
10 |
70 |
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PO – Output Power – W |
G012 |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD, PurePath Digital are trademarks of Texas Instruments. All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. |
Copyright © 2005, Texas Instruments Incorporated |
Products conform to specifications per the terms of the Texas |
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Instruments standard warranty. Production processing does not |
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necessarily include testing of all parameters. |
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TAS5186
www.ti.com
SLES136 –MAY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
TERMINAL ASSIGNMENT
The TAS5186 is available in a thermally enhanced 44-pin HTSSOP PowerPAD™ package. The heat slug is located on the top side of the device for convenient thermal coupling to a heatsink.
DDV PACKAGE
(TOP VIEW)
PGND_EF |
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1 |
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44 |
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BST_F |
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PWM_F |
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2 |
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43 |
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PVDD_F |
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GVDD_DEF |
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3 |
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OUT_F |
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VDD |
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PGND_EF |
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PWM_E |
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40 |
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OUT_E |
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PWM_D |
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39 |
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PVDD_E |
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BST_E |
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RESET |
7 |
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38 |
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M3 |
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37 |
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BST_D |
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M2 |
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36 |
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PVDD_D |
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M1 |
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10 |
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35 |
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OUT_D |
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GND |
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11 |
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34 |
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PGND_D |
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AGND |
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12 |
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33 |
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PGND_C |
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VREG |
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32 |
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OUT_C |
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OC_ADJ |
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31 |
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PVDD_C |
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30 |
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BST_C |
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SD |
15 |
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OTW |
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16 |
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29 |
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BST_B |
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PWM_C |
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17 |
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28 |
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PVDD_B |
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PWM_B |
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18 |
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27 |
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OUT_B |
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PWM_A |
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26 |
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PGND_AB |
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GVDD_ABC |
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25 |
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OUT_A |
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BST_BIAS |
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24 |
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PVDD_A |
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OUT_BIAS |
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22 |
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23 |
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BST_A |
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P0016-01
2
TAS5186
www.ti.com
SLES136 –MAY 2005
GENERAL INFORMATION (continued)
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TERMINAL FUNCTIONS |
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TERMINAL |
TYPE(1) |
DESCRIPTION |
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NAME |
NO. |
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AGND |
12 |
P |
Analog ground |
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BST_A |
23 |
P |
HS bootstrap supply (BST), capacitor to OUT_A required |
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BST_B |
29 |
P |
HS bootstrap supply (BST), external capacitor to OUT_B required |
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BST_BIAS |
21 |
P |
BIAS bootstrap supply, external capacitor to OUT_BIAS required |
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BST_C |
30 |
P |
HS bootstrap supply (BST), external capacitor to OUT_C required |
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BST_D |
37 |
P |
HS bootstrap supply (BST), external capacitor to OUT_D required |
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BST_E |
38 |
P |
HS bootstrap supply (BST), external capacitor to OUT_E required |
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BST_F |
44 |
P |
HS bootstrap supply (BST), external capacitor to OUT_F required |
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GND |
11 |
P |
Chip ground |
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GVDD_ABC |
20 |
P |
Gate drive voltage supply |
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GVDD_DEF |
3 |
P |
Gate drive voltage supply |
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M1 |
10 |
I |
Mode selection pin |
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M2 |
9 |
I |
Mode selection pin |
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M3 |
8 |
I |
Mode selection pin |
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OC_ADJ |
14 |
O |
Overcurrent threshold programming pin, resistor to ground required |
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OTW |
16 |
O |
Overtemperature warning open-drain output signal, active-low |
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OUT_A |
25 |
O |
Output, half-bridge A, satellite |
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OUT_B |
27 |
O |
Output, half-bridge B, satellite |
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OUT_BIAS |
22 |
O |
BIAS half-bridge output pin |
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OUT_C |
32 |
O |
Output, half-bridge C, subwoofer |
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OUT_D |
35 |
O |
Output, half-bridge D, satellite |
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OUT_E |
40 |
O |
Output, half-bridge E, satellite |
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OUT_F |
42 |
O |
Output, half-bridge F, satellite |
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PGND_AB |
26 |
P |
Power ground |
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PGND_C |
33 |
P |
Power ground |
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PGND_D |
34 |
P |
Power ground |
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PGND_EF |
1, 41 |
P |
Power ground |
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PVDD_A |
24 |
P |
Power-supply input for half-bridge A |
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PVDD_B |
28 |
P |
Power-supply input for half-bridge B |
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PVDD_C |
31 |
P |
Power-supply input for half-bridge C |
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PVDD_D |
36 |
P |
Power-supply input for half-bridge D |
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PVDD_E |
39 |
P |
Power-supply input for half-bridge E |
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PVDD_F |
43 |
P |
Power-supply input for half-bridge F |
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PWM_A |
19 |
I |
PWM input signal for half-bridge A |
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PWM_B |
18 |
I |
PWM input signal for half-bridge B |
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PWM_C |
17 |
I |
PWM input signal for half-bridge C |
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PWM_D |
6 |
I |
PWM input signal for half-bridge D |
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PWM_E |
5 |
I |
PWM input signal for half-bridge E |
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PWM_F |
2 |
I |
PWM input signal for half-bridge F |
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RESET |
7 |
I |
Reset signal (active-low logic) |
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SD |
15 |
O |
Shutdown open-drain output signal, active-low |
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VDD |
4 |
P |
Power supply for digital voltage regulator |
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VREG |
13 |
O |
Digital regulator supply filter pin, output |
(1)I = input; O = output; P = power
3
TAS5186
www.ti.com
SLES136 –MAY 2005
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Table 1. MODE Selection Pins |
MODE PINS(1) |
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MODE |
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M2 |
M3 |
NAME |
DESCRIPTION |
0 |
0 |
2.1 mode |
Channels A, B, and C enabled; channels D, E, and F disabled |
0 |
1 |
5.1 mode |
All channels enabled |
1 |
0/1 |
Reserved |
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(1)M1 must always be connected to ground. 0 indicates a pin connected to GND; 1 indicates a pin connected to VREG.
PACKAGE HEAT DISSIPATION RATINGS(1)
PARAMETER |
TAS5186DDV |
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RθJC (°C/W)—1 satellite (sat.) FET only |
10.3 |
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RθJC (°C/W)—1 subwoofer (sub.) FET only |
5.2 |
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RθJC (°C/W)—1 |
sat. half-bridge |
5.2 |
RθJC (°C/W)—1 |
sub. half-bridge |
2.6 |
RθJC (°C/W)—5 sat. half-bridges + 1 sub. |
1.74 |
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Typical pad area(2) |
34.9 mm2 |
(1)JC is junction-to-case, CH is case-to-heatsink.
(2)RθCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The RθCH with this condition is typically 2°C/W for this package.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
TAS5186 |
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VDD to AGND |
–0.3 V to 13.2 V |
GVDD_X to AGND |
–0.3 V to 13.2 V |
PVDD_X to PGND_X (2) |
–0.3 V to 50 V |
OUT_X to PGND_X (2) |
–0.3 V to 50 V |
BST_X to PGND_X (2) |
–0.3 V to 63.2 V |
VREG to AGND |
–0.3 V to 4.2 V |
PGND_X to GND |
–0.3 V to 0.3 V |
PGND_X to AGND |
–0.3 V to 0.3 V |
GND to AGND |
–0.3 V to 0.3 V |
PWM_X, OC_ADJ, M1, M2, M3 to AGND |
–0.3 V to 4.2 V |
RESET, SD, OTW to AGND |
–0.3 V to 7 V |
Maximum operating junction temperature range (TJ ) |
0 to 125°C |
Storage temperature |
–40°C to 125°C |
Lead temperature – 1,6 mm (1/16 inch) from case for 10 seconds |
260°C |
Minimum PWM pulse duration, low |
30 ns |
(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
4
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TAS5186 |
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www.ti.com |
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SLES136 –MAY 2005 |
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TYPICAL SYSTEM DIAGRAM |
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BST_BIAS |
33 nF |
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680 Ω |
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22 |
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OUT_BIAS |
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12 V |
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3 |
GVDD_DEF |
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PVDD |
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1 μF |
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43 |
0.1 μF |
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20 |
GVDD_ABC |
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PVDD_F |
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1 μF |
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44 |
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0.47 μF |
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BST_F |
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SAT |
270 |
μF |
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+ |
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42 |
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10 μF |
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4 |
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VDD |
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OUT_F |
33 nF |
22 |
μ |
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330 |
Ω |
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0.1 μF |
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41 |
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H |
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270 |
μ |
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PGND_EF |
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F |
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1 |
μF |
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13 |
VREG |
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1 |
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0.1 μF |
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PGND_EF |
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0.1 μF |
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39 |
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14 |
OC_ADJ |
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PVDD_E |
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+ |
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38 |
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0.47 μF |
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BST_E |
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15 kΩ |
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SAT |
270 |
μF |
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12 |
AGND |
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OUT_E |
33 nF |
22 |
μ |
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330 |
Ω |
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H |
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10 |
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270 μF |
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M1 |
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1 μF |
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9 |
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0.1 μF |
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M2 |
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36 |
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PVDD_D |
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+ |
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11 |
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37 |
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0.47 μF |
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GND |
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BST_D |
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TAS5186 |
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SAT |
270 |
μF |
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35 |
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OUT_D |
33 nF |
22 |
μ |
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330 |
Ω |
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34 |
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H |
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|||
|
|
|
|
|
|
PGND_D |
|
|
|
|
270 μF |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
PWM1 |
2 |
PWM_F |
|
|
0.1 μF |
|
1 μF |
|
|
|
|
|
|
|
31 |
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
||||
|
|
PWM2 |
5 |
PWM_E |
|
PVDD_C |
|
+ |
|
|
|
|
|
|
|
|
|
30 |
|
|
|
|
|
|
|||
|
|
|
|
|
0.47 μF |
|
|
|
|
||||
|
|
|
6 |
|
|
BST_C |
|
|
|
|
|
||
|
|
PWM3 |
PWM_D |
|
|
|
SUB |
|
|
|
|||
|
|
|
|
32 |
|
|
1000 |
μF |
|
||||
|
|
|
|
|
|
|
|
|
|||||
PurePath |
|
PWM4 |
17 |
PWM_C |
|
OUT_C |
33 nF |
22 |
μ |
|
|
330 |
Ω |
Digital |
|
|
18 |
|
|
33 |
|
H |
|
|
|
||
|
PWM5 |
PWM_B |
|
PGND_C |
|
|
|
|
1000 μF |
|
|||
Modulator |
|
|
|
|
|
1 μF |
|
||||||
19 |
|
|
|
|
|
|
|
||||||
TAS5086 |
|
PWM6 |
PWM_A |
|
|
0.1 μF |
|
|
|
|
|||
|
|
28 |
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
7 |
|
|
PVDD_B |
|
+ |
|
|
|
|
|
|
|
|
|
|
29 |
|
|
|
|
|
|
||
|
|
|
|
|
|
0.47 μF |
|
|
|
|
|||
|
|
VALID2 |
|
RESET |
|
BST_B |
|
|
|
|
|
||
|
|
8 |
|
|
|
SAT |
270 |
μF |
|
||||
|
|
|
|
|
27 |
|
|
|
|||||
|
|
VALID1 |
M3 |
|
|
|
|
|
|
||||
|
|
|
|
OUT_B |
33 nF |
22 μH |
|
|
330 Ω |
||||
|
|
|
15 |
|
|
26 |
|
|
|||||
|
|
|
SD |
|
|
|
|
|
270 μF |
|
|||
|
|
|
|
|
PGND_AB |
|
|
1 |
μF |
|
|
|
|
|
|
|
16 |
OTW |
|
|
0.1 μF |
|
|
|
|
||
|
|
|
|
24 |
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
PVDD_A |
|
+ |
|
|
|
|
|
|
|
|
|
|
|
23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0.47 μF |
|
|
|
|
||
|
|
|
|
|
|
BST_A |
|
|
|
|
|
||
To μP |
|
|
|
|
|
|
|
SAT |
270 |
μF |
|
||
|
|
|
|
|
25 |
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
OUT_A |
33 nF |
22 |
μ |
|
|
330 Ω |
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
H |
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
270 μF |
|
|
|
|
|
|
|
|
|
|
|
1 μF |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
S0061-01 |
5
TAS5186
www.ti.com
SLES136 –MAY 2005
|
|
FUNCTIONAL BLOCK DIAGRAM |
|
|||
OTW |
|
|
Undervoltage |
VDD |
||
|
|
Protection |
||||
|
|
|
|
|||
|
Internal Pullup |
|
|
|
|
|
|
Resistors to VREG |
|
|
|
|
|
SD |
|
|
Power On |
VREG |
VREG |
|
|
|
Protection |
Reset |
|||
|
|
|
|
|||
|
|
|
|
|
||
M1 |
|
and |
|
|
AGND |
|
M2 |
|
I/O Logic |
Temperature |
|||
|
|
GND |
||||
|
|
|
Sense |
|
||
M3 |
|
|
|
|
||
|
|
|
|
|
||
RESET |
|
|
Overload |
ISense |
OC_ADJ |
|
|
|
|
||||
|
|
|
Protection |
|
||
|
|
|
|
|
GVDD_DEF |
|
|
|
|
|
|
BST_F |
|
|
PWM |
|
|
Gate |
PVDD_F |
|
PWM_F |
Control |
Timing |
OUT_F |
|||
Receiver |
Drive |
|||||
|
|
|
PGND_EF |
|||
|
|
|
|
|
||
|
|
|
|
|
BST_E |
|
|
PWM |
|
|
Gate |
PVDD_E |
|
PWM_E |
Control |
Timing |
OUT_E |
|||
Receiver |
Drive |
|||||
|
|
|
PGND_EF |
|||
|
|
|
|
|
||
|
|
|
|
|
BST_D |
|
|
PWM |
|
|
Gate |
PVDD_D |
|
PWM_D |
Control |
Timing |
OUT_D |
|||
Receiver |
Drive |
|||||
|
|
|
PGND_D |
|||
|
|
|
|
|
||
|
|
|
|
|
GVDD_ABC |
|
|
|
|
|
|
BST_C |
|
|
PWM |
|
|
Gate |
PVDD_C |
|
PWM_C |
Control |
Timing |
OUT_C |
|||
Receiver |
Drive |
|||||
|
|
|
PGND_C |
|||
|
|
|
|
|
||
|
|
|
|
|
BST_B |
|
|
PWM |
|
|
Gate |
PVDD_B |
|
PWM_B |
Control |
Timing |
OUT_B |
|||
Receiver |
Drive |
|||||
|
|
|
PGND_AB |
|||
|
|
|
|
|
||
|
|
|
|
|
BST_A |
|
|
PWM |
|
|
Gate |
PVDD_A |
|
PWM_A |
Control |
Timing |
OUT_A |
|||
Receiver |
Drive |
|||||
|
|
|
|
|||
|
|
|
|
|
BST_BIAS |
|
|
|
Control |
Timing |
Gate |
OUT_BIAS |
|
|
|
Drive |
||||
|
|
|
|
|
||
|
|
|
|
|
B0034-01 |
6