TM
www.ti.com
PVDD = 40 V
TC = 75°C
10 70
G012
0.01
0.1
20
1
1
10
PO – Output Power – W
THD+N – Total Harmonic Distortion + Noise – %
6 Ω Satellite
3 Ω Subwoofer
查询TAS5186供应商
TAS5186
SLES136 – MAY 2005
6-Channel, 210-W, Digital-Amplifier Power Stage
FEATURES
• Total Output Power @ 10% THD+N
– 5×30 W @ 6 Ω + 1×60 W @ 3 Ω
• 105-dB SNR (A-Weighted)
• < 0.05% THD+N @ 1 W
• Power Stage Efficiency > 90% Into
Recommended Loads (SE)
• Integrated Self-Protection Circuits
– Undervoltage
– Overtemperature
– Overload
– Short Circuit
• Integrated Active-Bias Control to Avoid DC
Pop
• Thermally Enhanced 44-pin HTSSOP Package
• EMI-Compliant When Used With
Recommended System Design
APPLICATIONS
• DVD Receiver
• Home Theater in a Box
The TAS5186 requires only simple passive demodulation filters on its outputs to deliver high-quality,
high-efficiency audio amplification. The efficiency of
the TAS5186 is greater than 90% when driving 6- Ω
satellites and a 3- Ω subwoofer speaker.
The TAS5186 has an innovative protection system
integrated on-chip, safeguarding the device against a
wide range of fault conditions that could damage the
system. These safeguards are short-circuit protection,
overload protection, undervoltage protection, and
overtemperature protection. The TAS5186 has a new
proprietary current-limiting circuit that reduces the
possibility of device shutdown during high-level music
transients. A new programmable overcurrent detector
allows the use of lower-cost inductors in the demodulation output filter.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
DESCRIPTION
The TAS5186 is a high-performance, six-channel,
digital-amplifier power stage with an improved protection system. The TAS5186 is capable of driving a
6- Ω , single-ended load up to 30 W per each
front/satellite channel and a 3- Ω , single-ended
subwoofer greater than 60 W at 10% THD+N performance.
A low-cost, high-fidelity audio system can be built
using a TI chipset comprising a modulator (e.g.,
TAS5086) and the TAS5186. This device does not
require power-up sequencing because of the internal
power-on reset.
PowerPAD, PurePath Digital are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2005, Texas Instruments Incorporated
www.ti.com
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PGND_EF
PWM_F
GVDD_DEF
VDD
PWM_E
PWM_D
RESET
M3
M2
M1
GND
AGND
VREG
OC_ADJ
SD
OTW
PWM_C
PWM_B
PWM_A
GVDD_ABC
BST_BIAS
OUT_BIAS
DDV PACKAGE
(TOP VIEW)
BST_F
PVDD_F
OUT_F
PGND_EF
OUT_E
PVDD_E
BST_E
BST_D
PVDD_D
OUT_D
PGND_D
PGND_C
OUT_C
PVDD_C
BST_C
BST_B
PVDD_B
OUT_B
PGND_AB
OUT_A
PVDD_A
BST_A
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
P0016-01
TAS5186
SLES136 – MAY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
TERMINAL ASSIGNMENT
The TAS5186 is available in a thermally enhanced 44-pin HTSSOP PowerPAD™ package. The heat slug is
located on the top side of the device for convenient thermal coupling to a heatsink.
2
www.ti.com
GENERAL INFORMATION (continued)
TERMINAL FUNCTIONS
TERMINAL
NAME NO.
AGND 12 P Analog ground
BST_A 23 P HS bootstrap supply (BST), capacitor to OUT_A required
BST_B 29 P HS bootstrap supply (BST), external capacitor to OUT_B required
BST_BIAS 21 P BIAS bootstrap supply, external capacitor to OUT_BIAS required
BST_C 30 P HS bootstrap supply (BST), external capacitor to OUT_C required
BST_D 37 P HS bootstrap supply (BST), external capacitor to OUT_D required
BST_E 38 P HS bootstrap supply (BST), external capacitor to OUT_E required
BST_F 44 P HS bootstrap supply (BST), external capacitor to OUT_F required
GND 11 P Chip ground
GVDD_ABC 20 P Gate drive voltage supply
GVDD_DEF 3 P Gate drive voltage supply
M1 10 I Mode selection pin
M2 9 I Mode selection pin
M3 8 I Mode selection pin
OC_ADJ 14 O Overcurrent threshold programming pin, resistor to ground required
OTW 16 O Overtemperature warning open-drain output signal, active-low
OUT_A 25 O Output, half-bridge A, satellite
OUT_B 27 O Output, half-bridge B, satellite
OUT_BIAS 22 O BIAS half-bridge output pin
OUT_C 32 O Output, half-bridge C, subwoofer
OUT_D 35 O Output, half-bridge D, satellite
OUT_E 40 O Output, half-bridge E, satellite
OUT_F 42 O Output, half-bridge F, satellite
PGND_AB 26 P Power ground
PGND_C 33 P Power ground
PGND_D 34 P Power ground
PGND_EF 1, 41 P Power ground
PVDD_A 24 P Power-supply input for half-bridge A
PVDD_B 28 P Power-supply input for half-bridge B
PVDD_C 31 P Power-supply input for half-bridge C
PVDD_D 36 P Power-supply input for half-bridge D
PVDD_E 39 P Power-supply input for half-bridge E
PVDD_F 43 P Power-supply input for half-bridge F
PWM_A 19 I PWM input signal for half-bridge A
PWM_B 18 I PWM input signal for half-bridge B
PWM_C 17 I PWM input signal for half-bridge C
PWM_D 6 I PWM input signal for half-bridge D
PWM_E 5 I PWM input signal for half-bridge E
PWM_F 2 I PWM input signal for half-bridge F
RESET 7 I Reset signal (active-low logic)
SD 15 O Shutdown open-drain output signal, active-low
VDD 4 P Power supply for digital voltage regulator
VREG 13 O Digital regulator supply filter pin, output
(1) I = input; O = output; P = power
(1)
TYPE
DESCRIPTION
TAS5186
SLES136 – MAY 2005
3
www.ti.com
TAS5186
SLES136 – MAY 2005
Table 1. MODE Selection Pins
MODE PINS
M2 M3 NAME DESCRIPTION
0 0 2.1 mode Channels A, B, and C enabled; channels D, E, and F disabled
0 1 5.1 mode All channels enabled
1 0/1 Reserved
(1) M1 must always be connected to ground. 0 indicates a pin connected to GND; 1 indicates a pin connected to VREG.
(1)
MODE
PACKAGE HEAT DISSIPATION RATINGS
(1)
PARAMETER TAS5186DDV
R
( ° C/W)—1 satellite (sat.) FET only 10.3
θ JC
R
( ° C/W)—1 subwoofer (sub.) FET only 5.2
θ JC
R
( ° C/W)—1 sat. half-bridge 5.2
θ JC
R
( ° C/W)—1 sub. half-bridge 2.6
θ JC
R
( ° C/W)—5 sat. half-bridges + 1 sub. 1.74
θ JC
Typical pad area
(2)
34.9 mm
2
(1) JC is junction-to-case, CH is case-to-heatsink.
(2) R
is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The
θ CH
R
with this condition is typically 2°C/W for this package.
θ CH
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
TAS5186
VDD to AGND –0.3 V to 13.2 V
GVDD_X to AGND –0.3 V to 13.2 V
PVDD_X to PGND_X
OUT_X to PGND_X
BST_X to PGND_X
VREG to AGND –0.3 V to 4.2 V
PGND_X to GND –0.3 V to 0.3 V
PGND_X to AGND –0.3 V to 0.3 V
GND to AGND –0.3 V to 0.3 V
PWM_X, OC_ADJ, M1, M2, M3 to AGND –0.3 V to 4.2 V
RESET, SD, OTW to AGND –0.3 V to 7 V
Maximum operating junction temperature range (T
Storage temperature –40°C to 125°C
Lead temperature – 1,6 mm (1/16 inch) from case for 10 seconds 260°C
Minimum PWM pulse duration, low 30 ns
(2)
(2)
(2)
) 0 to 125°C
J
(1)
–0.3 V to 50 V
–0.3 V to 50 V
–0.3 V to 63.2 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
4
www.ti.com
+
M3
M1
M2
OUT_F
PVDD_F
BST_F
GVDD_DEF
PWM_E
PWM_F
PWM_A
PWM_B
OTW
SD
PWM_C
VDD
AGND
OC_ADJ
VREG
PWM_D
RESET
OUT_E
PVDD_E
PGND_EF
BST_E
GVDD_ABC
GND
OUT_D
PVDD_D
PGND_D
BST_D
OUT_C
PVDD_C
BST_C
OUT_B
PVDD_B
PGND_AB
BST_B
OUT_A
PVDD_A
BST_A
VALID2
VALID1
To µP
PVDD
12 V
OUT_BIAS
BST_BIAS
21
22
43
44
42
41
39
38
40
36
37
35
34
31
30
32
SAT
28
29
27
26
25
23
24
3
20
4
13
14
12
10
9
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
2
5
6
15
16
11
PGND_C
33
17
18
19
7
8
PGND_EF
1
PurePath
Digital
Modulator
TAS5086
TAS5186
S0061-01
SAT
SAT
SUB
SAT
SAT
680 Ω
33 nF
+
+
+
+
+
+
22 µH
270 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
33 nF
33 nF
33 nF
33 nF
33 nF
270 µF
270 µF
270 µF
270 µF
270 µF
1000 µF
1000 µF
270 µF
270 µF
270 µF
270 µF
22 µH
22 µH
22 µH
22 µH
22 µH
330 Ω
330 Ω
330 Ω
330 Ω
330 Ω
330 Ω
0.47 µF
0.47 µF
0.47 µF
0.47 µF
0.47 µF
0.47 µF
1 µF
1 µF
1 µF
1 µF
1 µF
1 µF
33 nF
1 µF
15 kΩ
1 µF
0.1 µF
0.1 µF
10 µF
TYPICAL SYSTEM DIAGRAM
TAS5186
SLES136 – MAY 2005
PurePath Digital™
5
www.ti.com
M1
M2
RESET
SD
OTW
AGND
OC_ADJ
VREG VREG
VDD
GVDD_DEF
M3
Undervoltage
Protection
GND
PWM_F OUT_F
PGND_EF
PVDD_F
BST_F
PWM
Receiver
I
Sense
Protection
and
I/O Logic
Power On
Reset
Temperature
Sense
Overload
Protection
Control Timing
Gate
Drive
PWM_E OUT_E
PGND_EF
PVDD_E
BST_E
PWM
Receiver
Control Timing
Gate
Drive
PWM_D OUT_D
PGND_D
PVDD_D
BST_D
PWM
Receiver
Control Timing
Gate
Drive
PWM_C OUT_C
PGND_C
PVDD_C
BST_C
PWM
Receiver
Control Timing
Gate
Drive
PWM_B OUT_B
PGND_AB
PVDD_B
BST_B
PWM
Receiver
Control Timing
Gate
Drive
PWM_A OUT_A
PVDD_A
BST_A
PWM
Receiver
Control Timing
Gate
Drive
OUT_BIAS
BST_BIAS
Control Timing
Gate
Drive
B0034-01
Internal Pullup
Resistors to VREG
GVDD_ABC
TAS5186
SLES136 – MAY 2005
FUNCTIONAL BLOCK DIAGRAM
6
www.ti.com
TAS5186
SLES136 – MAY 2005
RECOMMENDED OPERATING CONDITIONS
MIN TYP MAX UNIT
PVDD_X Half-bridge supply, SE DC supply voltage at pin(s) 0 40 V
GVDD Gate drive and guard ring supply voltage DC voltage at pin(s) 10.8 12 13.2 V
VDD Digital regulator supply DC supply voltage at pin 10.8 12 13.2 V
VPU Pullup voltage supply 3 5 5.5 V
R
L,SAT
R
L,SUB
L
output
C
output,sat
C
output,sub
F
PWM
Resistive load impedance, satellite Recommended demodulation filter
channels
(1)
Resistive load impedance, subwoofer Recommended demodulation filter
channel
Demodulation filter inductance 5 22 µ H
Demodulation filter capacitance 1 µ F
Demodulation filter capacitance 0.47 µ F
PWM frame rate 192 384 432 kHz
Any value of R
recommended range
Minimum output inductance under
short-circuit condition
(1) Load impedance outside range listed might cause shutdown due to OLP, OTE, or NLP.
AUDIO SPECIFICATION
PVDD_X = 40 V, GVDD = 12 V, audio frequency = 1 kHz, AES17 measurement filter, F
75°C. Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of
97%. All performance is in accordance with the foregoing specifications and recommended operating conditions unless
otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNIT
RL= 6 Ω , 10% THD, clipped input signal 30
P
O,sat
P
O,sub
Power output per satellite channel W
Power output, subwoofer W
Total harmonic distortion + noise,
satellite
THD + N
Total harmonic distortion + noise,
subwoofer
V
n
Output integrated noise, satellite A-weighted 55
Output integrated noise, subwoofer A-weighted 60
SNR System signal-to-noise ratio A-weighted 105 dB
DNR Dynamic range
P
idle
Power dissipation due to idle losses
(IPVDDX)
(1)
(1) SNR is calculated relative to 0-dBFS input level.
(2) Actual system idle losses are affected by core losses of output inductors.
RL= 8 Ω , 10% THD, clipped input signal 25
RL= 6 Ω , 0 dBFS, unclipped input signal 25
RL= 8 Ω , 0 dBFS, unclipped input signal 20
RL= 3 Ω , 10% THD, clipped input signal 60
RL= 4 Ω , 10% THD, clipped input signal 52
RL= 3 Ω , 0 dBFS, unclipped input signal 50
RL= 4 Ω , 0 dBFS, unclipped input signal 40
RL= 6 Ω , PO= 25 W 0.3%
RL= 6 Ω , 1 W 0.03%
RL= 3 Ω , PO= 50 W 0.5%
RL= 3 Ω , 1 W 0.03%
A-weighted, –60 dBFs input signal 105 dB
PO= 0 W, all channels running 5.1 mode
PO= 0 W, 2.1 mode 4 W
within
PU,EXT
4 6 Ω
2.25 3 Ω
= 384 kHz, case temperature =
PWM
(2)
8 W
µ V
7
www.ti.com
TAS5186
SLES136 – MAY 2005
ELECTRICAL CHARACTERISTICS
F
= 384 kHz, GVDD = 12 V, VDD = 12 V, TC(case temperature) = 25 ° C, unless otherwise noted. All performance is in
PWM
accordance with recommended operating conditions, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG Voltage regulator, only used as reference node VDD = 12 V 3 3.3 3.6 V
IVDD VDD supply current mA
IGVDD_X Gate supply current per half-bridge mA
IPVDD_X Half-bridge idle current mA
OUTPUT STAGE MOSFETs
R
, LS Sat Drain-to-source resistance, low side, satellite TJ= 25°C, includes metallization resistance 210 m Ω
DSon
R
, HS Sat Drain-to-source resistance, high side, satellite TJ= 25°C, includes metallization resistance 210 m Ω
DSon
R
, LS Sub Drain-to-source resistance, low side, subwoofer TJ= 25°C, includes metallization resistance 110 m Ω
Dson
R
, HS Sub Drain-to-source resistance, high side, subwoofer TJ= 25°C, includes metallization resistance 110 m Ω
Dson
I/O PROTECTION
V
UVP, G
(1)
V
UVP, hyst
(1)
OTW
(1)
OTW
hyst
(1)
OTE
(1)
OTE
HYST
Undervoltage protection limit GVDD_X 10 V
Undervoltage protection hysteresis 250 mV
Overtemperature warning 125 °C
Temperature drop needed below OTW temp. for
OTW to be inactive after the OTW event
Overtemperature error 155 °C
Temperature drop needed below OTE temp. for SD
to be released after the OTE event
OLCP Overload protection counter 1.25 ms
Overcurrent limit protection, sat. 5 A
I
OC
Overcurrent limit protection, sub. 8 A
I
OCT
Overcurrent response time 210 ns
Rocp OC programming resistor range Resistor tolerance = 5% 15 k Ω
STATIC DIGITAL SPECIFICATION
V
IH
V
IL
I
LEAK
High-level input voltage 2
Low-level input voltage 0.8
Input leakage current Static condition –80 80 µ A
OTW/SHUTDOWN (SD)
R
INT_PU
V
OH
V
OL
Internal pullup resistor to DREG (3.3 V) for SD and
OTW
High-level output voltage
Low-level output voltage IO= 4 mA 0.2 0.4
FANOUT Device fanout OTW, SD No external pullup 30 Devices
Operating, 50% duty cycle 7 20
Idle, reset mode 6 16
50% duty cycle 5 22
Idle, reset mode 1 3
50% duty cycle, without output filter or load, 5.1 180
mode
50% duty cycle, without output filter or load, 2.1 100
mode
25 °C
25 °C
Resistor programmable, high end,
Rocp = 15 k Ω
Resistor programmable, high end,
Rocp = 15 k Ω
PWM_X, M1, M2, M3, RESET V
26 k Ω
Internal pullup resistor only 3 3.3 3.6
External pullup: 4.7-k Ω resistor to 5 V 4.5 5 V
(1) Specified by design.
8
www.ti.com
TYPICAL CHARACTERISTICS, 5.1 MODE
Satellite
PVDD = 40 V
TC = 75°C
THD+N – Total Harmonic Distortion + Noise – %
10 40
G001
0.01
0.1
20
1
1
10
6 Ω
8 Ω
PO – Output Power – W
Subwoofer
PVDD = 40 V
TC = 75°C
10 70
G002
0.01
0.1
20
1
1
10
3 Ω
4 Ω
PO – Output Power – W
THD+N – Total Harmonic Distortion + Noise – %
PVDD – Supply Voltage – V
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
0 5 10 15 20 25 30 35 40
P
O
– Output Power – W
G003
Satellite
1 Channel
TC = 75°C
THD+N = 10%
6 Ω
8 Ω
PVDD – Supply Voltage – V
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
0 5 10 15 20 25 30 35 40
G004
Subwoofer
1 Channel
TC = 75°C
THD+N = 10%
3 Ω
4 Ω
P
O
– Output Power – W
TAS5186
SLES136 – MAY 2005
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
OUTPUT POWER OUTPUT POWER
Figure 1. Figure 2.
OUTPUT POWER OUTPUT POWER
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 3. Figure 4.
9
www.ti.com
PVDD – Supply Voltage – V
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
0 5 10 15 20 25 30 35 40
G005
Satellite
1 Channel
TC = 75°C
Unclipped Input Signal
6 Ω
8 Ω
P
O
– Output Power – W
PVDD – Supply Voltage – V
0
5
10
15
20
25
30
35
40
45
50
55
0 5 10 15 20 25 30 35 40
G006
Subwoofer
1 Channel
TC = 75°C
Unclipped Input Signal
3 Ω
4 Ω
P
O
– Output Power – W
0
10
20
30
40
50
60
70
80
90
100
0 20 40 60 80 100 120 140 160 180 200 220 240
System Efficiency – %
G007
5.1 Mode
PVDD = 40 V
TC = 25°C
R
L(SAT)
= 8 Ω
R
L(SUB)
= 4 Ω
PO – Total Output Power – W
R
L(SAT)
= 6 Ω
R
L(SUB)
= 3 Ω
0
5
10
15
20
25
30
35
40
0 20 40 60 80 100 120 140 160 180 200 220 240
System Power Loss – W
G008
5.1 Mode
PVDD = 40 V
TC = 25°C
PO – Total Output Power – W
R
L(SAT)
= 8 Ω
R
L(SUB)
= 4 Ω
R
L(SAT)
= 6 Ω
R
L(SUB)
= 3 Ω
TAS5186
SLES136 – MAY 2005
TYPICAL CHARACTERISTICS, 5.1 MODE (continued)
OUTPUT POWER OUTPUT POWER
SUPPLY VOLTAGE SUPPLY VOLTAGE
vs vs
SYSTEM EFFICIENCY SYSTEM POWER LOSS
TOTAL OUTPUT POWER TOTAL OUTPUT POWER
10
Figure 5. Figure 6.
vs vs
Figure 7. Figure 8.
www.ti.com
TC – Case Temperature – °C
0
5
10
15
20
25
30
35
40
20 30 40 50 60 70 80 90 100 110
G009
Satellite
1 Channel
THD+N = 10%
6 Ω
8 Ω
P
O
– Output Power – W
TC – Case Temperature – °C
0
10
20
30
40
50
60
70
80
20 30 40 50 60 70 80 90 100 110
G010
3 Ω
4 Ω
Subwoofer
1 Channel
THD+N = 10%
P
O
– Output Power – W
f – Frequency – kHz
−150
−140
−130
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 2 4 6 8 10 12 14 16 18 20 22
Amplitude – dB
G011
Satellite
1 Channel
PVDD = 40 V
TC = 75°C
TYPICAL CHARACTERISTICS, 5.1 MODE (continued)
OUTPUT POWER OUTPUT POWER
vs vs
CASE TEMPERATURE CASE TEMPERATURE
TAS5186
SLES136 – MAY 2005
Figure 9. Figure 10.
AMPLITUDE
vs
FREQUENCY
Figure 11.
11
www.ti.com
TAS5186
SLES136 – MAY 2005
THEORY OF OPERATION
decoupled with a 100-nF ceramic capacitor placed as
POWER SUPPLIES
To facilitate system design, the TAS5186 needs only
a 12-V supply in addition to a typical 39-V
power-stage supply. An internal voltage regulator
provides suitable voltage levels for the digital and
low-voltage analog circuitry. Additionally, all circuitry
requiring a floating voltage supply, e.g., the high-side
gate drive, is accommodated by built-in bootstrap
circuitry requiring only a few external capacitors.
In order to provide outstanding electrical and acoustic
characteristics, the PWM signal path including gate
drive and output stage is designed as identical,
independent half-bridges. For this reason, each
half-bridge has separate bootstrap pins (BST_X) and
power-stage supply pins (PVDD_X). Furthermore, an
additional pin (VDD) is provided as power supply for
all common circuits. Although supplied from the same
12-V source, it is highly recommended to separate
GVDD_X and VDD on the printed-circuit board (PCB)
by RC filters (see application diagram for details).
These RC filters provide the recommended
high-frequency isolation. Special attention should be
paid to placing all decoupling capacitors as close to
their associated pins as possible. In general, inductance between the power-supply pins and decoupling
capacitors must be avoided. (See reference board
documentation for additional information.)
For a properly functioning bootstrap circuit, a small
ceramic capacitor must be connected from each
bootstrap pin (BST_X) to the power-stage output pin
(OUT_X). When the power-stage output is low, the
bootstrap capacitor is charged through an internal
diode connected between the gate-drive
power-supply pin (GVDD_X) and the bootstrap pin. The TAS5186 does not require a power-down seWhen the power-stage output voltage is high, the quence. The device remains fully operational as long
bootstrap capacitor voltage is shifted above the as the gate-drive supply (GVDD_X) voltage and VDD
output voltage potential and thus provides a suitable voltage are above the undervoltage protection (UVP)
voltage supply for the high-side gate driver. In an threshold level (see the Electrical Characteristics
application with PWM switching frequencies in the section of this data sheet). Although not specifically
range 352 kHz to 384 kHz, it is recommended to use required, it is a good practice to hold RESET low
33-nF ceramic capacitors, size 0603 or 0805, for the during power down, thus preventing audible artifacts
bootstrap capacitor. These 33-nF capacitors ensure including pops and clicks
sufficient energy storage, even during minimal PWM
duty cycles, to keep the high-side power stage FET
(LDMOS) fully started during all of the remaining part
of the PWM cycle. In an application running at a
reduced switching frequency, generally 250 kHz to
192 kHz, the bootstrap capacitor might need to be
increased in value. Special attention should be paid
to the power-stage power supply; this includes
component selection, PCB placement and routing. As
indicated, each half-bridge has independent
power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability it is important that each PVDD_X pin is
close as possible to each supply pin on the same
side of the PCB as the TAS5186. It is recommended
to follow the PCB layout of the TAS5186 reference
design. For additional information on the recommended power supply and required components,
see the application diagrams given in this data sheet.
The 12-V supply should be powered from a
low-noise, low-output-impedance voltage regulator.
Likewise, the 39-V power-stage supply is assumed to
have low output impedance and low noise. The
power-supply sequence is not critical due to the
internal power-on-reset circuit. Moreover, the
TAS5186 is fully protected against erroneous
power-stage turnon due to parasitic gate charging.
Thus, voltage-supply ramp rates (dv/dt) are typically
noncritical.
SYSTEM POWER-UP/DOWN SEQUENCE
The TAS5186 does not require a power-up sequence.
The outputs of the H-bridge remain in a
high-impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the
undervoltage protection (UVP) voltage threshold (see
the Electrical Characteristics section of this data
sheet). Although not specifically required, it is recommended to hold RESET in a low state while
powering up the device.
When the TAS5186 is being used with TI PWM
modulators such as the TAS5086, no special attention to the state of RESET is required, provided that
the chipset is configured as recommended.
Powering Down
When the TAS5186 is being used with TI PWM
modulators such as the TAS5086, no special attention to the state of RESET is required, provided that
the chipset is configured as recommended.
Error Reporting
The SD and OTW pins are both active-low,
open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other
system-control device.
12
www.ti.com
TAS5186
SLES136 – MAY 2005
Any fault resulting in device shutdown is signaled by two protection systems. The first protection system
the SD pin going low. Likewise, OTW goes low when controls the power stage in order to prevent the
the device junction temperature exceeds 125°C (see output current from further increasing. I.e., it performs
the following table). a current-limiting function rather than prematurely
shutting down during combinations of high-level music transients and extreme speaker load-impedance
SD OTW DESCRIPTION
0 0 Overtemperature (OTE) or overload (OLP) or
undervoltage (UVP)
0 1 Overload (OLP) or undervoltage (UVP)
1 0 Overtemperature warning. Junction temperature
higher than 125°C, typical
1 1 Normal operation. Junction temperature lower than
125°C, typical
It should be noted that asserting RESET low forces
the SD and OTW signals high independently of faults
being present. It is recommended to monitor the
OTW signal using the system microcontroller and to
respond to an overtemperature warning signal by,
e.g., turning down the volume to prevent further
heating of the device that would result in device
shutdown (OTE). To reduce external component
count, an internal pullup resistor to 3.3 V is provided
on both the SD and OTW outputs. Level compliance
for 5-V logic can be obtained by adding external
pullup resistors to 5 V (see the Electrical Character-
istics section of this data sheet for further specifi-
cations).
Device Protection System
The TAS5186 contains advanced protection circuitry
carefully designed to facilitate system integration and
ease of use, as well as safeguarding the device from
permanent failure due to a wide range of fault
conditions such as short circuit, overload, and
undervoltage. The TAS5186 responds to a fault by
immediately setting the power stage in a
high-impedance state (Hi-Z) and asserting the SD pin
low. In situations other than overload, the device
automatically recovers when the fault condition has
been removed, e.g., the supply voltage has
increasedor the temperature has dropped. For
highest possible reliability, recovering from an overload fault requires external reset of the device no
sooner than 1 second after the shutdown (see the
Device Reset section of this data sheet).
OVERCURRENT (OC) PROTECTION WITH
CURRENT LIMITING AND OVERLOAD DETECTION
The device has independent, fast-reacting current
detectors with programmable trip threshold (OC
threshold) on all high-side and low-side power-stage
FETs. See the following table for OC-adjust resistor
values. The detector outputs are closely monitored by
drops. If the high-current situation persists, i.e., the
power stage is being overloaded, a second protection
system triggers a latching shutdown, resulting in the
power stage being set in the high-impedance (Hi-Z)
state.
For added flexibility, the OC threshold is
programmable within a limited range using a single
external resistor connected between the OC_ADJ pin
and AGND.
OC-Adjust Resistor Values Maximum Current Before OC
(k Ω ) Occurs (A)
15 5 (sat.), 8 (sub.)
18 4.5 (sat.), 7.5 (sub.)
It should be noted that a properly functioning
overcurrent detector assumes the presence of a
properly designed demodulation filter at the
power-stage output. Short-circuit protection is not
provided directly at the output pins of the power stage
but only on the speaker terminals (after the demodulation filter). It is required to follow certain guidelines
when selecting the OC threshold and an appropriate
demodulation inductor.
• For the lowest-cost bill of materials in terms of
component selection, the OC threshold current
should be limited, considering the power output
requirement and minimum load impedance.
Higher-impedance loads require a lower OC
threshold.
• The demodulation filter inductor must retain at
least 5 µ H of inductance at twice the OC
threshold setting.
Most inductors have decreasing inductance with increasing temperature and increasing current
(saturation). To some degree, an increase in temperature naturally occurs when operating at high
output currents, due to inductor core losses and the
dc resistance of the inductor copper winding. A
thorough analysis of inductor saturation and thermal
properties is strongly recommended.
Setting the OC threshold too low might cause issues
such as lack of output power and/or unexpected
shutdowns due to sensitive overload detection.
In general, it is recommended to follow closely the
external component selection and PCB layout as
given in the application section.
13
www.ti.com
TAS5186
SLES136 – MAY 2005
Overtemperature Protection
The TAS5186 has a two-level temperature-protection
system that asserts an active-low warning signal
( OTW) when the device junction temperature exceeds 125°C (typical), and If the device junction
temperature exceeds 155°C (typical), the device is
ABC can pre-charge the dc-blocking element in the
audio path, i.e., split-cap capacitors or series capacitor, to the desired potential before switching is started
on the PWM outputs. (For recommended configuration, see the typical application schematic included
in this data sheet).
put into thermal shutdown, resulting in all half-bridge The start-up sequence can be controlled through
outputs being set in the high-impedance state (Hi-Z) sequencing the M3 and RESET pins according to
and SD being asserted low. Table 2 and Table 3 .
UNDERVOLTAGE PROTECTION (UVP) AND
POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5186 fully
protect the device in any power-up/down and
brownout situation. While powering up, the POR
circuit resets the overload circuit (OLP) and ensures
that all circuits are fully operational when the
GVDD_X and VDD supply voltages reach 10 V
(typical). Although GVDD_X and VDD are independently monitored, a supply voltage drop below the
UVP threshold on any VDD or GVDD_X pin results in
all half-bridge outputs immediately being set in the
Table 2. 5.1 Mode—All Output Channels Active
M3 RESET OUT_BIAS OUT_A, OUT_D, COMMENT
_B, _C _E, _F
0 0 Hi-Z Hi-Z Hi-Z All outputs dis-
abled, nothing is
switching.
1 0 Active Hi-Z Hi-Z OUT_BIAS en-
abled, all other
outputs disabled
1 1 Hi-Z Active Active OUT_BIAS dis-
abled, all other
outputs
switching
high-impedance (Hi-Z) state and SD being asserted
low. The device automatically resumes operation
when all supply voltages have increased above the
UVP threshold.
DEVICE RESET
When RESET is asserted low, the output FETs in all
half-bridges are forced into a high-impedance (Hi-Z)
state.
Asserting the RESET input low removes any fault
information to be signaled on the SD output, i.e., SD
is forced high.
Table 3. 2.1 Mode—Only Output Channels A, B,
and C Active
M3 RESET OUT_BIAS OUT_A, OUT_D, COMMENT
_B, _C _E, _F
0 0 Hi-Z Hi-Z Hi-Z All outputs dis-
abled, nothing is
switching.
1 0 Active Hi-Z Hi-Z OUT_BIAS en-
abled, all other
outputs disabled
0 1 Hi-Z Active Hi-Z OUT_BIAS dis-
abled, all other
outputs
A rising-edge transition on the RESET input allows switching
the device to resume operation after an overload
fault.
When the TAS5186 is used with the TAS5086 PWM
modulator, no special attention to start-up sequencing
ACTIVE-BIAS CONTROL (ABC)
is required, provided that the chipset is configured as
recommended.
Audible pop noises are often associated with
single-rail, single-ended power stages at power-up or
at the start of switching. This commonly known
problem has been virtually eliminated by incorporating a proprietary active-bias control circuitry as part
of the TAS5186 feature set. By the use of only a few
passive external components (typically resistors), the
14
PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2005
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
TAS5186DDV ACTIVE HTSSOP DDV 44 35 Green (RoHS &
no Sb/Br)
TAS5186DDVG4 ACTIVE HTSSOP DDV 44 35 Green (RoHS &
no Sb/Br)
TAS5186DDVR ACTIVE HTSSOP DDV 44 2000 Green (RoHS &
no Sb/Br)
TAS5186DDVRG4 ACTIVE HTSSOP DDV 44 2000 Green (RoHS &
no Sb/Br)
TAS5186DKD PREVIEW SSOP DKD 44 TBD Call TI Call TI
TAS5186DKDR PREVIEW SSOP DKD 44 TBD Call TI Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will bediscontinued,and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
(3)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless
Mailing Address: Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
Loading...