TEXAS INSTRUMENTS TAS5186 Technical data
TM
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PVDD = 40 V
TC = 75°C
10 70
G012
0.01
0.1
20
1
1
10
PO – Output Power – W
THD+N – Total Harmonic Distortion + Noise – %
6 Ω Satellite
3 Ω Subwoofer
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TAS5186
SLES136 – MAY 2005
6-Channel, 210-W, Digital-Amplifier Power Stage
FEATURES
• Total Output Power @ 10% THD+N
– 5×30 W @ 6 Ω + 1×60 W @ 3 Ω
• 105-dB SNR (A-Weighted)
• < 0.05% THD+N @ 1 W
• Power Stage Efficiency > 90% Into
Recommended Loads (SE)
• Integrated Self-Protection Circuits
– Undervoltage
– Overtemperature
– Overload
– Short Circuit
• Integrated Active-Bias Control to Avoid DC
Pop
• Thermally Enhanced 44-pin HTSSOP Package
• EMI-Compliant When Used With
Recommended System Design
APPLICATIONS
• DVD Receiver
• Home Theater in a Box
The TAS5186 requires only simple passive demodulation filters on its outputs to deliver high-quality,
high-efficiency audio amplification. The efficiency of
the TAS5186 is greater than 90% when driving 6- Ω
satellites and a 3- Ω subwoofer speaker.
The TAS5186 has an innovative protection system
integrated on-chip, safeguarding the device against a
wide range of fault conditions that could damage the
system. These safeguards are short-circuit protection,
overload protection, undervoltage protection, and
overtemperature protection. The TAS5186 has a new
proprietary current-limiting circuit that reduces the
possibility of device shutdown during high-level music
transients. A new programmable overcurrent detector
allows the use of lower-cost inductors in the demodulation output filter.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
DESCRIPTION
The TAS5186 is a high-performance, six-channel,
digital-amplifier power stage with an improved protection system. The TAS5186 is capable of driving a
6- Ω , single-ended load up to 30 W per each
front/satellite channel and a 3- Ω , single-ended
subwoofer greater than 60 W at 10% THD+N performance.
A low-cost, high-fidelity audio system can be built
using a TI chipset comprising a modulator (e.g.,
TAS5086) and the TAS5186. This device does not
require power-up sequencing because of the internal
power-on reset.
PowerPAD, PurePath Digital are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2005, Texas Instruments Incorporated
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PGND_EF
PWM_F
GVDD_DEF
VDD
PWM_E
PWM_D
RESET
M3
M2
M1
GND
AGND
VREG
OC_ADJ
SD
OTW
PWM_C
PWM_B
PWM_A
GVDD_ABC
BST_BIAS
OUT_BIAS
DDV PACKAGE
(TOP VIEW)
BST_F
PVDD_F
OUT_F
PGND_EF
OUT_E
PVDD_E
BST_E
BST_D
PVDD_D
OUT_D
PGND_D
PGND_C
OUT_C
PVDD_C
BST_C
BST_B
PVDD_B
OUT_B
PGND_AB
OUT_A
PVDD_A
BST_A
44
43
42
41
40
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37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
P0016-01
TAS5186
SLES136 – MAY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
TERMINAL ASSIGNMENT
The TAS5186 is available in a thermally enhanced 44-pin HTSSOP PowerPAD™ package. The heat slug is
located on the top side of the device for convenient thermal coupling to a heatsink.
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GENERAL INFORMATION (continued)
TERMINAL FUNCTIONS
TERMINAL
NAME NO.
AGND 12 P Analog ground
BST_A 23 P HS bootstrap supply (BST), capacitor to OUT_A required
BST_B 29 P HS bootstrap supply (BST), external capacitor to OUT_B required
BST_BIAS 21 P BIAS bootstrap supply, external capacitor to OUT_BIAS required
BST_C 30 P HS bootstrap supply (BST), external capacitor to OUT_C required
BST_D 37 P HS bootstrap supply (BST), external capacitor to OUT_D required
BST_E 38 P HS bootstrap supply (BST), external capacitor to OUT_E required
BST_F 44 P HS bootstrap supply (BST), external capacitor to OUT_F required
GND 11 P Chip ground
GVDD_ABC 20 P Gate drive voltage supply
GVDD_DEF 3 P Gate drive voltage supply
M1 10 I Mode selection pin
M2 9 I Mode selection pin
M3 8 I Mode selection pin
OC_ADJ 14 O Overcurrent threshold programming pin, resistor to ground required
OTW 16 O Overtemperature warning open-drain output signal, active-low
OUT_A 25 O Output, half-bridge A, satellite
OUT_B 27 O Output, half-bridge B, satellite
OUT_BIAS 22 O BIAS half-bridge output pin
OUT_C 32 O Output, half-bridge C, subwoofer
OUT_D 35 O Output, half-bridge D, satellite
OUT_E 40 O Output, half-bridge E, satellite
OUT_F 42 O Output, half-bridge F, satellite
PGND_AB 26 P Power ground
PGND_C 33 P Power ground
PGND_D 34 P Power ground
PGND_EF 1, 41 P Power ground
PVDD_A 24 P Power-supply input for half-bridge A
PVDD_B 28 P Power-supply input for half-bridge B
PVDD_C 31 P Power-supply input for half-bridge C
PVDD_D 36 P Power-supply input for half-bridge D
PVDD_E 39 P Power-supply input for half-bridge E
PVDD_F 43 P Power-supply input for half-bridge F
PWM_A 19 I PWM input signal for half-bridge A
PWM_B 18 I PWM input signal for half-bridge B
PWM_C 17 I PWM input signal for half-bridge C
PWM_D 6 I PWM input signal for half-bridge D
PWM_E 5 I PWM input signal for half-bridge E
PWM_F 2 I PWM input signal for half-bridge F
RESET 7 I Reset signal (active-low logic)
SD 15 O Shutdown open-drain output signal, active-low
VDD 4 P Power supply for digital voltage regulator
VREG 13 O Digital regulator supply filter pin, output
(1) I = input; O = output; P = power
(1)
TYPE
DESCRIPTION
TAS5186
SLES136 – MAY 2005
3
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TAS5186
SLES136 – MAY 2005
Table 1. MODE Selection Pins
MODE PINS
M2 M3 NAME DESCRIPTION
0 0 2.1 mode Channels A, B, and C enabled; channels D, E, and F disabled
0 1 5.1 mode All channels enabled
1 0/1 Reserved
(1) M1 must always be connected to ground. 0 indicates a pin connected to GND; 1 indicates a pin connected to VREG.
(1)
MODE
PACKAGE HEAT DISSIPATION RATINGS
(1)
PARAMETER TAS5186DDV
R
( ° C/W)—1 satellite (sat.) FET only 10.3
θ JC
R
( ° C/W)—1 subwoofer (sub.) FET only 5.2
θ JC
R
( ° C/W)—1 sat. half-bridge 5.2
θ JC
R
( ° C/W)—1 sub. half-bridge 2.6
θ JC
R
( ° C/W)—5 sat. half-bridges + 1 sub. 1.74
θ JC
Typical pad area
(2)
34.9 mm
2
(1) JC is junction-to-case, CH is case-to-heatsink.
(2) R
is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The
θ CH
R
with this condition is typically 2°C/W for this package.
θ CH
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
TAS5186
VDD to AGND –0.3 V to 13.2 V
GVDD_X to AGND –0.3 V to 13.2 V
PVDD_X to PGND_X
OUT_X to PGND_X
BST_X to PGND_X
VREG to AGND –0.3 V to 4.2 V
PGND_X to GND –0.3 V to 0.3 V
PGND_X to AGND –0.3 V to 0.3 V
GND to AGND –0.3 V to 0.3 V
PWM_X, OC_ADJ, M1, M2, M3 to AGND –0.3 V to 4.2 V
RESET, SD, OTW to AGND –0.3 V to 7 V
Maximum operating junction temperature range (T
Storage temperature –40°C to 125°C
Lead temperature – 1,6 mm (1/16 inch) from case for 10 seconds 260°C
Minimum PWM pulse duration, low 30 ns
(2)
(2)
(2)
) 0 to 125°C
J
(1)
–0.3 V to 50 V
–0.3 V to 50 V
–0.3 V to 63.2 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
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+
M3
M1
M2
OUT_F
PVDD_F
BST_F
GVDD_DEF
PWM_E
PWM_F
PWM_A
PWM_B
OTW
SD
PWM_C
VDD
AGND
OC_ADJ
VREG
PWM_D
RESET
OUT_E
PVDD_E
PGND_EF
BST_E
GVDD_ABC
GND
OUT_D
PVDD_D
PGND_D
BST_D
OUT_C
PVDD_C
BST_C
OUT_B
PVDD_B
PGND_AB
BST_B
OUT_A
PVDD_A
BST_A
VALID2
VALID1
To µP
PVDD
12 V
OUT_BIAS
BST_BIAS
21
22
43
44
42
41
39
38
40
36
37
35
34
31
30
32
SAT
28
29
27
26
25
23
24
3
20
4
13
14
12
10
9
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
2
5
6
15
16
11
PGND_C
33
17
18
19
7
8
PGND_EF
1
PurePath
Digital
Modulator
TAS5086
TAS5186
S0061-01
SAT
SAT
SUB
SAT
SAT
680 Ω
33 nF
+
+
+
+
+
+
22 µH
270 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
33 nF
33 nF
33 nF
33 nF
33 nF
270 µF
270 µF
270 µF
270 µF
270 µF
1000 µF
1000 µF
270 µF
270 µF
270 µF
270 µF
22 µH
22 µH
22 µH
22 µH
22 µH
330 Ω
330 Ω
330 Ω
330 Ω
330 Ω
330 Ω
0.47 µF
0.47 µF
0.47 µF
0.47 µF
0.47 µF
0.47 µF
1 µF
1 µF
1 µF
1 µF
1 µF
1 µF
33 nF
1 µF
15 kΩ
1 µF
0.1 µF
0.1 µF
10 µF
TYPICAL SYSTEM DIAGRAM
TAS5186
SLES136 – MAY 2005
PurePath Digital™
5
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M1
M2
RESET
SD
OTW
AGND
OC_ADJ
VREG VREG
VDD
GVDD_DEF
M3
Undervoltage
Protection
GND
PWM_F OUT_F
PGND_EF
PVDD_F
BST_F
PWM
Receiver
I
Sense
Protection
and
I/O Logic
Power On
Reset
Temperature
Sense
Overload
Protection
Control Timing
Gate
Drive
PWM_E OUT_E
PGND_EF
PVDD_E
BST_E
PWM
Receiver
Control Timing
Gate
Drive
PWM_D OUT_D
PGND_D
PVDD_D
BST_D
PWM
Receiver
Control Timing
Gate
Drive
PWM_C OUT_C
PGND_C
PVDD_C
BST_C
PWM
Receiver
Control Timing
Gate
Drive
PWM_B OUT_B
PGND_AB
PVDD_B
BST_B
PWM
Receiver
Control Timing
Gate
Drive
PWM_A OUT_A
PVDD_A
BST_A
PWM
Receiver
Control Timing
Gate
Drive
OUT_BIAS
BST_BIAS
Control Timing
Gate
Drive
B0034-01
Internal Pullup
Resistors to VREG
GVDD_ABC
TAS5186
SLES136 – MAY 2005
FUNCTIONAL BLOCK DIAGRAM
6
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