Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
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SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
TM
FEATURES
D2×125 W at 10% THD+N Into 4-W BTL
D2×98 W at 10% THD+N Into 6-W BTL
D2×76 W at 10% THD+N Into 8-W BTL
D4×45 W at 10% THD+N Into 3-W SE
D4×35 W at 10% THD+N Into 4-W SE
D1×192 W at 10% THD+N Into 3-W PBTL
D1×240 W at 10% THD+N Into 2-W PBTL
D>100-dB SNR (A-Weighted)
D<0.1% THD+N at 1 W
DThermally Enhanced Package Option:
− DKD (36-Pin PSOP3)
DHigh-Efficiency Power Stage (>90%) With
140-mW Output MOSFETs
DPower-On Reset for Protection on Power Up
Without Any Power-Supply Sequencing
DIntegrated Self-Protection Circuits Including:
− Undervoltage
− Overtemperature
− Overload
− Short Circuit
DError Reporting
DEMI Compliant When Used With
Recommended System Design
DIntelligent Gate Drive
APPLICATIONS
DMini/Micro Audio System
DDVD Receiver
DHome Theater
DESCRIPTION
The TAS5152 is a third-generation, high-performance,
integrated stereo digital amplifier power stage with
improved protection system. The TAS5152 is capable
of driving a 4-Ω bridge-tied load (BTL) at up to 125 W
per channel with low integrated noise at the output, low
THD+N performance, and low idle power dissipation.
A low-cost, high-fidelity audio system can be built using
a TI chipset, comprised of a modulator (e.g., T AS5508)
and the TAS5152. This system only requires a simple
passive LC demodulation filter to deliver high-quality,
high-efficiency audio amplification with proven EMI
compliance. This device requires two power supplies,
12 V for GVDD and VDD, and 35 V for PVDD. The
TAS5152 does not require power-up sequencing due to
internal power-on reset. The efficiency of this digital
amplifier is g rea t e r t h a n 9 0 % i n t o 6 Ω, which enables the
use of smaller power supplies and heatsinks.
The TAS5152 has an innovative protection system
integrated on-chip, safeguarding the device against a
wide range of fault conditions that could damage the
system. These safeguards are short-circuit protection,
overcurrent protection, undervoltage protection, and
overtemperature protection. The TAS5152 has a new
proprietary current-limiting circuit that reduces the
possibility of device shutdown during high-level music
transients. A new programmable overcurrent detector
allows the use of lower-cost inductors in the
demodulation output filter.
BTL OUTPUT POWER vs SUPPLY VOL TAGE
130
TC = 75°C
120
THD+N @ 10%
110
100
90
80
70
60
50
− Output Power − W
40
O
P
30
20
10
0
05101520253035
PVDD − Supply V oltage − V
4 Ω
6 Ω
8 Ω
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath Digital and PowerPAD are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
The TAS5152 is available in a 36-pin PSOP3 (DKD)
thermally enhanced package. The package contains a
heat slug that is located on the top side of the device for
convenient thermal coupling to the heatsink.
The 1N and 2N naming convention is used to indicate the required
number of PWM lines to the power stage per channel in a specific
mode.
(2)
An overload protection (OLP) occurring on A or B causes both
channels to shut down. An OLP on C or D works similarly. Global
errors like overtemperature error (OTE), undervoltage protection
(UVP) and power-on reset (POR) affect all channels.
AD/BD
modulation
(1)
1N
AD
modulation
(1)
1N
AD
modulation
(1)
1N
AD
modulation
Reserved
RATION
2 channels
BTL output
2 channels
BTL output
1 channel
PBTL output
4 channels
SE output
Package Heat Dissipation Ratings
PARAMETERTAS5152DKD
R
(°C/W)—2 BTL or 4 SE
θJC
channels (8 transistors)
R
〈°C/W)—1 BTL or 2 SE
θJC
channel(s) (4 transistors)
R
(°C/W)—(1 transistor)8.6
θJC
Pad area
(1)
JC is junction-to-case, CH is case-to-heatsink.
(2)
R
is an important consideration. Assume a 2-mil thickness of
θCH
typical thermal grease between the pad area and the heatsink. The
R
with this condition is 0.8°C/W for the DKD package and
θCH
1.8°C/W for the DDV package.
(2)
PROTECTION
BTL mode
BTL mode
PBTL mode.
Only PWM_A
input is used.
Protection works
similarly to BTL
(2)
mode
difference in SE
mode is that
OUT_x is Hi-Z
instead of a
pulldown through
internal pulldown
resistor.
(1)
1.28
2.56
2
80 mm
(2)
(2)
. Only
2
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SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted
TAS5152
VDD to AGND–0.3 V to 13.2 V
GVDD_X to AGND–0.3 V to 13.2 V
(2)
(2)
(2)
J
–0.3 V to 50 V
–0.3 V to 50 V
–0.3 V to 63.2 V
–0.3 V to 4.2 V
9 mA
0°C to 125°C
260_C
PVDD_X to GND_X
OUT_X to GND_X
BST_X to GND_X
VREG to AGND–0.3 V to 4.2 V
GND_X to GND–0.3 V to 0.3 V
GND_X to AGND–0.3 V to 0.3 V
GND to AGND–0.3 V to 0.3 V
PWM_X, OC_ADJ, M1, M2, M3 to
AGND
RESET_X, SD, OTW to AGND–0.3 V to 7 V
Maximum continuous sink current (SD,
OTW)
Maximum operating junction
temperature range, T
Storage temperature–40_C to 125_C
Lead temperature, 1,6 mm (1/16 inch)
from case for 10 seconds
Minimum pulse width low50 ns
(1)
Stresses beyond those listed under “absolute maximum ratings”
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device
reliability.
(2)
These voltages represent the dc voltage + peak ac waveform
measured at the terminal of the device in all conditions.
(1)
Ordering Information
T
A
0°C to 70°CTAS5152DKD36-pin PSOP3
PACKAGEDESCRIPTION
For the most current specification and package
information, see the TI Web site at www.ti.com.
3
FUNCTION
(1)
DESCRIPTION
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
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Terminal Functions
TERMINAL
NAMENO.
AGND9PAnalog ground
BST_A35PHS bootstrap supply (BST), external capacitor to OUT_A required
BST_B28PHS bootstrap supply (BST), external capacitor to OUT_B required
BST_C27PHS bootstrap supply (BST), external capacitor to OUT_C required
BST_D20PHS bootstrap supply (BST), external capacitor to OUT_D required
GND8PGround
GND_A32PPower ground for half-bridge A
GND_B31PPower ground for half-bridge B
GND_C24PPower ground for half-bridge C
GND_D23PPower ground for half-bridge D
GVDD_A36PGate-drive voltage supply requires 0.1-µF capacitor to AGND
GVDD_B1PGate-drive voltage supply requires 0.1-µF capacitor to AGND
GVDD_C18PGate-drive voltage supply requires 0.1-µF capacitor to AGND
GVDD_D19PGate-drive voltage supply requires 0.1-µF capacitor to AGND
M113IMode selection pin
M212IMode selection pin
M311IMode selection pin
OC_ADJ7OAnalog overcurrent programming pin requires resistor to ground
OTW2OOvertemperature warning signal, open drain, active-low
OUT_A33OOutput, half-bridge A
OUT_B30OOutput, half-bridge B
OUT_C25OOutput, half-bridge C
OUT_D22OOutput, half-bridge D
PVDD_A34PPower-supply input for half-bridge A requires close decoupling of 0.1-µF capacitor to
GND_A
PVDD_B29PPower-supply input for half-bridge B requires close decoupling of 0.1-µF capacitor to
GND_B
PVDD_C26PPower-supply input for half-bridge C requires close decoupling of 0.1-µF capacitor to
GND_C
PVDD_D21PPower-supply input for half-bridge D requires close decoupling of 0.1-µF capacitor to
GND_D
PWM_A4IInput signal for half-bridge A
PWM_B6IInput signal for half-bridge B
PWM_C14IInput signal for half-bridge C
PWM_D16IInput signal for half-bridge D
RESET_AB5IReset signal for half-bridge A and half-bridge B, active-low
RESET_CD15IReset signal for half-bridge C and half-bridge D, active-low
SD3OShutdown signal, open drain, active-low
VDD17PPower supply for digital voltage regulator requires 0.1-µF capacitor to GND.
VREG10PDigital regulator supply filter pin requires 0.1-µF capacitor to AGND
Output AD modulation, switching
frequency > 350 kHz
Minimum output inductance under
23
1.52
10
10
10
Ω
µH
AUDIO SPECIFICATIONS (BTL)
PVDD_X = 35 V, GVDD = VDD = 12 V , BTL mode, RL = 4 Ω, audio frequency = 1 kHz, AES17 filter, F
unless otherwise noted. Audio performance is recorded as a chipset, using TAS5508 PWM processor with an ef fective modulation in dex limit of
96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified.
RL = 4 Ω,10% THD, clipped input
signal
RL = 6Ω,10% THD, clipped input
signal
RL = 8Ω,10% THD, clipped input
signal
RL = 4 Ω, 0 dBFS, unclipped input
signal
RL = 6Ω, 0 dBFS, unclipped input
signal
RL = 8Ω,0 dBFS, unclipped input
signal
0 dBFS0.1
1 W0.02
V
n
SNRSignal-to-noise ratio
P
idle
(1)
SNR is calculated relative to 0-dBFS input level.
(2)
Actual system idle losses are affected by core losses of output inductors.
Output integrated noiseA-weighted145µV
(1)
Power dissipation due to idle losses (IPVDDx)PO = 0 W, 2 channels switching
using TAS5508 modulator
A-weighted, input level = –60 dBFS
using TAS5518 modulator
= 384 kHz, case temperature = 75°C,
PWM
TAS5152
MINTYPMAX
125
98
76
96
72
57
102dB
110dB
(2)
2W
7
SYMBOL
PARAMETER
CONDITIONS
UNIT
PoPower output per channel
W
THD+N
Total harmonic distortion + noise
%
SYMBOL
PARAMETER
CONDITIONS
UNIT
PoPower output per channel
W
THD+N
Total harmonic distortion + noise
%
DNR
Dynamic range
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
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AUDIO SPECIFICATIONS (Single-Ended Output)
PVDD_X = 35 V, GVDD = VDD = 12 V , SE mode, RL = 4 Ω, audio frequency = 1 kHz, AES17 filter, F
unless otherwise noted. Audio performance is recorded as a chipset, using TAS5086 PWM processor with an ef fective modulation index limit of
96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified.
RL = 3 Ω,10% THD, clipped input
signal
RL = 4 Ω,10% THD, clipped input
signal
RL = 3 Ω, 0 dBFS, unclipped input
signal
RL = 4Ω, 0 dBFS, unclipped input
signal
0 dBFS0.2
1 W0.03
V
n
SNRSignal-to-noise ratio
DNRDynamic range
P
idle
(1)
SNR is calculated relative to 0-dBFS input level.
(2)
Actual system idle losses are affected by core losses of output inductors.
Output integrated noiseA-weighted90µV
(1)
Power dissipation due to idle losses (IPVDDx)PO = 0 W, 4 channels switching
PVDD_X = 35 V, GVDD = VDD = 12 V , PBTL mode, RL = 3 Ω, audio frequency = 1 kHz, AES17 filter, F
75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5508 PWM processor with an effective modulation index
limit of 96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified.
RL = 3 Ω,10% THD, clipped input
signal
RL = 2 Ω,10% THD, clipped input
signal
RL = 3 Ω, 0 dBFS, unclipped input
signal
RL = 2Ω, 0 dBFS, unclipped input
signal
0 dBFS0.2
1 W0.02
V
n
SNRSignal-to-noise ratio
P
idle
(1)
SNR is calculated relative to 0-dBFS input level.
(2)
Actual system idle losses are affected by core losses of output inductors.
Output integrated noiseA-weighted160µV
(1)
Power dissipation due to idle losses (IPVDDx)PO = 0 W, 1 channel switching