Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
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SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
TM
FEATURES
D 2×125 W at 10% THD+N Into 4-W BTL
D 2×98 W at 10% THD+N Into 6-W BTL
D 2×76 W at 10% THD+N Into 8-W BTL
D 4×45 W at 10% THD+N Into 3-W SE
D 4×35 W at 10% THD+N Into 4-W SE
D 1×192 W at 10% THD+N Into 3-W PBTL
D 1×240 W at 10% THD+N Into 2-W PBTL
D >100-dB SNR (A-Weighted)
D <0.1% THD+N at 1 W
D Thermally Enhanced Package Option:
− DKD (36-Pin PSOP3)
D High-Efficiency Power Stage (>90%) With
140-mW Output MOSFETs
D Power-On Reset for Protection on Power Up
Without Any Power-Supply Sequencing
D Integrated Self-Protection Circuits Including:
− Undervoltage
− Overtemperature
− Overload
− Short Circuit
D Error Reporting
D EMI Compliant When Used With
Recommended System Design
D Intelligent Gate Drive
APPLICATIONS
D Mini/Micro Audio System
D DVD Receiver
D Home Theater
DESCRIPTION
The TAS5152 is a third-generation, high-performance,
integrated stereo digital amplifier power stage with
improved protection system. The TAS5152 is capable
of driving a 4-Ω bridge-tied load (BTL) at up to 125 W
per channel with low integrated noise at the output, low
THD+N performance, and low idle power dissipation.
A low-cost, high-fidelity audio system can be built using
a TI chipset, comprised of a modulator (e.g., T AS5508)
and the TAS5152. This system only requires a simple
passive LC demodulation filter to deliver high-quality,
high-efficiency audio amplification with proven EMI
compliance. This device requires two power supplies,
12 V for GVDD and VDD, and 35 V for PVDD. The
TAS5152 does not require power-up sequencing due to
internal power-on reset. The efficiency of this digital
amplifier is g rea t e r t h a n 9 0 % i n t o 6 Ω, which enables the
use of smaller power supplies and heatsinks.
The TAS5152 has an innovative protection system
integrated on-chip, safeguarding the device against a
wide range of fault conditions that could damage the
system. These safeguards are short-circuit protection,
overcurrent protection, undervoltage protection, and
overtemperature protection. The TAS5152 has a new
proprietary current-limiting circuit that reduces the
possibility of device shutdown during high-level music
transients. A new programmable overcurrent detector
allows the use of lower-cost inductors in the
demodulation output filter.
BTL OUTPUT POWER vs SUPPLY VOL TAGE
130
TC = 75°C
120
THD+N @ 10%
110
100
90
80
70
60
50
− Output Power − W
40
O
P
30
20
10
0
0 5 10 15 20 25 30 35
PVDD − Supply V oltage − V
4 Ω
6 Ω
8 Ω
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath Digital and PowerPAD are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
! "#$ %!& %
"! "! '! ! !( ! %% )*&
% "!+ %! !!$* $%! !+ $$ "!!&
Copyright 2005, Texas Instruments Incorporated
A
A
B
C
D
D
DKD PACKAGE
CONFIGU-
SCHEME
Reserved
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
The TAS5152 is available in a 36-pin PSOP3 (DKD)
thermally enhanced package. The package contains a
heat slug that is located on the top side of the device for
convenient thermal coupling to the heatsink.
(TOP VIEW)
GVDD_B
OTW
SD
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
VDD
GVDD_C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GVDD_
BST_A
PVDD_
OUT_A
GND_A
GND_B
OUT_B
PVDD_
BST_B
BST_C
PVDD_
OUT_C
GND_C
GND_D
OUT_D
PVDD_
BST_D
GVDD_
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MODE Selection Pins
MODE PINS PWM INPUT OUTPUT
M3 M2 M1
(1)
2N
0 0 0
0 0 1 Reserved
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
(1)
The 1N and 2N naming convention is used to indicate the required
number of PWM lines to the power stage per channel in a specific
mode.
(2)
An overload protection (OLP) occurring on A or B causes both
channels to shut down. An OLP on C or D works similarly. Global
errors like overtemperature error (OTE), undervoltage protection
(UVP) and power-on reset (POR) affect all channels.
AD/BD
modulation
(1)
1N
AD
modulation
(1)
1N
AD
modulation
(1)
1N
AD
modulation
Reserved
RATION
2 channels
BTL output
2 channels
BTL output
1 channel
PBTL output
4 channels
SE output
Package Heat Dissipation Ratings
PARAMETER TAS5152DKD
R
(°C/W)—2 BTL or 4 SE
θJC
channels (8 transistors)
R
〈°C/W)—1 BTL or 2 SE
θJC
channel(s) (4 transistors)
R
(°C/W)—(1 transistor) 8.6
θJC
Pad area
(1)
JC is junction-to-case, CH is case-to-heatsink.
(2)
R
is an important consideration. Assume a 2-mil thickness of
θCH
typical thermal grease between the pad area and the heatsink. The
R
with this condition is 0.8°C/W for the DKD package and
θCH
1.8°C/W for the DDV package.
(2)
PROTECTION
BTL mode
BTL mode
PBTL mode.
Only PWM_A
input is used.
Protection works
similarly to BTL
(2)
mode
difference in SE
mode is that
OUT_x is Hi-Z
instead of a
pulldown through
internal pulldown
resistor.
(1)
1.28
2.56
2
80 mm
(2)
(2)
. Only
2
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SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted
TAS5152
VDD to AGND –0.3 V to 13.2 V
GVDD_X to AGND –0.3 V to 13.2 V
(2)
(2)
(2)
J
–0.3 V to 50 V
–0.3 V to 50 V
–0.3 V to 63.2 V
–0.3 V to 4.2 V
9 mA
0°C to 125°C
260_C
PVDD_X to GND_X
OUT_X to GND_X
BST_X to GND_X
VREG to AGND –0.3 V to 4.2 V
GND_X to GND –0.3 V to 0.3 V
GND_X to AGND –0.3 V to 0.3 V
GND to AGND –0.3 V to 0.3 V
PWM_X, OC_ADJ, M1, M2, M3 to
AGND
RESET_X, SD, OTW to AGND –0.3 V to 7 V
Maximum continuous sink current (SD,
OTW)
Maximum operating junction
temperature range, T
Storage temperature –40_C to 125_C
Lead temperature, 1,6 mm (1/16 inch)
from case for 10 seconds
Minimum pulse width low 50 ns
(1)
Stresses beyond those listed under “absolute maximum ratings”
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device
reliability.
(2)
These voltages represent the dc voltage + peak ac waveform
measured at the terminal of the device in all conditions.
(1)
Ordering Information
T
A
0°C to 70°C TAS5152DKD 36-pin PSOP3
PACKAGE DESCRIPTION
For the most current specification and package
information, see the TI Web site at www.ti.com.
3
FUNCTION
(1)
DESCRIPTION
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
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Terminal Functions
TERMINAL
NAME NO.
AGND 9 P Analog ground
BST_A 35 P HS bootstrap supply (BST), external capacitor to OUT_A required
BST_B 28 P HS bootstrap supply (BST), external capacitor to OUT_B required
BST_C 27 P HS bootstrap supply (BST), external capacitor to OUT_C required
BST_D 20 P HS bootstrap supply (BST), external capacitor to OUT_D required
GND 8 P Ground
GND_A 32 P Power ground for half-bridge A
GND_B 31 P Power ground for half-bridge B
GND_C 24 P Power ground for half-bridge C
GND_D 23 P Power ground for half-bridge D
GVDD_A 36 P Gate-drive voltage supply requires 0.1-µF capacitor to AGND
GVDD_B 1 P Gate-drive voltage supply requires 0.1-µF capacitor to AGND
GVDD_C 18 P Gate-drive voltage supply requires 0.1-µF capacitor to AGND
GVDD_D 19 P Gate-drive voltage supply requires 0.1-µF capacitor to AGND
M1 13 I Mode selection pin
M2 12 I Mode selection pin
M3 11 I Mode selection pin
OC_ADJ 7 O Analog overcurrent programming pin requires resistor to ground
OTW 2 O Overtemperature warning signal, open drain, active-low
OUT_A 33 O Output, half-bridge A
OUT_B 30 O Output, half-bridge B
OUT_C 25 O Output, half-bridge C
OUT_D 22 O Output, half-bridge D
PVDD_A 34 P Power-supply input for half-bridge A requires close decoupling of 0.1-µF capacitor to
GND_A
PVDD_B 29 P Power-supply input for half-bridge B requires close decoupling of 0.1-µF capacitor to
GND_B
PVDD_C 26 P Power-supply input for half-bridge C requires close decoupling of 0.1-µF capacitor to
GND_C
PVDD_D 21 P Power-supply input for half-bridge D requires close decoupling of 0.1-µF capacitor to
GND_D
PWM_A 4 I Input signal for half-bridge A
PWM_B 6 I Input signal for half-bridge B
PWM_C 14 I Input signal for half-bridge C
PWM_D 16 I Input signal for half-bridge D
RESET_AB 5 I Reset signal for half-bridge A and half-bridge B, active-low
RESET_CD 15 I Reset signal for half-bridge C and half-bridge D, active-low
SD 3 O Shutdown signal, open drain, active-low
VDD 17 P Power supply for digital voltage regulator requires 0.1-µF capacitor to GND.
VREG 10 P Digital regulator supply filter pin requires 0.1-µF capacitor to AGND
(1)
I = input, O = Output, P = Power
4
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SYSTEM BLOCK DIAGRAM
System
Microcontroller
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
OTW
SD
TAS5508
Channel
Output
Right-
Channel
Output
Left-
VALID
Hardwire
Mode
Control
PWM_A
PWM_B
PWM_C
PWM_D
M1
M2
M3
RESET_AB
RESET_CD
Input
H-Bridge 1
Input
H-Bridge 2
PVDD_A, B, C, D
2-Channel
H-Bridge
BTL Mode
GND_A, B, C, D
GVDD_A, B, C, D
GND
SD
VDD
OTW
Output
H-Bridge 1
Output
H-Bridge 2
VREG
AGND
OUT_A
OUT_B
OUT_C
OUT_D
OC_ADJ
BST_A
BST_B
BST_C
BST_D
Bootstrap
Capacitors
2nd-Order L- C
Output Filter
for Each
Half-Bridge
2nd-Order L- C
Output Filter
for Each
Half-Bridge
Bootstrap
Capacitors
System
Power
Supply
VAC
35 V
GND
12 V
4
PVDD
Decoupling
GND
GVDD (12 V)/VDD (12 V)
44
PVDD
PowerSupply
GVDD
VDD
VREG
Power-Supply
Decoupling
Hardwire
OC Limit
5
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
FUNCTIONAL BLOCK DIAGRAM
Under-
OTW
SD
M1
M2
Internal Pullup
Resistors to VREG
Protection
and
voltage
Protection
Power
On
Reset
I/O Logic
M3
Temp.
Sense
RESET_AB
RESET_CD
PWM_D OUT_D
PWM_C OUT_C
PWM_B OUT_B
PWM_A OUT_A
PWM
Rcv.
PWM
Rcv.
PWM
Rcv.
PWM
Rcv.
Ctrl.
Ctrl.
Ctrl.
Ctrl.
Overload
Protection
Timing
Timing
Timing
Timing
Gate
Drive
Gate
Drive
Gate
Drive
Gate
Drive
4
VREG VREG
Isense
BTL/PBTL−Configuration
Pulldown Resistor
BTL/PBTL−Configuration
Pulldown Resistor
BTL/PBTL−Configuration
Pulldown Resistor
BTL/PBTL−Configuration
Pulldown Resistor
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VDD
AGND
GND
OC_ADJ
GVDD_D
BST_D
PVDD_D
GND_D
GVDD_C
BST_C
PVDD_C
GND_C
GVDD_B
BST_B
PVDD_B
GND_B
GVDD_A
BST_A
PVDD_A
GND_A
6
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Output filter: L = 10 µH, C = 470 nF
Load impedance
Output AD modulation, switching
Ω
Output-filter inductance
short-circuit condition
µH
SYMBOL
PARAMETER
CONDITIONS
UNIT
PoPower output per channel
W
THD+N
Total harmonic distortion + noise
%
DNR
Dynamic range
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
RECOMMENDED OPERATING CONDITIONS
CONDITIONS MIN NOM MAX UNIT
PVDD_x Half-bridge supply DC supply voltage 0 35 37 V
GVDD_x
VDD Digital regulator input DC supply voltage 10.8 12 13.2 V
RL (BTL)
RL (SE)
RL (PBTL)
L
(BTL)
Output
L
(SE)
Output
L
(PBTL)
Output
F
PWM
T
J
Supply for logic regulators and gate-drive
circuitry
Load impedance
Output-filter inductance
PWM frame rate 192 384 432 kHz
Junction temperature 0 125 _C
DC supply voltage 10.8 12 13.2 V
3 4
Output AD modulation, switching
frequency > 350 kHz
Minimum output inductance under
2 3
1.5 2
10
10
10
Ω
µH
AUDIO SPECIFICATIONS (BTL)
PVDD_X = 35 V, GVDD = VDD = 12 V , BTL mode, RL = 4 Ω, audio frequency = 1 kHz, AES17 filter, F
unless otherwise noted. Audio performance is recorded as a chipset, using TAS5508 PWM processor with an ef fective modulation in dex limit of
96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified.
RL = 4 Ω,10% THD, clipped input
signal
RL = 6 Ω,10% THD, clipped input
signal
RL = 8 Ω,10% THD, clipped input
signal
RL = 4 Ω, 0 dBFS, unclipped input
signal
RL = 6 Ω, 0 dBFS, unclipped input
signal
RL = 8 Ω, 0 dBFS, unclipped input
signal
0 dBFS 0.1
1 W 0.02
V
n
SNR Signal-to-noise ratio
P
idle
(1)
SNR is calculated relative to 0-dBFS input level.
(2)
Actual system idle losses are affected by core losses of output inductors.
Output integrated noise A-weighted 145 µV
(1)
Power dissipation due to idle losses (IPVDDx) PO = 0 W, 2 channels switching
A-weighted 102 dB
A-weighted, input level = –60 dBFS
using TAS5508 modulator
A-weighted, input level = –60 dBFS
using TAS5518 modulator
= 384 kHz, case temperature = 75°C,
PWM
TAS5152
MIN TYP MAX
125
98
76
96
72
57
102 dB
110 dB
(2)
2 W
7
SYMBOL
PARAMETER
CONDITIONS
UNIT
PoPower output per channel
W
THD+N
Total harmonic distortion + noise
%
SYMBOL
PARAMETER
CONDITIONS
UNIT
PoPower output per channel
W
THD+N
Total harmonic distortion + noise
%
DNR
Dynamic range
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
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AUDIO SPECIFICATIONS (Single-Ended Output)
PVDD_X = 35 V, GVDD = VDD = 12 V , SE mode, RL = 4 Ω, audio frequency = 1 kHz, AES17 filter, F
unless otherwise noted. Audio performance is recorded as a chipset, using TAS5086 PWM processor with an ef fective modulation index limit of
96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified.
RL = 3 Ω,10% THD, clipped input
signal
RL = 4 Ω,10% THD, clipped input
signal
RL = 3 Ω, 0 dBFS, unclipped input
signal
RL = 4 Ω, 0 dBFS, unclipped input
signal
0 dBFS 0.2
1 W 0.03
V
n
SNR Signal-to-noise ratio
DNR Dynamic range
P
idle
(1)
SNR is calculated relative to 0-dBFS input level.
(2)
Actual system idle losses are affected by core losses of output inductors.
Output integrated noise A-weighted 90 µV
(1)
Power dissipation due to idle losses (IPVDDx) PO = 0 W, 4 channels switching
A-weighted 100 dB
A-weighted, input level = –60 dBFS
using TAS5508 modulator
= 384 kHz, case temperature = 75°C,
PWM
TAS5152
MIN TYP MAX
45
35
35
25
100 dB
(2)
2 W
AUDIO SPECIFICATIONS (PBTL)
PVDD_X = 35 V, GVDD = VDD = 12 V , PBTL mode, RL = 3 Ω, audio frequency = 1 kHz, AES17 filter, F
75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5508 PWM processor with an effective modulation index
limit of 96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified.
RL = 3 Ω,10% THD, clipped input
signal
RL = 2 Ω,10% THD, clipped input
signal
RL = 3 Ω, 0 dBFS, unclipped input
signal
RL = 2 Ω, 0 dBFS, unclipped input
signal
0 dBFS 0.2
1 W 0.02
V
n
SNR Signal-to-noise ratio
P
idle
(1)
SNR is calculated relative to 0-dBFS input level.
(2)
Actual system idle losses are affected by core losses of output inductors.
Output integrated noise A-weighted 160 µV
(1)
Power dissipation due to idle losses (IPVDDx) PO = 0 W, 1 channel switching
A-weighted 102 dB
A-weighted, input level = –60 dBFS
using TAS5508 modulator
A-weighted, input level = –60 dBFS
using TAS5518 modulator
= 384 kHz, case temperature =
PWM
TAS5152
MIN TYP MAX
192
240
145
190
102 dB
110 dB
(2)
2 W
8
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SYMBOL
PARAMETER
CONDITIONS
IVDD
VDD supply current
mA
IGVDD_x
Gate supply current per half-bridge
mA
Half-bridge idle current
IPVDD_x
Half-bridge idle current
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
ELECTRICAL CHARACTERISTICS
RL= 4 Ω. F
specified.
Internal Voltage Regulator and Current Consumption
VREG Voltage regulator, only used as a reference node VDD = 12 V 3 3.3 3.6 V
IPVDD_x
Output Stage MOSFETs
R
DSon,LS
R
DSon,HS
= 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise
PWM
TAS5152
MIN TYP MAX UNITS
Operating, 50% duty cycle 7 17
Idle, reset mode 6 11
50% duty cycle 5 16
Reset mode 0.3 1
Drain-to-source resistance, LS
Drain-to-source resistance, HS
50% duty cycle, without
output filter or load
Reset mode, no switching 7 25 µA
T
25°C, includes
J
=
metallization resistance,
GVDD = 12 V
T
25°C, includes
J
=
metallization resistance,
GVDD = 12 V
15 25 mA
140 155 mΩ
140 155 mΩ
9
SYMBOL
PARAMETER
CONDITIONS
PWM_D, M1, M2, M3,
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
RL= 4 Ω. F
specified.
I/O Protection
V
uvp,G
V
uvp,hyst
(1)
OTW
OTW
HYST
(1)
OTE
OTE-OTW
differential
OTE
HYST
OLPC Overload protection counter F
I
OC
I
OCT
R
OCP
R
PD
Static Digital Specifications
V
IH
V
IL
Leakage Input leakage current –10 10 µA
OTW/SHUTDOWN (SD)
R
INT_PU
V
OH
V
OL
FANOUT Device fanout OTW , SD No external pullup 30 Devices
(1)
Specified by design
= 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise
PWM
TAS5152
MIN TYP MAX UNITS
Undervoltage protection limit, GVDD_x 9.8 V
(1)
Undervoltage protection hysteresis 250 mV
Overtemperature warning 115 125 135 _C
Temperature drop needed below OTW temp. for
(1)
OTW to be inactive after the OTW event
Overtemperature error 145 155 165 _C
OTE-OTW differential 30 _C
(1)
Temperature drop needed below OTE temp. for
(1)
SD to be released following an OTE event
= 384 kHz 1.25 ms
pwm
Overcurrent limit protection
Overcurrent response time 210 ns
OC programming resistor range Resistor tolerance = 5% 15 69 kΩ
Internal pulldown resistor at the output of each
half-bridge
High-level input voltage
Low-level input voltage
Internal pullup resistance, OTW to VREG, SD to
VREG
High-level output voltage
Low-level output voltage IO = 4 mA 0.2 0.4 V
Resistor-programmable, high
end, R
Connected when RESET is
active to provide bootstrap
capacitor charge. Not used in
SE mode
PWM_A, PWM_B, PWM_C,
RESET_AB, RESET_CD
Internal pullup resistor 3 3.3 3.6
External pullup of 4.7 kΩ to
5 V
OCP
= 15 kΩ
8.5 10.8 11.8 A
2 V
20 26 32 kΩ
4.5 5
25 _C
25 _C
2.5 kΩ
0.8 V
V
10
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THD+N − Total Harmonic Distortion + Noise − %
P
− Output Power − W
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TC = 75°C
10
PVDD = 35 V
One Channel
1
4 Ω
0.1
0.01
PO − Output Power − W
6 Ω
8 Ω
101
Figure 1
100
OUTPUT POWER
vs
SUPPLY VOL TAGE
130
TC = 75°C
120
THD+N @ 10%
110
100
90
80
70
60
50
− Output Power − W
40
O
P
30
20
10
0
0 5 10 15 20 25 30 35
PVDD − Supply Voltage − V
4 Ω
6 Ω
Figure 2
8 Ω
UNCLIPPED OUTPUT POWER
130
120
TC = 75°C
110
100
90
80
70
60
50
40
O
30
20
10
0
0 5 10 15 20 25 30 35
vs
SUPPLY VOL TAGE
4 Ω
6 Ω
PVDD − Supply Voltage − V
Figure 3
8 Ω
SYSTEM EFFICIENCY
vs
OUTPUT POWER
100
90
80
70
60
50
40
Efficiency − %
30
20
10
0
0 25 50 75 100 125 150 175 200 225 250
8 Ω
PO − Output Power − W
6 Ω
Figure 4
4 Ω
TC = 25°C
Two Channels
11
Power Loss − W
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
www.ti.com
SYSTEM POWER LOSS
vs
OUTPUT POWER
50
TC = 25°C
45
40
35
30
25
20
15
10
5
0
0 25 50 75 100 125 150 175 200 225 250
PO − Output Power − W
4 Ω
6 Ω
8 Ω
Figure 5
SYSTEM OUTPUT POWER
vs
CASE TEMPERATURE
150
140
130
120
110
100
90
80
70
60
− Output Power − W
50
O
P
40
30
20
THD+N @10%
10
0
10 20 30 40 50 60 70 80 90 100 110 120
TC − Case Temperature − °C
6 Ω
8 Ω
Figure 6
4 Ω
NOISE AMPLITUDE
vs
FREQUENCY
0
TC = 75°C
−10
–60 dB
−20
1 kHz
−30
−40
−50
−60
−70
−80
−90
−100
Noise Amplitude − dBr
−110
−120
−130
−140
−150
0 2 4 6 8 10121416182022
f − Frequency − kHz
Figure 7
12
www.ti.com
THD+N − Total Harmonic Distortion + Noise − %
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
TYPICAL CHARACTERISTICS, SE CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TC = 75°C
10
PVDD = 35 V
One Channel
1
3 Ω
0.1
0.01
PO − Output Power − W
101
Figure 8
4 Ω
50
OUTPUT POWER
vs
SUPPLY VOL TAGE
50
TC = 75°C
45
THD+N @ 10%
40
35
30
25
20
− Output Power − W
O
15
P
10
5
0
0 5 10 15 20 25 30 35
PVDD − Supply Voltage − V
3 Ω
Figure 9
4 Ω
OUTPUT POWER
vs
CASE TEMPERATURE
60
55
50
45
40
35
30
25
− Output Power − W
20
O
P
15
10
5
THD+N@ 10%
0
10 20 30 40 50 60 70 80 90 100 110 120
TC − Case Temperature − °C
4 Ω
Figure 10
3 Ω
13
THD+N − Total Harmonic Distortion + Noise − %
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
www.ti.com
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TC = 75°C
10
PVDD = 35 V
One Channel
1
0.1
0.01
2 Ω
3 Ω
101
PO − Output Power − W
Figure 11
100
260
TC = 75°C
240
THD+N @ 10%
220
200
180
160
140
120
100
− Output Power − W
80
O
P
60
40
20
0
0 5 10 15 20 25 30 35
OUTPUT POWER
vs
SUPPLY VOL TAGE
2 Ω
3 Ω
PVDD − Supply Voltage − V
Figure 12
SYSTEM OUTPUT POWER
vs
CASE TEMPERATURE
300
THD+N @ 10%
280
260
240
220
200
180
− Output Power − W
O
160
P
140
120
100
10 20 30 40 50 60 70 80 90 100 110 120
TC − Case Temperature − °C
2 Ω
Figure 13
3 Ω
14
www.ti.com
GVDD
Microcontroller
BKND_ERR
PWM_P_1
PWM_M_1
PWM_P_2
PWM_M_2
TAS5508
GVDD
10 µF
VALID
1 Ω
10 µF
10 Ω
0 Ω
Optional
10 Ω
100 nF
22 kΩ
100 nF
100 nF
100 nF
1
GVDD_B
2
OTW
3
SD
4
PWM_A
5
RESET_AB
6
PWM_B
7
OC_ADJ
8
GND
9
AGND
10
VREG
11
M3
12
M2
13
M1
14
PWM_C
15
RESET_CD
16
PWM_D
17
VDD
18
GVDD_C
TAS5152DKD
GVDD_A
BST_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
BST_D
GVDD_D
100 nF
10 Ω
10 Ω
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
PVDD
100 nF
47 µF
50 V
36
33 nF
35
33 nF
33 nF
100 nF
50 V
100 nF
100 nF
100 nF
50 V
50 V
50 V
34
33
32
31
30
29
28
27
33 nF
26
25
24
23
22
21
20
19
3.3 Ω
10 nF
50 V
10 µH @ 10 A
10 µH @ 10 A
47 µF
50 V
47 µF
50 V
10 µH @ 10 A
10 µH @ 10 A
47 µF
50 V
10 nF
50 V
3.3 Ω
100 nF
50 V
100 nF
50 V
100 nF
50 V
100 nF
50 V
1000 µF
50 V
470 nF
100 V
470 nF
100 V
10 nF
10 nF
PVDD
1000 µF
50 V
50 V
50 V
3.3 Ω
3.3 Ω
3.3 Ω
3.3 Ω
10 nF
50 V
10 nF
50 V
Figure 14. Typical Differential (2N) BTL Application With AD Modulation Filters
15
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
GVDD
10 µF
Microcontroller
BKND_ERR
PWM_P_1
VALID
PWM_P_2
TAS5508
1 Ω
GVDD
10 µF
10 Ω
0 Ω
Optional
10 Ω
100 nF
No connect
100 nF
No connect
100 nF
22 kΩ
10
12
13
14
15
16
17
18
100 nF
1
2
3
4
5
6
7
8
9
11
TAS5152DKD
GVDD_B
OTW
SD
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
VDD
GVDD_C
GVDD_A
BST_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
BST_D
GVDD_D
100 nF
10 Ω
10 Ω
www.ti.com
PVDD
100 nF
47 µF
50 V
36
33 nF
35
33 nF
33 nF
100 nF
50 V
100 nF
100 nF
100 nF
50 V
50 V
50 V
34
33
32
31
30
29
28
27
33 nF
26
25
24
23
22
21
20
19
3.3 Ω
10 nF
50 V
10 µH @ 10 A
10 µH @ 10 A
47 µF
50 V
47 µF
50 V
10 µH @ 10 A
10 µH @ 10 A
47 µF
50 V
10 nF
50 V
3.3 Ω
100 nF
50 V
100 nF
50 V
100 nF
50 V
50 nF
100 V
1000 µF
50 V
470 nF
100 V
470 nF
100 V
10 nF
10 nF
PVDD
1000 µF
50 V
50 V
50 V
3.3 Ω
3.3 Ω
3.3 Ω
3.3 Ω
10 nF
50 V
10 nF
50 V
16
Figure 15. Typical Non-Differential (1N) BTL Application With AD Modulation Filters
www.ti.com
GVDD
Microcontroller
BKND_ERR
TAS5508
GVDD
10 µF
PWM_P_1
VALID
PWM_P_2
PWM_P_3
PWM_P_4
1 Ω
10 µF
10 Ω
0 Ω
Optional
10 Ω
100 nF
100 nF
39 kΩ
100 nF
10
12
13
14
15
16
17
18
100 nF
1
2
3
4
5
6
7
8
9
11
TAS5152DKD
GVDD_B
OTW
SD
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
VDD
GVDD_C
GVDD_A
BST_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
BST_D
GVDD_D
100 nF
10 Ω
10 Ω
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
100 nF
47 µF
50 V
36
33 nF
35
33 nF
33 nF
100 nF
50 V
100 nF
100 nF
100 nF
50 V
50 V
50 V
34
33
32
31
30
29
28
27
33 nF
26
25
24
23
22
21
20
19
3.3 Ω
10 nF
50 V
10 µH @ 10 A
10 µH @ 10 A
47 µF
50 V
47 µF
50 V
10 µH @ 10 A
10 µH @ 10 A
47 µF
50 V
10 nF
50 V
3.3 Ω
PVDD
1000 µF
50 V
PVDD
1000 µF
50 V
A
B
C
D
10 nF
100 nF
100 V
A
2.7 kΩ
PVDD
PVDD/2
B
PVDD
PVDD/2
220 µF
50 V
220 µF
50 V
220 µF
50 V
220 µF
50 V
2.7 kΩ
1 µF
50 V
1 µF
50 V
100 nF
100 V
100 nF
100 V
100 nF
100 V
50 V
3.3 Ω
10 nF @ 50 V
3.3 Ω
10 nF
50 V
3.3 Ω
10 nF @ 50 V
3.3 Ω
C
D
PVDD
PVDD/2
PVDD
PVDD/2
220 µF
50 V
220 µF
50 V
220 µF
50 V
220 µF
50 V
2.7 kΩ
2.7 kΩ
1 µF
50 V
1 µF
50 V
100 nF
100 V
100 nF
100 V
100 nF
100 V
100 nF
100 V
10 nF
50 V
3.3 Ω
10 nF @ 50 V
3.3 Ω
10 nF
50 V
3.3 Ω
10 nF @ 50 V
3.3 Ω
Figure 16. Typical SE Application
17
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
GVDD
10 µF
Microcontroller
BKND_ERR
PWM_P_1 PWM_A
VALID
PWM_M_1
TAS5508
1 Ω
GVDD
10 µF
10 Ω
0 Ω
Optional
10 Ω
100 nF
100 nF
30 kΩ
100 nF
10
11
12
13
14
15
16
17
18
100 nF
1
GVDD_B
2
OTW
3
SD
4
5
RESET_AB
6
PWM_B
7
OC_ADJ
8
GND
9
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
VDD
GVDD_C
TAS5152DKD
GVDD_A
BST_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
BST_D
GVDD_D
100 nF
10 Ω
10 Ω
www.ti.com
PVDD
100 nF
47 µF
50 V
36
33 nF
35
33 nF
33 nF
100 nF
50 V
100 nF
100 nF
100 nF
50 V
50 V
50 V
34
33
32
31
30
29
28
27
33 nF
26
25
24
23
22
21
20
19
3.3 Ω
10 nF
50 V
10 µH @ 10 A
10 µH @ 10 A
47 µF
50 V
47 µF
50 V
10 µH @ 10 A
10 µH @ 10 A
47 µF
50 V
10 nF
50 V
470 nF
63 V
3.3 Ω
1000 µF
50 V
100 nF
100 V
100 nF
100 V
PVDD
1000 µF
50 V
10 nF
50 V
3.3 Ω
3.3 Ω
10 nF
50 V
18
Figure 17. Typical Differential (2N) PBTL Application With AD Modulation Filters
www.ti.com
GVDD
10 µF
Microcontroller
BKND_ERR
PWM_P_1 PWM_A
VALID
0 Ω
Optional
10 Ω
100 nF
No connect
100 nF
30 kΩ
TAS5508
No connect
GVDD
1 Ω
10 µF
10 Ω
No connect
100 nF
10
11
12
13
14
15
16
17
18
100 nF
1
GVDD_B
2
OTW
3
SD
4
5
RESET_AB
6
PWM_B
7
OC_ADJ
8
GND
9
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
VDD
GVDD_C
TAS5152DKD
GVDD_A
BST_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
BST_D
GVDD_D
100 nF
10 Ω
10 Ω
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
PVDD
100 nF
47 µF
50 V
36
33 nF
35
33 nF
33 nF
100 nF
50 V
100 nF
100 nF
100 nF
50 V
50 V
50 V
34
33
32
31
30
29
28
27
33 nF
26
25
24
23
22
21
20
19
3.3 Ω
10 nF
50 V
10 µH @ 10 A
10 µH @ 10 A
47 µF
50 V
47 µF
50 V
10 µH @ 10 A
10 µH @ 10 A
47 µF
50 V
10 nF
50 V
3.3 Ω
1000 µF
50 V
100 nF
100 V
470 nF
63 V
100 nF
100 V
PVDD
1000 µF
50 V
10 nF
50 V
3.3 Ω
3.3 Ω
10 nF
50 V
Figure 18. Typical Non-Differential (1N) PBTL Application
19
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
www.ti.com
THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5152 needs only a
12-V supply in addition to the (typically) 35-V power-stage
supply. An internal voltage regulator provides suitable
voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating
voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring
only a few external capacitors.
In order to provide outstanding electrical and acoustical
characteristics, the PWM signal path including gate drive
and output stage is designed as identical, independent
half-bridges. For this reason, each half-bridge has
separate gate drive supply (GVDD_X), bootstrap pins
(BST_X), and power-stage supply pins (PVDD_X).
Furthermore, a n additional pin (VDD) is provided as supply
for all common circuits. Although supplied from the same
12-V source, it is highly recommended to separate
GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on
the printed-circuit board (PCB) by RC filters (see
application diagram for details). These RC filters provide
the recommended high-frequency isolation. Special
attention should be paid to placing all decoupling
capacitors as close to their associated pins as possible. In
general, inductance between the power-supply pins and
decoupling capacitors must be avoided. (See reference
board documentation for additional information.)
For a properly functioning bootstrap circuit, a small
ceramic capacitor must be connected from each bootstrap
pin (BST_X) to the power-stage output pin (OUT_X).
When the power−stage output is low, the bootstrap
capacitor is charged through an internal diode connected
between the gate-drive power-supply pin (GVDD_X) and
the bootstrap pin. When the power-stage output is high,
the bootstrap capacitor potential is shifted above the
output potential and thus provides a suitable voltage
supply for the high-side gate driver. In an application with
PWM switching frequencies in the range 352 kHz to 384
kHz, it is recommended to use 33-nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF
capacitors ensure sufficient energy storage, even during
minimal PWM duty cycles, to keep the high-side
power-stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle. In an application running
at a reduced switching frequency, generally 192 kHz, the
bootstrap capacitor might need to be increased in value.
Special attention should be paid to the power-stage power
supply; this includes component selection, PCB
placement and routing. As indicated, each half-bridge has
independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and
system reliability, it is important that each PVDD_X pin is
decoupled with a 100-nF ceramic capacitor placed as
close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5152 reference design.
For additional information on recommended power supply
and required components, see the application diagrams
given previously in this data sheet.
The 12-V supply should be from a low-noise,
low-output-impedance voltage regulator. Likewise, the
35-V power-stage supply is assumed to have low output
impedance and low noise. The power-supply sequence is
not critical as facilitated by the internal power-on-reset
circuit. Moreover, the TAS5152 is fully protected against
erroneous power-stage turnon due to parasitic gate
charging. Thus, voltage-supply ramp rates (dV/dt) are
non-critical within the specified range (see the
Recommended Operating Conditions section of this data
sheet).
SYSTEM POWER-UP/POWER-DOWN
SEQUENCE
Powering Up
The TAS5152 does not require a power-up sequence. The
outputs of the H−bridges remain in a high-impedance state
until the gate-drive supply voltage (GVDD_X) and VDD
voltage are above the undervoltage protection (UVP)
voltage threshold (see the Electrical Characteristics
section of this data sheet). Although not specifically
required, it is recommended to hold RESET_AB and
RESET_CD in a low state while powering up the device.
This allows an internal circuit to charge the external
bootstrap capacitors by enabling a weak pulldown of the
half-bridge output.
When the TAS5152 is being used with TI PWM modulators
such as the TAS5508, no special attention to the state of
RESET_AB and RESET_CD is required, provided that the
chipset is configured as recommended.
Powering Down
The TAS5152 does not require a power-down sequence.
The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage a re
above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics section of this
data sheet). Although not specifically required, it is a good
practice to hold RESET_AB and RESET_CD low during
power down, thus preventing audible artifacts including
pops or clicks.
When the TAS5152 is being used with TI PWM modulators
such as the TAS5508, no special attention to the state of
RESET_AB and RESET_CD is required, provided that the
chipset is configured as recommended.
20
www.ti.com
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
ERROR REPORTING
The SD and OTW pins are both active-low, open-drain
outputs. Their function is for protection-mode signaling to
a PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the
pin going low. Likewise, OTW goes low when the
SD
device junction temperature exceeds 125°C (see the
following table).
SD OTW DESCRIPTION
0 0 Overtemperature (OTE) or overload (OLP) or
undervoltage (UVP)
0 1 Overload (OLP) or undervoltage (UVP)
1 0 Junction temperature higher than 125°C
(overtemperature warning)
1 1 Junction temperature lower than 125°C and no
OLP or UVP faults (normal operation)
Note that asserting either RESET_AB or RESET_CD low
forces the SD signal high, independent of faults being
present. TI recommends monitoring the OTW signal using
the system microcontroller and responding to an
overtemperature warning signal by, e.g., turning down the
volume to prevent further heating of the device resulting in
device shutdown (OTE).
To reduce external component count, an internal pullup
resistor to 3.3 V is provided on both SD and OTW outputs.
Level compliance for 5-V logic can be obtained by adding
external pullup resistors to 5 V (see the Electrical
Characteristics section of this data sheet for further
specifications).
DEVICE PROTECTION SYSTEM
TAS5152 contains advanced protection circuitry carefully
designed to facilitate system integration and ease of use,
as well as to safeguard the device from permanent failure
due to a wide range of fault conditions such as short
circuits, overload, overtemperature, and undervoltage.
The TAS5152 responds to a fault by immediately setting
the power stage in a high-impedance state (Hi-Z) and
asserting the SD pin low. In situations other than overload,
the device automatically recovers when the fault condition
has been removed, i.e., the junction temperature has
dropped or the voltage supply has increased. For highest
possible reliability, recovering from an overload fault
requires external reset of the device (see the Device Reset
section of this data sheet) no sooner than 1 second after
the shutdown.
Use of TAS5152 in High-Modulation-Index
Capable Systems
This device requires at least 50 ns of low time on the output
per 384-kHz PWM frame rate in order to keep the
bootstrap capacitors charged. As an example, if the
modulation index is set to 99.2% in the TAS5508, this
setting allows PWM pulse durations down to 20 ns. This
signal, which does not meet the 50-ns requirement, is sent
to the PWM_x pin and this low-state pulse time does not
allow the bootstrap capacitor to stay charged. In this
situation, the low voltage across the bootstrap capacitor
can cause a failure of the high-side MOSFET transistor,
especially when driving a low-impedance load. The
TAS5152 device requires limiting the TAS5508 modulation
index to 96.1% to keep the bootstrap capacitor charged
under all signals and loads.
Therefore, TI strongly recommends using a TI PWM
processor, such as TAS5508 or TAS5086, with the
modulation index set at 96.1% to interface with TAS5152.
Overcurrent (OC) Protection With Current
Limiting and Overload Detection
The device has independent, fast-reacting current
detectors with programmable trip threshold (OC threshold)
on all high-side and low-side power-stage FETs. See the
following table for OC-adjust resistor values. The detector
outputs are closely monitored by two protection systems.
The first protection system controls the power stage in
order to prevent the output current from further increasing,
i.e., it performs a current-limiting function rather than
prematurely shutting down during combinations of
high-level music transients and extreme speaker load
impedance drops. If the high-current situation persists,
i.e., the power stage is being overloaded, a second
protection system triggers a latching shutdown, resulting
in the power stage being set in the high-impedance (Hi-Z)
state. Current limiting and overload protection are
independent for the half-bridges A and B and, respectively ,
C and D. That is, if the bridge-tied load between
half-bridges A and B causes an overload fault, only
half-bridges A and B are shut down.
D For the lowest-cost bill of materials in terms
of component selection, the OC threshold
measure should be limited, considering the
power output requirement and minimum
load impedance. Higher-impedance loads
require a lower OC threshold.
D The demodulation-filter inductor must retain
at least 3 µH of inductance at twice the OC
threshold setting.
21
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
www.ti.com
Unfortunately, most inductors have decreasing inductance
with increasing temperature and increasing current
(saturation). To some degree, an increase in temperature
naturally occurs when operating at high output currents,
due to core losses and the DC resistance of the inductor’s
copper winding. A thorough analysis of inductor saturation
and thermal properties is strongly recommended.
Setting the OC threshold too low might cause issues such
as lack of enough output power and/or unexpected
shutdowns due to too-sensitive overload detection.
In general, it is recommended to follow closely the external
component selection and PCB layout as given in the
Application section.
For added flexibility, the OC threshold is programmable
within a limited range using a single external resistor
connected between the OC_ADJ pin and AGND. (See t h e
Electrical Characteristics section of this data sheet for
information on the correlation between programmingresistor value and the OC threshold.) It should be noted
that a properly functioning overcurrent detector assumes
the presence of a properly designed demodulation filter at
the power-stage output. Short-circuit protection is not
provided directly at the output pins of the power stage but
only on the speaker terminals (after the demodulation
filter). It is required to follow certain guidelines when
selecting the OC threshold and an appropriate
demodulation inductor:
OC-Adjust Resistor Values
(kW)
15 10.8
22 9.4
27 8.6
39 6.4
47 6
69 4.7
Max. Current Before OC
Occurs (A)
Overtemperature Protection
The TAS5152 has a two-level temperature-protection
system that asserts an active-low warning signal (OTW)
when the device junction temperature exceeds 125°C
(nominal) and, if the device junction temperature exceeds
155°C (nominal), the device is put into thermal shutdown,
resulting in all half-bridge outputs being set in the
high-impedance state (Hi-Z) and SD being asserted low.
OTE is latched in this case. To clear the OTE latch, both
RESET_AB and RESET_CD must be asserted.
Thereafter, the device resumes normal operation.
Undervoltage Protection (UVP) and Power-On
Reset (POR)
The UVP and POR circuits of the TAS5152 fully protect the
device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload
circuit (OLP) and ensures that all circuits are fully
operational when the GVDD_X and VDD supply voltages
reach 9.8 V (typical). Although GVDD_X and VDD are
independently monitored, a supply voltage drop below the
UVP threshold on any VDD or GVDD_X pin results in all
half-bridge outputs immediately being set in the
high-impedance state (Hi-Z) and SD being asserted low.
The device automatically resumes operation when all
supply voltages have increased above the UVP threshold.
DEVICE RESET
Two reset pins are provided for independent control of
half-bridges A/B and C/D. When RESET_AB is asserted
low, all four power-stage FETs in half-bridges A and B are
forced into a high-impedance state (Hi-Z). Likewise,
asserting RESET_CD low forces all four power-stage
FET s in half-bridges C and D into a high-impedance state.
Thus, both reset pins are well suited for hard-muting the
power stage if needed.
In BTL modes, to accommodate bootstrap charging prior
to switching start, asserting the reset inputs low enables
weak pulldown of the half-bridge outputs. In the SE mode,
the weak pulldowns are not enabled, and it is therefore
recommended to ensure bootstrap capacitor charging by
providing a low pulse on the PWM inputs when reset is
asserted high.
Asserting either reset input low removes any fault
information to be signalled on the SD output, i.e., SD is
forced high.
A rising-edge transition on either reset input allows the
device to resume operation after an overload fault.
22
www.ti.com
SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
MECHANICAL DATA
23
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
TAS5152DKD ACTIVE SSOP DKD 36 29 Green (RoHS &
no Sb/Br)
TAS5152DKDG4 ACTIVE SSOP DKD 36 29 Green (RoHS &
no Sb/Br)
TAS5152DKDR ACTIVE SSOP DKD 36 500 Green (RoHS &
no Sb/Br)
TAS5152DKDRG4 ACTIVE SSOP DKD 36 500 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-4-260C-72 HR
CU NIPDAU Level-4-260C-72 HR
CU NIPDAU Level-4-260C-72 HR
CU NIPDAU Level-4-260C-72 HR
(3)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device Package Pins Site Reel
Diameter
(mm)
TAS5152DKDR DKD 36 TAI 330 24 14.7 16.4 4.0 20 24 NONE
Reel
Width
(mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
23-May-2007
Pin1
Quadrant
TAPE AND REEL BOX INFORMATION
Device Package Pins Site Length (mm) Width (mm) Height (mm)
TAS5152DKDR DKD 36 TAI 0.0 0.0 0.0
Pack Materials-Page 2
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