TEXAS INSTRUMENTS TAS5142 Technical data

TAS5142

TM

TAS5142

www.ti.com	SLES126B –DECEMBER 2004 –REVISED MAY 2005

STEREO DIGITAL AMPLIFIER POWER STAGE

FEATURES

∙2×100 W at 10% THD+N Into 4-Ω BTL (1)

∙2×80 W at 10% THD+N Into 6-Ω BTL

∙2×65 W at 10% THD+N Into 8-Ω BTL

∙4×40 W at 10% THD+N Into 3-Ω SE

∙4×30 W at 10% THD+N Into 4-Ω SE

∙1×160 W at 10% THD+N Into 3-Ω PBTL

∙1×200 W at 10% THD+N Into 2-Ω PBTL (1)

∙>100 dB SNR (A-Weighted)

∙<0.1% THD+N at 1 W

∙Two Thermally Enhanced Package Options:

–DKD (36-pin PSOP3)

–DDV (44-pin HTSSOP)

∙High-Efficiency Power Stage (>90%) With 140-mΩ Output MOSFETs

∙Power-On Reset for Protection on Power Up Without Any Power-Supply Sequencing

∙Integrated Self-Protection Circuits Including Undervoltage, Overtemperature, Overload, Short Circuit

∙Error Reporting

∙EMI Compliant When Used With Recommended System Design

∙Intelligent Gate Drive

APPLICATIONS

∙Mini/Micro Audio System

∙DVD Receiver

∙Home Theater

DESCRIPTION

The TAS5142 is a third-generation, high-perform- ance, integrated stereo digital amplifier power stage with an improved protection system. The TAS5142 is capable of driving a 4-Ω bridge-tied load (BTL) at up to 100 W per channel with low integrated noise at the output, low THD+N performance, and low idle power dissipation.

A low-cost, high-fidelity audio system can be built using a TI chipset, comprising a modulator (e.g., TAS5508) and the TAS5142. This system only requires a simple passive LC demodulation filter to

deliver high-quality, high-efficiency audio amplification with proven EMI compliance. This device requires two power supplies, at 12 V for GVDD and VDD, and at 32 V for PVDD. The TAS5142 does not require power-up sequencing due to internal power-on reset. The efficiency of this digital amplifier is greater than 90% into 6 Ω, which enables the use of smaller power supplies and heatsinks.

The TAS5142 has an innovative protection system integrated on-chip, safeguarding the device against a wide range of fault conditions that could damage the system. These safeguards are short-circuit protection, overcurrent protection, undervoltage protection, and overtemperature protection. The TAS5142 has a new proprietary current-limiting circuit that reduces the possibility of device shutdown during high-level music transients. A new programmable overcurrent detector allows the use of lower-cost inductors in the demodulation output filter.

BTL OUTPUT POWER vs SUPPLY VOLTAGE

	120
	110	TC = 75°C
		THD+N @ 10%
	100
− W	90					4	Ω
	80
Power	70
	60
− Output					6	Ω
	50
	40
O
P	30
	20							8 Ω
	10
	0
	0	4	8	12	16	20	24	28	32
			PVDD − Supply Voltage − V

G002

(1) It is not recommended to drive 200 W (total power) into the DDV package continuously. For multichannel systems that require two channels to be driven at full power with the DDV package option, it is recommended to design the system so that the two channels are in two separate devices.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PurePath Digital, PowerPad are trademarks of Texas Instruments. All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.	Copyright © 2004–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

TAS5142

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SLES126B –DECEMBER 2004 –REVISED MAY 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

GENERAL INFORMATION

Terminal Assignment

The TAS5142 is available in two thermally enhanced packages:

∙36-pin PSOP3 package (DKD)

∙44-pin HTSSOP PowerPad™ package (DDV)

Both package types contain a heat slug that is located on the top side of the device for convenient thermal coupling to the heatsink.

							DKD PACKAGE															DDV PACKAGE
							(TOP VIEW)																(TOP VIEW)
														GVDD_B															GVDD_A
GVDD_B						1				36			GVDD_A							1		44
														OTW						2				43					BST_A
	OTW					2				35			BST_A
															NC					3					42				NC
		SD				3				34			PVDD_A
															NC					4					41				PVDD_A
PWM_A						4				33			OUT_A
																SD				5					40				PVDD_A
RESET_AB						5				32			GND_A
														PWM_A						6					39				OUT_A
PWM_B						6				31			GND_B
														RESET_AB						7					38				GND_A
OC_ADJ						7				30			OUT_B
	GND					8				29			PVDD_B	PWM_B						8					37				GND_B
AGND						9				28			BST_B	OC_ADJ						9					36				OUT_B
VREG						10				27			BST_C		GND					10					35				PVDD_B
		M3				11				26			PVDD_C	AGND						11					34				BST_B
		M2				12				25			OUT_C	VREG						12					33				BST_C
		M1				13				24			GND_C			M3				13					32				PVDD_C
PWM_C						14				23			GND_D			M2				14					31				OUT_C
																M1				15					30				GND_C
RESET_CD						15				22			OUT_D
														PWM_C						16					29				GND_D
PWM_D						16				21			PVDD_D
																													OUT_D
														RESET_CD						17					28
	VDD					17				20			BST_D
GVDD_C						18				19			GVDD_D	PWM_D						18					27				PVDD_D
															NC					19					26				PVDD_D
													P0018-01		NC					20					25				NC
															VDD					21		24							BST_D
														GVDD_C						22		23							GVDD_D

P0016-02

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TAS5142

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SLES126B –DECEMBER 2004 –REVISED MAY 2005

GENERAL INFORMATION (continued)

MODE Selection Pins for Both Packages

		MODE PINS		PWM INPUT	OUTPUT CONFIGURATION	PROTECTION SCHEME
	M3	M2	M1
	0	0	0	2N (1) AD/BD modulation	2 channels BTL output	BTL mode (2)
	0	0	1	Reserved
	0	1	0	1N (1) AD modulation	2 channels BTL output	BTL mode (2)
	0	1	1	1N (1) AD modulation	1 channel PBTL output	PBTL mode. Only PWM_A input is used.
						Protection works similarly to BTL mode (2). Only
	1	0	0	1N (1) AD modulation	4 channels SE output	difference in SE mode is that OUT_X is Hi-Z
						instead of a pulldown through internal pulldown
						resistor.
	1	0	1
	1	1	0	Reserved
	1	1	1

(1)The 1N and 2N naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specific mode.

(2)An overload protection (OLP) occurring on A or B causes both channels to shut down. An OLP on C or D works similarly. Global errors like overtemperature error (OTE), undervoltage protection (UVP), and power-on reset (POR) affect all channels.

Package Heat Dissipation Ratings(1)

PARAMETER	TAS5142DKD	TAS5142DDV
RθJC (°C/W)—2 BTL or 4 SE channels (8 transistors)	1.28	1.28
RθJC (°C/W)—1 BTL or 2 SE channel(s) (4 transistors)	2.56	2.56
RθJC (°C/W)—(1 transistor)	8.6	8.6
Pad area(2)	80 mm2	36 mm2

(1)JC is junction-to-case, CH is case-to-heatsink.

(2)RθCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The RθCH with this condition is 0.8°C/W for the DKD package and 1.8°C/W for the DDV package.

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TAS5142

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SLES126B –DECEMBER 2004 –REVISED MAY 2005

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted (1)

	TAS5142
VDD to AGND	–0.3 V to 13.2 V
GVDD_X to AGND	–0.3 V to 13.2 V
PVDD_X to GND_X (2)	–0.3 V to 50 V
OUT_X to GND_X (2)	–0.3 V to 50 V
BST_X to GND_X (2)	–0.3 V to 63.2 V
VREG to AGND	–0.3 V to 4.2 V
GND_X to GND	–0.3 V to 0.3 V
GND_X to AGND	–0.3 V to 0.3 V
GND to AGND	–0.3 V to 0.3 V
PWM_X, OC_ADJ, M1, M2, M3 to AGND	–0.3 V to 4.2 V
RESET_X, SD, OTW to AGND	–0.3 V to 7 V
Maximum continuous sink current (SD, OTW)	9 mA
Maximum operating junction temperature range, TJ	0°C to 125°C
Storage temperature	–40°C to 125°C
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds	260°C
Minimum pulse duration, low	50 ns

(1)Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.

ORDERING INFORMATION

TA	PACKAGE	DESCRIPTION
0°C to 70°C	TAS5146DKD	36-pin PSOP3
0°C to 70°C	TAS5142DDV	44-pin HTSSOP

For the most current specification and package information, see the TI Web site at www.ti.com.

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TAS5142

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					SLES126B –DECEMBER 2004 –REVISED MAY 2005
	Terminal Functions
		TERMINAL		FUNCTION (1)	DESCRIPTION
	NAME	DKD NO.	DDV NO.
	AGND	9	11	P	Analog ground
	BST_A	35	43	P	HS bootstrap supply (BST), external capacitor to OUT_A required
	BST_B	28	34	P	HS bootstrap supply (BST), external capacitor to OUT_B required
	BST_C	27	33	P	HS bootstrap supply (BST), external capacitor to OUT_C required
	BST_D	20	24	P	HS bootstrap supply (BST), external capacitor to OUT_D required
	GND	8	10	P	Ground
	GND_A	32	38	P	Power ground for half-bridge A
	GND_B	31	37	P	Power ground for half-bridge B
	GND_C	24	30	P	Power ground for half-bridge C
	GND_D	23	29	P	Power ground for half-bridge D
	GVDD_A	36	44	P	Gate-drive voltage supply requires 0.1-μF capacitor to AGND
	GVDD_B	1	1	P	Gate-drive voltage supply requires 0.1-μF capacitor to AGND
	GVDD_C	18	22	P	Gate-drive voltage supply requires 0.1-μF capacitor to AGND
	GVDD_D	19	23	P	Gate-drive voltage supply requires 0.1-μF capacitor to AGND
	M1	13	15	I	Mode selection pin
	M2	12	14	I	Mode selection pin
	M3	11	13	I	Mode selection pin
	NC	–	3, 4, 19, 20, 25,	–	No connect. Pins may be grounded.
			42
	OC_ADJ	7	9	O	Analog overcurrent programming pin requires resistor to ground
	OTW	2	2	O	Overtemperature warning signal, open-drain, active-low
	OUT_A	33	39	O	Output, half-bridge A
	OUT_B	30	36	O	Output, half-bridge B
	OUT_C	25	31	O	Output, half-bridge C
	OUT_D	22	28	O	Output, half-bridge D
	PVDD_A	34	40, 41	P	Power supply input for half-bridge A requires close decoupling of
					0.1-μF capacitor to GND_A.
	PVDD_B	29	35	P	Power supply input for half-bridge B requires close decoupling of
					0.1-μF capacitor to GND_B.
	PVDD_C	26	32	P	Power supply input for half-bridge C requires close decoupling of
					0.1-μF capacitor to GND_C.
	PVDD_D	21	26, 27	P	Power supply input for half-bridge D requires close decoupling of
					0.1-μF capacitor to GND_D.
	PWM_A	4	6	I	Input signal for half-bridge A
	PWM_B	6	8	I	Input signal for half-bridge B
	PWM_C	14	16	I	Input signal for half-bridge C
	PWM_D	16	18	I	Input signal for half-bridge D
	RESET_AB	5	7	I	Reset signal for half-bridge A and half-bridge B, active-low
	RESET_CD	15	17	I	Reset signal for half-bridge C and half-bridge D, active-low
	SD	3	5	O	Shutdown signal, open-drain, active-low
	VDD	17	21	P	Power supply for digital voltage regulator requires 0.1-μF capacitor
					to GND.
	VREG	10	12	P	Digital regulator supply filter pin requires 0.1-μF capacitor to AGND.

(1)I = input, O = output, P = power

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TAS5142

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SLES126B –DECEMBER 2004 –REVISED MAY 2005

SYSTEM BLOCK DIAGRAM

OTW

System

Microcontroller

SD

TAS5508

SD

OTW

BST_A

Bootstrap

BST_B

Capacitors

VALID

RESET_AB

RESET_CD

PWM_A

OUT_A

Left-

Output

2nd-Order L-C

Input

Output Filter

Channel

H-Bridge 1

H-Bridge 1

OUT_B

for Each

Output

PWM_B

Half-Bridge

					2-Channel
					H-Bridge
					BTL Mode
	PWM_C							OUT_C	2nd-Order L-C
Right-							Output
									Output Filter
Channel				Input		H-Bridge 2		OUT_D	for Each
Output				H-Bridge 2					Half-Bridge
	PWM_D
		M1	B,A,PVDDC, D	C,B,A,GNDD	B,A,GVDDC, D GND VDD VREG	AGND	ADJOC
	Hardwire							BST_C
		M2							Bootstrap
	Mode
	Control	M3						BST_D	Capacitors
			4	4	4
			PVDD		GVDD
32 V	PVDD		Power		VDD		Hardwire
			Supply		VREG
System							OC Limit
			Decoupling		Power Supply
Power					Decoupling
Supply
GND	GND
12 V	GVDD (12 V)/VDD (12 V)
VAC

B0047-01

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TAS5142

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SLES126B –DECEMBER 2004 –REVISED MAY 2005

FUNCTIONAL BLOCK DIAGRAM

OTW

SD

M1

M2

M3

RESET_AB

RESET_CD

PWM_D

PWM_C

PWM_B

PWM_A

					VDD
			Under-	4
			voltage
Internal Pullup			Protection	VREG	VREG
Resistors to VREG
			Power
			On
	Protection		Reset		AGND
	and
	I/O Logic
			Temp.
			Sense		GND
			Overload	Isense	OC_ADJ
			Protection
					GVDD_D
					BST_D
					PVDD_D
PWM	Ctrl.	Timing	Gate		OUT_D
Rcv.			Drive
					BTL/PBTL−Configuration
					Pulldown Resistor
					GND_D
					GVDD_C
					BST_C
					PVDD_C
PWM	Ctrl.	Timing	Gate		OUT_C
Rcv.			Drive
					BTL/PBTL−Configuration
					Pulldown Resistor
					GND_C
					GVDD_B
					BST_B
					PVDD_B
PWM	Ctrl.	Timing	Gate		OUT_B
Rcv.			Drive
					BTL/PBTL−Configuration
					Pulldown Resistor
					GND_B
					GVDD_A
					BST_A
					PVDD_A
PWM	Ctrl.	Timing	Gate		OUT_A
Rcv.			Drive
					BTL/PBTL−Configuration
					Pulldown Resistor
					GND_A

B0034-02

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TAS5142

SLES126B –DECEMBER 2004 –REVISED MAY 2005

RECOMMENDED OPERATING CONDITIONS

	PVDD_X	Half-bridge supply
	GVDD_X	Supply for logic regulators and gate-drive
		circuitry
	VDD	Digital regulator input
	RL (BTL)
	RL (SE)	Load impedance
	RL (PBTL)
	LOutput (BTL)
	LOutput (SE)	Output-filter inductance
	LOutput (PBTL)
	FPWM	PWM frame rate
	TJ	Junction temperature

DC supply voltage

DC supply voltage

DC supply voltage

Output filter: L = 10 μH, C = 470 nF. Output AD modulation, switching fre-

quency > 350 kHz

Minimum output inductance under short-circuit condition

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MIN	TYP	MAX	UNIT
0	32	34	V
10.8	12	13.2	V
10.8	12	13.2	V
3	4
2	3		Ω

1.52

5	10
5	10		μH
5	10
192	384	432	kHz
0		125	°C

AUDIO SPECIFICATIONS (BTL)

PVDD_X = 32 V, GVDD = VDD = 12 V, BTL mode, RL = 4 Ω, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature = 75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5508 PWM processor

with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified.

	PARAMETER	TEST CONDITIONS	TAS5142	UNIT
			TYP
		MIN		MAX
		RL = 4 Ω, 10% THD, clipped input	100
		signal
		RL = 6 Ω, 10% THD, clipped input	80
		signal
		RL = 8 Ω, 10% THD, clipped input	65	W
PO	Power output per channel, DKD package	signal
		RL = 4 Ω, 0 dBFS, unclipped input
			80
		signal
		RL = 6 Ω, 0 dBFS, unclipped input	60
		signal
		RL = 8 Ω, 0 dBFS, unclipped input	50
		signal
THD+N	Total harmonic distortion + noise	0 dBFS	0.3%
		1 W	0.1%
Vn	Output integrated noise	A-weighted	140	μV
SNR	Signal-to-noise ratio (1)	A-weighted	102	dB
		A-weighted, input level = –60 dBFS	102
		using TAS5508 modulator
DNR	Dynamic range			dB
		A-weighted, input level = –60 dBFS
			110
		using TAS5518 modulator
P	Power dissipation due to idle losses (IPVDD_X)	P = 0 W, 4 channels switching(2)	2	W
idle		O

(1)SNR is calculated relative to 0-dBFS input level.

(2)Actual system idle losses are affected by core losses of output inductors.

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