TEXAS INSTRUMENTS TAS5122 Technical data

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

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FEATURES

D 2 × 30 W (BTL) Into 6 Ω at 1 kHz
D 95-dB Dynamic Range (in System With

TAS5026)

D < 0.2% THD+N (in System – 30 W RMS Into

6-Ω Resistive Load)

D Device Power Efficiency Typical >90% Into

6-Ω Load

D Self-Protection Design (Including

Undervoltage, Overtemperature, and Short
Conditions) With Error Reports

D Internal Gate Drive Supply Voltage Regulator
D EMI Compliant When Used With

Recommended System Design

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SLES088D – AUGUST 2003 – REVISED MAY 2004

TM

APPLICATIONS

D DVD Receiver
D Home Theatre
D Mini/Micro Component Systems
D Internet Music Appliance

DESCRIPTION

The TAS5122 is a high-performance, integrated stereo
digital amplifier power stage designed to drive 6-Ω
speakers at up to 30 W per channel. The device
incorporates TI’s PurePath Digitalt technology and is
used with a digital audio PWM processor (TAS50XX) and
a simple passive demodulation filter to deliver high-quality,
high-efficiency, true-digital audio amplification.

The efficiency of this digital amplifier is typically greater
than 90%. Overcurrent protection, overtemperature
protection, and undervoltage protection are built into the
TAS5122, safeguarding the device and speakers against
fault conditions that could damage the system.

1

0.1

THD+N − Total Harmonic Distortion + Noise − %

0.01
40m 100m 10 40

THD + NOISE vs OUTPUT POWER

RL = 6 Ω
TC = 75°C

THD+N − Total Harmonic Distortion + Noise − %

1

PO − Output Power − W

semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

0.1

0.01
20 100 1k 10k

THD + NOISE vs FREQUENCY

RL = 6 Ω
TC = 75°C

PO = 30 W

PO = 10 W

PO = 1 W

f − Frequency − Hz

20k

PurePath Digital and PowerPAD are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.

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Copyright  2004, Texas Instruments Incorporated

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D

R

A
A

B
B

C
C

D
D

DCA PACKAGE

SLES088D – AUGUST 2003 – REVISED MAY 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.

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GENERAL INFORMATION

Terminal Assignment

The TAS5122 is offered in a thermally enhanced 56-pin
DCA package (thermal pad is on the bottom). Output of the
DCA package is highly dependent on thermal design. See
the Thermal Information section. Therefore, it is important
to design the heatsink carefully.

(TOP VIEW)

GND
GVDD
BST_A
PVDD_
PVDD_
OUT_A
OUT_A
GND
GND
OUT_B
OUT_B
PVDD_
PVDD_
BST_B
BST_C
PVDD_
PVDD_
OUT_C
OUT_C
GND
GND
OUT_D
OUT_D
PVDD_
PVDD_
BST_D
GVDD
GND

GND
GND

GREG

DVDD

GND

DGND

GND

PWM_AP

PWM_AM

RESET_AB

PWM_BM

PWM_BP

DREG

M1
M2
M3

REG_RTN

PWM_CP

PWM_CM

ESET_CD

PWM_DM

PWM_DP

SD_AB

SD_CD

OTW

GREG

GND
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

TAS5122 UNITS

DVDD to DGND –0.3 V to 4.2 V
GVDD to GND 28 V
PVDD_X to GND (dc voltage) 28 V
OUT_X to GND (dc voltage) 28 V
BST_X to GND (dc voltage) 40 V
GREG to GND
PWM_XP, RESET, M1, M2, M3, SD,

OTW
Maximum operating junction

temperature, T
Storage temperature –40°C to 125°C

(1)

Stresses beyond those listed under “absolute maximum ratings”
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute­maximum-rated conditions for extended periods may affect device
reliability.

(2)

GREG is treated as an input when the GREG pin is overdriven by
GVDD of 12 V .

(2)

–0.3 V to DVDD + 0.3 V

J

14.2 V

–40°C to 150°C

ORDERING INFORMATION

T

A

0°C to 70°C TAS5122DCA 56-pin small TSSOP

PACKAGE DESCRIPTION

PACKAGE DISSIPATION RATINGS

R

PACKAGE

56-pin DCA TSSOP 1.14 See Note 1

(1)

The TAS5122 package is thermally enhanced for conductive
cooling using an exposed metal pad area. It is impractical to use the
device with the pad exposed to ambient air as the only heat sinking
of the device.

For this reason, R
thermal treatment provided in the application. An example and
discussion of typical system R
Thermal Information section. This example provides additional
information regarding the power dissipation ratings. This example
should be used as a reference to calculate the heat dissipation
ratings for a specific application. TI application engineering
provides technical support to design heatsinks if needed.

a system parameter that characterizes the

θJA

θJC

(°C/W)

values are provided in the

θJA

R

θJA

(°C/W)

(1)

2

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FUNCTION

(1)

DESCRIPTION

TERMINAL

NAME NO.

BST_A
BST_B
BST_C
BST_D
DGND
DREG
DREG_RTN
DVDD
GND

GREG
GVDD
M1
M2
M3
OTW
OUT_A
OUT_B
OUT_C
OUT_D
PVDD_A
PVDD_B
PVDD_C
PVDD_D
PWM_AM
PWM_AP
PWM_BM
PWM_BP
PWM_CM
PWM_CP
PWM_DM
PWM_DP
RESET_AB
RESET_CD
SD_AB
SD_CD

(1)

I = input, O = output, P = power

54 P
43 P
42 P
31 P

6 P
13 P
17 P

4 P

1, 2, 5,

7, 27, 28,

29, 36, 37,

48, 49, 56

3, 26 P

30, 55 P

14 I
15 I
16 I
25 O

50, 51 O
46, 47 O
38, 39 O
34, 35 O
52, 53 P
44, 45 P
40, 41 P
32, 33 P

9 I

8 I
11 I
12 I
19 I
18 I
21 I
22 I
10 I
20 I
23 O
24 O

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SLES088D – AUGUST 2003 – REVISED MAY 2004

Terminal Functions

HS bootstrap supply (BST), external capacitor to OUT_A required
HS bootstrap supply (BST), external capacitor to OUT_B required
HS bootstrap supply (BST), external capacitor to OUT_C required
HS bootstrap supply (BST), external capacitor to OUT_D required
Digital I/O reference ground
Digital supply voltage regulator decoupling pin, capacitor connected to GND
Digital supply voltage regulator decoupling return pin
I/O reference supply input (3.3 V)

P

Power ground (I/O reference ground – pin 22)

Gate drive voltage regulator decoupling pin, capacitor to GND
Voltage supply to on−chip gate drive and digital supply voltage regulators
Mode selection pin
Mode selection pin
Mode selection pin
Overtemperature warning output, open drain with internal pullup
Output, half-bridge A
Output, half-bridge B
Output, half-bridge C
Output, half-bridge D
Power supply input for half-bridge A
Power supply input for half-bridge B
Power supply input for half-bridge C
Power supply input for half-bridge D
Input signal (negative), half-bridge A
Input signal (positive), half-bridge A
Input signal (negative), half-bridge B
Input signal (positive), half-bridge B
Input signal (negative), half-bridge C
Input signal (positive), half-bridge C
Input signal (negative), half-bridge D
Input signal (positive), half-bridge D
Reset signal, active low
Reset signal, active low
Shutdown signal for half-bridges A and B
Shutdown signal for half-bridges C and D

3

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SLES088D – AUGUST 2003 – REVISED MAY 2004

FUNCTIONAL BLOCK DIAGRAM

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GREG

Gate

PWM_AP OUT_A

RESET

PWM_BP OUT_B

OTW

SD

PWM

Receiver

PWM

Receiver

To

Protection

Blocks

OT

Protection

UVP

Protection A

Protection B

Timing

Control

GREG

Timing

Control

GREG

DREG

Drive

Gate

Drive

Gate

Drive

Gate

Drive

GREG

DREG_RTN

BST_A

PVDD_A

GND

BST_B

PVDD_B

GND

DREG

GVDD

GREG

DREG_RTN

GREG

Gate

PWM_CP OUT_C

RESET

PWM_DP OUT_D

4

PWM

Receiver

Protection C

Protection D

PWM

Receiver

Timing

Control

GREG

Timing

Control

Drive

Gate

Drive

Gate

Drive

Gate

Drive

BST_C

PVDD_C

GND

BST_D

PVDD_D

GND

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POOutput power

SLES088D – AUGUST 2003 – REVISED MAY 2004



RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT

DVDD Digital supply
GVDD
PVDD_x Half-bridge supply Relative to GND, RL= 6 Ω to 8 Ω 0 23 25.5 V

T

J

(1)

It is recommended for DVDD to be connected to DREG via a 100-Ω resistor.

Supply for internal gate drive and logic
regulators

Junction temperature 0 125 _C

(1)

Relative to DGND 3 3.3 3.6 V
Relative to GND 16 23 25.5 V

ELECTRICAL CHARACTERISTICS

PVDD_X = 23 V, GVDD = 23 V, DVDD = 3.3 V, DVDD connected to DREG via a 100-Ω resistor, RL = 6 Ω, 8X fs = 384 kHz, unless otherwise
noted. AC performance is recorded as a chipset with TAS5010 as the PWM processor and TAS5122 as the power stage.

SYMBOL PARAMETER TEST CONDITIONS

AC PERFORMANCE, BTL MODE, 1 kHz

RL = 8 Ω, unclipped,
AES17 filter

RL = 8 Ω, THD = 10%,
AES17 filter

RL = 6 Ω, THD = 0.4%,
AES17 filter

RL = 6 Ω, THD = 10%,
AES17 filter

Po = 1 W/ channel, RL = 6 Ω,
AES17 filter

THD+N Total harmonic distortion + noise

V

n

SNR Signal-to-noise ratio

DR Dynamic range

INTERNAL VOLTAGE REGULATOR

DREG Voltage regulator

GREG Voltage regulator

IVGDD GVDD supply current, operating
IDVDD DVDD supply current, operating fS = 384 kHz, no load 1 5 mA Max

OUTPUT STAGE MOSFETs

R

DSon,LS

R

DSon ,HS

Output RMS noise

Forward on-resistance, LS TJ = 25°C 155 mΩ Max
Forward on-resistance, HS TJ = 25°C 155 mΩ Max

Po = 10 W/channel, RL = 6 Ω,
AES17 filter

Po = 30 W/channel, RL = 6 Ω,
AES17 filter

A-weighted, mute, RL = 6 Ω,
20 Hz to 20 kHz, AES17 filter

f = 1 kHz, A-weighted,
RL = 6 Ω,, AES17 filter

f = 1 kHz, A-weighted,
RL = 6 Ω,, AES17 filter

Io = 1 mA,
PVDD = 18 V−30.5 V

Io = 1.2 mA,
PVDD = 18 V−30.5 V

fS = 384 kHz, no load, 50%
duty cycle

TYPICAL

TA=25°C

3.1 V Typ

13.4 V Typ

TA=25°C

T

=

Case

75°C

0.05% Typ

0.05% Typ

0.2% Typ

240 µV Max

24 mA Max

UNITS

24 W Typ

29 W Typ

30 W Typ

37 W Typ

95 dB Typ

95 dB Typ

MIN/TYP/

MAX

5



V

Undervoltage protection limit, GVDD

7.4

VIHHigh-level input voltage

Leakage

Input leakage current

SLES088D – AUGUST 2003 – REVISED MAY 2004

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ELECTRICAL CHARACTERISTICS

PVDD_x = 23 V, GVDD = 23 V, DVDD = 3.3 V, RL = 6 Ω, 8X fs = 384 kHz, unless otherwise noted

SYMBOL

INPUT/OUTPUT PROTECTION

uvp,G

OTW Overtemperature warning 125 °C Typ
OTE Overtemperature error 150 °C Typ
OC Overcurrent protection 5.0 A Min

STATIC DIGITAL SPECIFICATION

PWM_AP, PWM_BP, M1, M2, M3, SD,
OTW

V

IL

OTW/SHUTDOWN (SD)

V

OL

Low-level input voltage 0.8 V Max

Internally pullup R from OTW/SD to
DVDD

Low level output voltage IO = 4 mA 0.4 V Max

PARAMETER TEST CONDITIONS

TYPICAL

TA=25°C

30 22.5 kΩ Min

TA=25°C

6.9 V Min

7.9 V Max

DVDD V Max

−10 µA Min

T

=

Case

75°C

2 V Min

10 µA Max

UNITS

MIN/TYP/

MAX

6