TEXAS INSTRUMENTS TAS5122 Technical data

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

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FEATURES

D 2 × 30 W (BTL) Into 6 Ω at 1 kHz D 95-dB Dynamic Range (in System With

TAS5026)

D < 0.2% THD+N (in System – 30 W RMS Into

6-Ω Resistive Load)

D Device Power Efficiency Typical >90% Into

6-Ω Load

D Self-Protection Design (Including

Undervoltage, Overtemperature, and Short Conditions) With Error Reports

D Internal Gate Drive Supply Voltage Regulator D EMI Compliant When Used With

Recommended System Design

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SLES088D – AUGUST 2003 – REVISED MAY 2004

APPLICATIONS

D DVD Receiver D Home Theatre D Mini/Micro Component Systems D Internet Music Appliance

DESCRIPTION

The TAS5122 is a high-performance, integrated stereo digital amplifier power stage designed to drive 6-Ω speakers at up to 30 W per channel. The device incorporates TI’s PurePath Digitalt technology and is used with a digital audio PWM processor (TAS50XX) and a simple passive demodulation filter to deliver high-quality, high-efficiency, true-digital audio amplification.

The efficiency of this digital amplifier is typically greater than 90%. Overcurrent protection, overtemperature protection, and undervoltage protection are built into the TAS5122, safeguarding the device and speakers against fault conditions that could damage the system.

0.1

THD+N − Total Harmonic Distortion + Noise − %

0.01 40m 100m 10 40

THD + NOISE vs OUTPUT POWER

RL = 6 Ω TC = 75°C

THD+N − Total Harmonic Distortion + Noise − %

PO − Output Power − W

semiconductor products and disclaimers thereto appears at the end of this data sheet.

0.1

0.01 20 100 1k 10k

THD + NOISE vs FREQUENCY

RL = 6 Ω TC = 75°C

PO = 30 W

PO = 10 W

PO = 1 W

f − Frequency − Hz

20k

PurePath Digital and PowerPAD are trademarks of Texas Instruments. Other trademarks are the property of their respective owners.

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A A

B B

C C

D D

DCA PACKAGE

SLES088D – AUGUST 2003 – REVISED MAY 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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GENERAL INFORMATION

Terminal Assignment

The TAS5122 is offered in a thermally enhanced 56-pin DCA package (thermal pad is on the bottom). Output of the DCA package is highly dependent on thermal design. See the Thermal Information section. Therefore, it is important to design the heatsink carefully.

(TOP VIEW)

GND GVDD BST_A PVDD_ PVDD_ OUT_A OUT_A GND GND OUT_B OUT_B PVDD_ PVDD_ BST_B BST_C PVDD_ PVDD_ OUT_C OUT_C GND GND OUT_D OUT_D PVDD_ PVDD_ BST_D GVDD GND

GND GND

GREG

DVDD

GND

DGND

GND

PWM_AP

PWM_AM

RESET_AB

PWM_BM

PWM_BP

DREG

M1 M2 M3

REG_RTN

PWM_CP

PWM_CM

ESET_CD

PWM_DM

PWM_DP

SD_AB

SD_CD

OTW

GREG

GND GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

TAS5122 UNITS

DVDD to DGND –0.3 V to 4.2 V GVDD to GND 28 V PVDD_X to GND (dc voltage) 28 V OUT_X to GND (dc voltage) 28 V BST_X to GND (dc voltage) 40 V GREG to GND PWM_XP, RESET, M1, M2, M3, SD,

OTW Maximum operating junction

temperature, T Storage temperature –40°C to 125°C

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.

(2)

GREG is treated as an input when the GREG pin is overdriven by GVDD of 12 V .

(2)

–0.3 V to DVDD + 0.3 V

14.2 V

–40°C to 150°C

ORDERING INFORMATION

0°C to 70°C TAS5122DCA 56-pin small TSSOP

PACKAGE DESCRIPTION

PACKAGE DISSIPATION RATINGS

PACKAGE

56-pin DCA TSSOP 1.14 See Note 1

(1)

The TAS5122 package is thermally enhanced for conductive cooling using an exposed metal pad area. It is impractical to use the device with the pad exposed to ambient air as the only heat sinking of the device.

For this reason, R thermal treatment provided in the application. An example and discussion of typical system R Thermal Information section. This example provides additional information regarding the power dissipation ratings. This example should be used as a reference to calculate the heat dissipation ratings for a specific application. TI application engineering provides technical support to design heatsinks if needed.

a system parameter that characterizes the

θJA

θJC

(°C/W)

values are provided in the

θJA

(°C/W)

(1)

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FUNCTION

(1)

DESCRIPTION

TERMINAL

NAME NO.

BST_A BST_B BST_C BST_D DGND DREG DREG_RTN DVDD GND

GREG GVDD M1 M2 M3 OTW OUT_A OUT_B OUT_C OUT_D PVDD_A PVDD_B PVDD_C PVDD_D PWM_AM PWM_AP PWM_BM PWM_BP PWM_CM PWM_CP PWM_DM PWM_DP RESET_AB RESET_CD SD_AB SD_CD

(1)

I = input, O = output, P = power

54 P 43 P 42 P 31 P

6 P 13 P 17 P

4 P

1, 2, 5,

7, 27, 28,

29, 36, 37,

48, 49, 56

3, 26 P

30, 55 P

14 I 15 I 16 I 25 O

50, 51 O 46, 47 O 38, 39 O 34, 35 O 52, 53 P 44, 45 P 40, 41 P 32, 33 P

9 I

8 I 11 I 12 I 19 I 18 I 21 I 22 I 10 I 20 I 23 O 24 O

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SLES088D – AUGUST 2003 – REVISED MAY 2004

Terminal Functions

HS bootstrap supply (BST), external capacitor to OUT_A required HS bootstrap supply (BST), external capacitor to OUT_B required HS bootstrap supply (BST), external capacitor to OUT_C required HS bootstrap supply (BST), external capacitor to OUT_D required Digital I/O reference ground Digital supply voltage regulator decoupling pin, capacitor connected to GND Digital supply voltage regulator decoupling return pin I/O reference supply input (3.3 V)

Power ground (I/O reference ground – pin 22)

Gate drive voltage regulator decoupling pin, capacitor to GND Voltage supply to on−chip gate drive and digital supply voltage regulators Mode selection pin Mode selection pin Mode selection pin Overtemperature warning output, open drain with internal pullup Output, half-bridge A Output, half-bridge B Output, half-bridge C Output, half-bridge D Power supply input for half-bridge A Power supply input for half-bridge B Power supply input for half-bridge C Power supply input for half-bridge D Input signal (negative), half-bridge A Input signal (positive), half-bridge A Input signal (negative), half-bridge B Input signal (positive), half-bridge B Input signal (negative), half-bridge C Input signal (positive), half-bridge C Input signal (negative), half-bridge D Input signal (positive), half-bridge D Reset signal, active low Reset signal, active low Shutdown signal for half-bridges A and B Shutdown signal for half-bridges C and D

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SLES088D – AUGUST 2003 – REVISED MAY 2004

FUNCTIONAL BLOCK DIAGRAM

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GREG

Gate

PWM_AP OUT_A

RESET

PWM_BP OUT_B

OTW

PWM

Receiver

PWM

Receiver

Protection

Blocks

Protection

UVP

Protection A

Protection B

Timing

Control

GREG

Timing

Control

GREG

DREG

Drive

Gate

Drive

Gate

Drive

Gate

Drive

GREG

DREG_RTN

BST_A

PVDD_A

GND

BST_B

PVDD_B

GND

DREG

GVDD

GREG

DREG_RTN

GREG

Gate

PWM_CP OUT_C

RESET

PWM_DP OUT_D

PWM

Receiver

Protection C

Protection D

PWM

Receiver

Timing

Control

GREG

Timing

Control

Drive

Gate

Drive

Gate

Drive

Gate

Drive

BST_C

PVDD_C

GND

BST_D

PVDD_D

GND

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POOutput power

SLES088D – AUGUST 2003 – REVISED MAY 2004

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RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT

DVDD Digital supply GVDD PVDD_x Half-bridge supply Relative to GND, RL= 6 Ω to 8 Ω 0 23 25.5 V

(1)

It is recommended for DVDD to be connected to DREG via a 100-Ω resistor.

Supply for internal gate drive and logic regulators

Junction temperature 0 125 _C

(1)

Relative to DGND 3 3.3 3.6 V Relative to GND 16 23 25.5 V

ELECTRICAL CHARACTERISTICS

PVDD_X = 23 V, GVDD = 23 V, DVDD = 3.3 V, DVDD connected to DREG via a 100-Ω resistor, RL = 6 Ω, 8X fs = 384 kHz, unless otherwise noted. AC performance is recorded as a chipset with TAS5010 as the PWM processor and TAS5122 as the power stage.

SYMBOL PARAMETER TEST CONDITIONS

AC PERFORMANCE, BTL MODE, 1 kHz

RL = 8 Ω, unclipped, AES17 filter

RL = 8 Ω, THD = 10%, AES17 filter

RL = 6 Ω, THD = 0.4%, AES17 filter

RL = 6 Ω, THD = 10%, AES17 filter

Po = 1 W/ channel, RL = 6 Ω, AES17 filter

THD+N Total harmonic distortion + noise

SNR Signal-to-noise ratio

DR Dynamic range

INTERNAL VOLTAGE REGULATOR

DREG Voltage regulator

GREG Voltage regulator

IVGDD GVDD supply current, operating IDVDD DVDD supply current, operating fS = 384 kHz, no load 1 5 mA Max

OUTPUT STAGE MOSFETs

DSon,LS

DSon ,HS

Output RMS noise

Forward on-resistance, LS TJ = 25°C 155 mΩ Max Forward on-resistance, HS TJ = 25°C 155 mΩ Max

Po = 10 W/channel, RL = 6 Ω, AES17 filter

Po = 30 W/channel, RL = 6 Ω, AES17 filter

A-weighted, mute, RL = 6 Ω, 20 Hz to 20 kHz, AES17 filter

f = 1 kHz, A-weighted, RL = 6 Ω,, AES17 filter

Io = 1 mA, PVDD = 18 V−30.5 V

Io = 1.2 mA, PVDD = 18 V−30.5 V

fS = 384 kHz, no load, 50% duty cycle

TYPICAL

TA=25°C

3.1 V Typ

13.4 V Typ

TA=25°C

Case

75°C

0.05% Typ

0.2% Typ

240 µV Max

24 mA Max

UNITS

24 W Typ

29 W Typ

30 W Typ

37 W Typ

95 dB Typ

MIN/TYP/

MAX



Undervoltage protection limit, GVDD

7.4

VIHHigh-level input voltage

Leakage

Input leakage current

SLES088D – AUGUST 2003 – REVISED MAY 2004

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ELECTRICAL CHARACTERISTICS

PVDD_x = 23 V, GVDD = 23 V, DVDD = 3.3 V, RL = 6 Ω, 8X fs = 384 kHz, unless otherwise noted

SYMBOL

INPUT/OUTPUT PROTECTION

uvp,G

OTW Overtemperature warning 125 °C Typ OTE Overtemperature error 150 °C Typ OC Overcurrent protection 5.0 A Min

STATIC DIGITAL SPECIFICATION

PWM_AP, PWM_BP, M1, M2, M3, SD, OTW

OTW/SHUTDOWN (SD)

Low-level input voltage 0.8 V Max

Internally pullup R from OTW/SD to DVDD

Low level output voltage IO = 4 mA 0.4 V Max

PARAMETER TEST CONDITIONS

TYPICAL

TA=25°C

30 22.5 kΩ Min

TA=25°C

6.9 V Min

7.9 V Max

DVDD V Max

−10 µA Min

Case

75°C

2 V Min

10 µA Max

UNITS

MIN/TYP/

MAX

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Gate-Drive

SLES088D – AUGUST 2003 – REVISED MAY 2004

SYSTEM CONFIGURATION USED FOR CHARACTERIZATION (BTL)

Power Supply

External Power Supply

H-Bridge

Power Supply

TAS5122

ERR_RCVY PWM_AP_1

PWM_AM_1

VALID_1

PWM PROCESSOR

TAS50xx

PWM_AP_2

PWM_AM_2

VALID_2

1 µF

100 nF

100 Ω

100 nF

1 µF

GND

GREG

OTW

SD_CD

SD_AB

PWM_DP

PWM_DM

RESET_CD

PWM_CM

PWM_CP

DREG_RTN

DREG

PWM_BP

PWM_BM

RESET_AB

PWM_AM

PWM_AP

GND

DGND

GND

DVDD

GREG

GND

BST_D PVDD_D PVDD_D

OUT_D OUT_D

OUT_C

OUT_C PVDD_C PVDD_C

BST_C

BST_B PVDD_B PVDD_B

OUT_B OUT_B

OUT_A

OUT_A PVDD_A PVDD_A

BST_A

GND

GVDD

GND GND

GVDD

GND

56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

1.5 Ω

1.5 Ω× 2

1.5 Ω

33 nF

100 nF

1.5 Ω

33 nF

100 nF

1.5 Ω

33 nF

(1)

PCB

(1)

100 nF

PCB

(1)

100 nF

PCB

(2)

10 µH

470 nF

10 µH

(2)

10 µH

470 nF

10 µH

(2)

100 nF

4.7 kΩ



1000 µF

(1)

Voltage Clamp 30 V, PN SMAJ28A, MFG MICROSEMI

(2)

: Track in the PCB (1 mm wide and 50 mm long)

PCB

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SLES088D – AUGUST 2003 – REVISED MAY 2004

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From

PWM

Processor

Figure 1. Typical Single-Ended Design With TAS5122 DCA

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THD+N − Total Harmonic Distortion + Noise − %

Noise Amplitude − dBr

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SLES088D – AUGUST 2003 – REVISED MAY 2004

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT POWER

RL = 6 Ω TC = 75°C

TAS5122SE

0.1

0.01 500m 1 10

PO − Output Power − W

Figure 2

TAS5122BTL

TOTAL HARMONIC DISTORTION + NOISE

FREQUENCY

RL = 6 Ω TC = 75°C

PO = 30 W

0.1

PO = 10 W

PO = 1 W

THD+N − Total Harmonic Distortion + Noise − %

0.01 20 100 1k 10k

f − Frequency − Hz

Figure 3

20k

−100

−120

−140

−60 dBFS FFT

RL = 6 Ω FFT = −60 dB

−20

TC = 75°C TAS5010 PWM Processor Device

−40

−60

−80

0 2 4 6 8 10121416182022

f − Frequency − kHz

Figure 4

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT POWER

RL = 6 Ω TC = 75°C

0.1

THD+N − Total Harmonic Distortion + Noise − %

0.01

40m 100m 10 40

PO − Output Power − W

Figure 5



− Output Power − W P

− Power Loss − W

SLES088D – AUGUST 2003 – REVISED MAY 2004

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OUTPUT POWER

H-BRIDGE VOLTAGE

TC = 75°C

50 45 40 35 30 25 20

15 10

5 0

0 2 4 6 8 101214161820222426

VDD − Supply Voltage − V

RL = 6 Ω

Figure 6

RL = 8 Ω

SYSTEM OUTPUT STAGE EFFICIENCY

OUTPUT POWER

100

80 70

60 50

40 30

η − System Output Stage Efficiency − %

0 5 10 15 20 25 30

PO − Output Power − W

Figure 7

f = 1 kHz RL = 6 Ω TC = 75°C

tot

POWER LOSS

OUTPUT POWER

f = 1 kHz RL = 6 Ω TC = 75°C

0 5 10 15 20 25 30

PO − Output Power − W

Figure 8

OUTPUT POWER

CASE TEMPERATURE

PVDD = 23 V

RL = 6 Ω

36 34

Channel 1

− Output Power − W O

24 22 20

0 10 20 30 40 50 60 70 80 90 100110 120130

TC − Case Temperature − °C

Channel 2

Figure 9

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Amplitude − dBr

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SLES088D – AUGUST 2003 – REVISED MAY 2004

AMPLITUDE

FREQUENCY

3.0

2.5

2.0

1.5

1.0

0.5

0.0

−0.5

−1.0

−1.5

−2.0

−2.5

−3.0 10 100 1k 50k10k

f − Frequency − Hz

Figure 10

RL = 8 Ω

RL = 6 Ω

ON-STATE RESISTANCE

JUNCTION TEMPERATURE

200

190

180

170

160

150

− On-State Resistance − mΩ

140

130

120

0 102030405060708090100

TJ − Junction Temperature − °C

Figure 11

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SLES088D – AUGUST 2003 – REVISED MAY 2004

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THEORY OF OPERATION

POWER SUPPLIES

The power device only requires two supply voltages, GVDD and PVDD_x.

GVDD is the gate drive supply for the device, regulated internally down to approximately 12 V, and decoupled with regards to board GND on the GREG pins through an external capacitor. GREG powers both the low side and high side via a bootstrap step-up conversion. The bootstrap supply is charged after the first low-side turnon pulse. Internal digital core voltage DREG is also derived from GVDD and regulated down by internal LDRs to 3.3 V.

The gate-driver LDR can be bypassed for reducing idle loss in the device by shorting GREG to GVDD and directly feeding in 12 V. This can be useful in an application where thermal conduction of heat from the device is difficult. Bypassing the LDR reduces power dissipation.

PVDD_x is the H-bridge power supply pin. T wo power pins exist for each half-bridge to handle the current density. It is important that the circuitry recommendations around the PVDD_x pins are followed carefully both topology- and layout-wise. For topology recommendations, see the System Configuration Used for Characterization section. Following these recommendations is important for parameters like EMI, reliability, and performance.

SYSTEM POWER-UP/POWER-DOWN SEQUENCE

Powering Up

> 1 ms

RESET

(1)

GVDD

PVDD_x

(1)

During power up when RESET is asserted LOW, all MOSFETs are turned off and the two internal half-bridges are in the high-impedance state (Hi-Z). The bootstrap capacitors supplying high-side gate drive are at this point not charged. To comply with the click and pop scheme and

(1)

PWM_xP

PVDD should not be powered up before GVDD.

use of non-TI PWM processors it is recommended to use a 4-kΩ pulldown resistor on each PWM output node to ground. This precharges the bootstrap supply capacitors and discharges the output filter capacitor (see the System Configuration Used for Characterization section).

After GVDD has been applied, it takes approximately 800 µs to fully charge the BST capacitor. Within this time, RESET must be kept low. After approximately 1 ms, the power stage bootstrap capacitor is charged.

RESET can now be released if the modulator is powered up and streaming PWM signals to the power stage PWM_xP.

A constant HIGH dc level on PWM_xP is not permitted, because it would force the high-side MOSFET ON until it eventually ran out of BST capacitor energy and might damage the device.

An unknown state of the PWM output signals from the processor is illegal and should be avoided, which in practice means that the PWM processor must be powered up and initialized before RESET is de-asserted HIGH to the power stage.

Powering Down

For powering down the power stage, an opposite approach is necessary. RESET must be asserted LOW before the valid PWM signal is removed.

When TI PWM processors are used with TI power stages, the correct timing control of RESET and PWM_xP is performed by the modulator.

Precaution

The TAS5122 must always start up in the high-impedance (Hi-Z) state. In this state, the bootstrap (BST) capacitor is precharged by a resistor on each PWM output node to ground. See System Configuration Used for Characterization. This ensures that the power stage is ready for receiving PWM pulses, indicating either HIGHor LOW-side turnon after RESET is deasserted to the power stage.

With the following pulldown and BST capacitor size, the charge time is:

C = 33 nF, R = 4.7 kΩ R × C × 5 = 775.5 µs

After GVDD has been applied, it takes approximately 800 µs to fully charge the BST capacitor. During this time, RESET must be kept low. After approximately 1 ms, the power stage BST is charged and ready. RESET can now be released if the PWM modulator is ready and is streaming valid PWM signals to the power stage. Valid PWM signals are switching PWM signals with a frequency between 350−400 kHz. A constant HIGH level on the PWM_xP forces the high side MOSFET ON until it eventually runs out of BST capacitor energy. Putting the device in this condition should be avoided.

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SLES088D – AUGUST 2003 – REVISED MAY 2004

In practice this means that the DVDD-to-PWM processor should be stable and initialization should be completed before RESET is deasserted to the power stage.

CONTROL I/O

Shutdown Pin: SD

The SD pin functions as an output pin and is intended for protection-mode signaling to, for example, a controller or other PWM processor device. The pin is open-drain with an internal pullup to DVDD.

The logic output is, as shown in the following table, a combination of the device state and RESET input:

SD RESET DESCRIPTION

0 0 Not used 0 1 Device in protection mode, i.e., UVP and/or OC

and/or OT error

(2)

1 1 Normal operation

Temperature Warning Pin: OTW

The OTW pin gives a temperature warning signal when temperature exceeds the set limit. The pin is of the open-drain type with an internal pullup to DVDD.

Overall Reporting

The SD pin, together with the OTW pin, gives chip state information as described in Table 1.

0 Device set high-impedance (Hi-Z), SD forced high

(2)

SD is pulled high when RESET is asserted low independent of chip state (i.e., protection mode). This is desirable to maintain compatibility with some TI PWM processors.

OTW DESCRIPTION

0 Junction temperature higher than 125°C 1 Junction temperature lower than 125°C

The device can be recovered by toggling RESET low and then high, after all errors are cleared.

Overcurrent (OC) Protection

The device has individual forward current protection on both high-side and low-side power stage FETs. The OC protection works only with the demodulation filter present at the output. See Demodulation Filter Design in the Application Information section of this data sheet for design constraints.

Overtemperature (OT) Protection

A dual temperature protection system asserts a warning signal when the device junction temperature exceeds 125°C. The OT protection circuit is shared by all half-bridges.

Undervoltage (UV) Protection

Undervoltage lockout occurs when GVDD is insufficient for proper device operation. The UV protection system protects the device under power-up and power-down situations. The UV protection circuits are shared by all half-bridges.

Reset Functions

The functions of the reset input are:

D Reset is used for re-enabling operation after a

latching error event (PMODE1).

D Reset is used for disabling output stage

switching (mute function).

The error latch is cleared on the falling edge of reset and normal operation is resumed when reset goes high.

PROTECTION MODE

Autorecovery (AR) After Errors (PMODE0)

Table 1. Error Signal Decoding

OTW SD DESCRIPTION

0 0 Overtemperature error (OTE) 0 1 Overtemperature warning (OTW) 1 0 Overcurrent (OC) or undervoltage (UVP) error 1 1 Normal operation, no errors/warnings

Chip Protection

The TAS5122 protection function is implemented in a closed loop with, for example, a system controller or other TI PWM processor device. The TAS5122 contains three individual systems protecting the device against fault conditions. All of the error events covered result in the output stage being set in a high-impedance state (Hi-Z) for maximum protection of the device and connected equipment.

In autorecovery mode (PMODE0) the TAS5122 is self-supported i n handling of error situations. All protection systems are active, setting the output stage in the high-impedance state to protect the output stage and connected equipment. However, after a short time period the device auto-recovers, i.e., operation is automatically resumed provided that the system is fully operational.

The auto-recovery timing is set by counting PWM input cycles, i.e., the timing is relative to the switching frequency.

The AR system is common to both half-bridges.

Timing and Function

The function of the autorecovery circuit is as follows:

1. An error event occurs and sets the protection latch (output stage goes Hi-Z).

2. The counter is started.

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3. After n/2 cycles, the protection latch is cleared but the output stage remains Hi-Z (identical to pulling RESET

low).

4. After n cycles, operation is resumed (identical to pulling RESET high) (n = 512).

Error

Protection

Latch

Shutdown

Autorecovery

PWM

Counter

R-RESET

Figure 12. Autorecovery Function

Latching Shutdown on All Errors (PMODE1)

In latching shutdown mode, all error situations result in a permanent shutdown (output stage Hi-Z). Re-enabling can be done by toggling the RESET pin.

All Protection Systems Disabled (PMODE2)

In PMODE2, all protection systems are disabled. This mode is purely intended for testing and characterization purposes and thus not recommended for normal device operation.

APPLICATION INFORMATION

DEMODULATION FILTER DESIGN AND SPIKE CONSIDERATIONS

The output square wave is susceptible to overshoots (voltage spikes). The spike characteristics depend on many elements, including silicon design and application design and layout. The device should be able to handle narrow spike pulses, less than 65 ns, up to 65 volts peak. For more detailed information, see TI application note SLEA025.

The PurePath Digital amplifier outputs are driven by heavy-duty DMOS transistors in an H-bridge configuration. These transistors are either off or fully on, which reduces the DMOS transistor on-state resistance, R

, and the power dissipated in the device, thereby

DSon

increasing efficiency. The result is a square-wave output signal with a duty cycle

that is proportional to the amplitude of the audio signal. It is recommended that a second-order LC filter be used to recover the audio signal. For this application, EMI is considered important; therefore, the selected filter is the full-output type shown in Figure 13.

TAS51xx

Output A

Output B

C1A

C1B

(Load)

MODE Pins Selection

The protection mode is selected by shorting M1/M2 to DREG or DGND according to Table 2.

Table 2. Protection Mode Selection

M1 M2 PROTECTION MODE

0 0 Reserved 0 1 Latching shutdown on all errors (PMODE1) 1 0 Reserved 1 1 Reserved

The output configuration mode is selected by shorting the M3 pin to DREG or DGND according to Table 3.

Figure 13. Demodulation Filter (AD Mode)

The main purpose of the output filter is to attenuate the high-frequency switching component of the PurePath Digital amplifier while preserving the signals in the audio band.

Design of the demodulation filter affects the performance of the power amplifier significantly. As a result, to ensure proper operation of the overcurrent (OC) protection circuit and meet the device THD+N specifications, the selection of the inductors used in the output filter must be considered according to the following. The rule is that the inductance should remain stable within the range of peak current seen at maximum output power and deliver at least 5 µH of

Table 3. Output Mode Selection

M3 OUTPUT MODE

0 Bridge-tied load output stage (BTL) 1 Reserved

inductance at 15 A. If this rule is observed, the TAS5122 does not have

distortion issues due to the output inductors, and overcurrent conditions do not occur due to inductor saturation in the output filter.

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L - Inductance -

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Another par a meter to be considered is the idle current loss in the inductor. This can be measured or specified as inductor dissipation (D). The target specification for dissipation is less than 0.05.

In general, 10-µH inductors suffice for most applications. The frequency response of the amplifier is slightly altered by the change in output load resistance; however, unless tight control of frequency response is necessary (better than 0.5 dB), it is not necessary to deviate from 10 µH.

The graphs in Figure 14 display the inductance vs current characteristics of two inductors that are recommended for use with the TAS5122.

INDUCTANCE

CURRENT

0 5 10 15

DASL983XX-1023

I - Current - A

DFB1310A

Figure 14. Inductance Saturation

The selection of the capacitor that is placed across the output of each inductor (C2 in Figure 13) is simple. To complete the output filter, use a 0.47-µF capacitor with a voltage rating at least twice the voltage applied to the output stage (PVDD).

This capacitor should be a good quality polyester dielectric such as a Wima MKS2-047ufd/100/10 or equivalent.

In order to minimize the EMI effect of unbalanced ripple loss in the inductors, 0.1-µF 50-V SMD capacitors (X7R or better) (C1A and C1B in Figure 13) should be added from the output of each inductor to ground.

THERMAL INFORMATION

is a system thermal resistance from junction to

ambient ai r. As such, it is a system parameter with roughly the following components:

D R

(the thermal resistance from junction to

case, or in this case the metal pad)

D Thermal grease thermal resistance D Heatsink thermal resistance

has been provided in the Package Dissipation

Ratings section. The thermal grease thermal resistance can be calculated

from the exposed pad area and the thermal grease manufacturer’s area thermal resistance (expressed in °C-in2/W). The area thermal resistance of the example thermal grease with a 0.002-inch-thick layer is about 0.1 °C-in2/W. The approximate exposed pad area is as follows:

56-pin HTSSOP 0.045 in

Dividing the example thermal grease area resistance by the surface area gives the actual resistance through the thermal grease for both ICs inside the package:

56-pin HTSSOP 2.27 °C/W

The thermal resistance of thermal pads is generally considerably higher than a thin thermal grease layer. Thermal tape has an even higher thermal resistance. Neither pads nor tape should be used with either of these two packages. A thin layer of thermal grease with careful clamping of the heatsink is recommended. It may be difficult to achieve a layer 0.001 inch thick or less, so the modeling below is done with a 0.002-inch-thick layer, which may be more representative of production thermal grease thickness.

Heatsink thermal resistance is generally predicted by the heatsink vendor, modeled using a continuous flow dynamics (CFD) model, or measured.

Thus, for a single monaural IC, the system R thermal grease resistance + heatsink resistance.

DCA THERMAL INFORMATION

The thermally enhanced DCA package is based on the 56-pin HTSSOP, but includes a thermal pad (see Figure 15) to provide an effective thermal contact between the IC and the PCB.

The PowerPAD package (thermally enhanced HTSSOP) combines fine-pitch, surface-mount technology with thermal performance comparable to much larger power packages.

The PowerP AD package is designed to optimize the heat transfer to the PWB. Because of the small size and limited mass of an HTSSOP package, thermal enhancement is

= R

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SLES088D – AUGUST 2003 – REVISED MAY 2004

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achieved by improving the thermal conduction paths that remove heat from the component. The thermal pad is formed using a patented lead-frame design and manufacturing technique to provide a direct connection to the heat-generating IC. When this pad is soldered or otherwise thermally coupled to an external heat dissipater, high power dissipation in the ultrathin, fine-pitch, surface-mount package can be reliably achieved.

Thermal Methodology for the DCA 56-Pin, 2y15-W, 8-W Package

The thermal design for the DCA part (e.g., thermal pad

Copper Layer − Component Side

Solder

TAS5122DCA

soldered to the board) should be similar to the design in the following figures. The cooling approach is to conduct the dissipated heat into the via pads on the board, through the vias in the board, and into a heatsink (aluminum bar) (if necessary).

Figure 15 shows a recommended land pattern on the PCB.

PowerPAD

5y1 1 Vias (f 0.3 mm)

4mm

Figure 15. Recommended Land Pattern

The lower via pad area, slightly larger than the IC pad itself, is exposed with a window in the solder resist on the bottom surface of the board. It is not coated with solder during the board construction to maintain a flat surface. In production, this can be accomplished with a peelable solder mask.

An aluminum bar is used to keep the through-hole leads

8 mm

from shorting to the chassis. The thermal compound shown has a pad-to-aluminum bar thermal resistance of about 3.2° C/W.

The chassis provides the only heatsink to air and is chosen as representative of a typical production cooling approach.

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SLES088D – AUGUST 2003 – REVISED MAY 2004

Insulating Front Panel

Stereo

Amplifier

Board

Wakefield T ype 126

Thermal Compound

Under Via Pads

(3.2°C/W)

PCB (3.65C/W)

Figure 16. 56-Pin DCA Package Cross-Sectional View (Side)

Plastic Top

56-Pin DCA Package

(1.145C/W)

Wakefield T ype 126

Thermal Compound

(0.1°C/W)

Insulating

Back Panel

1 mm

8-mm y 10-mm y 40 mm

Aluminum Bar

(0.09°C/W) Aluminum Chassis 7.2 in. y 1 in. y 0.1 in. Thick

Sides of U-Shaped Chassis Are 1.25 in. High (3.9°C/W)

Plastic Top

PCB (3.6°C/W)

Stereo

Amplifier

Board

Wakefield T ype 126

Thermal Compound

Aluminum Chassis 7.2 in. y. 1 in y 0.1 in. Thick

Sides of U-Shaped Chassis Are 1.25 in. High (3.9°C/W)

56-Pin DCA Package

(1.14°C/W)

(2 Places)

(0.1°C/W)

Figure 17. Spatial Separation With Multiple Packages

The land pattern recommendation shown in Figure 15 is for optimal performance with aluminum bar thermal resistance of 0.09 ° C/W. The following table shows the

4-40 Machine Screw

With Star Washer

and Nut

(3 Places)

Wakefield T ype 126

Thermal Compound

Under Via Pads

(3.2°C/W)

8-mm y 10-mm y 40-mm

Aluminum Bar

(0.09°C/W)

decrease in thermal resistance through the PCB with a corresponding increase in the land pattern size. Use the table for thermal design tradeoffs.

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LAND PATTERN

7×13 vias (5×10 mm) 2.2°C/W 5×11 vias (4×8 mm) 3.6°C/W

Thermal

Pad

3,90 mm 2,98 mm

PCB THERMAL

RESISTANCE

8,20 mm 7,20 mm

Figure 18. Thermal Pad Dimensions for DCA

Package

the output stage prior to operation is in the high-impedance state, this is done by having a passive pulldown resistor on each speaker output to GND (see System Configuration Used for Characterization).

Other things that can affect the audible click level:

D The spectrum of the click seems to follow the

speaker impedance vs frequency curve—the higher the impedance, the higher the click energy.

D Crossover filters used between woofer and

tweeter in a speaker can have high impedance in the audio band, which should be avoided if possible.

Another way to look at it is that the speaker impulse response is a major contributor to how the click energy is shaped in the audio band and how audible the click is.

The following mode transitions feature click and pop reduction in Texas Instruments PWM processors.

STATE

(1)

Normal Mute → Normal

(1)

Normal Error recovery → Normal

(1)

Normal Hard Reset → Normal

(1)

Normal = switching

→ Mute Yes

Error recovery

→

(ERRCVY)

→ Hard Reset No

(1)

CLICK AND

POP REDUCED

Yes Yes Yes

Yes

REFERENCES

CLICK AND POP REDUCTION

TI modulators feature a pop and click reduction system that controls the timing when switching starts and stops.

Going from nonswitching to switching operation causes a spectral energy burst to occur within the audio bandwidth, which is heard in the speaker as an audible click, for instance, after having asserted RESET LH during a system start-up.

To make this system work properly, the following design rules must be followed when using the TAS5122 power stage:

D The relative timing between the PWM_AP/M_x

signals and their corresponding VALID_x signal should not be skewed by inserting delays, because this increases the audible amplitude level of the click.

D The output stage must start switching from a

fully discharged output filter capacitor. Because

1. TAS5000 Digital Audio PWM Processor data manual – TI (SLAS270)

2. True Digital Audio Amplifier TAS5001 Digital Audio PWM Processor data sheet – TI (SLES009)

3. True Digital Audio Amplifier TAS5010 Digital Audio PWM Processor data sheet – TI (SLAS328)

4. True Digital Audio Amplifier TAS5012 Digital Audio PWM Processor data sheet – TI (SLES006)

5. TAS5026 Six-Channel Digital Audio PWM Processor data manual – TI (SLES041)

6. TAS5036A Six-Channel Digital Audio PWM Processor data manual – TI (SLES061)

7. TAS3103 Digital Audio Processor With 3D Effects data manual – TI (SLES038)

8. Digital Audio Measurements application report – TI (SLAA114)

9. System Design Considerations for True Digital Audio Power Amplifiers application report – TI (SLAA117)

MECHANICAL DATA

MPDS044 – JANUARY 1998

DCA (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,50

1,20 MAX

0,27 0,17

0,15 0,05

0,08

6,20 8,30 6,00

7,90

Seating Plane

0,10

Thermal Pad (See Note D)

0,15 NOM

Gage Plane

0°–8°

0,25

0,75 0,50

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.

This pad is electrically and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MO-153

PowerPAD is a trademark of Texas Instruments Incorporated.

12,60

12,40

14,10

17,10

16,9013,90

4073259/A 01/98

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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TEXAS INSTRUMENTS TAS5122 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual