TEXAS INSTRUMENTS TAS5112A Technical data

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

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SLES094A - OCTOBER 2003 - REVISED MARCH 2004

   



TM

FEATURES

D 50 W per Channel (BTL) Into 6 Ω (Stereo)
D 95-dB Dynamic Range With TAS5026
D Less Than 0.1% THD+N (1 W RMS Into 6 Ω)
D Less Than 0.2% THD+N (50 W RMS into 6 Ω)
D Power Efficiency Typically 90% Into 6-Ω Load
D Self-Protecting Design (Undervoltage,

Overtemperature and Short Conditions) With
Error Reporting

D Internal Gate Drive Supply Voltage Regulator
D EMI Compliant When Used With

Recommended System Design

1

THD + NOISE vs OUTPUT POWER

RL = 6 Ω
TC = 75°C

APPLICATIONS

D DVD Receiver
D Home Theatre
D Mini/Micro Component Systems
D Internet Music Appliance

DESCRIPTION

The TAS5112A is a high-performance, integrated stereo
digital amplifier power stage designed to drive 6-Ω
speakers at up to 50 W per channel. The device
incorporates TI’s PurePath Digitalt technology and is
used with a digital audio PWM processor (TAS50XX) and
a simple passive demodulation filter to deliver high-quality,
high-efficiency, true-digital audio amplification.

The efficiency of this digital amplifier is typically 90%,
reducing the size of both the power supplies and heatsinks
needed. Overcurrent protection, overtemperature
protection, and undervoltage protection are built into the
TAS5112A, safeguarding the device and speakers against
fault conditions that could damage the system.

1

THD + NOISE vs FREQUENCY

RL = 6 Ω
TC = 75°C

PO = 50 W

0.1

0.1

0.01

THD+N - Total Harmonic Distortion + Noise - %

0.01
100m

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PurePath Digital and PowerPAD are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.

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1 10 100

PO - Output Power - W

THD+N - Total Harmonic Distortion + Noise - %

0.001

PO = 10 W

PO = 1 W

20 100 1k 10k

f - Frequency - Hz

Copyright  2004, Texas Instruments Incorporated

20k



R

D

D
D

C
C

B
B

A
A

DFD PACKAGE

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.

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GENERAL INFORMATION

Terminal Assignment

The TAS5112A is offered in a thermally enhanced 56-pin
TSSOP DFD (thermal pad is on the top), shown as follows.

(TOP VIEW)

GND
GVDD
BST_D
PVDD_
PVDD_
OUT_D
OUT_D
GND
GND
OUT_C
OUT_C
PVDD_
PVDD_
BST_C
BST_B
PVDD_
PVDD_
OUT_B
OUT_B
GND
GND
OUT_A
OUT_A
PVDD_
PVDD_
BST_A
GVDD
GND

GND
GND

GREG

OTW

SD_CD

SD_AB

PWM_DP

PWM_DM

ESET_CD

PWM_CM

PWM_CP

REG_RTN

M3
M2
M1

DREG

PWM_BP

PWM_BM

RESET_AB

PWM_AM

PWM_AP

GND

DGND

GND

DVDD

GREG

GND
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

Absolute Maximum Ratings

over operating free-air temperature range unless otherwise noted

TAS5112A UNITS

DVDD TO DGND –0.3 V to 4.2 V
GVDD TO GND 33.5 V
PVDD_X TO GND (dc voltage) 33.5 V
PVDD_X TO GND (spike voltage
OUT_X TO GND (dc voltage) 33.5 V
OUT_X TO GND (spike voltage
BST_X TO GND (dc voltage) 48 V
BST_X TO GND (spike voltage
GREG TO GND
PWM_XP, RESET, M1, M2, M3, SD,

OTW
Maximum operating junction

temperature, T
Storage temperature –40°C to 125°C

(1)

Stresses beyond those listed under “absolute maximum ratings”
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute­maximum-rated conditions for extended periods may affect device
reliability.

(2)

The duration of voltage spike should be less than 100 ns; see
application note SLEA025.

(3)

GREG is treated as an input when the GREG pin is overdriven by
GVDD of 12 V .

(3)

J

(2)

) 48 V

(2)

) 48 V

(2)

) 53 V

–0.3 V to DVDD + 0.3 V

–40°C to 150°C

14.2 V

(1)

Package Dissipation Ratings

R

PACKAGE

56-pin DFD TSSOP 1.14 See Note 4

(4)

The TAS5112A package is thermally enhanced for conductive
cooling using an exposed metal pad area. It is impractical to use the
device with the pad exposed to ambient air as the only heat sinking
of the device.
For this reason, R
thermal treatment, is provided in the Application Information section
of the data sheet. An example and discussion of typical system
R

values are provided in the Thermal Information section. This

θJA

example provides additional information regarding the power
dissipation ratings. This example should be used as a reference to
calculate the heat dissipation ratings for a specific application. TI
application engineering provides technical support to design
heatsinks if needed.

a system parameter that characterizes the

θJA,

θJC

(°C/W)

R

θJA

(°C/W)

Ordering Information

T

A

0°C to 70°C TAS5112ADFD 56-pin small TSSOP

PACKAGE DESCRIPTION

For the most current specification and package
information, refer to our W eb site at www.ti.com.

2

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FUNCTION

(1)

DESCRIPTION

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

Terminal Functions

TERMINAL

NAME NO.

BST_A 31 P High-side bootstrap supply (BST), external capacitor to OUT_A required
BST_B 42 P High-side bootstrap supply (BST), external capacitor to OUT_B required
BST_C 43 P HS bootstrap supply (BST), external capacitor to OUT_C required
BST_D 54 P HS bootstrap supply (BST), external capacitor to OUT_D required
DGND 23 P Digital I/O reference ground
DREG 16 P Digital supply voltage regulator decoupling pin, capacitor connected to GND
DREG_RTN 12 P Digital supply voltage regulator decoupling return pin
DVDD 25 P I/O reference supply input (3.3 V)
GND 1, 2, 22, 24,

27, 28, 29, 36,

37, 48, 49, 56
GREG 3, 26 P Gate drive voltage regulator decoupling pin, capacitor to REG_GND
GVDD 30, 55 P Voltage supply to on-chip gate drive and digital supply voltage regulators
M1 (TST0) 15 I Mode selection pin
M2 14 I Mode selection pin
M3 13 I Mode selection pin
OTW 4 O Overtemperature warning output, open drain with internal pullup resistor
OUT_A 34, 35 O Output, half-bridge A
OUT_B 38, 39 O Output, half-bridge B
OUT_C 46, 47 O Output, half-bridge C
OUT_D 50, 51 O Output, half-bridge D
PVDD_A 32, 33 P Power supply input for half-bridge A
PVDD_B 40, 41 P Power supply input for half-bridge B
PVDD_C 44, 45 P Power supply input for half-bridge C
PVDD_D 52, 53 P Power supply input for half-bridge D
PWM_AM 20 I Input signal (negative), half-bridge A
PWM_AP 21 I Input signal (positive), half-bridge A
PWM_BM 18 I Input signal (negative), half-bridge B
PWM_BP 17 I Input signal (positive), half-bridge B
PWM_CM 10 I Input signal (negative), half-bridge C
PWM_CP 11 I Input signal (positive), half-bridge C
PWM_DM 8 I Input signal (negative), half-bridge D
PWM_DP 7 I Input signal (positive), half-bridge D
RESET_AB 19 I Reset signal, active low
RESET_CD 9 I Reset signal, active low
SD_AB 6 O Shutdown signal for half-bridges A and B, active-low
SD_CD 5 O Shutdown signal for half-bridges C and D, active-low

(1)

I = input, O = Output, P = Power

P Power ground



3



SLES094A - OCTOBER 2003 - REVISED MARCH 2004

FUNCTIONAL BLOCK DIAGRAM

PWM_AP

RESET

PWM

Receiver

Protection A

Protection B

GREG

Timing

Control

GREG

Gate

Drive

Gate

Drive

Gate

Drive

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BST_A

PVDD_A

OUT_A

GND

BST_B

PVDD_B

PWM_BP

OTW

SD

PWM

Receiver

To Protection

Blocks

OT

Protection

UVP

This diagram shows one channel.

Control

GREG

Timing

DREG

DREG

Gate

Drive

GREG

DREG_RTN

OUT_B

GND

DREG

GVDD

GREG

GREG

DREG_RTN

4

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Po

Output power

+ noise

SLES094A - OCTOBER 2003 - REVISED MARCH 2004



RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT

DVDD Digital supply
GVDD
PVDD_x Half-bridge supply Relative to GND, RL= 6 Ω to 8 Ω 0 29.5 30.5 V

T

J

(1)

It is recommended for DVDD to be connected to DREG via a 100-Ω resistor.

Supply for internal gate drive and logic
regulators

Junction temperature 0 125 _C

(1)

Relative to DGND 3 3.3 3.6 V
Relative to GND 16 29.5 30.5 V

ELECTRICAL CHARACTERISTICS

PVDD_X = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-Ω resistor, RL = 6 Ω, 8X fs = 384 kHz, unless otherwise noted

TYPICAL OVER TEMPERATURE

SYMBOL PARAMETER TEST CONDITIONS

AC PERFORMANCE, BTL Mode, 1 kHz

RL = 8 Ω, THD = 0.2%,
AES17 filter, 1 kHz

RL = 8 Ω, THD = 10%, AES17
filter, 1 kHz

RL = 6 Ω, THD = 0.2%,
AES17 filter, 1 kHz

RL = 6 Ω, THD = 10%, AES17
filter, 1 kHz

Po = 1 W/ channel, RL = 6 Ω,
AES17 filter

THD+N

V

n

SNR Signal-to-noise ratio A-weighted, AES17 filter 96 dB Typ
DR Dynamic range

INTERNAL VOLTAGE REGULATOR

DREG Voltage regulator

GREG Voltage regulator

IVGDD

IDVDD

OUTPUT STAGE MOSFETs

R

DSon,LS

R

DSon ,HS

Total harmonic distortion
+ noise

Output integrated voltage
noise

GVDD supply current,
operating

DVDD supply current,
operating

Forward on-resistance,
low side

Forward on-resistance,
high side

Po = 10 W/channel, RL = 6 Ω,
AES17 filter

Po = 50 W/channel, RL = 6 Ω,
AES17 filter

A-weighted, mute, RL = 6 Ω,,
20 Hz to 20 kHz, AES17 filter

f = 1 kHz, A-weighted,
AES17 filter

Io = 1 mA,
PVDD = 18 V-30.5 V

Io = 1.2 mA,
PVDD = 18 V-30.5 V

fS = 384 kHz, no load, 50%
duty cycle

fS = 384 kHz, no load 1 5 mA Max

TJ = 25°C 155 mΩ Typ

TJ = 25°C 155 mΩ Typ

TA=25°C TA=25°C

3.1 V Typ

13.4 V Typ

24 mA Max

T

=

Case

75°C

0.03% Typ

0.04% Typ

0.2% Typ

260 µV Max

TA=40°C

TO 85°C

40 W Typ

50 W Typ

50 W Typ

62 W Typ

96 dB Typ

UNITS

MIN/TYP/

MAX

5



Undervoltage protection

V

Undervoltage protection
GVDD up and down. Monitor

7.4

VIHHigh-level input voltage

Leakage

Input leakage current

SLES094A - OCTOBER 2003 - REVISED MARCH 2004

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ELECTRICAL CHARACTERISTICS

PVDD_x = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-Ω resistor, RL = 6 Ω, 8X fs = 384 kHz, unless otherwise noted

TYPICAL OVER TEMPERATURE

SYMBOL PARAMETER TEST CONDITIONS

INPUT/OUTPUT PROTECTION

Set the DUT in normal
operation mode with all the
protections enabled. Sweep

uvp,G

OTW

OTE
OC Overcurrent protection See Note 1. 6.7 A Typ

STATIC DIGITAL SPECIFICATION

V

IL

OTW/SHUTDOWN (SD)

V

OL

(1)

To optimize device performance and prevent overcurrent (OC) protection tripping, the demodulation filter must be designed with special care.
See Demodulation Filter Design in the Application Information section of the data sheet and consider the recommended inductors and capacitors
for optimal performance. It is also important to consider PCB design and layout for optimum performance of the TAS5112A. It is recommended
to follow the TAS5112F2EVM (S/N 112) design and layout guidelines for best performance.

limit, GVDD

Overtemperature warning,
junction temperature

Overtemperature error,
junction temperature

PWM_AP, PWM_BP, M1,
M2, M3, SD, OTW

Low-level input voltage 0.8 V Max

Internally pull up R from
OTW/SD to DVDD

Low-level output voltage IO = 4 mA 0.4 V Max

SD output. Record the
GREG reading when SD is
triggered.

TA=25°C TA=25°C

6.9 V Min

7.9 V Max

125 °C Typ

150 °C Typ

DVDD V Max

-10 µA Min
10 µA Max

30 22.5 kΩ Min

T

=

Case

75°C

2 V Min

TA=40°C

TO 85°C

UNITS

MIN/TYP/

MAX

6

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Gate-Drive

PCB

SYSTEM CONFIGURATION USED FOR CHARACTERIZATION

Power Supply

External Power Supply

H-Bridge

Power Supply

TAS5112ADFD

ERR_RCVY
PWM_AP_1

PWM_AM_1

VALID_1

PWM PROCESSOR

TAS5026

PWM_AP_2

PWM_AM_2

VALID_2

1 µF

100 nF

100 Ω

100 nF

1 µF

1

GND

2

GND

3

GREG

4

OTW

5

SD_CD

6

SD_AB

7

PWM_DP

8

PWM_DM

9

RESET_CD

10

PWM_CM

11

PWM_CP

12

DREG_RTN

13

M3

14

M2

15

M1

16

DREG

17

PWM_BP

18

PWM_BM

19

RESET_AB

20

PWM_AM

21

PWM_AP

22

GND

23

DGND

24

GND

25

DVDD

26

GREG

27

GND

28

GND

BST_D
PVDD_D
PVDD_D

OUT_D
OUT_D

OUT_C

OUT_C
PVDD_C
PVDD_C

BST_C

BST_B
PVDD_B
PVDD_B

OUT_B
OUT_B

OUT_A

OUT_A
PVDD_A
PVDD_A

BST_A

GND

GVDD

GND
GND

GND
GND

GVDD

GND

56
55

1.5 Ω

54
53
52
51
50
49
48
47
46
45
44
43

1.5 Ω

42
41
40
39
38
37
36
35
34
33
32
31

1.5 Ω

30
29

33 nF

100 nF

1.5 Ω

1.5 Ω

†

33 nF

33 nF

100 nF

1.5 Ω

1.5 Ω

†

33 nF



SLES094A - OCTOBER 2003 - REVISED MARCH 2004

100 nF

‡

L

PCB

10 µH

†

†

10 µH

100 nF

L

PCB

L

PCB

10 µH

10 µH

100 nF

L

PCB

470 nF

‡

‡

470 nF

‡

100 nF

100 nF

100 nF

100 nF

100 nF

4.7 kΩ

4.7 kΩ

4.7 kΩ

4.7 kΩ

1000 µF

1000 µF

†

Voltage suppressor diodes: 1SMA33CAT

‡

L

: Track in the PCB (1,0 mm wide and 50 mm long)

7