TEXAS INSTRUMENTS TAS5112A Technical data

www.ti.com	TAS5112A
	SLES094A - OCTOBER 2003 - REVISED MARCH 2004

TM

DIGITAL AMPLIFIER POWER STAGE

FEATURES

D50 W per Channel (BTL) Into 6 Ω (Stereo)

D95-dB Dynamic Range With TAS5026

DLess Than 0.1% THD+N (1 W RMS Into 6 Ω)

DLess Than 0.2% THD+N (50 W RMS into 6 Ω)

DPower Efficiency Typically 90% Into 6-Ω Load

DSelf-Protecting Design (Undervoltage, Overtemperature and Short Conditions) With Error Reporting

DInternal Gate Drive Supply Voltage Regulator

DEMI Compliant When Used With Recommended System Design

APPLICATIONS

DDVD Receiver

DHome Theatre

DMini/Micro Component Systems

DInternet Music Appliance

DESCRIPTION

The TAS5112A is a high-performance, integrated stereo digital amplifier power stage designed to drive 6-Ω speakers at up to 50 W per channel. The device incorporates TI’s PurePath Digitalt technology and is used with a digital audio PWM processor (TAS50XX) and a simple passive demodulation filter to deliver high-quality, high-efficiency, true-digital audio amplification.

The efficiency of this digital amplifier is typically 90%, reducing the size of both the power supplies and heatsinks needed. Overcurrent protection, overtemperature protection, and undervoltage protection are built into the TAS5112A, safeguarding the device and speakers against fault conditions that could damage the system.

THD + NOISE vs OUTPUT POWER

	1
%		RL = 6 Ω
-		TC = 75°C
Distortion + Noise
THD+N - Total Harmonic	0.1
	0.01
	100m	1	10	100
		PO - Output Power - W

THD + NOISE vs FREQUENCY

	1
%		RL = 6 Ω
-		TC = 75°C
+ Noise
			PO = 50 W
Distortion	0.1
		PO = 10 W
Harmonic			PO = 1 W
	0.01
THD+N - Total
	0.001
	20	100	1k	10k	20k
			f - Frequency - Hz

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PurePath Digital and PowerPAD are trademarks of Texas Instruments.

Other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products	Copyright 2004, Texas Instruments Incorporated
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.

TAS5112A	www.ti.com
SLES094A - OCTOBER 2003 - REVISED MARCH 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

GENERAL INFORMATION

Terminal Assignment

The TAS5112A is offered in a thermally enhanced 56-pin TSSOP DFD (thermal pad is on the top), shown as follows.

DFD PACKAGE (TOP VIEW)

		GND						1	56			GND
		GND						2	55			GVDD
		GREG						3	54			BST_D
		OTW						4	53			PVDD_D
		SD_CD						5	52			PVDD_D
		SD_AB						6	51			OUT_D
	PWM_DP							7	50			OUT_D
	PWM_DM							8	49			GND
	RESET_CD							9	48			GND
	PWM_CM							10	47			OUT_C
	PWM_CP							11	46			OUT_C
DREG_RTN								12	45			PVDD_C
		M3						13	44			PVDD_C
		M2						14	43			BST_C
		M1						15	42			BST_B
		DREG						16	41			PVDD_B
	PWM_BP							17	40			PVDD_B
	PWM_BM							18	39			OUT_B
	RESET_AB							19	38			OUT_B
	PWM_AM							20	37			GND
	PWM_AP							21	36			GND
		GND						22	35			OUT_A
		DGND						23	34			OUT_A
		GND						24	33			PVDD_A
		DVDD						25	32			PVDD_A
		GREG						26	31			BST_A
		GND						27	30			GVDD
		GND						28	29			GND

Absolute Maximum Ratings

over operating free-air temperature range unless otherwise noted(1)

		TAS5112A				UNITS
	DVDD TO DGND					–0.3 V to 4.2 V
	GVDD TO GND					33.5 V
	PVDD_X TO GND (dc voltage)					33.5 V
	PVDD_X TO GND (spike voltage(2))					48 V
	OUT_X TO GND (dc voltage)					33.5 V
	OUT_X TO GND (spike voltage(2))					48 V
	BST_X TO GND (dc voltage)					48 V
	BST_X TO GND (spike voltage(2))					53 V
	GREG TO GND (3)					14.2 V
	PWM_XP,		M1, M2, M3,
		RESET,		SD,		–0.3 V to DVDD + 0.3 V
	OTW
	Maximum operating junction					–40°C to 150°C
	temperature, TJ
	Storage temperature					–40°C to 125°C

(1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute- maximum-rated conditions for extended periods may affect device reliability.

(2)The duration of voltage spike should be less than 100 ns; see application note SLEA025.

(3)GREG is treated as an input when the GREG pin is overdriven by GVDD of 12 V.

Package Dissipation Ratings

	PACKAGE	RθJC	RθJA
		(°C/W)	(°C/W)
	56-pin DFD TSSOP	1.14	See Note 4

(4)The TAS5112A package is thermally enhanced for conductive cooling using an exposed metal pad area. It is impractical to use the device with the pad exposed to ambient air as the only heat sinking of the device.

For this reason, RθJA, a system parameter that characterizes the thermal treatment, is provided in the Application Information section

of the data sheet. An example and discussion of typical system

RθJA values are provided in the Thermal Information section. This example provides additional information regarding the power dissipation ratings. This example should be used as a reference to calculate the heat dissipation ratings for a specific application. TI application engineering provides technical support to design heatsinks if needed.

Ordering Information

TA	PACKAGE	DESCRIPTION
0°C to 70°C	TAS5112ADFD	56-pin small TSSOP

For the most current specification and package information, refer to our Web site at www.ti.com.

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	www.ti.com									TAS5112A
										SLES094A - OCTOBER 2003 - REVISED MARCH 2004
										Terminal Functions
				TERMINAL					FUNCTION(1)	DESCRIPTION
	NAME							NO.
	BST_A							31	P	High-side bootstrap supply (BST), external capacitor to OUT_A required
	BST_B							42	P	High-side bootstrap supply (BST), external capacitor to OUT_B required
	BST_C							43	P	HS bootstrap supply (BST), external capacitor to OUT_C required
	BST_D							54	P	HS bootstrap supply (BST), external capacitor to OUT_D required
	DGND							23	P	Digital I/O reference ground
	DREG							16	P	Digital supply voltage regulator decoupling pin, capacitor connected to GND
	DREG_RTN							12	P	Digital supply voltage regulator decoupling return pin
	DVDD							25	P	I/O reference supply input (3.3 V)
	GND							1, 2, 22, 24,	P	Power ground
								27, 28, 29, 36,
								37, 48, 49, 56
	GREG							3, 26	P	Gate drive voltage regulator decoupling pin, capacitor to REG_GND
	GVDD							30, 55	P	Voltage supply to on-chip gate drive and digital supply voltage regulators
	M1 (TST0)							15	I	Mode selection pin
	M2							14	I	Mode selection pin
	M3							13	I	Mode selection pin
								4	O	Overtemperature warning output, open drain with internal pullup resistor
	OTW
	OUT_A							34, 35	O	Output, half-bridge A
	OUT_B							38, 39	O	Output, half-bridge B
	OUT_C							46, 47	O	Output, half-bridge C
	OUT_D							50, 51	O	Output, half-bridge D
	PVDD_A							32, 33	P	Power supply input for half-bridge A
	PVDD_B							40, 41	P	Power supply input for half-bridge B
	PVDD_C							44, 45	P	Power supply input for half-bridge C
	PVDD_D							52, 53	P	Power supply input for half-bridge D
	PWM_AM							20	I	Input signal (negative), half-bridge A
	PWM_AP							21	I	Input signal (positive), half-bridge A
	PWM_BM							18	I	Input signal (negative), half-bridge B
	PWM_BP							17	I	Input signal (positive), half-bridge B
	PWM_CM							10	I	Input signal (negative), half-bridge C
	PWM_CP							11	I	Input signal (positive), half-bridge C
	PWM_DM							8	I	Input signal (negative), half-bridge D
	PWM_DP							7	I	Input signal (positive), half-bridge D
								19	I	Reset signal, active low
	RESET_AB
								9	I	Reset signal, active low
	RESET_CD
								6	O	Shutdown signal for half-bridges A and B, active-low
	SD_AB
								5	O	Shutdown signal for half-bridges C and D, active-low
	SD_CD

(1) I = input, O = Output, P = Power

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TAS5112A	www.ti.com
SLES094A - OCTOBER 2003 - REVISED MARCH 2004

FUNCTIONAL BLOCK DIAGRAM

PWM_AP

RESET

PWM_BP

OTW

SD

BST_A

GREG

PVDD_A

Gate

Drive

PWM

Timing

OUT_A

Receiver

Control

Gate

Drive

GND

Protection A

BST_B

GREG

PVDD_B

Protection B

Gate

Drive

PWM

Timing

OUT_B

Receiver

Control

Gate

Drive

To Protection

GND

Blocks

DREG

DREG

GVDD

GREG

OT

GREG

GREG

Protection

DREG

GREG

UVP

DREG_RTN	DREG_RTN

This diagram shows one channel.

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	www.ti.com					TAS5112A
			SLES094A - OCTOBER 2003 - REVISED MARCH 2004
	RECOMMENDED OPERATING CONDITIONS
				MIN	TYP	MAX	UNIT
	DVDD	Digital supply (1)	Relative to DGND	3	3.3	3.6	V
	GVDD	Supply for internal gate drive and logic	Relative to GND	16	29.5	30.5	V
		regulators
	PVDD_x	Half-bridge supply	Relative to GND, RL= 6 Ω to 8 Ω	0	29.5	30.5	V
	TJ	Junction temperature		0		125	_C

(1) It is recommended for DVDD to be connected to DREG via a 100-Ω resistor.

ELECTRICAL CHARACTERISTICS

PVDD_X = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-Ω resistor, RL = 6 Ω, 8X fs = 384 kHz, unless otherwise noted

			TYPICAL		OVER TEMPERATURE
SYMBOL	PARAMETER	TEST CONDITIONS
			TA=25°C	TA=25°C	TCase=	TA=40°C	UNITS	MIN/TYP/
					75°C	TO 85°C		MAX
AC PERFORMANCE, BTL Mode, 1 kHz
		RL = 8 Ω, THD = 0.2%,			40		W	Typ
		AES17 filter, 1 kHz
		RL = 8 Ω, THD = 10%, AES17			50		W	Typ
		filter, 1 kHz
Po	Output power
		RL = 6 Ω, THD = 0.2%,			50		W	Typ
		AES17 filter, 1 kHz
		RL = 6 Ω, THD = 10%, AES17			62		W	Typ
		filter, 1 kHz
		Po = 1 W/ channel, RL = 6 Ω,			0.03%			Typ
		AES17 filter
THD+N	Total harmonic distortion	Po = 10 W/channel, RL = 6 Ω,			0.04%			Typ
	+ noise	AES17 filter
		Po = 50 W/channel, RL = 6 Ω,			0.2%			Typ
		AES17 filter
Vn	Output integrated voltage	A-weighted, mute, RL = 6 Ω,,			260		µV	Max
	noise	20 Hz to 20 kHz, AES17 filter
SNR	Signal-to-noise ratio	A-weighted, AES17 filter			96		dB	Typ
DR	Dynamic range	f = 1 kHz, A-weighted,			96		dB	Typ
		AES17 filter
INTERNAL VOLTAGE REGULATOR
DREG	Voltage regulator	Io = 1 mA,	3.1				V	Typ
		PVDD = 18 V-30.5 V
GREG	Voltage regulator	Io = 1.2 mA,	13.4				V	Typ
		PVDD = 18 V-30.5 V
IVGDD	GVDD supply current,	fS = 384 kHz, no load, 50%		24			mA	Max
	operating	duty cycle
IDVDD	DVDD supply current,	fS = 384 kHz, no load	1	5			mA	Max
	operating
OUTPUT STAGE MOSFETs
RDSon,LS	Forward on-resistance,	TJ = 25°C	155				mΩ	Typ
	low side
RDSon,HS	Forward on-resistance,	TJ = 25°C	155				mΩ	Typ
	high side

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TAS5112A	www.ti.com
SLES094A - OCTOBER 2003 - REVISED MARCH 2004

ELECTRICAL CHARACTERISTICS

PVDD_x = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-Ω resistor, RL = 6 Ω, 8X fs = 384 kHz, unless otherwise noted

						TYPICAL		OVER TEMPERATURE
SYMBOL		PARAMETER	TEST CONDITIONS
						TA=25°C	TA=25°C	TCase=	TA=40°C	UNITS	MIN/TYP/
								75°C	TO 85°C		MAX
INPUT/OUTPUT PROTECTION
			Set the DUT in normal
			operation mode with all the				6.9			V	Min
	Undervoltage protection		protections enabled. Sweep
Vuvp,G			GVDD up and down. Monitor			7.4
	limit, GVDD
			SD output. Record the
							7.9			V	Max
			GREG reading when	SD	is
			triggered.
OTW	Overtemperature warning,					125				°C	Typ
	junction temperature
OTE	Overtemperature error,					150				°C	Typ
	junction temperature
OC	Overcurrent protection		See Note 1.			6.7				A	Typ
STATIC DIGITAL SPECIFICATION
	PWM_AP, PWM_BP, M1,
	M2, M3, SD, OTW
VIH	High-level input voltage						2			V	Min
							DVDD			V	Max
VIL	Low-level input voltage						0.8			V	Max
Leakage	Input leakage current						-10			µA	Min
							10			µA	Max
OTW/SHUTDOWN (SD)
	Internally pull up R from					30	22.5			kΩ	Min
	OTW/SD to DVDD
VOL	Low-level output voltage		IO = 4 mA				0.4			V	Max

(1)To optimize device performance and prevent overcurrent (OC) protection tripping, the demodulation filter must be designed with special care. See Demodulation Filter Design in the Application Information section of the data sheet and consider the recommended inductors and capacitors for optimal performance. It is also important to consider PCB design and layout for optimum performance of the TAS5112A. It is recommended to follow the TAS5112F2EVM (S/N 112) design and layout guidelines for best performance.

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www.ti.com	TAS5112A
	SLES094A - OCTOBER 2003 - REVISED MARCH 2004

SYSTEM CONFIGURATION USED FOR CHARACTERIZATION

		Gate-Drive
		Power Supply
	External Power Supply
		H-Bridge
		Power Supply
	TAS5112ADFD
	1	56
1 µF	GND	GND
	2	55
	GND	GVDD	1.5 Ω
	3	54				100 nF
	GREG	BST_D
	4	53		33 nF	LPCB‡
	OTW	PVDD_D
	5	52
	SD_CD	PVDD_D		100 nF
	6	51
ERR_RCVY
	SD_AB	OUT_D
PWM_AP_1	7	50		†	10 µH		4.7 kΩ
	PWM_DP	OUT_D	1.5 Ω
PWM_AM_1	8	49			470 nF	100 nF
	PWM_DM	GND
VALID_1	9	48
	RESET_CD	GND
	10	47		1.5 Ω	10 µH	100 nF	4.7 kΩ
	PWM_CM	OUT_C
	11	46		†
	PWM_CP	OUT_C			100 nF
	12	45
100 nF	DREG_RTN	PVDD_C
	13	44			LPCB‡
PWM PROCESSOR	M3	PVDD_C		33 nF
TAS5026	14	43					1000 µF
	M2	BST_C	1.5 Ω
	15	42
	M1	BST_B			LPCB‡
	16	41		33 nF
	DREG	PVDD_B
PWM_AP_2	17	40
	PWM_BP	PVDD_B		100 nF
	18	39
PWM_AM_2
	PWM_BM	OUT_B
VALID_2	19	38		†	10 µH		4.7 kΩ
	RESET_AB	OUT_B	1.5 Ω
	20	37			470 nF
	PWM_AM	GND				100 nF
	21	36
	PWM_AP	GND
100 Ω	22	35		1.5 Ω	10 µH	100 nF	4.7 kΩ
	GND	OUT_A
	23	34		†
100 nF	DGND	OUT_A			100 nF
	24	33
	GND	PVDD_A
	25	32			LPCB‡
	DVDD	PVDD_A		33 nF
	26	31					1000 µF
1 µF	GREG	BST_A	1.5 Ω
	27	30
	GND	GVDD
	28	29				100 nF
	GND	GND

† Voltage suppressor diodes: 1SMA33CAT

‡ LPCB : Track in the PCB (1,0 mm wide and 50 mm long)

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