www.ti.com |
TAS5112A |
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SLES094A - OCTOBER 2003 - REVISED MARCH 2004 |
TM
DIGITAL AMPLIFIER POWER STAGE
FEATURES
D50 W per Channel (BTL) Into 6 Ω (Stereo)
D95-dB Dynamic Range With TAS5026
DLess Than 0.1% THD+N (1 W RMS Into 6 Ω)
DLess Than 0.2% THD+N (50 W RMS into 6 Ω)
DPower Efficiency Typically 90% Into 6-Ω Load
DSelf-Protecting Design (Undervoltage, Overtemperature and Short Conditions) With Error Reporting
DInternal Gate Drive Supply Voltage Regulator
DEMI Compliant When Used With Recommended System Design
APPLICATIONS
DDVD Receiver
DHome Theatre
DMini/Micro Component Systems
DInternet Music Appliance
DESCRIPTION
The TAS5112A is a high-performance, integrated stereo digital amplifier power stage designed to drive 6-Ω speakers at up to 50 W per channel. The device incorporates TI’s PurePath Digitalt technology and is used with a digital audio PWM processor (TAS50XX) and a simple passive demodulation filter to deliver high-quality, high-efficiency, true-digital audio amplification.
The efficiency of this digital amplifier is typically 90%, reducing the size of both the power supplies and heatsinks needed. Overcurrent protection, overtemperature protection, and undervoltage protection are built into the TAS5112A, safeguarding the device and speakers against fault conditions that could damage the system.
THD + NOISE vs OUTPUT POWER
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1 |
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RL = 6 Ω |
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TC = 75°C |
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Distortion + Noise |
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THD+N - Total Harmonic |
0.1 |
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0.01 |
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100m |
1 |
10 |
100 |
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PO - Output Power - W |
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THD + NOISE vs FREQUENCY
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1 |
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% |
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RL = 6 Ω |
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TC = 75°C |
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+ Noise |
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PO = 50 W |
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Distortion |
0.1 |
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PO = 10 W |
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Harmonic |
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PO = 1 W |
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0.01 |
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THD+N - Total |
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0.001 |
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20 |
100 |
1k |
10k |
20k |
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f - Frequency - Hz |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath Digital and PowerPAD are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products |
Copyright 2004, Texas Instruments Incorporated |
conform to specifications per the terms of Texas Instruments standard warranty. |
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Production processing does not necessarily include testing of all parameters. |
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TAS5112A |
www.ti.com |
SLES094A - OCTOBER 2003 - REVISED MARCH 2004 |
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
Terminal Assignment
The TAS5112A is offered in a thermally enhanced 56-pin TSSOP DFD (thermal pad is on the top), shown as follows.
DFD PACKAGE (TOP VIEW)
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GND |
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1 |
56 |
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GND |
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GND |
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GVDD |
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GREG |
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54 |
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BST_D |
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OTW |
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PVDD_D |
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SD_CD |
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5 |
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PVDD_D |
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SD_AB |
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OUT_D |
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PWM_DP |
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50 |
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OUT_D |
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PWM_DM |
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49 |
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GND |
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RESET_CD |
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9 |
48 |
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GND |
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PWM_CM |
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10 |
47 |
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OUT_C |
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PWM_CP |
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11 |
46 |
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OUT_C |
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DREG_RTN |
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12 |
45 |
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PVDD_C |
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M3 |
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PVDD_C |
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M2 |
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BST_C |
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M1 |
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15 |
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BST_B |
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DREG |
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PVDD_B |
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PWM_BP |
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17 |
40 |
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PVDD_B |
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PWM_BM |
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18 |
39 |
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OUT_B |
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RESET_AB |
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19 |
38 |
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OUT_B |
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PWM_AM |
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20 |
37 |
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GND |
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PWM_AP |
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21 |
36 |
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GND |
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GND |
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22 |
35 |
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OUT_A |
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DGND |
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34 |
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OUT_A |
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GND |
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24 |
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PVDD_A |
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DVDD |
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PVDD_A |
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GREG |
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BST_A |
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GND |
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30 |
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GVDD |
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GND |
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29 |
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GND |
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Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted(1)
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TAS5112A |
UNITS |
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DVDD TO DGND |
–0.3 V to 4.2 V |
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GVDD TO GND |
33.5 V |
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PVDD_X TO GND (dc voltage) |
33.5 V |
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PVDD_X TO GND (spike voltage(2)) |
48 V |
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OUT_X TO GND (dc voltage) |
33.5 V |
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OUT_X TO GND (spike voltage(2)) |
48 V |
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BST_X TO GND (dc voltage) |
48 V |
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BST_X TO GND (spike voltage(2)) |
53 V |
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GREG TO GND (3) |
14.2 V |
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PWM_XP, |
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M1, M2, M3, |
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RESET, |
SD, |
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–0.3 V to DVDD + 0.3 V |
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OTW |
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Maximum operating junction |
–40°C to 150°C |
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temperature, TJ |
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Storage temperature |
–40°C to 125°C |
(1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute- maximum-rated conditions for extended periods may affect device reliability.
(2)The duration of voltage spike should be less than 100 ns; see application note SLEA025.
(3)GREG is treated as an input when the GREG pin is overdriven by GVDD of 12 V.
Package Dissipation Ratings
PACKAGE |
RθJC |
RθJA |
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(°C/W) |
(°C/W) |
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56-pin DFD TSSOP |
1.14 |
See Note 4 |
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(4)The TAS5112A package is thermally enhanced for conductive cooling using an exposed metal pad area. It is impractical to use the device with the pad exposed to ambient air as the only heat sinking of the device.
For this reason, RθJA, a system parameter that characterizes the thermal treatment, is provided in the Application Information section
of the data sheet. An example and discussion of typical system
RθJA values are provided in the Thermal Information section. This example provides additional information regarding the power dissipation ratings. This example should be used as a reference to calculate the heat dissipation ratings for a specific application. TI application engineering provides technical support to design heatsinks if needed.
Ordering Information
TA |
PACKAGE |
DESCRIPTION |
0°C to 70°C |
TAS5112ADFD |
56-pin small TSSOP |
For the most current specification and package information, refer to our Web site at www.ti.com.
2
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www.ti.com |
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TAS5112A |
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SLES094A - OCTOBER 2003 - REVISED MARCH 2004 |
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Terminal Functions |
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TERMINAL |
FUNCTION(1) |
DESCRIPTION |
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NAME |
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NO. |
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BST_A |
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31 |
P |
High-side bootstrap supply (BST), external capacitor to OUT_A required |
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BST_B |
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42 |
P |
High-side bootstrap supply (BST), external capacitor to OUT_B required |
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BST_C |
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43 |
P |
HS bootstrap supply (BST), external capacitor to OUT_C required |
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BST_D |
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54 |
P |
HS bootstrap supply (BST), external capacitor to OUT_D required |
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DGND |
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23 |
P |
Digital I/O reference ground |
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DREG |
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16 |
P |
Digital supply voltage regulator decoupling pin, capacitor connected to GND |
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DREG_RTN |
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12 |
P |
Digital supply voltage regulator decoupling return pin |
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DVDD |
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25 |
P |
I/O reference supply input (3.3 V) |
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GND |
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1, 2, 22, 24, |
P |
Power ground |
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27, 28, 29, 36, |
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37, 48, 49, 56 |
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GREG |
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3, 26 |
P |
Gate drive voltage regulator decoupling pin, capacitor to REG_GND |
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GVDD |
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30, 55 |
P |
Voltage supply to on-chip gate drive and digital supply voltage regulators |
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M1 (TST0) |
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15 |
I |
Mode selection pin |
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M2 |
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14 |
I |
Mode selection pin |
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M3 |
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13 |
I |
Mode selection pin |
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4 |
O |
Overtemperature warning output, open drain with internal pullup resistor |
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OTW |
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OUT_A |
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34, 35 |
O |
Output, half-bridge A |
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OUT_B |
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38, 39 |
O |
Output, half-bridge B |
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OUT_C |
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46, 47 |
O |
Output, half-bridge C |
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OUT_D |
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50, 51 |
O |
Output, half-bridge D |
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PVDD_A |
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32, 33 |
P |
Power supply input for half-bridge A |
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PVDD_B |
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P |
Power supply input for half-bridge B |
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PVDD_C |
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44, 45 |
P |
Power supply input for half-bridge C |
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PVDD_D |
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52, 53 |
P |
Power supply input for half-bridge D |
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PWM_AM |
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20 |
I |
Input signal (negative), half-bridge A |
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PWM_AP |
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21 |
I |
Input signal (positive), half-bridge A |
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PWM_BM |
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18 |
I |
Input signal (negative), half-bridge B |
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PWM_BP |
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17 |
I |
Input signal (positive), half-bridge B |
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PWM_CM |
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10 |
I |
Input signal (negative), half-bridge C |
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PWM_CP |
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I |
Input signal (positive), half-bridge C |
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PWM_DM |
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8 |
I |
Input signal (negative), half-bridge D |
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PWM_DP |
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I |
Input signal (positive), half-bridge D |
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19 |
I |
Reset signal, active low |
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RESET_AB |
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9 |
I |
Reset signal, active low |
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RESET_CD |
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6 |
O |
Shutdown signal for half-bridges A and B, active-low |
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SD_AB |
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5 |
O |
Shutdown signal for half-bridges C and D, active-low |
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SD_CD |
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(1) I = input, O = Output, P = Power
3
TAS5112A |
www.ti.com |
SLES094A - OCTOBER 2003 - REVISED MARCH 2004 |
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FUNCTIONAL BLOCK DIAGRAM
PWM_AP
RESET
PWM_BP
OTW
SD
BST_A
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GREG |
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PVDD_A |
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Drive |
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PWM |
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Timing |
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OUT_A |
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Receiver |
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Control |
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Gate |
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GND |
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Protection A |
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BST_B |
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GREG |
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PVDD_B |
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Protection B |
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Gate |
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Drive |
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PWM |
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Timing |
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OUT_B |
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Receiver |
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Control |
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Gate |
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Drive |
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To Protection |
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GND |
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Blocks |
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DREG |
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DREG |
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GVDD |
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GREG |
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OT |
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GREG |
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GREG |
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Protection |
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DREG |
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GREG |
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UVP |
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DREG_RTN |
DREG_RTN |
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This diagram shows one channel.
4
www.ti.com |
|
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TAS5112A |
|||
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|
SLES094A - OCTOBER 2003 - REVISED MARCH 2004 |
|||||
RECOMMENDED OPERATING CONDITIONS |
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MIN |
TYP |
MAX |
UNIT |
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DVDD |
Digital supply (1) |
Relative to DGND |
3 |
3.3 |
3.6 |
V |
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GVDD |
Supply for internal gate drive and logic |
Relative to GND |
16 |
29.5 |
30.5 |
V |
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regulators |
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PVDD_x |
Half-bridge supply |
Relative to GND, RL= 6 Ω to 8 Ω |
0 |
29.5 |
30.5 |
V |
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TJ |
Junction temperature |
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0 |
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125 |
_C |
(1) It is recommended for DVDD to be connected to DREG via a 100-Ω resistor.
ELECTRICAL CHARACTERISTICS
PVDD_X = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-Ω resistor, RL = 6 Ω, 8X fs = 384 kHz, unless otherwise noted
|
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TYPICAL |
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OVER TEMPERATURE |
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SYMBOL |
PARAMETER |
TEST CONDITIONS |
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TA=25°C |
TA=25°C |
TCase= |
TA=40°C |
UNITS |
MIN/TYP/ |
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75°C |
TO 85°C |
MAX |
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AC PERFORMANCE, BTL Mode, 1 kHz |
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RL = 8 Ω, THD = 0.2%, |
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40 |
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W |
Typ |
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AES17 filter, 1 kHz |
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RL = 8 Ω, THD = 10%, AES17 |
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50 |
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W |
Typ |
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filter, 1 kHz |
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Po |
Output power |
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RL = 6 Ω, THD = 0.2%, |
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50 |
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W |
Typ |
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AES17 filter, 1 kHz |
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RL = 6 Ω, THD = 10%, AES17 |
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62 |
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W |
Typ |
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filter, 1 kHz |
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Po = 1 W/ channel, RL = 6 Ω, |
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0.03% |
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Typ |
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AES17 filter |
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THD+N |
Total harmonic distortion |
Po = 10 W/channel, RL = 6 Ω, |
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0.04% |
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Typ |
+ noise |
AES17 filter |
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Po = 50 W/channel, RL = 6 Ω, |
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0.2% |
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Typ |
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AES17 filter |
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Vn |
Output integrated voltage |
A-weighted, mute, RL = 6 Ω,, |
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260 |
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µV |
Max |
noise |
20 Hz to 20 kHz, AES17 filter |
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SNR |
Signal-to-noise ratio |
A-weighted, AES17 filter |
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96 |
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dB |
Typ |
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DR |
Dynamic range |
f = 1 kHz, A-weighted, |
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96 |
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dB |
Typ |
AES17 filter |
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INTERNAL VOLTAGE REGULATOR |
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DREG |
Voltage regulator |
Io = 1 mA, |
3.1 |
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V |
Typ |
PVDD = 18 V-30.5 V |
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GREG |
Voltage regulator |
Io = 1.2 mA, |
13.4 |
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V |
Typ |
PVDD = 18 V-30.5 V |
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IVGDD |
GVDD supply current, |
fS = 384 kHz, no load, 50% |
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24 |
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mA |
Max |
operating |
duty cycle |
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IDVDD |
DVDD supply current, |
fS = 384 kHz, no load |
1 |
5 |
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mA |
Max |
operating |
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OUTPUT STAGE MOSFETs |
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RDSon,LS |
Forward on-resistance, |
TJ = 25°C |
155 |
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mΩ |
Typ |
low side |
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RDSon,HS |
Forward on-resistance, |
TJ = 25°C |
155 |
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mΩ |
Typ |
high side |
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5
TAS5112A |
www.ti.com |
SLES094A - OCTOBER 2003 - REVISED MARCH 2004 |
|
ELECTRICAL CHARACTERISTICS
PVDD_x = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-Ω resistor, RL = 6 Ω, 8X fs = 384 kHz, unless otherwise noted
|
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TYPICAL |
|
OVER TEMPERATURE |
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||
SYMBOL |
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PARAMETER |
TEST CONDITIONS |
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TA=25°C |
TA=25°C |
TCase= |
TA=40°C |
UNITS |
MIN/TYP/ |
|||||
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75°C |
TO 85°C |
MAX |
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INPUT/OUTPUT PROTECTION |
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Set the DUT in normal |
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operation mode with all the |
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6.9 |
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V |
Min |
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Undervoltage protection |
protections enabled. Sweep |
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Vuvp,G |
GVDD up and down. Monitor |
7.4 |
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limit, GVDD |
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SD output. Record the |
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7.9 |
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V |
Max |
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GREG reading when |
SD |
is |
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triggered. |
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OTW |
Overtemperature warning, |
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125 |
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°C |
Typ |
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junction temperature |
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OTE |
Overtemperature error, |
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150 |
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°C |
Typ |
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junction temperature |
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OC |
Overcurrent protection |
See Note 1. |
6.7 |
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A |
Typ |
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STATIC DIGITAL SPECIFICATION |
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PWM_AP, PWM_BP, M1, |
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M2, M3, SD, OTW |
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VIH |
High-level input voltage |
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2 |
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V |
Min |
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DVDD |
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V |
Max |
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VIL |
Low-level input voltage |
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0.8 |
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V |
Max |
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Leakage |
Input leakage current |
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-10 |
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µA |
Min |
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10 |
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µA |
Max |
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OTW/SHUTDOWN (SD) |
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Internally pull up R from |
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30 |
22.5 |
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kΩ |
Min |
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OTW/SD to DVDD |
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VOL |
Low-level output voltage |
IO = 4 mA |
|
0.4 |
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V |
Max |
(1)To optimize device performance and prevent overcurrent (OC) protection tripping, the demodulation filter must be designed with special care. See Demodulation Filter Design in the Application Information section of the data sheet and consider the recommended inductors and capacitors for optimal performance. It is also important to consider PCB design and layout for optimum performance of the TAS5112A. It is recommended to follow the TAS5112F2EVM (S/N 112) design and layout guidelines for best performance.
6
www.ti.com |
TAS5112A |
|
SLES094A - OCTOBER 2003 - REVISED MARCH 2004 |
SYSTEM CONFIGURATION USED FOR CHARACTERIZATION
|
|
Gate-Drive |
|
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Power Supply |
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External Power Supply |
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H-Bridge |
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Power Supply |
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TAS5112ADFD |
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1 |
56 |
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1 µF |
GND |
GND |
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2 |
55 |
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GND |
GVDD |
1.5 Ω |
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3 |
54 |
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100 nF |
||
|
GREG |
BST_D |
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4 |
53 |
|
33 nF |
LPCB‡ |
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OTW |
PVDD_D |
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5 |
52 |
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SD_CD |
PVDD_D |
|
100 nF |
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6 |
51 |
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ERR_RCVY |
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SD_AB |
OUT_D |
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PWM_AP_1 |
7 |
50 |
|
† |
10 µH |
|
4.7 kΩ |
PWM_DP |
OUT_D |
1.5 Ω |
|
||||
PWM_AM_1 |
8 |
49 |
|
|
470 nF |
100 nF |
|
PWM_DM |
GND |
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|||
VALID_1 |
9 |
48 |
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RESET_CD |
GND |
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10 |
47 |
|
1.5 Ω |
10 µH |
100 nF |
4.7 kΩ |
|
PWM_CM |
OUT_C |
|
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||
|
11 |
46 |
|
† |
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PWM_CP |
OUT_C |
|
100 nF |
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12 |
45 |
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100 nF |
DREG_RTN |
PVDD_C |
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13 |
44 |
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LPCB‡ |
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|||
PWM PROCESSOR |
M3 |
PVDD_C |
|
33 nF |
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|
TAS5026 |
14 |
43 |
|
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|
1000 µF |
|
M2 |
BST_C |
1.5 Ω |
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15 |
42 |
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M1 |
BST_B |
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|
LPCB‡ |
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16 |
41 |
|
33 nF |
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DREG |
PVDD_B |
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PWM_AP_2 |
17 |
40 |
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PWM_BP |
PVDD_B |
|
100 nF |
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18 |
39 |
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|
|
PWM_AM_2 |
|
|
|
|
|
||
PWM_BM |
OUT_B |
|
|
|
|
|
|
VALID_2 |
19 |
38 |
|
† |
10 µH |
|
4.7 kΩ |
RESET_AB |
OUT_B |
1.5 Ω |
|
||||
|
20 |
37 |
|
|
470 nF |
|
|
|
PWM_AM |
GND |
|
|
100 nF |
|
|
|
21 |
36 |
|
|
|
|
|
|
PWM_AP |
GND |
|
|
|
|
|
100 Ω |
22 |
35 |
|
1.5 Ω |
10 µH |
100 nF |
4.7 kΩ |
|
GND |
OUT_A |
|
|
|
||
|
23 |
34 |
|
† |
|
|
|
100 nF |
DGND |
OUT_A |
|
100 nF |
|
|
|
24 |
33 |
|
|
|
|
||
|
|
|
|
|
|||
|
GND |
PVDD_A |
|
|
|
|
|
|
25 |
32 |
|
|
LPCB‡ |
|
|
|
DVDD |
PVDD_A |
|
33 nF |
|
|
|
|
26 |
31 |
|
|
|
|
1000 µF |
1 µF |
GREG |
BST_A |
1.5 Ω |
|
|
|
|
27 |
30 |
|
|
|
|
||
|
GND |
GVDD |
|
|
|
|
|
|
28 |
29 |
|
|
|
100 nF |
|
|
GND |
GND |
|
|
|
||
|
|
|
|
|
|
† Voltage suppressor diodes: 1SMA33CAT
‡ LPCB : Track in the PCB (1,0 mm wide and 50 mm long)
7