TAS5111
TAS5111
www.ti.com
SLES049D − JULY 2003 − REVISED MARCH 2004
TM
DIGITAL AMPLIFIER POWER STAGE
FEATURES
D70-W RMS Power (BTL) Into 4 Ω With Less
Than 0.2% THD+N
D95-dB Dynamic Range (TDAA System With TAS5026)
DPower Efficiency Greater Than 90% Into 4-Ω and 8-Ω Loads
−Smaller Power Supplies
DSelf-Protecting Design With Autorecovery
D32-Pin TSSOP (DAD) PowerPAD Package
D3.3-V Digital Interface
DEMI-Compliant When Used With Recommended System Design
APPLICATIONS
DDVD Receiver
THD + NOISE vs OUTPUT POWER
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RL = 4 Ω |
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TC = 75°C |
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Distortion + Noise |
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0.1 |
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THD+N − Total Harmonic |
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0.01 |
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100m |
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10 |
100 |
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PO − Output Power − W |
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DHome Theatre
DMini/Micro Component Systems
DInternet Music Appliance
DESCRIPTION
The TAS5111 is a high-performance digital amplifier power stage designed to drive a 4-Ω speaker up to 70 W with 0.2% distortion plus noise. The device incorporates TI’s PurePath Digital technology and is used with a digital audio PWM processor (TAS50XX) and a simple passive demodulation filter to deliver high-quality, high-efficiency digital audio amplification.
The efficiency of this digital amplifier can be greater than 90%, depending on the system design. Overcurrent protection, overtemperature protection, and undervoltage protection are built into the TAS5111, safeguarding the device and speakers against fault conditions that could damage the system.
THD + NOISE vs FREQUENCY
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RL = 4 Ω |
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TC = 75°C |
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+ Noise |
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Distortion |
0.1 |
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PO = 70 W |
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PO = 1 W |
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Harmonic |
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0.01 |
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PO = 10 W |
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THD+N − Total |
0.001 |
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20 |
100 |
1k |
10k |
20k |
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f − Frequency − Hz |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath Digital and PowerPAD are trademarks of Texas Instruments. Other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products |
Copyright 2004, Texas Instruments Incorporated |
conform to specifications per the terms of Texas Instruments standard warranty. |
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Production processing does not necessarily include testing of all parameters. |
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TAS5111 |
www.ti.com |
SLES049D − JULY 2003 − REVISED MARCH 2004 |
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
Terminal Assignment
The TAS5111 is offered in a thermally enhanced 32-pin TSSOP surface-mount package (DAD), which has the thermal pad on top.
DAD PACKAGE
(TOP VIEW)
PWM_BP |
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GVDD |
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GND |
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GND |
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RESET |
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BST_B |
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DREG_RTN |
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PVDD_B |
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GREG |
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PVDD_B |
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M3 |
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OUT_B |
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DREG |
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OUT_B |
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DGND |
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GND |
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M1 |
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GND |
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M2 |
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OUT_A |
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DVDD |
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OUT_A |
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SD |
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DGND |
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PVDD_A |
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OTW |
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BST_A |
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GND |
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GND |
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PWM_AP |
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GVDD |
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
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TAS5111 |
UNITS |
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DVDD TO DGND |
–0.3 V to 4.2 V |
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GVDD TO GND |
33.5 V |
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PVDD_X TO GND (dc voltage) |
33.5 V |
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PVDD_X TO GND (spike voltage(2)) |
48 V |
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OUT_X TO GND (dc voltage) |
33.5 V |
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OUT_X TO GND (spike voltage(2)) |
48 V |
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BST_X TO GND (dc voltage) |
48 V |
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BST_X TO GND (spike voltage(2)) |
53 V |
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GREG TO GND (3) |
14.2 V |
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PWM_XP, |
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M1, M2, M3, |
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RESET, |
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–0.3 V to DVDD + 0.3 V |
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OTW |
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Maximum operating junction |
–40°C to 150°C |
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temperature, TJ |
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Storage temperature |
–40°C to 125°C |
(1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute- maximum-rated conditions for extended periods may affect device reliability.
(2)The duration of a voltage spike should be less than 100 ns.
(3)GREG is treated as an input when the GREG pin is overdriven by a GVDD voltage of 12 V.
PACKAGE DISSIPATION RATINGS
PACKAGE |
RθJC |
RθJA |
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(°C/W) |
(°C/W) |
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32-Pin DAD TSSOP |
1.69 |
See Note 1 |
(1) The TAS5111 package is thermally enhanced for conductive cooling using an exposed metal pad area. It is impractical to use the device with the pad exposed to ambient air as the only means for heat dissipation.
For this reason, RθJA, a system parameter that characterizes the thermal treatment, is provided in the Application Information section of the data sheet. An example and discussion of typical system
RθJA values are provided in the Thermal Information section. This example provides additional information regarding the power dissipation ratings. This example should be used as a reference to calculate the heat dissipation ratings for a specific application. TI application engineering provides technical support to design heatsinks if needed. Also, for additional general information on PowerPad packages, see TI document SLMA002.
ORDERING INFORMATION
TA |
PACKAGE |
DESCRIPTION |
0°C to 70°C |
TAS5111DAD |
32-pin small TSSOP |
For the most current specification and package information, refer to the TI Web site at www.ti.com.
2
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www.ti.com |
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TAS5111 |
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SLES049D − JULY 2003 − REVISED MARCH 2004 |
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Terminal Functions |
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TERMINAL |
FUNCTION(1) |
DESCRIPTION |
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NO. |
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BST_A |
19 |
P |
High side bootstrap supply (BST), external capacitor to OUT_A required |
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BST_B |
30 |
P |
High side bootstrap supply (BST), external capacitor to OUT_B required |
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DGND |
8, 13 |
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I/O reference ground |
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DREG |
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Digital supply voltage regulator decoupling pin, capacitor connected to DREG_RTN |
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DREG_RTN |
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Decoupling return pin |
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DVDD |
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I/O reference supply input (3.3 V): 100 Ω to DREG |
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GND |
2,15, 18, |
P |
Power ground |
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24, 25, |
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31 |
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GREG |
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P |
Gate drive voltage regulator decoupling pin, capacitor to GND |
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GVDD |
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P |
Voltage supply to on-chip gate drive and digital supply voltage regulators |
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M1 |
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I |
Mode selection pin |
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M2 |
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Mode selection pin |
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M3 |
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Mode selection pin |
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Overtemperature warning output, open drain with internal pullup resistor |
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OTW |
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OUT_A |
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Output, half-bridge A |
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OUT_B |
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O |
Output, half-bridge B |
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PVDD_A |
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P |
Power supply input for half-bridge A |
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PVDD_B |
28, 29 |
P |
Power supply input for half-bridge B |
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PWM_AP |
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I |
Input signal, half-bridge A |
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PWM_BP |
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I |
Input signal, half-bridge B |
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Reset signal, active low |
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Shutdown signal for half-bridges A and B |
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(1) I = input, O = Output, P = Power
3
TAS5111 |
www.ti.com |
SLES049D − JULY 2003 − REVISED MARCH 2004 |
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FUNCTIONAL BLOCK DIAGRAM
PWM_AP
RESET
PWM_BP
OTW
SD
BST_A
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GREG |
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PVDD_A |
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Timing |
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OUT_A |
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Receiver |
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Control |
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GND |
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Protection A |
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BST_B |
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GREG |
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Protection B |
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OUT_B |
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Receiver |
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GVDD |
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GREG |
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OT |
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GREG |
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Protection |
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DREG_RTN |
DREG_RTN |
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4
www.ti.com |
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TAS5111 |
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SLES049D − JULY 2003 − REVISED MARCH 2004 |
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RECOMMENDED OPERATING CONDITIONS |
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MIN |
TYP |
MAX |
UNIT |
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DVDD |
Digital supply (1) |
Relative to DGND |
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3 |
3.3 |
3.6 |
V |
GVDD |
Supply for internal gate drive and logic |
Relative to GND |
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16 |
29.5 |
30.5 |
V |
regulators |
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PVDD_x |
Half-bridge supply |
Relative to GND, RL= 4 Ω to 8 Ω |
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0 |
29.5 |
30.5 |
V |
TJ |
Junction temperature |
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0 |
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125 |
_C |
(1) It is recommended for DVDD to be connected to DREG via a 100-Ω resistor.
ELECTRICAL CHARACTERISTICS
PVDD_X = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-Ω resistor, RL = 4 Ω, 8X fs = 384 kHz, unless otherwise noted
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TYPICAL |
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OVER TEMPERATURE |
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SYMBOL |
PARAMETER |
TEST CONDITIONS |
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TA = 25°C |
TA = 25°C |
TC = 75°C |
TA = 40°C |
UNITS |
MIN/TYP/ |
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to 85°C |
MAX |
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AC PERFORMANCE, BTL Mode, 1 kHz |
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RL = 8 Ω, THD = 0.2%, |
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40 |
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W |
Typ |
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AES17 filter |
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RL = 8 Ω, THD = 10%, AES17 |
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53 |
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W |
Typ |
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filter |
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RL = 6 Ω, THD = 0.2%, |
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53 |
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W |
Typ |
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AES17 filter |
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Po |
Output power |
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RL = 6 Ω, THD = 10%, AES17 |
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68 |
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W |
Typ |
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filter |
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RL = 4 Ω, THD = 0.2%, |
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74 |
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W |
Typ |
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AES17 filter |
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RL = 4 Ω, THD = 10%, AES17 |
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93 |
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W |
Typ |
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filter |
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Po = 1 W/ channel, RL = 4 Ω, |
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0.05% |
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Typ |
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AES17 filter |
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THD+N |
Total harmonic |
Po = 10 W/channel, RL = 4 Ω, |
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0.03% |
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Typ |
distortion + noise |
AES17 filter |
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Po = 70 W/channel, RL = 4 Ω, |
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0.2% |
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Typ |
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AES17 filter |
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Vn |
Output integrated |
A-weighted, mute, RL = 4 Ω, |
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295 |
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µV |
Max |
voltage noise |
20 Hz to 20 kHz, AES17 filter |
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SNR |
Signal-to-noise ratio |
A-weighted, AES17 filter |
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95 |
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dB |
Typ |
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DR |
Dynamic range |
f = 1 kHz, A-weighted, |
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95 |
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dB |
Typ |
AES17 filter |
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INTERNAL VOLTAGE REGULATOR |
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DREG |
Voltage regulator |
Io = 1 mA, |
3.1 |
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V |
Min |
PVDD = 18 V−30.5 V |
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V |
Max |
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GREG |
Voltage regulator |
Io = 1.2 mA, |
13.4 |
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V |
Min |
PVDD = 18 V−30.5 V |
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V |
Max |
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IVGDD |
GVDD supply current, |
fS = 384 kHz, no load, |
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27 |
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mA |
Max |
operating |
50% duty cycle |
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IDVDD |
DVDD supply current, |
fS = 384 kHz, no load |
1 |
5 |
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mA |
Max |
operating |
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OUTPUT STAGE MOSFETs |
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Ron,LS |
Forward on-resistance, |
TJ = 25°C |
120 |
132 |
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mΩ |
Max |
low side |
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Ron,HS |
Forward on-resistance, |
TJ = 25°C |
120 |
132 |
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mΩ |
Max |
high side |
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5