TEXAS INSTRUMENTS TAS5111 Technical data

TAS5111

TAS5111

www.ti.com

SLES049D − JULY 2003 − REVISED MARCH 2004

TM

DIGITAL AMPLIFIER POWER STAGE

FEATURES

D70-W RMS Power (BTL) Into 4 Ω With Less

Than 0.2% THD+N

D95-dB Dynamic Range (TDAA System With TAS5026)

DPower Efficiency Greater Than 90% Into 4-Ω and 8-Ω Loads

−Smaller Power Supplies

DSelf-Protecting Design With Autorecovery

D32-Pin TSSOP (DAD) PowerPAD Package

D3.3-V Digital Interface

DEMI-Compliant When Used With Recommended System Design

APPLICATIONS

DDVD Receiver

THD + NOISE vs OUTPUT POWER

	1
%		RL = 4 Ω
−		TC = 75°C
Distortion + Noise
	0.1
THD+N − Total Harmonic
	0.01
	100m	1	10	100
		PO − Output Power − W

DHome Theatre

DMini/Micro Component Systems

DInternet Music Appliance

DESCRIPTION

The TAS5111 is a high-performance digital amplifier power stage designed to drive a 4-Ω speaker up to 70 W with 0.2% distortion plus noise. The device incorporates TI’s PurePath Digital technology and is used with a digital audio PWM processor (TAS50XX) and a simple passive demodulation filter to deliver high-quality, high-efficiency digital audio amplification.

The efficiency of this digital amplifier can be greater than 90%, depending on the system design. Overcurrent protection, overtemperature protection, and undervoltage protection are built into the TAS5111, safeguarding the device and speakers against fault conditions that could damage the system.

THD + NOISE vs FREQUENCY

	1
%		RL = 4 Ω
−		TC = 75°C
+ Noise
Distortion	0.1		PO = 70 W
		PO = 1 W
Harmonic
	0.01		PO = 10 W
THD+N − Total	0.001
	20	100	1k	10k	20k
			f − Frequency − Hz

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PurePath Digital and PowerPAD are trademarks of Texas Instruments. Other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products	Copyright 2004, Texas Instruments Incorporated
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.

TAS5111	www.ti.com
SLES049D − JULY 2003 − REVISED MARCH 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

GENERAL INFORMATION

Terminal Assignment

The TAS5111 is offered in a thermally enhanced 32-pin TSSOP surface-mount package (DAD), which has the thermal pad on top.

DAD PACKAGE

(TOP VIEW)

PWM_BP						1	32				GVDD
	GND					2	31				GND
	RESET					3	30				BST_B
DREG_RTN						4	29				PVDD_B
	GREG					5	28				PVDD_B
	M3					6		27			OUT_B
	DREG					7		26			OUT_B
	DGND					8		25			GND
	M1					9		24			GND
	M2					10		23			OUT_A
	DVDD					11		22			OUT_A
	SD					12	21				PVDD_A
	DGND					13	20				PVDD_A
	OTW					14	19				BST_A
	GND					15	18				GND
PWM_AP						16	17				GVDD

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)

		TAS5111				UNITS
	DVDD TO DGND					–0.3 V to 4.2 V
	GVDD TO GND					33.5 V
	PVDD_X TO GND (dc voltage)					33.5 V
	PVDD_X TO GND (spike voltage(2))					48 V
	OUT_X TO GND (dc voltage)					33.5 V
	OUT_X TO GND (spike voltage(2))					48 V
	BST_X TO GND (dc voltage)					48 V
	BST_X TO GND (spike voltage(2))					53 V
	GREG TO GND (3)					14.2 V
	PWM_XP,		M1, M2, M3,
		RESET,		SD,		–0.3 V to DVDD + 0.3 V
	OTW
	Maximum operating junction					–40°C to 150°C
	temperature, TJ
	Storage temperature					–40°C to 125°C

(1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute- maximum-rated conditions for extended periods may affect device reliability.

(2)The duration of a voltage spike should be less than 100 ns.

(3)GREG is treated as an input when the GREG pin is overdriven by a GVDD voltage of 12 V.

PACKAGE DISSIPATION RATINGS

	PACKAGE	RθJC	RθJA
		(°C/W)	(°C/W)
	32-Pin DAD TSSOP	1.69	See Note 1

(1) The TAS5111 package is thermally enhanced for conductive cooling using an exposed metal pad area. It is impractical to use the device with the pad exposed to ambient air as the only means for heat dissipation.

For this reason, RθJA, a system parameter that characterizes the thermal treatment, is provided in the Application Information section of the data sheet. An example and discussion of typical system

RθJA values are provided in the Thermal Information section. This example provides additional information regarding the power dissipation ratings. This example should be used as a reference to calculate the heat dissipation ratings for a specific application. TI application engineering provides technical support to design heatsinks if needed. Also, for additional general information on PowerPad packages, see TI document SLMA002.

ORDERING INFORMATION

TA	PACKAGE	DESCRIPTION
0°C to 70°C	TAS5111DAD	32-pin small TSSOP

For the most current specification and package information, refer to the TI Web site at www.ti.com.

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		www.ti.com					TAS5111
							SLES049D − JULY 2003 − REVISED MARCH 2004
							Terminal Functions
			TERMINAL			FUNCTION(1)	DESCRIPTION
	NAME				NO.
	BST_A				19	P	High side bootstrap supply (BST), external capacitor to OUT_A required
	BST_B				30	P	High side bootstrap supply (BST), external capacitor to OUT_B required
	DGND				8, 13	P	I/O reference ground
	DREG				7	P	Digital supply voltage regulator decoupling pin, capacitor connected to DREG_RTN
	DREG_RTN				4	P	Decoupling return pin
	DVDD				11	P	I/O reference supply input (3.3 V): 100 Ω to DREG
	GND				2,15, 18,	P	Power ground
					24, 25,
					31
	GREG				5	P	Gate drive voltage regulator decoupling pin, capacitor to GND
	GVDD				17, 32	P	Voltage supply to on-chip gate drive and digital supply voltage regulators
	M1				9	I	Mode selection pin
	M2				10	I	Mode selection pin
	M3				6	I	Mode selection pin
					14	O	Overtemperature warning output, open drain with internal pullup resistor
	OTW
	OUT_A				22, 23	O	Output, half-bridge A
	OUT_B				26, 27	O	Output, half-bridge B
	PVDD_A				20, 21	P	Power supply input for half-bridge A
	PVDD_B				28, 29	P	Power supply input for half-bridge B
	PWM_AP				16	I	Input signal, half-bridge A
	PWM_BP				1	I	Input signal, half-bridge B
					3	I	Reset signal, active low
	RESET
					12	O	Shutdown signal for half-bridges A and B
	SD

(1) I = input, O = Output, P = Power

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TAS5111	www.ti.com
SLES049D − JULY 2003 − REVISED MARCH 2004

FUNCTIONAL BLOCK DIAGRAM

PWM_AP

RESET

PWM_BP

OTW

SD

BST_A

GREG

PVDD_A

Gate

Drive

PWM

Timing

OUT_A

Receiver

Control

Gate

Drive

GND

Protection A

BST_B

GREG

PVDD_B

Protection B

Gate

Drive

PWM

Timing

OUT_B

Receiver

Control

Gate

Drive

To Protection

GND

Blocks

DREG

DREG

GVDD

GREG

OT

GREG

GREG

Protection

DREG

GREG

UVP

DREG_RTN	DREG_RTN

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www.ti.com						TAS5111
			SLES049D − JULY 2003 − REVISED MARCH 2004
RECOMMENDED OPERATING CONDITIONS
				MIN	TYP	MAX	UNIT
DVDD	Digital supply (1)	Relative to DGND		3	3.3	3.6	V
GVDD	Supply for internal gate drive and logic	Relative to GND		16	29.5	30.5	V
	regulators
PVDD_x	Half-bridge supply	Relative to GND, RL= 4 Ω to 8 Ω		0	29.5	30.5	V
TJ	Junction temperature			0		125	_C

(1) It is recommended for DVDD to be connected to DREG via a 100-Ω resistor.

ELECTRICAL CHARACTERISTICS

PVDD_X = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-Ω resistor, RL = 4 Ω, 8X fs = 384 kHz, unless otherwise noted

			TYPICAL		OVER TEMPERATURE
SYMBOL	PARAMETER	TEST CONDITIONS
			TA = 25°C	TA = 25°C	TC = 75°C	TA = 40°C	UNITS	MIN/TYP/
						to 85°C		MAX
AC PERFORMANCE, BTL Mode, 1 kHz
		RL = 8 Ω, THD = 0.2%,			40		W	Typ
		AES17 filter
		RL = 8 Ω, THD = 10%, AES17			53		W	Typ
		filter
		RL = 6 Ω, THD = 0.2%,			53		W	Typ
		AES17 filter
Po	Output power
		RL = 6 Ω, THD = 10%, AES17			68		W	Typ
		filter
		RL = 4 Ω, THD = 0.2%,			74		W	Typ
		AES17 filter
		RL = 4 Ω, THD = 10%, AES17			93		W	Typ
		filter
		Po = 1 W/ channel, RL = 4 Ω,			0.05%			Typ
		AES17 filter
THD+N	Total harmonic	Po = 10 W/channel, RL = 4 Ω,			0.03%			Typ
	distortion + noise	AES17 filter
		Po = 70 W/channel, RL = 4 Ω,			0.2%			Typ
		AES17 filter
Vn	Output integrated	A-weighted, mute, RL = 4 Ω,			295		µV	Max
	voltage noise	20 Hz to 20 kHz, AES17 filter
SNR	Signal-to-noise ratio	A-weighted, AES17 filter			95		dB	Typ
DR	Dynamic range	f = 1 kHz, A-weighted,			95		dB	Typ
		AES17 filter
INTERNAL VOLTAGE REGULATOR
DREG	Voltage regulator	Io = 1 mA,	3.1				V	Min
		PVDD = 18 V−30.5 V					V	Max
GREG	Voltage regulator	Io = 1.2 mA,	13.4				V	Min
		PVDD = 18 V−30.5 V					V	Max
IVGDD	GVDD supply current,	fS = 384 kHz, no load,		27			mA	Max
	operating	50% duty cycle
IDVDD	DVDD supply current,	fS = 384 kHz, no load	1	5			mA	Max
	operating
OUTPUT STAGE MOSFETs
Ron,LS	Forward on-resistance,	TJ = 25°C	120	132			mΩ	Max
	low side
Ron,HS	Forward on-resistance,	TJ = 25°C	120	132			mΩ	Max
	high side

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