D50 W RMS Power Into 6 Ω at 10% THD
D40 W RMS Power Into 6 Ω at 0.1% THD
DTHD+N < 0.09% Typical (1-kHz Input Signal)
D93-dB Dynamic Range (TDAA System)
DPower Efficiency > 90% Into 6-Ω and 8-Ω
Load
DLow Profile, SMD 32-Pin PowerPAD
Package
DSelf-Protecting Design
D3.3-V Digital Interface
DEMI Compliant When Used With
Recommended System Design
APPLICATIONS
DDVD Receiver
DHome Theater
DMini/Micro Component Systems
DInternet Music Appliance
DCar Audio Amplifiers and Head Units
TYPICAL TDAA STEREO AUDIO SYSTEM
DESCRIPTION
The TAS5110A is a high-performance true-digital audio
amplifier (TDAA) power stage, designed to drive 50 W per
channel. The TAS5110A incorporates TI’s Equibit and
PurePath Digital technology and is used in conjunction
with a digital audio PWM processor (TAS50xx) to deliver
high-power , true-digital audio amplification. The efficiency
of this digital amplifier can be greater than 90%, reducing
the size of both the power supplies and heat sinks needed.
The TAS5110A accepts a mono PWM 3.3-V input and
controls the switching of an internal CMOS H-bridge.
When used with the TAS50xx PWM processor, system
performance of less than 0.09% THD is attainable.
Overcurrent protection, overtemperature, and
undervoltage protections are built into the TAS5110A,
safeguarding the H-bridge and speakers against output
shorts, overvoltage conditions, and other fault conditions
that could damage the system.
Left
Digital Audio
• TAS3001
• DSP
• S/PDIF
• 1394
• Volume
• EQ
• DRC
• Bass
• Treble
Please be aware that an important notice concerning availability , standard warranty, and use in critical applications of TexasInstruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerP AD, PurePath Digital, and Equibit are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
• Serial Audio Input Port
• Internal PLL
• PWM Processor
TAS50xx
Right
TAS5110A
TAS5110A
• Two H-Bridge Power Devices
Copyright 2003, Texas Instruments Incorporated
L-C
Filter
L-C
Filter
TAS5110A
www.ti.com
SLES079A – APRIL 2003 – REVISED MA Y 2003
TERMINAL ASSIGNMENTS
The TAS51 10A is offered in a thermally enhanced 32-pin TSSOP surface-mount package (DAD). The DAD package
has the PowerPAD on top.
Figure 1. System #1: Stereo Configuration With a TAS3001 Digital Audio Processor
TAS30xx
• Digital Parametric EQ
• Volume
• DRC
• Bass
• Treble
• Serial Audio Input Port
• Internal PLL
TAS50xx
Left
Right
TAS5110A
TAS5110A
• Two H-Bridges
www.ti.com
L-C
Filter
L-C
Filter
Home Theater
DVD 6-Channel
Encoded Digital
Audio Source
6
TI DSP
• Dolby AC-3
• DTS
• Volume
• EQ
• DRC
• Bass
• Treble
TAS50xx
TAS50xx
TAS50xx
CH1
CH2
CH3
CH4
CH5
CH6
TAS5110A
TAS5110A
TAS5110A
TAS5110A
TAS5110A
TAS5110A
L-C
Filter
L-C
Filter
L-C
Filter
L-C
Filter
L-C
Filter
L-C
Filter
Left
Right
Surround Left
Surround Right
Center
Subwoofer
Figure 2. System #2: 6-Channel Audio Playback
4
TAS5110A
www.ti.com
SLES079A – APRIL 2003 – REVISED MAY 2003
Terminal Functions
TERMINAL
NAMEDAD
NO.
BIAS_A6IConnect external resistor to DVSS.
BIAS_B5IConnect external resistor to DVSS.
BOOTSTRAPA19OBootstrap capacitor pin for H-bridge A
BOOTSTRAPB30OBootstrap capacitor pin for H-bridge B
DVDD11—3.3-V digital voltage supply for logic
DVSS8, 9,10—Digital ground for logic is internally connected to PVSS. All three pins must be tied together but not
ERR114OError/warning report indicator . This output is open drain with internal pullup resistor .
ERR013OError/warning report indicator . This output is open drain with internal pullup resistor .
LDROUTA18OLow-voltage drop-out regulator output A (not to be used to supply current to external circuitry)
LDROUTB31OLow-voltage drop-out regulator output B (not to be used to supply current to external circuitry)
OUTPUTA22, 23OH-bridge output A
OUTPUTB26, 27OH-bridge output B
PVDDA120, 21—High-voltage power supply, H-bridge A
PVDDA217—High-voltage power supply for low-dropout voltage regulator A-side
PVDDB128, 29—High-voltage power supply, H-bridge B
PVDDB232—High-voltage power supply for low-dropout voltage regulator B-side
PVSS24, 25—High-voltage power supply ground
PWDN4IPower down = 0, normal mode = 1
PWM_AM15IPWM input A(–)
PWM_AP16IPWM input A(+)
PWM_BP1IPWM input B(+)
PWM_BM2IPWM input B(–)
RESET3IReset and mute mode = 0, normal mode = 1; when in reset mode, H-bridge MOSFETs are in low-low
SHUTDOWN12ODevice is in shutdown due to fault condition, normal mode = 1, shutdown = 0; when device is in
VRFILT7OA filter capacitor must be added between the VRFILT and DVSS pins.
NOTE:
The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS50xx output pins and never
left floating. Floating PWM input pins cause an illegal PWM input state signal to be asserted.
Dual pins: OUTPUTA, OUTPUTB, PVDDA1, and PVDDB1 must have both pins connected externally to the same point on the circuit board,
respectively . Both PVSS pins must also be connected together externally. These multiple pins are for the high-current DMOS output devices.
Failure to connect all the multiple pins to the same respective node results in excessive current flow in the internal bond wires and can cause
the device to fail. All electrical characteristics are specified and measured with all of the multiple pins of each type connected to a single node.
I/ODESCRIPTION
connected externally to PVSS. See Figure 5.
output state. Asserting the RESET signal low causes all fault conditions to be cleared.
shutdown mode the H-bridge MOSFETs are in low-low output state. The latched output can be
cleared by asserting the RESET signal. This output is open drain with internal pullup resistor.
5
TAS5110A
www.ti.com
SLES079A – APRIL 2003 – REVISED MAY 2003
FUNCTIONAL DESCRIPTION
PWM H-Bridge State Control
The digital interface control signals consists of PWM_AP, PWM_AM, PWM_BP, and PWM_BM. These signals are
a complementary differential signal format for the A-side half-bridge and the B-side half-bridge.
Bootstrapped Gate Drive
The TAS5110A includes two dedicated bootstrapped power supplies. A bootstrap capacitor is connected between
the individual bootstrap pin and the associated output. For example, a capacitor is connected between the
BOOTSTRAPA pin and the OUTPUT A pin and another capacitor is connected between the BOOTSTRAPB pin and
the OUTPUTB pin. The bootstrap power supply minimizes the number of high voltage power supply levels externally
supplied to the system, while providing a low-noise supply level for driving the high-side N-channel DMOS transistors.
Low-Dropout Voltage Regulator
Two on-chip low-dropout voltage regulators (LDO) are provided to minimize the number of external power supplies
needed for the system. These voltage regulators are for internal circuits only and cannot be used for external circuitry .
Each LDO is dedicated to a half-bridge and its gate driver. An LDO output capacitor is connected between the
individual LDO output pin and the associated output return. For example, a capacitor is connected between the
LDROUTA pin and the PVSS pin and another capacitor is connected between the LDROUTB pin and the PVSS pin.
High-Current H-bridge Output Stage
The positive outputs of the H-bridge are the two OUTPUT A pins. The negative outputs of the H-bridge are the two
OUTPUTB pins. The logic for the input command to H-bridge outputs is described in the H-bridge output mapping
section immediately following. When the T AS5110A is in the normal mode, as seen in the H-bridge output mapping
tables, the outputs are decoded from the inputs. However, the TAS5110A is immediately shut down if any of the
following error conditions occur: overcurrent, overtemperature, low regulator output voltage, or an illegal PWM input
state is applied. For these conditions, the outputs are set to the appropriate disabled state as specified in the H-bridge
output mapping section, and the SHUTDOWN pin is set low.
H-Bridge Output Mapping
The A-side half-bridge output is designed to the following truth table:
INPUTSOUTPUTS
RESETPWDNPWM_APPWM_AMSHUTDOWNOUTPUTA
XXXX00 or Hi-Z
X0XX1Hi-ZPower down
01XX10Reset
110000Shutdown
110110Normal
111011Normal
111100Shutdown
(1)
Output is 0 for low voltage, overtemperature, and illegal input. Hi-Z is for overcurrent.
(1)
DESCRIPTION
Shutdown
The B-side half-bridge output is designed to the following truth table:
INPUTSOUTPUTS
RESETPWDN PWM_BP PWM_BM SHUTDOWNOUTPUTB
XXXX00 or Hi-Z
X0XX1Hi-ZPower down
01XX10Reset
110000Shutdown
110110Normal
111011Normal
111100Shutdown
(1)
Output is 0 for low voltage, overtemperature, or illegal input. Hi-Z is for overcurrent.
(1)
DESCRIPTION
Shutdown
6
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