TAS5110A
TAS5110A
www.ti.com
SLES079A – APRIL 2003 – REVISED MAY 2003
PurePath Digital AMPLIFIER
TAS5110A 50-W DIGITAL AMPLIFIER POWER STAGE
FEATURES
D50 W RMS Power Into 6 Ω at 10% THD
D40 W RMS Power Into 6 Ω at 0.1% THD
DTHD+N < 0.09% Typical (1-kHz Input Signal)
D93-dB Dynamic Range (TDAA System)
DPower Efficiency > 90% Into 6-Ω and 8-Ω
Load
DLow Profile, SMD 32-Pin PowerPAD
Package
DSelf-Protecting Design
D3.3-V Digital Interface
DEMI Compliant When Used With Recommended System Design
APPLICATIONS
DDVD Receiver
DHome Theater
DMini/Micro Component Systems
DInternet Music Appliance
DCar Audio Amplifiers and Head Units
DESCRIPTION
The TAS5110A is a high-performance true-digital audio amplifier (TDAA) power stage, designed to drive 50 W per channel. The TAS5110A incorporates TI’s Equibit and PurePath Digital technology and is used in conjunction with a digital audio PWM processor (TAS50xx) to deliver high-power, true-digital audio amplification. The efficiency of this digital amplifier can be greater than 90%, reducing the size of both the power supplies and heat sinks needed. The TAS5110A accepts a mono PWM 3.3-V input and controls the switching of an internal CMOS H-bridge.
When used with the TAS50xx PWM processor, system performance of less than 0.09% THD is attainable. Overcurrent protection, overtemperature, and undervoltage protections are built into the TAS5110A, safeguarding the H-bridge and speakers against output shorts, overvoltage conditions, and other fault conditions that could damage the system.
TYPICAL TDAA STEREO AUDIO SYSTEM
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Left |
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Digital Audio |
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TAS5110A |
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L-C |
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Filter |
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TAS3001 |
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DSP |
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TAS50xx |
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S/PDIF |
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Right |
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• |
1394 |
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TAS5110A |
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L-C |
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Filter |
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•Volume
•EQ
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DRC |
• Serial Audio Input Port |
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Bass |
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Internal PLL |
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Treble |
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PWM Processor |
• Two H-Bridge Power Devices |
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD, PurePath Digital, and Equibit are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products |
Copyright 2003, Texas Instruments Incorporated |
conform to specifications per the terms of Texas Instruments standard warranty. |
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Production processing does not necessarily include testing of all parameters. |
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TAS5110A
www.ti.com
SLES079A – APRIL 2003 – REVISED MAY 2003
TERMINAL ASSIGNMENTS
The TAS5110A is offered in a thermally enhanced 32-pin TSSOP surface-mount package (DAD). The DAD package has the PowerPAD on top.
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DAD PACKAGE |
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(TOP VIEW) |
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PWM_BP |
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PVDDB2 |
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1 |
32 |
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PWM_BM |
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31 |
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LDROUTB |
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RESET |
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30 |
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BOOTSTRAPB |
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29 |
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PVDDB1 |
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PWDN |
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BIAS_B |
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28 |
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PVDDB1 |
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BIAS_A |
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27 |
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OUTPUTB |
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VRFILT |
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26 |
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OUTPUTB |
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DVSS |
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25 |
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PVSS |
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DVSS |
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PVSS |
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DVSS |
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23 |
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OUTPUTA |
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DVDD |
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OUTPUTA |
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PVDDA1 |
SHUTDOWN |
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ERR0 |
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20 |
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PVDDA1 |
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ERR1 |
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19 |
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BOOTSTRAPA |
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PWM_AM |
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LDROUTA |
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PWM_AP |
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PVDDA2 |
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ORDERING INFORMATION
TC |
PACKAGE |
TAPE AND REEL |
0° C to 70° C |
TAS5110ADAD |
TAS5110ADADR |
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REFERENCES
1.TAS5000 Digital Audio PWM Processor data manual (SLAS270)
2.True Digital Audio Amplifier TAS5001 Digital Audio PWM Processor data sheet (SLES009)
3.True Digital Audio Amplifier TAS5010 Digital Audio PWM Processor data sheet (SLAS328)
4.True Digital Audio Amplifier TAS5012 Digital Audio PWM Processor data sheet (SLES006)
5.Digital Audio Measurements application report (SLAA114)
6.PowerPAD Thermally Enhanced Package technical brief (SLMA002)
2
TAS5110A
www.ti.com
SLES079A – APRIL 2003 – REVISED MAY 2003
FUNCTIONAL BLOCK DIAGRAM
PVDDA2 |
LDROUTA |
BOOTSTRAPA |
PVDDA1 |
PVDDA1 |
1/2 H-Bridge
LDR |
PWM_AP |
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OUTPUTA |
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DIFF |
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OUTPUTA |
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Bootstrap |
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PWM_AM |
RCVR |
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Gate Drive |
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PVSS
BIAS_A
PWDN |
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RESET |
Control/Sense |
Band-Gap |
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SHUTDOWN |
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Circuit |
Reference |
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ERR1 |
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ERR0 |
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LDROUTB |
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BOOTSTRAPB |
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PVDDB2 |
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VRFILT |
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PVDDB1 |
BIAS_B |
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1/2 H-Bridge |
PVDDB1 |
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LDR |
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PWM_BM |
DIFF |
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OUTPUTB |
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Bootstrap |
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PWM_BP |
RCVR |
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Gate Drive |
OUTPUTB |
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DVDD |
DVSS |
PVSS |
3
TAS5110A
www.ti.com
SLES079A – APRIL 2003 – REVISED MAY 2003
SUGGESTED SYSTEM BLOCK DIAGRAMS
Digital Audio
•USB
•IEEE 1394
•S/PDIF
•ADC
•Automotive MOST
Network |
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I2C |
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TAS30xx |
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Audio |
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Control |
• |
Digital Parametric EQ |
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•Volume
•DRC
•Bass
•Treble
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TAS5110A |
L-C |
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Left |
Filter |
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TAS50xx |
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Right |
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TAS5110A |
L-C |
Serial Audio Input Port |
Filter |
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Internal PLL |
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Two H-Bridges |
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Figure 1. System #1: Stereo Configuration With a TAS3001 Digital Audio Processor
CH1 |
TAS5110A |
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TAS50xx |
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CH2 |
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TAS5110A |
L-C
Filter Left
L-C
Right
Filter
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CH3 |
TAS5110A |
Home Theater |
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TI DSP |
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DVD 6-Channel |
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Dolby AC-3 |
TAS50xx |
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Encoded Digital |
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DTS |
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CH4 |
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Audio Source |
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Volume |
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EQ |
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TAS5110A |
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DRC |
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Bass |
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Treble |
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CH5 |
TAS5110A |
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TAS50xx |
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CH6 |
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TAS5110A |
Figure 2. System #2: 6-Channel Audio Playback
L-C |
Surround Left |
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Filter |
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L-C |
Surround Right |
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Filter |
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L-C |
Center |
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Filter |
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L-C |
Subwoofer |
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Filter |
4
TAS5110A
www.ti.com
SLES079A – APRIL 2003 – REVISED MAY 2003
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Terminal Functions |
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TERMINAL |
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I/O |
DESCRIPTION |
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NAME |
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DAD |
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NO. |
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BIAS_A |
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Connect external resistor to DVSS. |
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BIAS_B |
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Connect external resistor to DVSS. |
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BOOTSTRAPA |
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19 |
O |
Bootstrap capacitor pin for H-bridge A |
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BOOTSTRAPB |
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30 |
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Bootstrap capacitor pin for H-bridge B |
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DVDD |
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3.3-V digital voltage supply for logic |
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DVSS |
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Digital ground for logic is internally connected to PVSS. All three pins must be tied together but not |
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connected externally to PVSS. See Figure 5. |
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ERR1 |
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14 |
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Error/warning report indicator. This output is open drain with internal pullup resistor. |
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ERR0 |
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Error/warning report indicator. This output is open drain with internal pullup resistor. |
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LDROUTA |
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18 |
O |
Low-voltage drop-out regulator output A (not to be used to supply current to external circuitry) |
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LDROUTB |
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31 |
O |
Low-voltage drop-out regulator output B (not to be used to supply current to external circuitry) |
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OUTPUTA |
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22, 23 |
O |
H-bridge output A |
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OUTPUTB |
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26, 27 |
O |
H-bridge output B |
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PVDDA1 |
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High-voltage power supply, H-bridge A |
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PVDDA2 |
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High-voltage power supply for low-dropout voltage regulator A-side |
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PVDDB1 |
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28, 29 |
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High-voltage power supply, H-bridge B |
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PVDDB2 |
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32 |
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High-voltage power supply for low-dropout voltage regulator B-side |
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PVSS |
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High-voltage power supply ground |
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PWDN |
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4 |
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Power down = 0, normal mode = 1 |
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PWM_AM |
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PWM input A(–) |
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PWM_AP |
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PWM input A(+) |
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PWM_BP |
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1 |
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PWM input B(+) |
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PWM_BM |
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2 |
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PWM input B(–) |
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RESET |
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3 |
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Reset and mute mode = 0, normal mode = 1; when in reset mode, H-bridge MOSFETs are in low-low |
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output state. Asserting the RESET signal low causes all fault conditions to be cleared. |
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SHUTDOWN |
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12 |
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Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0; when device is in |
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shutdown mode the H-bridge MOSFETs are in low-low output state. The latched output can be |
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cleared by asserting the RESET signal. This output is open drain with internal pullup resistor. |
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VRFILT |
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7 |
O |
A filter capacitor must be added between the VRFILT and DVSS pins. |
NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS50xx output pins and never left floating. Floating PWM input pins cause an illegal PWM input state signal to be asserted.
Dual pins: OUTPUTA, OUTPUTB, PVDDA1, and PVDDB1 must have both pins connected externally to the same point on the circuit board, respectively. Both PVSS pins must also beconnectedtogetherexternally.These multiplepins arefor thehigh-currentDMOS output devices. Failure to connect all the multiple pins to the same respective node results in excessive current flow in the internal bond wires and can cause the device to fail. All electrical characteristics are specified and measured with all of the multiple pins of each type connected to a single node.
5
TAS5110A
www.ti.com
SLES079A – APRIL 2003 – REVISED MAY 2003
FUNCTIONAL DESCRIPTION
PWM H-Bridge State Control
The digital interface control signals consists of PWM_AP, PWM_AM, PWM_BP, and PWM_BM. These signals are a complementary differential signal format for the A-side half-bridge and the B-side half-bridge.
Bootstrapped Gate Drive
The TAS5110A includes two dedicated bootstrapped power supplies. A bootstrap capacitor is connected between the individual bootstrap pin and the associated output. For example, a capacitor is connected between the BOOTSTRAPA pin and the OUTPUTA pin and another capacitor is connected between the BOOTSTRAPB pin and the OUTPUTB pin. The bootstrap power supply minimizes the number of high voltage power supply levels externally supplied to the system, while providing a low-noise supply level for driving the high-side N-channel DMOS transistors.
Low-Dropout Voltage Regulator
Two on-chip low-dropout voltage regulators (LDO) are provided to minimize the number of external power supplies needed for the system. These voltage regulators are for internal circuits only and cannot be used for external circuitry. Each LDO is dedicated to a half-bridge and its gate driver. An LDO output capacitor is connected between the individual LDO output pin and the associated output return. For example, a capacitor is connected between the LDROUTA pin and the PVSS pin and another capacitor is connected between the LDROUTB pin and the PVSS pin.
High-Current H-bridge Output Stage
The positive outputs of the H-bridge are the two OUTPUTA pins. The negative outputs of the H-bridge are the two OUTPUTB pins. The logic for the input command to H-bridge outputs is described in the H-bridge output mapping section immediately following. When the TAS5110A is in the normal mode, as seen in the H-bridge output mapping tables, the outputs are decoded from the inputs. However, the TAS5110A is immediately shut down if any of the following error conditions occur: overcurrent, overtemperature, low regulator output voltage, or an illegal PWM input state is applied. For these conditions, the outputs are set to the appropriate disabled state as specified in the H-bridge output mapping section, and the SHUTDOWN pin is set low.
H-Bridge Output Mapping
The A-side half-bridge output is designed to the following truth table:
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INPUTS |
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OUTPUTS |
DESCRIPTION |
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RESET |
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PWDN |
PWM_AP |
PWM_AM |
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SHUTDOWN |
OUTPUTA |
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X |
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X |
X |
X |
0 |
0 or Hi-Z(1) |
Shutdown |
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X |
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0 |
X |
X |
1 |
Hi-Z |
Power down |
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0 |
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1 |
X |
X |
1 |
0 |
Reset |
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1 |
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1 |
0 |
0 |
0 |
0 |
Shutdown |
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1 |
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1 |
0 |
1 |
1 |
0 |
Normal |
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1 |
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1 |
1 |
0 |
1 |
1 |
Normal |
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1 |
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1 |
1 |
1 |
0 |
0 |
Shutdown |
(1) Output is 0 for low voltage, overtemperature, and illegal input. Hi-Z is for overcurrent.
The B-side half-bridge output is designed to the following truth table:
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INPUTS |
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OUTPUTS |
DESCRIPTION |
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RESET |
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PWDN |
PWM_BP |
PWM_BM |
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SHUTDOWN |
OUTPUTB |
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X |
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X |
X |
X |
0 |
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0 or Hi-Z(1) |
Shutdown |
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X |
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0 |
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X |
X |
1 |
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Hi-Z |
Power down |
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0 |
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1 |
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X |
X |
1 |
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0 |
Reset |
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1 |
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1 |
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0 |
0 |
0 |
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0 |
Shutdown |
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1 |
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1 |
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0 |
1 |
1 |
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0 |
Normal |
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1 |
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1 |
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0 |
1 |
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1 |
Normal |
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1 |
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1 |
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1 |
1 |
0 |
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0 |
Shutdown |
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(1) Output is 0 for low voltage, overtemperature, or illegal input. Hi-Z is for overcurrent.
6