TEXAS INSTRUMENTS TAS5110A Technical data

TAS5110A

TAS5110A

www.ti.com

SLES079A – APRIL 2003 – REVISED MAY 2003

PurePath Digital AMPLIFIER

TAS5110A 50-W DIGITAL AMPLIFIER POWER STAGE

FEATURES

D50 W RMS Power Into 6 Ω at 10% THD

D40 W RMS Power Into 6 Ω at 0.1% THD

DTHD+N < 0.09% Typical (1-kHz Input Signal)

D93-dB Dynamic Range (TDAA System)

DPower Efficiency > 90% Into 6-Ω and 8-Ω

Load

DLow Profile, SMD 32-Pin PowerPAD

Package

DSelf-Protecting Design

D3.3-V Digital Interface

DEMI Compliant When Used With Recommended System Design

APPLICATIONS

DDVD Receiver

DHome Theater

DMini/Micro Component Systems

DInternet Music Appliance

DCar Audio Amplifiers and Head Units

DESCRIPTION

The TAS5110A is a high-performance true-digital audio amplifier (TDAA) power stage, designed to drive 50 W per channel. The TAS5110A incorporates TI’s Equibit and PurePath Digital technology and is used in conjunction with a digital audio PWM processor (TAS50xx) to deliver high-power, true-digital audio amplification. The efficiency of this digital amplifier can be greater than 90%, reducing the size of both the power supplies and heat sinks needed. The TAS5110A accepts a mono PWM 3.3-V input and controls the switching of an internal CMOS H-bridge.

When used with the TAS50xx PWM processor, system performance of less than 0.09% THD is attainable. Overcurrent protection, overtemperature, and undervoltage protections are built into the TAS5110A, safeguarding the H-bridge and speakers against output shorts, overvoltage conditions, and other fault conditions that could damage the system.

TYPICAL TDAA STEREO AUDIO SYSTEM

				Left
Digital Audio					TAS5110A			L-C
								Filter
•	TAS3001
•	DSP		TAS50xx
•	S/PDIF			Right
•	1394				TAS5110A			L-C
								Filter

•Volume

•EQ

•	DRC	• Serial Audio Input Port
•	Bass	•	Internal PLL
•	Treble	•	PWM Processor	• Two H-Bridge Power Devices

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD, PurePath Digital, and Equibit are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products	Copyright 2003, Texas Instruments Incorporated
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.

TAS5110A

www.ti.com

SLES079A – APRIL 2003 – REVISED MAY 2003

TERMINAL ASSIGNMENTS

The TAS5110A is offered in a thermally enhanced 32-pin TSSOP surface-mount package (DAD). The DAD package has the PowerPAD on top.

								DAD PACKAGE
								(TOP VIEW)
PWM_BP												PVDDB2
								1	32
PWM_BM								2	31			LDROUTB
RESET								3	30			BOOTSTRAPB
								4	29			PVDDB1
	PWDN
BIAS_B								5	28			PVDDB1
BIAS_A								6	27			OUTPUTB
VRFILT								7	26			OUTPUTB
	DVSS							8	25			PVSS
	DVSS							9	24			PVSS
	DVSS							10	23			OUTPUTA
	DVDD							11	22			OUTPUTA
								12	21			PVDDA1
SHUTDOWN
		ERR0						13	20			PVDDA1
		ERR1						14	19			BOOTSTRAPA
PWM_AM								15	18			LDROUTA
PWM_AP								16	17			PVDDA2

ORDERING INFORMATION

TC	PACKAGE	TAPE AND REEL
0° C to 70° C	TAS5110ADAD	TAS5110ADADR

REFERENCES

1.TAS5000 Digital Audio PWM Processor data manual (SLAS270)

2.True Digital Audio Amplifier TAS5001 Digital Audio PWM Processor data sheet (SLES009)

3.True Digital Audio Amplifier TAS5010 Digital Audio PWM Processor data sheet (SLAS328)

4.True Digital Audio Amplifier TAS5012 Digital Audio PWM Processor data sheet (SLES006)

5.Digital Audio Measurements application report (SLAA114)

6.PowerPAD Thermally Enhanced Package technical brief (SLMA002)

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TAS5110A

www.ti.com

SLES079A – APRIL 2003 – REVISED MAY 2003

FUNCTIONAL BLOCK DIAGRAM

PVDDA2

LDROUTA

BOOTSTRAPA

PVDDA1

PVDDA1

1/2 H-Bridge

LDR

	PWM_AP			OUTPUTA
		DIFF		OUTPUTA
			Bootstrap
	PWM_AM	RCVR
			Gate Drive

PVSS

BIAS_A

	PWDN
	RESET	Control/Sense	Band-Gap
	SHUTDOWN
		Circuit	Reference
	ERR1
	ERR0
	LDROUTB		BOOTSTRAPB
	PVDDB2
	VRFILT
			PVDDB1

	BIAS_B		1/2 H-Bridge	PVDDB1
		LDR
	PWM_BM	DIFF		OUTPUTB
			Bootstrap
	PWM_BP	RCVR
			Gate Drive	OUTPUTB

DVDD

DVSS

PVSS

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TAS5110A

www.ti.com

SLES079A – APRIL 2003 – REVISED MAY 2003

SUGGESTED SYSTEM BLOCK DIAGRAMS

Digital Audio

•USB

•IEEE 1394

•S/PDIF

•ADC

•Automotive MOST

Network
I2C		TAS30xx
Audio
Control	•	Digital Parametric EQ

•Volume

•DRC

•Bass

•Treble

		TAS5110A	L-C
	Left		Filter
	TAS50xx
	Right
•		TAS5110A	L-C
	Serial Audio Input Port		Filter
•	Internal PLL
	•	Two H-Bridges

Figure 1. System #1: Stereo Configuration With a TAS3001 Digital Audio Processor

CH1	TAS5110A
TAS50xx
CH2
	TAS5110A

L-C

Filter Left

L-C

Right

Filter

				CH3	TAS5110A
Home Theater		TI DSP
	6
DVD 6-Channel		•	Dolby AC-3	TAS50xx
Encoded Digital		•	DTS
				CH4
Audio Source		•	Volume
		•	EQ		TAS5110A
		•	DRC
		•	Bass
		•	Treble
				CH5	TAS5110A
				TAS50xx
				CH6
					TAS5110A

Figure 2. System #2: 6-Channel Audio Playback

	L-C	Surround Left
	Filter
	L-C	Surround Right
	Filter
	L-C	Center
	Filter
	L-C	Subwoofer
	Filter

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TAS5110A

www.ti.com

SLES079A – APRIL 2003 – REVISED MAY 2003

										Terminal Functions
				TERMINAL
									I/O	DESCRIPTION
	NAME							DAD
								NO.
	BIAS_A							6	I	Connect external resistor to DVSS.
	BIAS_B							5	I	Connect external resistor to DVSS.
	BOOTSTRAPA							19	O	Bootstrap capacitor pin for H-bridge A
	BOOTSTRAPB							30	O	Bootstrap capacitor pin for H-bridge B
	DVDD							11	—	3.3-V digital voltage supply for logic
	DVSS							8, 9,	—	Digital ground for logic is internally connected to PVSS. All three pins must be tied together but not
								10		connected externally to PVSS. See Figure 5.
	ERR1							14	O	Error/warning report indicator. This output is open drain with internal pullup resistor.
	ERR0							13	O	Error/warning report indicator. This output is open drain with internal pullup resistor.
	LDROUTA							18	O	Low-voltage drop-out regulator output A (not to be used to supply current to external circuitry)
	LDROUTB							31	O	Low-voltage drop-out regulator output B (not to be used to supply current to external circuitry)
	OUTPUTA							22, 23	O	H-bridge output A
	OUTPUTB							26, 27	O	H-bridge output B
	PVDDA1							20, 21	—	High-voltage power supply, H-bridge A
	PVDDA2							17	—	High-voltage power supply for low-dropout voltage regulator A-side
	PVDDB1							28, 29	—	High-voltage power supply, H-bridge B
	PVDDB2							32	—	High-voltage power supply for low-dropout voltage regulator B-side
	PVSS							24, 25	—	High-voltage power supply ground
	PWDN							4	I	Power down = 0, normal mode = 1
	PWM_AM							15	I	PWM input A(–)
	PWM_AP							16	I	PWM input A(+)
	PWM_BP							1	I	PWM input B(+)
	PWM_BM							2	I	PWM input B(–)
	RESET							3	I	Reset and mute mode = 0, normal mode = 1; when in reset mode, H-bridge MOSFETs are in low-low
										output state. Asserting the RESET signal low causes all fault conditions to be cleared.
	SHUTDOWN							12	O	Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0; when device is in
										shutdown mode the H-bridge MOSFETs are in low-low output state. The latched output can be
										cleared by asserting the RESET signal. This output is open drain with internal pullup resistor.
	VRFILT							7	O	A filter capacitor must be added between the VRFILT and DVSS pins.

NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS50xx output pins and never left floating. Floating PWM input pins cause an illegal PWM input state signal to be asserted.

Dual pins: OUTPUTA, OUTPUTB, PVDDA1, and PVDDB1 must have both pins connected externally to the same point on the circuit board, respectively. Both PVSS pins must also beconnectedtogetherexternally.These multiplepins arefor thehigh-currentDMOS output devices. Failure to connect all the multiple pins to the same respective node results in excessive current flow in the internal bond wires and can cause the device to fail. All electrical characteristics are specified and measured with all of the multiple pins of each type connected to a single node.

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TAS5110A

www.ti.com

SLES079A – APRIL 2003 – REVISED MAY 2003

FUNCTIONAL DESCRIPTION

PWM H-Bridge State Control

The digital interface control signals consists of PWM_AP, PWM_AM, PWM_BP, and PWM_BM. These signals are a complementary differential signal format for the A-side half-bridge and the B-side half-bridge.

Bootstrapped Gate Drive

The TAS5110A includes two dedicated bootstrapped power supplies. A bootstrap capacitor is connected between the individual bootstrap pin and the associated output. For example, a capacitor is connected between the BOOTSTRAPA pin and the OUTPUTA pin and another capacitor is connected between the BOOTSTRAPB pin and the OUTPUTB pin. The bootstrap power supply minimizes the number of high voltage power supply levels externally supplied to the system, while providing a low-noise supply level for driving the high-side N-channel DMOS transistors.

Low-Dropout Voltage Regulator

Two on-chip low-dropout voltage regulators (LDO) are provided to minimize the number of external power supplies needed for the system. These voltage regulators are for internal circuits only and cannot be used for external circuitry. Each LDO is dedicated to a half-bridge and its gate driver. An LDO output capacitor is connected between the individual LDO output pin and the associated output return. For example, a capacitor is connected between the LDROUTA pin and the PVSS pin and another capacitor is connected between the LDROUTB pin and the PVSS pin.

High-Current H-bridge Output Stage

The positive outputs of the H-bridge are the two OUTPUTA pins. The negative outputs of the H-bridge are the two OUTPUTB pins. The logic for the input command to H-bridge outputs is described in the H-bridge output mapping section immediately following. When the TAS5110A is in the normal mode, as seen in the H-bridge output mapping tables, the outputs are decoded from the inputs. However, the TAS5110A is immediately shut down if any of the following error conditions occur: overcurrent, overtemperature, low regulator output voltage, or an illegal PWM input state is applied. For these conditions, the outputs are set to the appropriate disabled state as specified in the H-bridge output mapping section, and the SHUTDOWN pin is set low.

H-Bridge Output Mapping

The A-side half-bridge output is designed to the following truth table:

			INPUTS				OUTPUTS		DESCRIPTION
	RESET		PWDN	PWM_AP	PWM_AM		SHUTDOWN	OUTPUTA
	X		X	X	X	0		0 or Hi-Z(1)	Shutdown
	X		0	X	X	1		Hi-Z	Power down
0			1	X	X	1		0	Reset
1			1	0	0	0		0	Shutdown
1			1	0	1	1		0	Normal
1			1	1	0	1		1	Normal
1			1	1	1	0		0	Shutdown

(1) Output is 0 for low voltage, overtemperature, and illegal input. Hi-Z is for overcurrent.

The B-side half-bridge output is designed to the following truth table:

				INPUTS					OUTPUTS			DESCRIPTION
	RESET			PWDN		PWM_BP	PWM_BM		SHUTDOWN		OUTPUTB
	X			X		X	X	0			0 or Hi-Z(1)	Shutdown
	X			0		X	X	1			Hi-Z	Power down
0				1		X	X	1			0	Reset
1				1		0	0	0			0	Shutdown
1				1		0	1	1			0	Normal
1				1		1	0	1			1	Normal
1				1		1	1	0			0	Shutdown

(1) Output is 0 for low voltage, overtemperature, or illegal input. Hi-Z is for overcurrent.

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