TEXAS INSTRUMENTS TAS5110 Technical data

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TAS5110

SLES028A – MAY 2002 – REVISED SEPTEMBER 2002

TRUE DIGITAL AUDIO AMPLIFIER

TAS5110 PWM POWER OUTPUT STAGE

FEATURES

50-W RMS Power Into 6 Ω at 10% THD

D
D 40-W RMS Power Into 6 Ω at 0.1% THD
D THD+N < 0.09% Typical (1-kHz Input Signal)
D 93-dB Dynamic Range (TDAA System)
D Power Efficiency > 90% Into 6-Ω and 8-Ω Load
D Low Profile, SMD 32-Pin PowerPAD Package
D Self-Protecting Design
D 3.3-V Digital Interface
D EMI Compliant When Used With

Recommended System Design

APPLICATIONS

DVD Receiver

D
D Home Theater
D Mini/Micro Component Systems
D Internet Music Appliance
D Car Audio Amplifiers and Head Units

DESCRIPTION

The TAS5110 is a high-performance true digital audio
amplifier (TDAA) power stage, designed to drive 50 W
per channel. The TAS5110 incorporates TI’s equibitt
technology and is used in conjunction with a digital
audio PWM processor (T AS50xx) to deliver high-power,
true digital audio amplification. The efficiency of this
digital amplifier can be greater than 90%, reducing the
size of both the power supplies and heat sinks needed.
The TAS5110 accepts a mono PWM 3.3-V input and
controls the switching of an internal CMOS H-bridge.

When used with the T AS50xx PWM processor, system
performance of less than 0.09% THD is attainable.
Over-current protection, over-temperature, and
under-voltage protections are built into the TAS5110,
safeguarding the H-bridge and speakers against output
shorts, over-voltage conditions, and other fault
conditions that could damage the system.

TYPICAL TDAA STEREO AUDIO SYSTEM

Digital Audio

• TAS3001

• DSP

• SPDIF

• 1394

• Volume

• EQ

• DRC

• Bass

• Treble

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD and Equibit are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

• Serial Audio Input Port

• Internal PLL

• PCM–PWM Modulator

TAS50xx

Left

Right

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TAS5110

TAS5110

• Two H-Bridge Power Devices

L-C

Filter

L-C

Filter

Copyright  2002, Texas Instruments Incorporated

1

TAS5110

SLES028A – MAY 2002 – REVISED SEPTEMBER 2002

terminal assignments

The TAS5110 is offered in a thermally enhanced 32-pin HTSSOP surface-mount package (DAP). The DAP
package has the PowerPAD on the bottom.

DAP PACKAGE

(TOP VIEW)

ordering information

T

C

0°C to 70°C TAS5110DAP TAS5110DAPR

–40°C to 85°C TAS5110IDAP TAS5110IDAPR

PWM_AP

PWM_AM

ERR1
ERR0

SHUTDOWN

DVDD

DVSS
DVSS
DVSS

VRFILT
BIAS_A
BIAS_B

PWDN

RESET

PWM_BM

PWM_BP

PACKAGE TAPE AND REEL

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

PVDDA2
LDROUTA
BOOTSTRAPA
PVDDA1
PVDDA1
OUTPUTA
OUTPUTA
PVSS
PVSS
OUTPUTB
OUTPUTB
PVDDB1
PVDDB1
BOOTSTRAPB
LDROUTB
PVDDB2

2

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SLES028A – MAY 2002 – REVISED SEPTEMBER 2002

terminal assignments

In addition to the 32-pin HTSSOP DAP package, the T AS5110 is of fered in a thermally enhanced 32-pin TSSOP
surface-mount package (DAD). The DAD package has the PowerPAD on top.

DAD PACKAGE

(TOP VIEW)

TAS5110

ordering information

T

C

0°C to 70°C TAS5110DAD TAS5110DADR

–40°C to 85°C TAS5110IDAD TAS5110IDADR

references

PWM_BP

PWM_BM

RESET

PWDN
BIAS_B
BIAS_A

VRFILT

DVSS
DVSS
DVSS

DVDD

SHUTDOWN

ERR0
ERR1

PWM_AM

PWM_AP

PACKAGE TAPE AND REEL

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

PVDDB2
LDROUTB
BOOTSTRAPB
PVDDB1
PVDDB1
OUTPUTB
OUTPUTB
PVSS
PVSS
OUTPUTA
OUTPUTA
PVDDA1
PVDDA1
BOOTSTRAPA
LDROUTA
PVDDA2

TAS5000 Digital Audio PWM Processor data manual – TI Literature Number SLAS270
T AS5001 Digital Audio PWM Processor data manual – TI Literature Number SLES009
T AS5010 Digital Audio PWM Processor data manual – TI Literature Number SLAS328
T AS5012 Digital Audio PWM Processor data manual – TI Literature Number SLES006
Digital Audio Measurements – TI literature number SLAA114
PowerPAD Thermally Enhanced Package – TI literature number SLMA002

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3

TAS5110

A

SLES028A – MAY 2002 – REVISED SEPTEMBER 2002

functional block diagram

PWM_AP

PWM_AM

BIAS_A

PWDN

RESET

SHUTDOWN

ERR1
ERR0

LDROUTB

PVDDB2

VRFILT

BIAS_B

PWM_BM

PWM_BP

PVDDA2

LDR

DIFF

RCVR

Control/Sense

Circuit

LDR

DIFF

RCVR

LDROUTA

Boot Strap
Gate Drive

Boot Strap
Gate Drive

BOOTSTRAP

1/2 H-Bridge

Bandgap

Reference

1/2 H-Bridge

PVDDA1

PVDDA1

OUTPUTA
OUTPUTA

PVSS

BOOTSTRAPB

PVDDB1

PVDDB1

OUTPUTB
OUTPUTB

DVSS

DVDD

4

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PVSS

suggested system block diagrams

Digital Audio

• USB

• IEEE 1394

• SPDIF

• ADC

• Automotive

MOST
Network

IIC

Audio

Control

Figure 1. System #1: Stereo Configuration With a TAS3001 Digital Audio Processor

TAS30xx

• Digital Parametric EQ

• Volume

• DRC

• Bass

• Treble

Left

TAS50xx

Right

• Serial Audio Input Port

• Internal PLL

SLES028A – MAY 2002 – REVISED SEPTEMBER 2002

TAS5110

TAS5110

L-C

Filter

L-C

Filter

• Two H-Bridges

TAS5110

Home Theater

DVD 6-Channel

Encoded Digital

Audio Source

6

TI DSP

• Dolby AC-3

• DTS

• Volume

• EQ

• DRC

• Bass

• Treble

TAS50xx

TAS50xx

TAS50xx

CH1

CH2

CH3

CH4

CH5

CH6

TAS5110

TAS5110

TAS5110

TAS5110

TAS5110

TAS5110

L-C

Filter

L-C

Filter

L-C

Filter

L-C

Filter

L-C

Filter

L-C

Filter

Left

Right

Surround Left

Surround Right

Center

Subwoofer

Figure 2. System #3: 6-Channel Audio Playback

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5

TAS5110

SLES028A – MAY 2002 – REVISED SEPTEMBER 2002

Terminal Functions

TERMINAL

NAME DAP

NO.

BIAS_A 11 6 I Connect external resistor to DVSS.
BIAS_B 12 5 I Connect external resistor to DVSS.
BOOTSTRAPA 30 19 O Bootstrap capacitor pin for H-bridge A
BOOTSTRAPB 19 30 O Bootstrap capacitor pin for H-bridge B
DVDD 6 11 I 3.3-V digital voltage supply for logic
DVSS 7, 8, 9 8, 9,

ERR1 3 14 O Error/warning report indicator. This output is open drain with internal pullup resistor.
ERR0 4 13 O Error/warning report indicator. This output is open drain with internal pullup resistor.
LDROUTA 31 18 O Low voltage drop-out regulator output A (not to be used to supply current to external

LDROUTB 18 31 O Low voltage drop-out regulator output B (not to be used to supply current to external

OUTPUTA 26, 27 22, 23 O H-bridge output A
OUTPUTB 22, 23 26, 27 O H-bridge output B
PVDDA1 28, 29 20, 21 I High voltage power supply, H-bridge A
PVDDA2 32 17 I High voltage power supply for low-dropout voltage regulator A-side
PVDDB1 20, 21 28, 29 I High voltage power supply, H-bridge B
PVDDB2 17 32 I High voltage power supply for low-dropout voltage regulator B-side
PVSS 24, 25 24, 25 I High voltage power supply ground
PWDN 13 4 I Power down = 0, normal mode = 1
PWM_AM 2 15 I PWM input A(–)
PWM_AP 1 16 I PWM input A(+)
PWM_BP 16 1 I PWM input B(+)
PWM_BM 15 2 I PWM input B(–)
RESET 14 3 I Reset and mute mode = 0, normal mode = 1, when in reset mode, H-bridge MOSFETs are

SHUTDOWN 5 12 O Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0, when

VRFILT 10 7 O A filter capacitor must be added between VRFILT and DVSS pins.

NOTE: The four PWM inputs: PWM_AP , PWM_AM, PWM_BP, and PWM_BM must always be connected to the T AS50xx output pins, and never

left floating. Floating PWM input pins causes an illegal PWM input state signal to be asserted.

DAD

NO.

I/O DESCRIPTION

10

I Digital ground for logic is internally connected to PVSS. All three pins must be tied

together but not connected externally to PVSS. See Figure 5.

circuitry)

circuitry)

in low-low output state. Asserting the RESET
cleared.

device is in shutdown mode the H-bridge MOSFETs are in low-low output state. The
latched output can be cleared by asserting the RESET
with internal pullup resistor.

signal low causes all fault conditions to be

signal. This output is open drain

Dual pins: OUTPUTA, OUTPUTB, PVDDA1, and PVDDB1 must have both pins connected externally to the same point on the circuit board,
respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high-current DMOS output
devices. Failure to connect all the multiple pins to the same respective node results in excessive current flow in the internal bond wires
and can cause the device to fail. All electrical characteristics are specified and measured with all of the multiple pins conne cted to the same
node, respectively .

6

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