TEXAS INSTRUMENTS TAS5110 Technical data

TAS5110

TAS5110

SLES028A – MAY 2002 – REVISED SEPTEMBER 2002

TRUE DIGITAL AUDIO AMPLIFIER

TAS5110 PWM POWER OUTPUT STAGE

FEATURES

D50-W RMS Power Into 6 Ω at 10% THD

D40-W RMS Power Into 6 Ω at 0.1% THD

DTHD+N < 0.09% Typical (1-kHz Input Signal)

D93-dB Dynamic Range (TDAA System)

D Power Efficiency > 90% Into 6-Ω and 8-Ω Load

DLow Profile, SMD 32-Pin PowerPAD Package

DSelf-Protecting Design

D3.3-V Digital Interface

DEMI Compliant When Used With Recommended System Design

APPLICATIONS

DDVD Receiver

DHome Theater

DMini/Micro Component Systems

DInternet Music Appliance

DCar Audio Amplifiers and Head Units

DESCRIPTION

The TAS5110 is a high-performance true digital audio amplifier (TDAA) power stage, designed to drive 50 W per channel. The TAS5110 incorporates TI’s equibitt technology and is used in conjunction with a digital audio PWM processor (TAS50xx) to deliver high-power, true digital audio amplification. The efficiency of this digital amplifier can be greater than 90%, reducing the size of both the power supplies and heat sinks needed. The TAS5110 accepts a mono PWM 3.3-V input and controls the switching of an internal CMOS H-bridge.

When used with the TAS50xx PWM processor, system performance of less than 0.09% THD is attainable. Over-current protection, over-temperature, and under-voltage protections are built into the TAS5110, safeguarding the H-bridge and speakers against output shorts, over-voltage conditions, and other fault conditions that could damage the system.

TYPICAL TDAA STEREO AUDIO SYSTEM

				Left
Digital Audio					TAS5110			L-C
								Filter
•	TAS3001
•	DSP		TAS50xx
•	SPDIF			Right
								L-C
•	1394				TAS5110
								Filter

•Volume

•EQ

•	DRC	• Serial Audio Input Port
•	Bass	•	Internal PLL
•	Treble	•	PCM–PWM Modulator • Two H-Bridge Power Devices

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD and Equibit are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.	Copyright 2002, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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1

TAS5110

SLES028A – MAY 2002 – REVISED SEPTEMBER 2002

terminal assignments

The TAS5110 is offered in a thermally enhanced 32-pin HTSSOP surface-mount package (DAP). The DAP package has the PowerPAD on the bottom.

				DAP PACKAGE
				(TOP VIEW)
PWM_AP								PVDDA2
				1	32
PWM_AM				2	31			LDROUTA
ERR1				3	30			BOOTSTRAPA
ERR0				4	29			PVDDA1
				5	28			PVDDA1
SHUTDOWN
DVDD				6	27			OUTPUTA
DVSS				7	26			OUTPUTA
DVSS				8	25			PVSS
DVSS				9	24			PVSS
VRFILT				10	23			OUTPUTB
BIAS_A				11	22			OUTPUTB
BIAS_B				12	21			PVDDB1
PWDN				13	20			PVDDB1
RESET				14	19			BOOTSTRAPB
PWM_BM				15	18			LDROUTB
PWM_BP				16	17			PVDDB2

ordering information

TC	PACKAGE	TAPE AND REEL
0° C to 70° C	TAS5110DAP	TAS5110DAPR
–40° C to 85° C	TAS5110IDAP	TAS5110IDAPR

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TAS5110

SLES028A – MAY 2002 – REVISED SEPTEMBER 2002

terminal assignments

In addition to the 32-pin HTSSOP DAP package, the TAS5110 is offered in a thermally enhanced 32-pin TSSOP surface-mount package (DAD). The DAD package has the PowerPAD on top.

				DAD PACKAGE
				(TOP VIEW)
PWM_BP								PVDDB2
				1	32
PWM_BM				2	31			LDROUTB
RESET				3	30			BOOTSTRAPB
PWDN				4	29			PVDDB1
BIAS_B				5	28			PVDDB1
BIAS_A				6	27			OUTPUTB
VRFILT				7	26			OUTPUTB
DVSS				8	25			PVSS
DVSS				9	24			PVSS
DVSS				10	23			OUTPUTA
DVDD				11	22			OUTPUTA
				12	21			PVDDA1
SHUTDOWN
ERR0				13	20			PVDDA1
ERR1				14	19			BOOTSTRAPA
PWM_AM				15	18			LDROUTA
PWM_AP				16	17			PVDDA2

ordering information

TC	PACKAGE	TAPE AND REEL
0° C to 70° C	TAS5110DAD	TAS5110DADR
–40° C to 85° C	TAS5110IDAD	TAS5110IDADR

references

TAS5000 Digital Audio PWM Processor data manual – TI Literature Number SLAS270

TAS5001 Digital Audio PWM Processor data manual – TI Literature Number SLES009

TAS5010 Digital Audio PWM Processor data manual – TI Literature Number SLAS328

TAS5012 Digital Audio PWM Processor data manual – TI Literature Number SLES006

Digital Audio Measurements – TI literature number SLAA114

PowerPAD Thermally Enhanced Package – TI literature number SLMA002

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3

TAS5110

SLES028A – MAY 2002 – REVISED SEPTEMBER 2002

functional block diagram

PWM_AP

PWM_AM

BIAS_A

PWDN

RESET

SHUTDOWN

ERR1

ERR0

LDROUTB

PVDDB2

VRFILT

BIAS_B

PWM_BM

PWM_BP

PVDDA2

LDROUTA

BOOTSTRAPA

PVDDA1

PVDDA1

1/2 H-Bridge

LDR

			OUTPUTA
	DIFF	Boot Strap	OUTPUTA
	RCVR
		Gate Drive
			PVSS

Control/Sense	Bandgap
Circuit	Reference

BOOTSTRAPB

PVDDB1

1/2 H-Bridge

PVDDB1

LDR

	DIFF	Boot Strap	OUTPUTB
	RCVR
		Gate Drive
			OUTPUTB

DVDD

DVSS

PVSS

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TAS5110

SLES028A – MAY 2002 – REVISED SEPTEMBER 2002

suggested system block diagrams

Digital Audio

•USB

•IEEE 1394

•SPDIF

•ADC

•Automotive MOST

Network
IIC		TAS30xx
Audio
Control	•	Digital Parametric EQ

•Volume

•DRC

•Bass

•Treble

		TAS5110	L-C
	Left		Filter
	TAS50xx
	Right
•		TAS5110	L-C
	Serial Audio Input Port		Filter
•	Internal PLL
	•	Two H-Bridges

Figure 1. System #1: Stereo Configuration With a TAS3001 Digital Audio Processor

CH1	TAS5110
TAS50xx
CH2
	TAS5110

L-C

Filter Left

L-C

Right

Filter

				CH3	TAS5110
Home Theater		TI DSP
DVD 6-Channel	6	•	Dolby AC-3	TAS50xx
Encoded Digital		•	DTS
				CH4
Audio Source		•	Volume
		•	EQ		TAS5110
		•	DRC
		•	Bass
		•	Treble
				CH5	TAS5110
				TAS50xx
				CH6
					TAS5110

Figure 2. System #3: 6-Channel Audio Playback

	L-C	Surround Left
	Filter
	L-C	Surround Right
	Filter
	L-C	Center
	Filter
	L-C	Subwoofer
	Filter

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5

TAS5110

SLES028A – MAY 2002 – REVISED SEPTEMBER 2002

										Terminal Functions
					TERMINAL
									I/O	DESCRIPTION
	NAME						DAP	DAD
							NO.	NO.
	BIAS_A						11	6	I	Connect external resistor to DVSS.
	BIAS_B						12	5	I	Connect external resistor to DVSS.
	BOOTSTRAPA						30	19	O	Bootstrap capacitor pin for H-bridge A
	BOOTSTRAPB						19	30	O	Bootstrap capacitor pin for H-bridge B
	DVDD						6	11	I	3.3-V digital voltage supply for logic
	DVSS						7, 8, 9	8, 9,	I	Digital ground for logic is internally connected to PVSS. All three pins must be tied
								10		together but not connected externally to PVSS. See Figure 5.
	ERR1						3	14	O	Error/warning report indicator. This output is open drain with internal pullup resistor.
	ERR0						4	13	O	Error/warning report indicator. This output is open drain with internal pullup resistor.
	LDROUTA						31	18	O	Low voltage drop-out regulator output A (not to be used to supply current to external
										circuitry)
	LDROUTB						18	31	O	Low voltage drop-out regulator output B (not to be used to supply current to external
										circuitry)
	OUTPUTA						26, 27	22, 23	O	H-bridge output A
	OUTPUTB						22, 23	26, 27	O	H-bridge output B
	PVDDA1						28, 29	20, 21	I	High voltage power supply, H-bridge A
	PVDDA2						32	17	I	High voltage power supply for low-dropout voltage regulator A-side
	PVDDB1						20, 21	28, 29	I	High voltage power supply, H-bridge B
	PVDDB2						17	32	I	High voltage power supply for low-dropout voltage regulator B-side
	PVSS						24, 25	24, 25	I	High voltage power supply ground
	PWDN						13	4	I	Power down = 0, normal mode = 1
	PWM_AM						2	15	I	PWM input A(–)
	PWM_AP						1	16	I	PWM input A(+)
	PWM_BP						16	1	I	PWM input B(+)
	PWM_BM						15	2	I	PWM input B(–)
	RESET						14	3	I	Reset and mute mode = 0, normal mode = 1, when in reset mode, H-bridge MOSFETs are
										in low-low output state. Asserting the RESET signal low causes all fault conditions to be
										cleared.
	SHUTDOWN						5	12	O	Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0, when
										device is in shutdown mode the H-bridge MOSFETs are in low-low output state. The
										latched output can be cleared by asserting the RESET signal. This output is open drain
										with internal pullup resistor.
	VRFILT						10	7	O	A filter capacitor must be added between VRFILT and DVSS pins.

NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS50xx output pins, and never left floating. Floating PWM input pins causes an illegal PWM input state signal to be asserted.

Dual pins: OUTPUTA, OUTPUTB, PVDDA1, and PVDDB1 must have both pins connected externally to the same point on the circuit board, respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high-current DMOS output devices. Failure to connect all the multiple pins to the same respective node results in excessive current flow in the internal bond wires and can cause the device to fail. All electrical characteristics are specified and measured with all of the multiple pins connected to the same node, respectively.

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