TAS5110
TAS5110
SLES028A – MAY 2002 – REVISED SEPTEMBER 2002
TRUE DIGITAL AUDIO AMPLIFIER
TAS5110 PWM POWER OUTPUT STAGE
FEATURES
D50-W RMS Power Into 6 Ω at 10% THD
D40-W RMS Power Into 6 Ω at 0.1% THD
DTHD+N < 0.09% Typical (1-kHz Input Signal)
D93-dB Dynamic Range (TDAA System)
D Power Efficiency > 90% Into 6-Ω and 8-Ω Load
DLow Profile, SMD 32-Pin PowerPAD Package
DSelf-Protecting Design
D3.3-V Digital Interface
DEMI Compliant When Used With Recommended System Design
APPLICATIONS
DDVD Receiver
DHome Theater
DMini/Micro Component Systems
DInternet Music Appliance
DCar Audio Amplifiers and Head Units
DESCRIPTION
The TAS5110 is a high-performance true digital audio amplifier (TDAA) power stage, designed to drive 50 W per channel. The TAS5110 incorporates TI’s equibitt technology and is used in conjunction with a digital audio PWM processor (TAS50xx) to deliver high-power, true digital audio amplification. The efficiency of this digital amplifier can be greater than 90%, reducing the size of both the power supplies and heat sinks needed. The TAS5110 accepts a mono PWM 3.3-V input and controls the switching of an internal CMOS H-bridge.
When used with the TAS50xx PWM processor, system performance of less than 0.09% THD is attainable. Over-current protection, over-temperature, and under-voltage protections are built into the TAS5110, safeguarding the H-bridge and speakers against output shorts, over-voltage conditions, and other fault conditions that could damage the system.
TYPICAL TDAA STEREO AUDIO SYSTEM
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Left |
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Digital Audio |
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TAS5110 |
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L-C |
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Filter |
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TAS3001 |
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DSP |
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TAS50xx |
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SPDIF |
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Right |
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L-C |
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1394 |
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TAS5110 |
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Filter |
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•Volume
•EQ
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DRC |
• Serial Audio Input Port |
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Bass |
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Internal PLL |
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Treble |
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PCM–PWM Modulator • Two H-Bridge Power Devices |
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and Equibit are trademarks of Texas Instruments.
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PRODUCTION DATA information is current as of publication date. |
Copyright 2002, Texas Instruments Incorporated |
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Products conform to specifications per the terms of Texas Instruments |
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standard warranty. Production processing does not necessarily include |
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testing of all parameters. |
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www.ti.com |
1 |
TAS5110
SLES028A – MAY 2002 – REVISED SEPTEMBER 2002
terminal assignments
The TAS5110 is offered in a thermally enhanced 32-pin HTSSOP surface-mount package (DAP). The DAP package has the PowerPAD on the bottom.
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DAP PACKAGE |
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(TOP VIEW) |
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PWM_AP |
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PVDDA2 |
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1 |
32 |
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PWM_AM |
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31 |
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LDROUTA |
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ERR1 |
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30 |
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BOOTSTRAPA |
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ERR0 |
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29 |
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PVDDA1 |
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5 |
28 |
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PVDDA1 |
SHUTDOWN |
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DVDD |
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27 |
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OUTPUTA |
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DVSS |
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26 |
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OUTPUTA |
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DVSS |
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25 |
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PVSS |
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DVSS |
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24 |
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PVSS |
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VRFILT |
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23 |
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OUTPUTB |
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BIAS_A |
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22 |
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OUTPUTB |
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BIAS_B |
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21 |
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PVDDB1 |
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PWDN |
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20 |
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PVDDB1 |
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RESET |
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19 |
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BOOTSTRAPB |
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PWM_BM |
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18 |
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LDROUTB |
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PWM_BP |
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17 |
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PVDDB2 |
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ordering information
TC |
PACKAGE |
TAPE AND REEL |
0° C to 70° C |
TAS5110DAP |
TAS5110DAPR |
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–40° C to 85° C |
TAS5110IDAP |
TAS5110IDAPR |
2 |
www.ti.com |
TAS5110
SLES028A – MAY 2002 – REVISED SEPTEMBER 2002
terminal assignments
In addition to the 32-pin HTSSOP DAP package, the TAS5110 is offered in a thermally enhanced 32-pin TSSOP surface-mount package (DAD). The DAD package has the PowerPAD on top.
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DAD PACKAGE |
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(TOP VIEW) |
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PWM_BP |
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PVDDB2 |
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1 |
32 |
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PWM_BM |
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31 |
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LDROUTB |
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RESET |
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30 |
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BOOTSTRAPB |
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PWDN |
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29 |
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PVDDB1 |
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BIAS_B |
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28 |
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PVDDB1 |
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BIAS_A |
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27 |
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OUTPUTB |
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VRFILT |
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26 |
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OUTPUTB |
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DVSS |
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25 |
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PVSS |
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DVSS |
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24 |
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PVSS |
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DVSS |
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23 |
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OUTPUTA |
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DVDD |
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22 |
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OUTPUTA |
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12 |
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PVDDA1 |
SHUTDOWN |
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ERR0 |
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PVDDA1 |
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ERR1 |
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BOOTSTRAPA |
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PWM_AM |
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18 |
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LDROUTA |
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PWM_AP |
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PVDDA2 |
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ordering information
TC |
PACKAGE |
TAPE AND REEL |
0° C to 70° C |
TAS5110DAD |
TAS5110DADR |
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–40° C to 85° C |
TAS5110IDAD |
TAS5110IDADR |
references
TAS5000 Digital Audio PWM Processor data manual – TI Literature Number SLAS270
TAS5001 Digital Audio PWM Processor data manual – TI Literature Number SLES009
TAS5010 Digital Audio PWM Processor data manual – TI Literature Number SLAS328
TAS5012 Digital Audio PWM Processor data manual – TI Literature Number SLES006
Digital Audio Measurements – TI literature number SLAA114
PowerPAD Thermally Enhanced Package – TI literature number SLMA002
www.ti.com |
3 |
TAS5110
SLES028A – MAY 2002 – REVISED SEPTEMBER 2002
functional block diagram
PWM_AP
PWM_AM
BIAS_A
PWDN
RESET
SHUTDOWN
ERR1
ERR0
LDROUTB
PVDDB2
VRFILT
BIAS_B
PWM_BM
PWM_BP
PVDDA2 |
LDROUTA |
BOOTSTRAPA |
PVDDA1 |
PVDDA1 |
1/2 H-Bridge
LDR |
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OUTPUTA |
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DIFF |
Boot Strap |
OUTPUTA |
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RCVR |
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Gate Drive |
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PVSS |
Control/Sense |
Bandgap |
Circuit |
Reference |
BOOTSTRAPB
PVDDB1
1/2 H-Bridge |
PVDDB1 |
LDR |
DIFF |
Boot Strap |
OUTPUTB |
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RCVR |
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Gate Drive |
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OUTPUTB |
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DVDD |
DVSS |
PVSS |
4 |
www.ti.com |
TAS5110
SLES028A – MAY 2002 – REVISED SEPTEMBER 2002
suggested system block diagrams
Digital Audio
•USB
•IEEE 1394
•SPDIF
•ADC
•Automotive MOST
Network |
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IIC |
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TAS30xx |
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Audio |
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Control |
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Digital Parametric EQ |
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•Volume
•DRC
•Bass
•Treble
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TAS5110 |
L-C |
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Left |
Filter |
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TAS50xx |
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Right |
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TAS5110 |
L-C |
Serial Audio Input Port |
Filter |
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Internal PLL |
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Two H-Bridges |
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Figure 1. System #1: Stereo Configuration With a TAS3001 Digital Audio Processor
CH1 |
TAS5110 |
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TAS50xx |
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CH2 |
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TAS5110 |
L-C
Filter Left
L-C
Right
Filter
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CH3 |
TAS5110 |
Home Theater |
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TI DSP |
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DVD 6-Channel |
6 |
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Dolby AC-3 |
TAS50xx |
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Encoded Digital |
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DTS |
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CH4 |
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Audio Source |
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Volume |
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• |
EQ |
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TAS5110 |
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DRC |
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Bass |
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Treble |
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CH5 |
TAS5110 |
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TAS50xx |
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CH6 |
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TAS5110 |
Figure 2. System #3: 6-Channel Audio Playback
L-C |
Surround Left |
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Filter |
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L-C |
Surround Right |
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Filter |
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L-C |
Center |
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Filter |
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L-C |
Subwoofer |
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Filter |
www.ti.com |
5 |
TAS5110
SLES028A – MAY 2002 – REVISED SEPTEMBER 2002
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Terminal Functions |
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TERMINAL |
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I/O |
DESCRIPTION |
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NAME |
DAP |
DAD |
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NO. |
NO. |
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BIAS_A |
11 |
6 |
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Connect external resistor to DVSS. |
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BIAS_B |
12 |
5 |
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Connect external resistor to DVSS. |
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BOOTSTRAPA |
30 |
19 |
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Bootstrap capacitor pin for H-bridge A |
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BOOTSTRAPB |
19 |
30 |
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Bootstrap capacitor pin for H-bridge B |
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DVDD |
6 |
11 |
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3.3-V digital voltage supply for logic |
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DVSS |
7, 8, 9 |
8, 9, |
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Digital ground for logic is internally connected to PVSS. All three pins must be tied |
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together but not connected externally to PVSS. See Figure 5. |
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ERR1 |
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14 |
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Error/warning report indicator. This output is open drain with internal pullup resistor. |
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ERR0 |
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4 |
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Error/warning report indicator. This output is open drain with internal pullup resistor. |
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LDROUTA |
31 |
18 |
O |
Low voltage drop-out regulator output A (not to be used to supply current to external |
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circuitry) |
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LDROUTB |
18 |
31 |
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Low voltage drop-out regulator output B (not to be used to supply current to external |
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circuitry) |
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OUTPUTA |
26, 27 |
22, 23 |
O |
H-bridge output A |
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OUTPUTB |
22, 23 |
26, 27 |
O |
H-bridge output B |
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PVDDA1 |
28, 29 |
20, 21 |
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High voltage power supply, H-bridge A |
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PVDDA2 |
32 |
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High voltage power supply for low-dropout voltage regulator A-side |
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PVDDB1 |
20, 21 |
28, 29 |
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High voltage power supply, H-bridge B |
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PVDDB2 |
17 |
32 |
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High voltage power supply for low-dropout voltage regulator B-side |
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PVSS |
24, 25 |
24, 25 |
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High voltage power supply ground |
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PWDN |
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Power down = 0, normal mode = 1 |
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PWM_AM |
2 |
15 |
I |
PWM input A(–) |
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PWM_AP |
1 |
16 |
I |
PWM input A(+) |
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PWM_BP |
16 |
1 |
I |
PWM input B(+) |
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PWM_BM |
15 |
2 |
I |
PWM input B(–) |
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RESET |
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14 |
3 |
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Reset and mute mode = 0, normal mode = 1, when in reset mode, H-bridge MOSFETs are |
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in low-low output state. Asserting the RESET signal low causes all fault conditions to be |
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cleared. |
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SHUTDOWN |
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12 |
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Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0, when |
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device is in shutdown mode the H-bridge MOSFETs are in low-low output state. The |
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latched output can be cleared by asserting the RESET signal. This output is open drain |
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with internal pullup resistor. |
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VRFILT |
10 |
7 |
O |
A filter capacitor must be added between VRFILT and DVSS pins. |
NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS50xx output pins, and never left floating. Floating PWM input pins causes an illegal PWM input state signal to be asserted.
Dual pins: OUTPUTA, OUTPUTB, PVDDA1, and PVDDB1 must have both pins connected externally to the same point on the circuit board, respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high-current DMOS output devices. Failure to connect all the multiple pins to the same respective node results in excessive current flow in the internal bond wires and can cause the device to fail. All electrical characteristics are specified and measured with all of the multiple pins connected to the same node, respectively.
6 |
www.ti.com |