TAS5101IDAP
TAS5101
SLES039 – JUNE 2002
TRUE DIGITAL STEREO AUDIO AMPLIFIER
WITH PWM STEREO POWER OUTPUT STAGE
FEATURES
D2 × 15 W High-Quality Digital Amplifier Power
Stage
DSingle-Ended Output
D>95-dB Dynamic Range (TDAA System)
DTHD+N < 0.1% (1 kHz, 1 W to 15 W RMS Into 4 Ω )
D Power Efficiency > 90% Into 4-Ω to 8-Ω Load
DLow Profile, SMD 32-Pin PowerPAD Package
Requires No Heat-Sink When Using Recommended Layout
D2 × 15-W RMS Continuous Power Into 4 Ω
DSelf-Protecting Design
D3.3-V Digital Interface
DEMI Compliant When Used With Recommended System Design
APPLICATIONS
DDigital TV Audio Amplifier
DCar Audio Amplifiers and Head Units
DInternet Music Appliance
DMini/Micro Component Systems
DESCRIPTION
The TAS5101 is a high-performance true digital stereo audio amplifier (TDAA) Power Stage, designed to drive 2 × 15 watts per channel. The TAS5101 incorporates TI’s equibitt technology and is used in conjunction with a Digital Audio PWM processor (TAS50xx) to deliver high-power, true digital audio amplification. The efficiency of this digital amplifier can be greater than 90%, reducing the size of both the power supplies and heat sinks needed. The TAS5101 accepts a stereo PWM 3.3V input and controls the switching of an internal CMOS H-bridge.
When used with the TAS50xx PWM Processor, system performance of less than 0.09% THD is attainable. Over-current protection, over-temperature, and under-voltage protections are built into the TAS5101, safeguarding the H-bridge and speakers against output shorts, over-voltage conditions, and other fault conditions that could damage the system.
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TYPICAL TDAA STEREO AUDIO SYSTEM |
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Digital Audio |
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L-C |
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Filter |
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TAS3001 |
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TAS3103 |
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TAS5010 |
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TAS5101 |
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DSP |
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DIR1703 |
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L-C |
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1394 |
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Filter |
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•Volume
•EQ
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DRC |
• Serial Audio Input Port |
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Bass |
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Internal PLL |
• 2 × 15 W Single-Ended |
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Treble |
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PCM–PWM Modulator |
H-Bridge Power Devices |
NOTE:
The TAS5000 in NOT recommended for use with the TAS5101
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and Equibit are trademarks of Texas Instruments.
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PRODUCTION DATA information is current as of publication date. |
Copyright 2002, Texas Instruments Incorporated |
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Products conform to specifications per the terms of Texas Instruments |
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standard warranty. Production processing does not necessarily include |
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testing of all parameters. |
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www.ti.com |
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TAS5101
SLES039 – JUNE 2002
terminal assignments
The TAS5101 is offered in a thermally enhanced 32-pin HTSSOP surface-mount package (DAP).
DAP PACKAGE (TOP VIEW)
PWM_AP |
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1 |
32 |
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PVDDA2 |
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PWM_AM |
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31 |
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LDROUTA |
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ERR1 |
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30 |
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BOOTSTRAPA |
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ERR0 |
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4 |
29 |
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PVDDA1 |
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5 |
28 |
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PVDDA1 |
SHUTDOWN |
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DVDD |
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27 |
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OUTPUTA |
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DVSS |
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26 |
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OUTPUTA |
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DVSS |
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PVSS |
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DVSS |
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24 |
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PVSS |
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VRFILT |
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23 |
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OUTPUTB |
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BIAS_A |
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22 |
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OUTPUTB |
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BIAS_B |
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21 |
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PVDDB1 |
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20 |
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PVDDB1 |
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HiZ |
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RESET |
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19 |
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BOOTSTRAPB |
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PWM_BM |
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18 |
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LDROUTB |
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PWM_BP |
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17 |
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PVDDB2 |
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ordering information
TA |
PACKAGE |
TAPE and Reel |
0° C to 70° C |
TAS5101DAP |
TAS5101DAPR |
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–40° C to 85° C |
TAS5101IDAP |
TAS5101IDAPR |
references
TAS5010 Digital Audio PWM Processor Data Manual – TI Literature Number SLAS328
System Design Considerations for True Digital Audio Power Amplifiers – TI Literature Number SLAA117
Digital Audio Measurements – TI Literature Number SLAA114
PowerPAD Thermally Enhanced Package – TI Literature Number SLMA002
TAS5101_SE Application Report – TI Literature Number SLEA001
suggested system block diagrams
See application note SLAA117 for more details.
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Digital Audio |
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L-C |
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Filter |
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TAS3001 |
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TAS3103 |
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TAS5010 |
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TAS5101 |
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DSP |
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DIR1703 |
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L-C |
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1394 |
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Filter |
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Digital Parametric EQ |
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Serial Audio Input Port |
• 2 × 1/2 H-Bridge |
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Volume |
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Internal PLL |
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DRC |
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Bass |
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Treble |
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Figure 1. System #1: Stereo Configuration With TAS3001 Digital Audio Processor
2 |
www.ti.com |
TAS5101
SLES039 – JUNE 2002
functional block diagram
PWM_AP
PWM_AM
BIAS_A
HiZ
RESET
SHUTDOWN
ERR1
ERR0
LDROUTB
PVDDB2
VRFILT
BIAS_B
PWM_BM
PWM_BP
PVDDA2 |
LDROUTA |
BOOTSTRAPA |
PVDDA1 |
PVDDA1 |
1/2 H-Bridge
LDR |
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OUTPUTA |
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DIFF |
Boot Strap |
OUTPUTA |
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RCVR |
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Gate Drive |
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PVSS |
Control/Sense |
Bandgap |
Circuit |
Reference |
BOOTSTRAPB
PVDDB1
1/2 H-Bridge |
PVDDB1 |
LDR |
DIFF |
Boot Strap |
OUTPUTB |
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RCVR |
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Gate Drive |
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OUTPUTB |
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DVDD |
DVSS |
PVSS |
www.ti.com |
3 |
TAS5101
SLES039 – JUNE 2002
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Terminal Functions |
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TERMINAL |
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I/O |
DESCRIPTION |
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NAME |
NO. |
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BIAS_A |
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11 |
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Connect external resistor to DVSS. See application note SLAA117 |
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BIAS_B |
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12 |
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Connect external resistor to DVSS. See application note SLAA117 |
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BOOTSTRAPA |
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30 |
O |
Bootstrap capacitor pin for H-bridge A |
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BOOTSTRAPB |
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19 |
O |
Bootstrap capacitor pin for H-bridge B |
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DVDD |
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3.3-V digital voltage supply for logic |
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DVSS |
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7, 8, 9 |
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Digital ground for logic is internally connected to PVSS. All three pins must be tied together but not |
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connected externally to PVSS. See Figure 5. |
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ERR1 |
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3 |
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Error/warning report indicator. This output is open drain with internal pullup resistor. |
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ERR0 |
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Error/warning report indicator. This output is open drain with internal pullup resistor. |
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LDROUTA |
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31 |
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Low voltage drop-out regulator output A (not to be used to supply current to external circuitry) |
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LDROUTB |
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18 |
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Low voltage drop-out regulator output B (not to be used to supply current to external circuitry) |
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OUTPUTA |
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26, 27 |
O |
H-bridge output A |
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OUTPUTB |
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22, 23 |
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H-bridge output B |
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PVDDA1 |
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28, 29 |
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High voltage power supply, H-bridge A |
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PVDDA2 |
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High voltage power supply for low-dropout voltage regulator A-side |
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PVDDB1 |
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20, 21 |
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High voltage power supply, H-bridge B |
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PVDDB2 |
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High voltage power supply for low-dropout voltage regulator B-side |
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PVSS |
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24, 25 |
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High voltage power supply ground |
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HiZ |
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13 |
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HiZ = 0, when asserted, the H-bridge output is set to high-impedance mode |
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PWM_AP |
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1 |
I |
PWM input A(+) |
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PWM_AM |
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2 |
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PWM input A(–) |
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PWM_BP |
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16 |
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PWM input B(+) |
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PWM_BM |
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15 |
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PWM input B(–) |
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RESET |
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14 |
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Reset and mute mode = 0, normal mode = 1, when in reset mode, H-bridge MOSFETs are in low-low |
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output state. Asserting the RESET signal low causes all fault conditions to be cleared. |
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SHUTDOWN |
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5 |
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Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0. The shutdown |
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condition can be cleared by asserting the RESET signal. This output is open drain with internal |
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pullup resistor. |
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VRFILT |
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10 |
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A filter capacitor should be added between VRFILT and DVSS pins. |
NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS5010 output pins, and never left floating. Floating PWM input pins will cause an illegal PWM input state signal to be asserted.
Dual pins: OUTPUTA, OUTPUTB, PVDDA1 and PVDDB1 must have both pins connected externally to the same point on the circuit board, respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high current DMOS output devices. Failure to connect all the multiple pins to the same respective node will result in excessive current flow in the internal bond wires and can cause the device to fail. All electrical characteristics are specified and measured with all of the multiple pins connected to the same node, respectively.
4 |
www.ti.com |
TAS5101
SLES039 – JUNE 2002
functional description
PWM H-bridge state control
The digital interface control signals consists of PWM_AP, PWM_AM, PWM_BP, and PWM_BM. These signals are a complementary differential signal format for the A-side H-bridge and the B-side H-bridge.
bootstrapped gate drive
The TAS5101 includes 2 dedicated bootstrapped power supplies. A bootstrap capacitor is connected between the individual bootstrap pin and the associated output as described in the application note SLAA117. For example, a capacitor will be connected between the BOOTSTRAPA pin and OUTPUTA pin, and another capacitor will be connected between the BOOTSTRAPB pin and the OUTPUTB pin. The bootstrap power supply minimizes the number of high voltage power supply levels externally supplied to the system while providing a low noise supply level for driving the high-side N-channel DMOS transistors. See application note SLAA117 for details.
low-dropout voltage regulator
Two on-chip low-dropout voltage regulators (LDO) are provided to minimize the number of external power supplies needed for the system. These voltage regulators are for internal circuits only and cannot be used for external circuitry. Each LDO is dedicated to an H-bridge and its gate driver. An LDO output capacitor is connected between the individual LDO output pin and the associated output return as described in the application note SLAA117. For example, a capacitor will be connected between the LDROUTA pin and PVSS pin, and another capacitor will be connected between the LDROUTB pin and PVSS pin. This capacitor is usually 0.1 F.
high-current H-bridge output stage
The positive outputs of the H-bridge are the two OUTPUTA pins. The negative outputs of the H-bridge are the two OUTPUTB pins. The logic for the input command to H-bridge outputs is described in the H-bridge output mapping section below. When the TAS5101 is in the normal mode, as seen in the H-bridge output mapping tables, the outputs are decoded from the inputs. However, the TAS5101 is immediately shut down if any of the following error conditions occur: over-current, over-temperature, low regulator output voltage, or an illegal PWM input state is applied. For these conditions, the outputs are set to the appropriate disabled state as specified in the H-bridge output mapping section, and the SHUTDOWN pin is set low.
H-bridge output mapping
The A-side and B-side H-bridge output is designed to the following truth table:
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INPUTS |
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OUTPUTS |
DESCRIPTION |
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RESET |
HiZ |
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PWM_AP/BP |
PWM_AM/BM |
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SHUTDOWN |
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OUTPUTA/B |
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0 or Hi-Z† |
Shutdown |
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0 |
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1 |
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Hi-Z |
High Impedance |
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0 |
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1 |
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X |
X |
1 |
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0 |
Low |
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1 |
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1 |
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0 |
0 |
0 |
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0 |
Low |
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1 |
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1 |
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0 |
1 |
1 |
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0 |
Normal |
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1 |
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1 |
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1 |
0 |
1 |
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1 |
Normal |
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1 |
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1 |
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1 |
1 |
0 |
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0 |
Low |
† Output is 0 for low voltage, over temperature, and illegal input. Hi-Z is for over current.
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5 |