TEXAS INSTRUMENTS TAS5101 Technical data

TAS5101IDAP

TAS5101

SLES039 – JUNE 2002

TRUE DIGITAL STEREO AUDIO AMPLIFIER

WITH PWM STEREO POWER OUTPUT STAGE

FEATURES

D2 × 15 W High-Quality Digital Amplifier Power

Stage

DSingle-Ended Output

D>95-dB Dynamic Range (TDAA System)

DTHD+N < 0.1% (1 kHz, 1 W to 15 W RMS Into 4 Ω )

D Power Efficiency > 90% Into 4-Ω to 8-Ω Load

DLow Profile, SMD 32-Pin PowerPAD Package

Requires No Heat-Sink When Using Recommended Layout

D2 × 15-W RMS Continuous Power Into 4 Ω

DSelf-Protecting Design

D3.3-V Digital Interface

DEMI Compliant When Used With Recommended System Design

APPLICATIONS

DDigital TV Audio Amplifier

DCar Audio Amplifiers and Head Units

DInternet Music Appliance

DMini/Micro Component Systems

DESCRIPTION

The TAS5101 is a high-performance true digital stereo audio amplifier (TDAA) Power Stage, designed to drive 2 × 15 watts per channel. The TAS5101 incorporates TI’s equibitt technology and is used in conjunction with a Digital Audio PWM processor (TAS50xx) to deliver high-power, true digital audio amplification. The efficiency of this digital amplifier can be greater than 90%, reducing the size of both the power supplies and heat sinks needed. The TAS5101 accepts a stereo PWM 3.3V input and controls the switching of an internal CMOS H-bridge.

When used with the TAS50xx PWM Processor, system performance of less than 0.09% THD is attainable. Over-current protection, over-temperature, and under-voltage protections are built into the TAS5101, safeguarding the H-bridge and speakers against output shorts, over-voltage conditions, and other fault conditions that could damage the system.

	TYPICAL TDAA STEREO AUDIO SYSTEM
Digital Audio								L-C
								Filter
•	TAS3001
•	TAS3103		TAS5010		TAS5101
•	DSP
•	DIR1703
								L-C
•	1394							Filter

•Volume

•EQ

•	DRC	• Serial Audio Input Port
•	Bass	•	Internal PLL	• 2 × 15 W Single-Ended
•	Treble	•	PCM–PWM Modulator	H-Bridge Power Devices

NOTE:

The TAS5000 in NOT recommended for use with the TAS5101

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD and Equibit are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.	Copyright 2002, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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TAS5101

SLES039 – JUNE 2002

terminal assignments

The TAS5101 is offered in a thermally enhanced 32-pin HTSSOP surface-mount package (DAP).

DAP PACKAGE (TOP VIEW)

PWM_AP						1	32			PVDDA2
PWM_AM						2	31			LDROUTA
	ERR1					3	30			BOOTSTRAPA
	ERR0					4	29			PVDDA1
						5	28			PVDDA1
SHUTDOWN
	DVDD					6	27			OUTPUTA
	DVSS					7	26			OUTPUTA
	DVSS					8	25			PVSS
	DVSS					9	24			PVSS
VRFILT						10	23			OUTPUTB
BIAS_A						11	22			OUTPUTB
BIAS_B						12	21			PVDDB1
						13	20			PVDDB1
		HiZ
	RESET					14	19			BOOTSTRAPB
PWM_BM						15	18			LDROUTB
PWM_BP						16	17			PVDDB2

ordering information

TA	PACKAGE	TAPE and Reel
0° C to 70° C	TAS5101DAP	TAS5101DAPR
–40° C to 85° C	TAS5101IDAP	TAS5101IDAPR

references

TAS5010 Digital Audio PWM Processor Data Manual – TI Literature Number SLAS328

System Design Considerations for True Digital Audio Power Amplifiers – TI Literature Number SLAA117

Digital Audio Measurements – TI Literature Number SLAA114

PowerPAD Thermally Enhanced Package – TI Literature Number SLMA002

TAS5101_SE Application Report – TI Literature Number SLEA001

suggested system block diagrams

See application note SLAA117 for more details.

Digital Audio

L-C

Filter

•

TAS3001

•

TAS3103

TAS5010

TAS5101

•

DSP

•

DIR1703

L-C

•

1394

Filter

•

Digital Parametric EQ

•

Serial Audio Input Port

• 2 × 1/2 H-Bridge

•

Volume

•

Internal PLL

•

DRC

•

Bass

•

Treble

Figure 1. System #1: Stereo Configuration With TAS3001 Digital Audio Processor

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TAS5101

SLES039 – JUNE 2002

functional block diagram

PWM_AP

PWM_AM

BIAS_A

HiZ

RESET

SHUTDOWN

ERR1

ERR0

LDROUTB

PVDDB2

VRFILT

BIAS_B

PWM_BM

PWM_BP

PVDDA2

LDROUTA

BOOTSTRAPA

PVDDA1

PVDDA1

1/2 H-Bridge

LDR

			OUTPUTA
	DIFF	Boot Strap	OUTPUTA
	RCVR
		Gate Drive
			PVSS

Control/Sense	Bandgap
Circuit	Reference

BOOTSTRAPB

PVDDB1

1/2 H-Bridge

PVDDB1

LDR

	DIFF	Boot Strap	OUTPUTB
	RCVR
		Gate Drive
			OUTPUTB

DVDD

DVSS

PVSS

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TAS5101

SLES039 – JUNE 2002

										Terminal Functions
				TERMINAL					I/O	DESCRIPTION
		NAME						NO.
	BIAS_A							11	I	Connect external resistor to DVSS. See application note SLAA117
	BIAS_B							12	I	Connect external resistor to DVSS. See application note SLAA117
	BOOTSTRAPA							30	O	Bootstrap capacitor pin for H-bridge A
	BOOTSTRAPB							19	O	Bootstrap capacitor pin for H-bridge B
	DVDD							6	I	3.3-V digital voltage supply for logic
	DVSS							7, 8, 9	I	Digital ground for logic is internally connected to PVSS. All three pins must be tied together but not
										connected externally to PVSS. See Figure 5.
	ERR1							3	O	Error/warning report indicator. This output is open drain with internal pullup resistor.
	ERR0							4	O	Error/warning report indicator. This output is open drain with internal pullup resistor.
	LDROUTA							31	O	Low voltage drop-out regulator output A (not to be used to supply current to external circuitry)
	LDROUTB							18	O	Low voltage drop-out regulator output B (not to be used to supply current to external circuitry)
	OUTPUTA							26, 27	O	H-bridge output A
	OUTPUTB							22, 23	O	H-bridge output B
	PVDDA1							28, 29	I	High voltage power supply, H-bridge A
	PVDDA2							32	I	High voltage power supply for low-dropout voltage regulator A-side
	PVDDB1							20, 21	I	High voltage power supply, H-bridge B
	PVDDB2							17	I	High voltage power supply for low-dropout voltage regulator B-side
	PVSS							24, 25	I	High voltage power supply ground
	HiZ							13	I	HiZ = 0, when asserted, the H-bridge output is set to high-impedance mode
	PWM_AP							1	I	PWM input A(+)
	PWM_AM							2	I	PWM input A(–)
	PWM_BP							16	I	PWM input B(+)
	PWM_BM							15	I	PWM input B(–)
	RESET							14	I	Reset and mute mode = 0, normal mode = 1, when in reset mode, H-bridge MOSFETs are in low-low
										output state. Asserting the RESET signal low causes all fault conditions to be cleared.
	SHUTDOWN							5	O	Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0. The shutdown
										condition can be cleared by asserting the RESET signal. This output is open drain with internal
										pullup resistor.
	VRFILT							10	O	A filter capacitor should be added between VRFILT and DVSS pins.

NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS5010 output pins, and never left floating. Floating PWM input pins will cause an illegal PWM input state signal to be asserted.

Dual pins: OUTPUTA, OUTPUTB, PVDDA1 and PVDDB1 must have both pins connected externally to the same point on the circuit board, respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high current DMOS output devices. Failure to connect all the multiple pins to the same respective node will result in excessive current flow in the internal bond wires and can cause the device to fail. All electrical characteristics are specified and measured with all of the multiple pins connected to the same node, respectively.

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TAS5101

SLES039 – JUNE 2002

functional description

PWM H-bridge state control

The digital interface control signals consists of PWM_AP, PWM_AM, PWM_BP, and PWM_BM. These signals are a complementary differential signal format for the A-side H-bridge and the B-side H-bridge.

bootstrapped gate drive

The TAS5101 includes 2 dedicated bootstrapped power supplies. A bootstrap capacitor is connected between the individual bootstrap pin and the associated output as described in the application note SLAA117. For example, a capacitor will be connected between the BOOTSTRAPA pin and OUTPUTA pin, and another capacitor will be connected between the BOOTSTRAPB pin and the OUTPUTB pin. The bootstrap power supply minimizes the number of high voltage power supply levels externally supplied to the system while providing a low noise supply level for driving the high-side N-channel DMOS transistors. See application note SLAA117 for details.

low-dropout voltage regulator

Two on-chip low-dropout voltage regulators (LDO) are provided to minimize the number of external power supplies needed for the system. These voltage regulators are for internal circuits only and cannot be used for external circuitry. Each LDO is dedicated to an H-bridge and its gate driver. An LDO output capacitor is connected between the individual LDO output pin and the associated output return as described in the application note SLAA117. For example, a capacitor will be connected between the LDROUTA pin and PVSS pin, and another capacitor will be connected between the LDROUTB pin and PVSS pin. This capacitor is usually 0.1 F.

high-current H-bridge output stage

The positive outputs of the H-bridge are the two OUTPUTA pins. The negative outputs of the H-bridge are the two OUTPUTB pins. The logic for the input command to H-bridge outputs is described in the H-bridge output mapping section below. When the TAS5101 is in the normal mode, as seen in the H-bridge output mapping tables, the outputs are decoded from the inputs. However, the TAS5101 is immediately shut down if any of the following error conditions occur: over-current, over-temperature, low regulator output voltage, or an illegal PWM input state is applied. For these conditions, the outputs are set to the appropriate disabled state as specified in the H-bridge output mapping section, and the SHUTDOWN pin is set low.

H-bridge output mapping

The A-side and B-side H-bridge output is designed to the following truth table:

						INPUTS				OUTPUTS			DESCRIPTION
RESET			HiZ				PWM_AP/BP	PWM_AM/BM		SHUTDOWN		OUTPUTA/B
	X			X			X	X	0			0 or Hi-Z†	Shutdown
	X		0				X	X	1			Hi-Z	High Impedance
0			1				X	X	1			0	Low
1			1				0	0	0			0	Low
1			1				0	1	1			0	Normal
1			1				1	0	1			1	Normal
1			1				1	1	0			0	Low

† Output is 0 for low voltage, over temperature, and illegal input. Hi-Z is for over current.

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