TEXAS INSTRUMENTS TAS5100A Technical data
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TAS5100A
SLES030 – FEBRUARY 2002
TRUE DIGITAL AUDIO AMPLIFIER
TAS5100A PWM POWER OUTPUT STAGE
FEATURES
TAS5000 + TAS5100A TDAA System-High
D
Quality Digital Audio Amplification
D 93-dB Dynamic Range (TDAA System)
D THD+N < 0.08% (1 kHz, 1 W to 30 W RMS
Into 6 Ω)
D Power Efficiency > 90% Into 8-Ω Load
D Low Profile, SMD 32-Pin PowerPAD Package
Requires No Heat-Sink When Using
Recommended Layout
D 30-W RMS Continuous Power Into 4 Ω to 8 Ω
D Self-Protecting Design
D 3.3-V Digital Interface
D EMI Compliant When Used With
Recommended System Design
APPLICATIONS
DVD Receiver
D
D Home Theater
D Car Audio Amplifiers and Head Units
D Internet Music Appliance
D Mini/Micro Component Systems
DESCRIPTION
True digital audio amplifier (TDAA) is a new paradigm
in digital audio. The TDAA system currently consists of
the TAS5000 PCM-PWM modulator device +
TAS5100A PWM power output device. This system
accepts a serial PCM digital audio stream and converts
it to a 3.3-V PWM audio stream (TAS5000). The
TAS5100A device then provides a large-signal PWM
output. This digital PWM signal is then demodulated
providing power output for driving loudspeakers. This
patented technology provides low-cost, high-quality,
high-efficient digital audio applicable to many audio
systems developed for the digital age. The TAS5100A
is a single-channel PWM power audio device. It
contains integrated gate drivers, four matched and
electrically isolated enhancement- mode N-channel
power DMOS transistors. Also, included are protection
and fault-reporting circuitry . This device is optimized for
use with the TAS5000 digital modulator.
TYPICAL TDAA STEREO AUDIO SYSTEM
Digital Audio
• TAS3001
• DSP
• SPDIF
• 1394
• Volume
• EQ
• DRC
• Bass
• Treble
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and Equibit are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• Serial Audio Input Port
• Internal PLL
• PCM–PWM Modulator
TAS5000
Left
Right
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TAS5100
A
TAS5100
A
• 2 H-Bridge Power Devices
Copyright 2002, Texas Instruments Incorporated
L-C
Filter
L-C
Filter
1
TAS5100A
SLES030 – FEBRUARY 2002
terminal assignments
The TAS5100A is offered in a thermally enhanced 32-pin HTSSOP surface-mount package (DAP).
DAP PACKAGE
(TOP VIEW)
ordering information
T
A
0°C to 70°C TAS5100ADAP
–40°C to 85°C TAS5100AIDAP
references
SHUTDOWN
PACKAGE
PWM_AP
PWM_AM
ERR1
ERR0
DVDD
DVSS
DVSS
DVSS
VRFILT
BIAS_A
BIAS_B
PWDN
RESET
PWM_BM
PWM_BP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PVDDA2
LDROUTA
BOOTSTRAPA
PVDDA1
PVDDA1
OUTPUTA
OUTPUTA
PVSS
PVSS
OUTPUTB
OUTPUTB
PVDDB1
PVDDB1
BOOTSTRAPB
LDROUTB
PVDDB2
TAS5000 Digital Audio PWM Process Data Manual – TI Literature Number SLAS270
System Design Considerations for True Digital Audio Power Amplifiers – TI Literature Number SLAA117
Digital Audio Measurements – TI Literature Number SLAA114
PowerPAD Thermally Enhanced Package – TI Literature Number SLMA002
2
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A
functional block diagram
TAS5100A
SLES030 – FEBRUARY 2002
PWM_AP
PWM_AM
BIAS_A
PWDN
RESET
SHUTDOWN
ERR1
ERR0
LDROUTB
PVDDB2
VRFILT
BIAS_B
PWM_BM
PWM_BP
PVDDA2
LDR
DIFF
RCVR
Control/Sense
Circuit
LDR
DIFF
RCVR
LDROUTA
Boot Strap
Gate Drive
Boot Strap
Gate Drive
BOOTSTRAP
1/2 H-Bridge
Bandgap
Reference
1/2 H-Bridge
PVDDA1
PVDDA1
OUTPUTA
OUTPUTA
PVSS
BOOTSTRAPB
PVDDB1
PVDDB1
OUTPUTB
OUTPUTB
DVDD
DVSS
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PVSS
3
TAS5100A
SLES030 – FEBRUARY 2002
suggested system block diagrams
See application note SLAA117 for more details.
Digital Audio
• USB
• IEEE 1394
• SPDIF
• ADC
• Automotive
MOST
Network
IIC
Audio
Control
Figure 1. System #1: Stereo Configuration With TAS3001 Digital Audio Processor
TAS3001
• Digital Parametric EQ
• Volume
• DRC
• Bass
• Treble
Left
TAS5000
Right
• Serial Audio Input Port
• Internal PLL
TAS5100A
TAS5100A
• Two H-Bridges
Home Theater
DVD 6-Channel
Encoded Digital
Audio Source
6
TI DSP
• Dolby AC-3
• DTS
• Volume
• EQ
• DRC
• Bass
• Treble
TAS5000
TAS5000
TAS5000
CH1
CH2
CH3
CH4
CH5
CH6
TAS5100A
TAS5100A
TAS5100A
TAS5100A
TAS5100A
TAS5100A
Left
Right
Surround Left
Surround Right
Center
Subwoofer
TAS5100A
Figure 2. System #3: 6-Channel Audio Playback
4
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SLES030 – FEBRUARY 2002
TAS5100A
Terminal Functions
TERMINAL
NAME NO.
BIAS_A 11 I Connect external resistor to DVSS. See application note SLAA117
BIAS_B 12 I Connect external resistor to DVSS. See application note SLAA1 17
BOOTSTRAPA 30 O Bootstrap capacitor pin for H-bridge A
BOOTSTRAPB 19 O Bootstrap capacitor pin for H-bridge B
DVDD 6 I 3.3-V digital voltage supply for logic
DVSS 7, 8, 9 I Digital ground for logic is internally connected to PVSS. All three pins must be tied together but not
ERR1 3 O Error/warning report indicator. This output is open drain with internal pullup resistor.
ERR0 4 O Error/warning report indicator. This output is open drain with internal pullup resistor.
LDROUTA 31 O Low voltage drop-out regulator output A (not to be used to supply current to external circuitry)
LDROUTB 18 O Low voltage drop-out regulator output B (not to be used to supply current to external circuitry)
OUTPUTA 26, 27 O H-bridge output A
OUTPUTB 22, 23 O H-bridge output B
PVDDA1 28, 29 I High voltage power supply, H-bridge A
PVDDA2 32 I High voltage power supply for low-dropout voltage regulator A-side
PVDDB1 20, 21 I High voltage power supply, H-bridge B
PVDDB2 17 I High voltage power supply for low-dropout voltage regulator B-side
PVSS 24, 25 I High voltage power supply ground
PWDN 13 I Power down = 0, normal mode = 1
PWM_AP 1 I PWM input A(+)
PWM_AM 2 I PWM input A(–)
PWM_BP 16 I PWM input B(+)
PWM_BM 15 I PWM input B(–)
RESET 14 I Reset and mute mode = 0, normal mode = 1, when in reset mode, H-bridge MOSFET s are in low-low
SHUTDOWN 5 O Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0, when device is in
VRFILT 10 O A filter capacitor must be added between VRFILT and DVSS pins.
NOTE: The four PWM inputs: PWM_AP , PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS5000 output pins, and never
left floating. Floating PWM input pins causes an illegal PWM input state signal to be asserted.
I/O
connected externally to PVSS. See Figure 5.
output state. Asserting the RESET
shutdown mode the H-bridge MOSFETs are in low-low output state. The latched output can be
cleared by asserting the RESET signal. This output is open drain with internal pullup resistor.
DESCRIPTION
signal low causes all fault conditions to be cleared.
Dual pins: OUTPUTA, OUTPUTB, PVDDA1 and PVDDB1 must have both pins connected externally to the same point on the circuit board,
respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high current DMOS output
devices. Failure to connect all the multiple pins to the same respective node results in excessive current flow in the internal bond wires
and can cause the device to fail. All electrical characteristics are specified and measured with all of the multiple pins conne cted to the same
node, respectively .
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