TEXAS INSTRUMENTS TAS5100A Technical data
TAS5100
TAS5100A
SLES030 – FEBRUARY 2002
TRUE DIGITAL AUDIO AMPLIFIER
TAS5100A PWM POWER OUTPUT STAGE
FEATURES
DTAS5000 + TAS5100A TDAA System-High Quality Digital Audio Amplification
D93-dB Dynamic Range (TDAA System)
DTHD+N < 0.08% (1 kHz, 1 W to 30 W RMS Into 6 Ω )
DPower Efficiency > 90% Into 8-Ω Load
DLow Profile, SMD 32-Pin PowerPAD Package
Requires No Heat-Sink When Using Recommended Layout
D30-W RMS Continuous Power Into 4 Ω to 8 Ω
DSelf-Protecting Design
D3.3-V Digital Interface
DEMI Compliant When Used With Recommended System Design
APPLICATIONS
DDVD Receiver
DHome Theater
DCar Audio Amplifiers and Head Units
DInternet Music Appliance
DMini/Micro Component Systems
DESCRIPTION
True digital audio amplifier (TDAA) is a new paradigm in digital audio. The TDAA system currently consists of the TAS5000 PCM-PWM modulator device + TAS5100A PWM power output device. This system accepts a serial PCM digital audio stream and converts it to a 3.3-V PWM audio stream (TAS5000). The TAS5100A device then provides a large-signal PWM output. This digital PWM signal is then demodulated providing power output for driving loudspeakers. This patented technology provides low-cost, high-quality, high-efficient digital audio applicable to many audio systems developed for the digital age. The TAS5100A is a single-channel PWM power audio device. It contains integrated gate drivers, four matched and electrically isolated enhancementmode N-channel power DMOS transistors. Also, included are protection and fault-reporting circuitry. This device is optimized for use with the TAS5000 digital modulator.
TYPICAL TDAA STEREO AUDIO SYSTEM
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Left |
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Digital Audio |
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TAS5100 |
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L-C |
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Filter |
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A |
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TAS3001 |
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DSP |
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TAS5000 |
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SPDIF |
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Right |
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1394 |
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TAS5100 |
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L-C |
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Filter |
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A |
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Volume |
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EQ |
• Serial Audio Input Port |
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DRC |
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Bass |
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Internal PLL |
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Treble |
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PCM–PWM Modulator |
• 2 H-Bridge Power Devices |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and Equibit are trademarks of Texas Instruments.
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PRODUCTION DATA information is current as of publication date. |
Copyright 2002, Texas Instruments Incorporated |
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Products conform to specifications per the terms of Texas Instruments |
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standard warranty. Production processing does not necessarily include |
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testing of all parameters. |
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www.ti.com |
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TAS5100A
SLES030 – FEBRUARY 2002
terminal assignments
The TAS5100A is offered in a thermally enhanced 32-pin HTSSOP surface-mount package (DAP).
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DAP PACKAGE |
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(TOP VIEW) |
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PWM_AP |
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PVDDA2 |
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1 |
32 |
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PWM_AM |
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2 |
31 |
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LDROUTA |
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ERR1 |
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3 |
30 |
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BOOTSTRAPA |
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ERR0 |
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4 |
29 |
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PVDDA1 |
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5 |
28 |
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PVDDA1 |
SHUTDOWN |
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DVDD |
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27 |
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OUTPUTA |
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DVSS |
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26 |
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OUTPUTA |
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DVSS |
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8 |
25 |
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PVSS |
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DVSS |
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24 |
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PVSS |
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VRFILT |
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23 |
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OUTPUTB |
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BIAS_A |
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22 |
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OUTPUTB |
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BIAS_B |
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12 |
21 |
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PVDDB1 |
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PWDN |
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20 |
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PVDDB1 |
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RESET |
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19 |
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BOOTSTRAPB |
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PWM_BM |
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18 |
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LDROUTB |
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PWM_BP |
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17 |
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PVDDB2 |
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ordering information
TA |
PACKAGE |
0° C to 70° C |
TAS5100ADAP |
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–40° C to 85° C |
TAS5100AIDAP |
references
TAS5000 Digital Audio PWM Process Data Manual – TI Literature Number SLAS270
System Design Considerations for True Digital Audio Power Amplifiers – TI Literature Number SLAA117
Digital Audio Measurements – TI Literature Number SLAA114
PowerPAD Thermally Enhanced Package – TI Literature Number SLMA002
2 |
www.ti.com |
TAS5100A
SLES030 – FEBRUARY 2002
functional block diagram
PWM_AP
PWM_AM
BIAS_A
PWDN
RESET
SHUTDOWN
ERR1
ERR0
LDROUTB
PVDDB2
VRFILT
BIAS_B
PWM_BM
PWM_BP
PVDDA2 |
LDROUTA |
BOOTSTRAPA |
PVDDA1 |
PVDDA1 |
1/2 H-Bridge
LDR |
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OUTPUTA |
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DIFF |
Boot Strap |
OUTPUTA |
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RCVR |
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Gate Drive |
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PVSS |
Control/Sense |
Bandgap |
Circuit |
Reference |
BOOTSTRAPB
PVDDB1
1/2 H-Bridge |
PVDDB1 |
LDR |
DIFF |
Boot Strap |
OUTPUTB |
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RCVR |
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Gate Drive |
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OUTPUTB |
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DVDD |
DVSS |
PVSS |
www.ti.com |
3 |
TAS5100A
SLES030 – FEBRUARY 2002
suggested system block diagrams
See application note SLAA117 for more details.
Digital Audio
•USB
•IEEE 1394
•SPDIF
•ADC
•Automotive MOST
Network |
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IIC |
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TAS3001 |
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Audio |
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Control |
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Digital Parametric EQ |
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•Volume
•DRC
•Bass
•Treble
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Left |
TAS5100A |
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TAS5000 |
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Right |
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Serial Audio Input Port |
TAS5100A |
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Internal PLL |
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Two H-Bridges |
Figure 1. System #1: Stereo Configuration With TAS3001 Digital Audio Processor
TAS5000 |
Home Theater |
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TI DSP |
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DVD 6-Channel |
6 |
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Dolby AC-3 |
TAS5000 |
Encoded Digital |
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DTS |
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Audio Source |
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Volume |
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EQ |
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DRC |
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Bass |
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Treble |
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TAS5000 |
CH1 |
TAS5100A |
Left |
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CH2 |
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TAS5100A |
Right |
CH3 |
TAS5100A |
Surround Left |
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CH4 |
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TAS5100A |
Surround Right |
CH5 |
TAS5100A |
Center |
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CH6 |
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TAS5100A |
Subwoofer |
TAS5100A
Figure 2. System #3: 6-Channel Audio Playback
4 |
www.ti.com |
TAS5100A
SLES030 – FEBRUARY 2002
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Terminal Functions |
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TERMINAL |
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I/O |
DESCRIPTION |
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NAME |
NO. |
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BIAS_A |
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11 |
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Connect external resistor to DVSS. See application note SLAA117 |
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BIAS_B |
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12 |
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Connect external resistor to DVSS. See application note SLAA117 |
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BOOTSTRAPA |
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30 |
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Bootstrap capacitor pin for H-bridge A |
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BOOTSTRAPB |
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19 |
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Bootstrap capacitor pin for H-bridge B |
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DVDD |
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6 |
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3.3-V digital voltage supply for logic |
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DVSS |
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Digital ground for logic is internally connected to PVSS. All three pins must be tied together but not |
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connected externally to PVSS. See Figure 5. |
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ERR1 |
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3 |
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Error/warning report indicator. This output is open drain with internal pullup resistor. |
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ERR0 |
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4 |
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Error/warning report indicator. This output is open drain with internal pullup resistor. |
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LDROUTA |
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31 |
O |
Low voltage drop-out regulator output A (not to be used to supply current to external circuitry) |
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LDROUTB |
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18 |
O |
Low voltage drop-out regulator output B (not to be used to supply current to external circuitry) |
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OUTPUTA |
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26, 27 |
O |
H-bridge output A |
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OUTPUTB |
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22, 23 |
O |
H-bridge output B |
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PVDDA1 |
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28, 29 |
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High voltage power supply, H-bridge A |
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PVDDA2 |
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32 |
I |
High voltage power supply for low-dropout voltage regulator A-side |
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PVDDB1 |
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20, 21 |
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High voltage power supply, H-bridge B |
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PVDDB2 |
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17 |
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High voltage power supply for low-dropout voltage regulator B-side |
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PVSS |
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24, 25 |
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High voltage power supply ground |
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PWDN |
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13 |
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Power down = 0, normal mode = 1 |
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PWM_AP |
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1 |
I |
PWM input A(+) |
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PWM_AM |
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2 |
I |
PWM input A(–) |
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PWM_BP |
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16 |
I |
PWM input B(+) |
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PWM_BM |
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15 |
I |
PWM input B(–) |
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RESET |
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14 |
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Reset and mute mode = 0, normal mode = 1, when in reset mode, H-bridge MOSFETs are in low-low |
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output state. Asserting the RESET signal low causes all fault conditions to be cleared. |
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SHUTDOWN |
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5 |
O |
Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0, when device is in |
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shutdown mode the H-bridge MOSFETs are in low-low output state. The latched output can be |
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cleared by asserting the RESET signal. This output is open drain with internal pullup resistor. |
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VRFILT |
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10 |
O |
A filter capacitor must be added between VRFILT and DVSS pins. |
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NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS5000 output pins, and never left floating. Floating PWM input pins causes an illegal PWM input state signal to be asserted.
Dual pins: OUTPUTA, OUTPUTB, PVDDA1 and PVDDB1 must have both pins connected externally to the same point on the circuit board, respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high current DMOS output devices. Failure to connect all the multiple pins to the same respective node results in excessive current flow in the internal bond wires and can cause the device to fail. All electrical characteristics are specified and measured with all of the multiple pins connected to the same node, respectively.
www.ti.com |
5 |
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