TEXAS INSTRUMENTS TAS5086 Technical data

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PurePath Digital™ AUDIO SIX-CHANNEL PWM PROCESSOR

TAS5086

SLES131B – FEBRUARY 2005 – REVISED JUNE 2007

FEATURES

– Full Six-Channel Input and Output Mapping

• Audio Input/Output – Selectable DC Blocking Filters – Automatic Master Clock Rate and Data • PWM Processing

Sample Rate Detection

– 8 × Oversampling With Fourth-Order Noise

– Four Serial Audio Inputs (Eight Channels) Shaping at 44.1, 48 kHz; 4 × Oversampling – Support for 32-, 44.1-, 48-, 88.2-, 96-, 176.4-,

and 192-kHz Sampling Rates

– Data Formats: 16-, 20-, or 24-Bit Input Data;

Left-Justified, Right-Justified, and I2S

– 64- or 48-f

Bit-Clock Rate

– 128-, 192-, 256-, 384-, and 512-f

Clock Rates (Up to a Maximum of 50 MHz) – Six PWM Audio Output Channels – Any Output Channel Can be Mapped to

Any Output Pin – Supports Single-Ended and Bridge-Tied

Loads – I2S Serial Audio Output

• Audio Processing

– Volume Control Range of 48 dB to –100 dB – Master Volume Control from 24 dB to –100

dB in 0.5-dB Increments – Six Individual Channel Volume Controls

With 24-dB to –100-dB Attenuation in

0.5-dB Increments

– Serial Output Can Be Produced by

Downmix of 5.1-Channel Input or Fourth

Serial Input – 5.1-Channel Downmix to 2.1 or 3.1 PWM

Output Speaker System – Integrated Bass Management – Two Programmable Biquads in Subwoofer

Master

at 88.2, 96 kHz; 2 × Oversampling at 176.4, 192 kHz; and 12 × Oversampling at 32 kHz

– ≥ 105-dB Dynamic Range

(TAS5086+TAS5186) – THD < 0.06% (TAS5086 Only) – 20-Hz–20-kHz Flat Noise Floor for 44.1-,

48-, 88.2-, 96-, 176.4- and 192-kHz Data

Rates – Digital De-Emphasis for 32-kHz, 44.1-kHz

and 48-kHz Data Rates – Intelligent AM Interference Avoidance

System Provides Clear AM Reception – Optimized PWM Sequence for Click- and

Popless Start and Stop – Optimized PWM Sequence for Charging of

AC-Coupling Capacitors in Single-Ended

Configurations – Adjustable Modulation Limit From 93.8% to

99.2%

• General Features

– Automated Operation With Easy-to-Use

Control Interface – I2C Serial Control Slave Interface – Control Interface Operational Without

MCLK – Single 3.3-V Power Supply – 38-Pin TSSOP Package

Channel

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PurePath Digital is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TAS5086

SLES131B – FEBRUARY 2005 – REVISED JUNE 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION

The TAS5086 is a six-channel digital pulse-width modulator (PWM) that provides both advanced performance and a high level of system integration. The TAS5086 is designed to interface seamlessly with most audio digital signal processors and MPEG decoders, accepting a wide range of input data and clock formats.

The TAS5086 drives six channels of speakers in either single-ended or bridge-tied load configurations that accept a 1N + 1 interface format. The TAS5086 also supports 2N + 1 power stages with the use of some external logic (e.g., TAS5112). Stereo line out in I2S format is available with either a pass-through signal (SDIN4) or an internal downmix.

The TAS5086 uses AD modulation operating at a 384-kHz switching rate for 32-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz data. The 8 × oversampling, combined with the 4th-order noise shaper, provides a broad, flat noise floor and excellent dynamic range from 20 Hz to 20 kHz.

The TAS5086 is only an I2C slave device, which always receives MCLK, SCLK, and LRCLK from other system components. The TAS5086 accepts clock rates of 128, 192, 256, 384, and 512 fS. The TAS5086 accepts a 64-f master clock for 176.4-kHz and 192-kHz data.

The TAS5086 accepts a 64-f MCLK ratios of 192 fSand 384 fS.

The TAS5086 is composed of five functional blocks.

• Power supply

• Clock, PLL, and serial data interface

• Serial control interface

• Device control

• PWM section

For detailed application information, see the Using the PurePath Digital PWM Processor application report (SLEA046 ).

bit clock for all data rates. The TAS5086 also can accept a 48-f

SCLK rate for

Figure 1 shows the functional structure of the TAS5086.

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Chan.

1 − 6

1− 5

SDIN1 SDIN2 SDIN3 SDIN4

SDA

SCL

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

VALID1

DVDD

DVSS

DVSS_ESD

VR_DIG VR_ANA VR_OSC

AVDD

AVSS_PLL

SDOUT

MCLK

SCLK

LRCLK

PLLFLTP

PLLFLTM

HFCLK

OSCFLT

OSC_RES

1 LF

2 RF

3 LS

4 RS

5 C

1− 6

L’

R’

L’

R’

(L’+R’) / 2

VALID2

1 − 5

1−6

SDIN4

Downmix

PWM

Control

PDN

RESET

MUTE

VREG_EN

BKNDERR

Channel Six Processing

Bass Management

B0080-01

Power Supply

Serial

Data

Interface

Channel Selector

Block

MUX

Down−

mix

Clock Rate

/Error

Detection

and PLL

Serial

Control

Interface

System Control

MUX

I2S Serial

Output

MUX

Vol

PWM

MUX

(L’+R’)/2

TAS5086

SLES131B – FEBRUARY 2005 – REVISED JUNE 2007

Figure 1. TAS5086 Functional Block Diagram

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TAS5086

SLES131B – FEBRUARY 2005 – REVISED JUNE 2007

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage

Input voltage

Input clamp current, IIK(V Output clamp current, IOK(V Operating free-air temperature 0 ° C to 70 ° C Storage temperature range, T

(1) Stresses beyond those listed under “absolute ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operation conditions” are not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.

(2) 5-V-tolerant inputs are RESET, PDN, MUTE, SCLK, LRCLK, MCLK, SDA, and SCL.

DVDD and DVD_ESD –0.3 V to 3.6 V AVDD –0.3 V to 3.6 V

3.3-V-digital input –0.5 V to DVDD + 0.5 V 5-V-tolerant

(2)

digital input –0.5 V to 6 V

< 0 or VI> 1.8 V ± 20 mA

< 0 or VO> 1.8 V ± 20 mA

stg

(1)

–65 ° C to 150 ° C

DISSIPATION RATINGS

PACKAGE

DBT 817.16 mW 10.214 mW/C 357.5 mW 204.29 mW

TA≤ 25 ° C DERATING FACTOR TA= 70 ° C TA= 85 ° C

POWER RATING ABOVE TA= 25 ° C POWER RATING POWER RATING

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

Digital supply voltage DVDD 3 3.3 3.6 V

Analog supply voltage AVDD 3 3.3 3.6 V V V T

High-level input voltage 3.3-V TTL, 5-V tolerant 2 V

Low-level input voltage 3.3-V TTL, 5-V tolerant 0.8 V

Operating ambient-air temperature range 0 25 70 ° C

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage 3.3-V TTL and 5-V

Low-level output voltage 3.3-V TTL and 5-V

High-impedance output current 3.3-V TTL 20 μ A

Low-level input current μ A

High-level input current μ A

3.3-V TTL VI= V 5-V tolerant

Digital supply voltage, DVDD mA

Input supply current

Analog supply voltage, AVDD mA

(1) 5-V-tolerant outputs are SCL and SDA (2) 5-V-tolerant inputs are SDA, SCL, RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, and SDIN4.

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(1)

tolerant IOH= –4 mA 2.4 V

(1)

tolerant IOL= 4 mA 0.5 V

(2)

VI= 0 V, DVDD = 3 V 1

VI= 5.5 V, DVDD = 3 V 20 fS= 48 kHz 140 fS= 96 kHz 150 fS= 192 kHz 155 Power down 8 Normal 20 Power down 2

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Serial Audio Port

su1

su2

SCLK

(Input)

LRCLK

(Input)

SDIN1 SDIN2 SDIN3

T0026-01

Serial audio port slave mode over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SCLK input frequency CL= 30 pF, SCLK = 64 f

SCLKIN

Setup time, LRCLK to SCLK rising edge 10 ns

su1

Hold time, LRCLK from SCLK rising edge 10 ns

Setup time, SDIN to SCLK rising edge 10 ns

su2

Hold time, SDIN from SCLK rising edge 10 ns

LRCLK frequency 32 48 192 kHz SCLK duty cycle 40% 50% 60% LRCLK duty cycle 40% 50% 60%

SCLK rising edges between LRCLK rising edges 64 64 LRCLK clock edge with respect to the falling edge of SCLK

SCLK period

TAS5086

SLES131B – FEBRUARY 2005 – REVISED JUNE 2007

2.048 12.288 MHz

–1/4 1/4

SCLK edges

Figure 2. Slave Mode Serial Data Interface Timing

TAS5086 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I2C-Bus Devices

PARAMETER TEST CONDITIONS UNIT

V V V

(1) Cb= capacitance of one bus line in pF. The output fall time is faster than the standard I2C specification.

LOW-level input voltage –0.5 0.3 V

HIGH-level input voltage 0.7 V

Hysteresis of Schmitt-trigger inputs N/A N/A 0.05 V

hys

LOW-level output voltage (open drain or

OL1

open collector)

Output fall time from V

Pulse duration of spikes suppressed

IHmin

VILmax

3-mA sink current 0 0.4 V Bus capacitance from 10 pF 7 + 0.1 C

to 400 pF

(2)

Input current, each I/O pin –30 30 –30

Capacitance, each I/O pin 10 10 pF

(2) SCL and SDA have a 30-ns glitch filter. (3) The I/O pins of fast-mode devices must not obstruct the SDA and SDL lines if V

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STANDARD MODE FAST MODE

MIN MAX MIN MAX

250 250 ns

N/A N/A 0 30 ns

is switched off.

0.7 V

–0.5 0.3 V

DD DD

(1)

(3)

V V

(3)

μ A

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SDA

SCL

SU-DAT

HD-STA

BUF

SU-STO

P S

SU-STA

HIGH

HD-DAT

LOW

HD-STA

T0114-01

TAS5086

SLES131B – FEBRUARY 2005 – REVISED JUNE 2007

TAS5086 Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I2C-Bus Devices

All values are referred to V

F/S-Mode I2C-Bus Devices ).

PARAMETER TEST CONDITIONS UNIT

SCL

HD-STA

LOW

HIGH

SU-STA

SU-DAT

HD-DAT

SU-STO

BUF

C V

(1) Note that SDA does not have the standard I2C specification 300-ns hold time and that SDA must be valid by the rising and falling edges (2) A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement t

(3) Cb= total capacitance of one bus line in pF. (4) Rise time varies with pullup resistor.

SCL clock frequency 0 100 0 400 kHz

Hold time (repeated) START condition.

After this period, the first clock pulse is 4 0.6 μ s

generated.

LOW period of the SCL clock 4.7 1.3 μ s

HIGH period of the SCL clock 4 0.6 μ s

Setup time for repeated START 4.7 0.6 μ s

Data setup time 250 100 μ s

Data hold time

(1) (2)

Rise time of both SDA and SCL 1000 7 + 0.1 C

Fall time of both SDA and SCL 300 7 + 0.1 C

Setup time for STOP condition 4 0.6 μ s

Bus free time between a STOP and 4.7 1.3 μ s

START condition

Capacitive loads for each bus line 400 400 pF

Noise margin at the LOW level for each

connected device (including hysteresis)

Noise margin at the HIGH level for each

connected device (including hysteresis)

of SCL. TI recommends that a 3.3-k Ω pullup resistor be used to avoid potential timing issues. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW

period of the SCL signal, it must output the next data bit to the SDA line t standard-mode I2C bus specification) before the SCL line is released.

and V

IHmin

(see TAS5086 Pin-Related Characteristics of the SDA and SCL I/O Stages for

ILmax

STANDARD MODE FAST MODE

MIN MAX MIN MAX

0 3.45 0 0.9 μ s

(3)

b b

0.1 V

0.2 V

+ t

r-max

= 1000 + 250 = 1250 ns (according to the

SU-DAT

0.1 V

0.2 V

≥ 250 ns must then be met.

SU-DAT

500

(3)

(4)

300 ns

Figure 3. Start and Stop Conditions Timing Waveforms

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Recommended I2C Pullup Resistors

B0099-05

TAS5086

External

Microcontroller

I(SDA)

5V

I(SCL)

SDA

SCL

B0100-05

TAS5086 External

Microcontroller

5V

SDA

SCL

(2)

(1)

(2)

It is recommended that the I2C pullup resistors R (see Figure 5 ), then the series resistor R

should be less than or equal to 300 Ω .

Figure 4. I2C Pullup Circuit (With No Series Resistor)

SLES131B – FEBRUARY 2005 – REVISED JUNE 2007

be 3.3 k Ω (see Figure 4 ). If a series resistor is in the circuit

TAS5086

(1) VS= 5 × RS/(R

+ RP). When driven low, VS<< VILrequirements.

(2) RS≤ 300 Ω

Figure 5. I2C Pullup Circuit (With Series Resistor)

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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20

VR_ANA

AVDD

AVSS AVSS

PLL_FLTM

PLL_FLTP

AVSS

MCLK

RESET

PDN DVDD DVSS

DVSS_OSC

OSC_RES

VR_OSC

MUTE

SDA

SCL

LRCLK

PWM_1 PWM_2 PWM_3 PWM_4 PWM_5 PWM_6 VALID2 VALID1 VR_DIG DVSS DVSS BKND_ERR SDIN1 SDIN2 SDIN3 SDIN4 SDOUT RESERVED SCLK

DBT PACKAGE

(TOP VIEW)

P0034-01

TAS5086

SLES131B – FEBRUARY 2005 – REVISED JUNE 2007

PHYSICAL CHARACTERISTICS

Table 1. TERMINAL FUNCTIONS

TERMINAL

NAME NO.

AVDD 2 P 3.3-V analog power supply

AVSS P Analog supply ground

BKND_ERR 27 DI Pullup LOW to this terminal. BKND_ERR results in no change to any system

DVDD 11 P 3.3-V digital power supply

DVSS 28, P Digital ground

DVSS_OSC 13 P Digital ground for oscillator

LRCLK 19 DI 5-V Pulldown Input serial audio data left/right clock (sampling rate clock)

MCLK 8 DI 5-V Pulldown

MUTE 16 DI 5-V Pullup

OSC_RES 14 AO Oscillator trim resistor

(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output (2) All pullups are 20- μ A weak pullups, and all pulldowns are 20- μ A weak pulldowns. The pullups and pulldowns are included to ensure

proper input logic levels if the terminals are left unconnected (pullups => logic 1 input; pulldowns => logic 0 input). Devices that drive inputs with pullups must be able to sink 20 μ A while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be able to source 20 μ A while maintaining a logic-1 drive level.

3, 4,

12,

(1)

I/O

5-V

TOLERANT

TERMINATION

(2)

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DESCRIPTION

Active-low. A back-end error sequence is generated by applying logic parameters while VALID2 goes low.

MCLK is a 3.3-V clock master clock input. The input frequency of this clock can range from 4 MHz to 50 MHz.

Performs a soft mute of outputs, active-low (muted signal = a logic low, normal operation = a logic high). The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp to previous volume.

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SLES131B – FEBRUARY 2005 – REVISED JUNE 2007

PHYSICAL CHARACTERISTICS (continued)

Table 1. TERMINAL FUNCTIONS (continued)

TERMINAL

NAME NO.

PDN 10 DI 5-V Pullup

PLL_FLTM 5 AO PLL negative input PLL_FLTP 6 AI PLL positive input

PWM_ 1 38 DO PWM 1 output PWM_ 2 37 DO PWM 2 output PWM_ 3 36 DO PWM 3 output PWM_ 4 35 DO PWM 4 output PWM_ 5 34 DO PWM 5 output PWM_ 6 33 DO PWM 6 output

RESERVED 21 – RESERVED (connect to ground)

RESET 9 DI 5-V Pullup

SCL 18 DI 5-V I2C serial control clock input

SCLK 20 DI 5-V Pulldown

SDA 17 DIO 5-V I2C serial control data interface input/output

SDIN1 26 DI Pulldown

SDIN2 25 DI Pulldown

SDIN3 24 DI Pulldown

SDIN4 23 DI Pulldown

SDOUT 22 DI

VALID1 31 DO VALID2 32 DO Output indicating validity of PWM outputs, active-high.

VR_ANA 1 P

VR_DIG 30 P

VR_OSC 15 P

(3) If desired, low-ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling

capacitors of equal value provides an extended high-frequency supply decoupling. This approach avoids the potential of producing parallel resonance circuits that have been observed when paralleling capacitors of different values.

(1)

I/O

5-V

TOLERANT

TERMINATION

(2)

Power down, active-low. PDN powers down all logic, stops all clocks, and performs a soft stop whenever a logic low is applied. The internal parameters are preserved through a power-down cycle, as long as RESET is not active. The duration for system recovery from power down is 100 ms. When released, PDN powers up all logic, starts all clocks, and performs a soft start that returns to the previous configuration.

A system reset is generated by applying a logic low to this terminal. RESET is an asynchronous control signal that restores the TAS5086 to its default conditions, sets the VALID2 output low, and places the PWM in the hard-mute (M) state. Master volume is immediately set to full attenuation. On the release of RESET, if PDN is high, the system performs a 4–5-ms device initialization and sets the volume at mute.

Serial audio data clock (shift clock). SCLKIN is the serial audio port (SAP) input data bit clock.

Serial audio data 1 input is one of the serial data input ports. SDIN1 supports four discrete (stereo) data formats.

Serial audio data 2 input is one of the serial data input ports. SDIN2 supports four discrete (stereo) data formats.

Serial audio data 3 input is one of the serial data input ports. SDIN3 supports four discrete (stereo) data formats.

Serial audio data 4 input is one of the serial data input ports. SDIN4 supports four discrete (stereo) data formats.

Serial audio data 1 output is the only serial data output port. SDOUT supports I2S format only.

Soft start valid. Output indicating validity of soft-start PWM output, active-high

Voltage reference for analog supply, 1.8 V. A pinout of the internally regulated 1.8-V power. A 0.1- μ F, low-ESR capacitor should be connected between this terminal and AVSS_PLL. This terminal must not be used to power external devices.

Voltage reference for digital PWM core supply, 1.8 V. A pinout of the internally regulated 1.8-V power used by digital PWM core logic. A 0.1- μ F, low-ESR DVSS_PWM. This terminal must not be used to power external devices.

Voltage reference for analog supply, 1.8 V. A pinout of the internally regulated 1.8-V power. A 0.1- μ F, low-ESR connected between this terminal and AVSS_PLL. This terminal must not be used to power external devices.

(3)

capacitor should be connected between this terminal and

DESCRIPTION

(3)

capacitor should be

TAS5086

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TAS5086

SLES131B – FEBRUARY 2005 – REVISED JUNE 2007

DETAILED DESCRIPTION

POWER SUPPLY

The TAS5086 power-supply section contains regulators that provide analog and digital regulated power for various sections of the TAS5086. The analog supply supports the analog PLL while digital supplies support the digital PLL, the digital audio processor, the pulse width modulator, and the output control (reclocker). The power-supply section is enabled via VREG_EN.

CLOCK, ERROR RATE DETECTION, AND PLL

This module provides the timing and serial data interface for the TAS5086.

The TAS5086 is a clock slave device. It accepts MCLK, SCLK, and LRCLK. The TAS5086 supports 64-f The TAS5086 accepts a 64-f

192 fSand 384 fS. TAS5086 checks to verify that SCLK is a specific value of 64 fSor 48 fS. The TAS5086 supports a 1-f The timing relationship of these clocks to SDIN[1:4] and SDOUT is shown in subsequent sections. The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable or absent) to produce

a 196-MHz PLL output.

The TAS5086 can auto-detect and set the internal clock control logic to the appropriate settings for the frequencies of 32 kHz, normal speed (44.1 or 48 kHz), double speed (88.2 kHz or 96 kHz), and quad speed (176.4 kHz or 192 kHz). The automatic sample rate detection can be disabled and the values set via I2C.

The TAS5086 also supports an AM interference-avoidance mode during which the clock rate is adjusted, in concert with the PWM sample rate converter, to produce a PWM output at 7-f

The sample rate must be set manually during AM interference avoidance and when de-emphasis is enabled. The TAS5086 uses an internal oscillator time base to provide reference timing information for the following

functions:

• MCLK, SCLK, and LRCLK error detection

• I2C communication when power is first applied to the device

• Automatic data-rate detection and setting (32 kHz, normal, double, and quad speed)

• Automatic MCLK rate detection and setting (64, 128, 192, 256, 384, and 512 fS)

MCLK for the 176.4-kHz and 192-kHz data rates.

SCLK rate for all MCLK ratios and a 48-f

LRCLK.

SCLK rate for MCLK ratios of

, 8-f

, or 9-f

OSCILLATOR TRIM

The TAS5086 PWM processor contains an internal oscillator for PLL reference. This reduces system cost because an external reference is not required. After each power up or reset, a oscillator trim is needed; see the

Oscillator Trim Register (0x1B) section for a detailed procedure.

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B0048-01

(L'+R')/2

Format

Channel

1–6

Channel

1–6

1–5

Down-

mix

SDIN1

PWM_1

PWM_2

PWM_3

PWM_4

PWM_5

PWM_6

1LF

2RF

3LS

4RS

5C

0x20

0x21

0x25

0x04

SDIN2 SDIN3

SDIN4

MUX

0x21

Ch-6Processing

MUX

Downmix

SDIN4

PWM

MUX

SDOUT I S

0x07– 0x0D

0x03

VOL

SEL

VOL

MUX

TAS5086

SLES131B – FEBRUARY 2005 – REVISED JUNE 2007

DETAILED DESCRIPTION (continued)

SERIAL DATA INTERFACE

Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The PWM outputs and downmix are derived from SDIN1, SDIN2, and SDIN3. SDIN4 is a selectable pass-through signal that is available at SDOUT as an I2S output. The TAS5086 accepts 32-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz serial data in 16-, 20-, or 24-bit, left-justified, right-justified, and I2S serial data formats.

Serial data is output on SDOUT. The SDOUT data format is I2S 24-bit at the same data rate as the input. The SDOUT output is synchronized to use the SCLK and LRCLK signals. There is a 1- to 2.5-LRCLK frame delay from the input data to the output data, depending on the input serial data format. The SDOUT output has no I2C-controllable functions. It is always operational.

The parameters of this clock and serial data interface input format are I2C configurable.

I2C SERIAL CONTROL INTERFACE

The TAS5086 has an I2C serial control slave interface to receive commands from a system controller. The serial control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait states. As an added feature, this interface operates even if MCLK is absent.

The serial control interface supports both single-byte and multi-byte read and write operations for status registers and the general control registers associated with the PWM.

The I2C interface supports a special mode that permits I2C write operations to be broken up into multiple-data write operations that are multiples of 4 data bytes. These are 6-, 10-, 14-, 18-, ... etc., -byte write operations that are composed of a device address, read/write bit, subaddress, and any multiple of 4 bytes of data. This permits the system to write large register values incrementally without blocking other I2C transactions.

Figure 6 shows the data flow and control through the TAS5086. The major I2C registers are shown above each

applicable block (e.g., 0x04 is the serial data format control register).

Figure 6. TAS5086 Data Flow Diagram With I2C Registers

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B0050-01

0x21

0x0D

BQ1(G)

0x23

Gain-

Compensated

Biquad

0x24 LowPass

Biquad

VOL

10dB

BassManagement

Ch1–5

Ch6Sub

FromDownmix(L’+R’)/2

BQ1 BQ2

MUX

TAS5086

SLES131B – FEBRUARY 2005 – REVISED JUNE 2007

DETAILED DESCRIPTION (continued)

Channel-6 Processing Section

Channel 6 has processing features that are directly applicable to the subwoofer channel.

Figure 7. Channel-6 Processing Block Diagram

PWM Section

The TAS5086 has six channels of high-performance digital PWM modulators that are designed to drive switching output stages (back ends) in both single-ended (SE) and H-bridge (bridge-tied load) configurations. The TAS5086 device uses noise-shaping and sophisticated error correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The TAS5086 uses a fourth-order noise shaper to provide >105-dB SNR performance from 20 Hz to 20 kHz.

The TAS5086 PWM interface is described by using the following notation:

PN + V

where

P = number of PWM signals per channel N = number of channels V = total number of valid signals used to reset the power stage

For example, the TAS5086 initial interface format means that there is 1 PWM signal per channel (N = 6) and 1 valid signal is used to reset the power stages. The shorthand notation to describe this is 1N+1.

The PWM section accepts 24-bit PCM data from the serial data interface and outputs six PWM audio output channels to drive 1N+1 single-ended and BTL power stages.

The PWM interface supports:

• TAS5186 in BTL or SE mode without any external glue logic, uses 1N+1 signaling.

• TAS5142 in BTL or SE mode without any external glue logic, uses 1N+1 signaling.

• TAS5111 SE without any external glue logic, and with a pulldown on the output, uses 1N+1 signaling.

• TAS5111 BTL or TAS5112 BTL with one inverter per BTL channel of glue logic and a pulldown on the

output, uses 1N+1 signaling from TAS5086, 2N+1 input to TAS5111/12.

• TAS5112 SE (with external glue logic) See the application schematics for an example of the TAS5086 with the TAS5186 and the TAS5086 with

TAS5112 SE and TAS5111 SE.

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OutputStage

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DETAILED DESCRIPTION (continued)

The TAS5086 has input multiplexers that allow any of the input channels to be routed to any PWM channel and output multiplexers to enable any PWM output to be routed to any PWM output pin.

It also has individual channel dc-blocking filters that are enabled by default. Individual channel de-emphasis filters for 32, 44.1, and 48 kHz are included and can be enabled and disabled. There is also a two-channel downmix result that can be output on SDOUT (I2S format). This result also can be

sent to the left and right front channels (channels 1 and 2) and/or to the center and subwoofer (channels 5 and

6) as well. A mixer on the subwoofer channel supports bass management configuration 1. PWM output characteristics

• Up to 8 × oversampling

• 12 × at fS= 32 kHz, 8 × at fS= 48 kHz, 4 × at fS= 96 kHz, 2 × at fS= 192 kHz

• Fourth-order noise shaping

• ≥ 105-dB dynamic range, 0–20 kHz (TAS5086 + TAS5186 system measured at speaker terminals)

• THD < 0.06% (measured at TAS5086 outputs)

• Adjustable maximum modulation limit of 93.8% to 99.2%

Transitions Between Shutdown and Playing

The TAS5086 outputs are switching all the time with the noise shaper active. Mute is acheived by inputting a zero into the noise shaper, with the noise shaper running and the output still switching. By using this approach, the transitions between off and operation is avoided. The only exception is shutdown of surround channels as described in the Surround Register (0x19) section.

Futhermore, the TAS5086 is designed to drive a load in single-ended and bridge-tied-load configurations. The principle in the SE and BTL configurations is shown in Figure 8 and Figure 9 . In both situations, care must be taken to ensure correct start-up sequences which charge the bootstrap capacitor and do not produce audible artifacts; the TAS5086 is designed to do that.

Figure 8. BTL Filter Configuration

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SLES131B – FEBRUARY 2005 – REVISED JUNE 2007

DETAILED DESCRIPTION (continued)

The SE configuration presents an additional challenge in order for starting up quietly. The second terminal of the loudspeaker is connected to a split capacitor between power and ground. The advantage of this circuitly is that it provides some degree of power-supply ripple rejection. The problem related to the split capacitor is that the voltage over it must be controlled when the modulator starts (i.e., when the power stage output goes out of high impedance state) to avoid a click in the speaker.

Figure 9. SE Filter Configuration

The TAS5086 supports two mechanisms for controlling the split-capacitor midpoint. In the extra half-bridge scheme (the TAS5186 power stage is an example of this) an additional half-bridge is

started and brought to a 50-percent duty cycle, i.e., a situation where the average voltage of the half-bridge is equal to the voltage which must be applied to the split-capacitor midpoint to start up without clicks in the speaker. A resistor per channel is connected between the extra half-bridge and each midpoint for the split capacitors. The split capacitors are charged through this resistor. This approach requires an extra VALID pin on the modulator to control the extra half-bridge, therefore the 1N+2 interface. Figure 10 shows the topology of the extra half-bridge. In some situations, a channel configured in BTL can be used to charge the split capacitor instead of the extra half-bridge. This is shown in Figure 11 .

The mid-Z scheme charges the split capacitor through the loudspeaker. In order to do this without audible artifacts the charge current must be limited. This is done by applying a start sequence which charges the output state between low, high and high-Z. Because the ouput stage is in high-Z in a part of the sequence, the resulting output impedance can be brought to a level suitable for charging the split capacitors without audible artifacts. This solution does not require external components, as shown in Figure 9 . Not all power stages are compatible with the mid-Z scheme, double-check the power-stage data sheet for compabitility. The PWM start register (0x18) programs the TAS5086 for mid-Z or the standard low-Z start sequence.

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DETAILED DESCRIPTION (continued)

TAS5086

SLES131B – FEBRUARY 2005 – REVISED JUNE 2007

Figure 10. Split-Capacitor Charging With Extra Half-Bridge

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Figure 11. Split-Capacitor Charging With BTL Subwoofer

+ 32 hidden pages

TEXAS INSTRUMENTS TAS5086 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

Serial Audio Port

TAS5086 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I2C-Bus Devices

TAS5086 Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I2C-Bus Devices

Recommended I2C Pullup Resistors

PHYSICAL CHARACTERISTICS

DETAILED DESCRIPTION

POWER SUPPLY

CLOCK, ERROR RATE DETECTION, AND PLL

OSCILLATOR TRIM

SERIAL DATA INTERFACE

I2C SERIAL CONTROL INTERFACE

Channel-6 Processing Section

PWM Section

Transitions Between Shutdown and Playing