TEXAS INSTRUMENTS TAS5076 Technical data

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TM
Data M anua
January 2004 DAV Digital Audio/Speaker
SLES090A
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Products Applications
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Contents
Contents
Section Page
1 Introduction 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Functional Block Diagram 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Terminal Assignments 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Ordering Information 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Terminal Functions 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Architecture Overview 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Clock and Serial Data Interface 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection 7. . . . . . . . . . . . . . . . . . .
2.1.2 Clock Master/Slave Mode (M_S) 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3 Clock Master Mode 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4 Clock Slave Mode 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5 PLL External Filter 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.6 DCLK 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.7 Serial Data Interface 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Reset, Power Down, and Status 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Reset—RESET 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Power Down—PDN 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3 General Status Register 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4 Error Status Register 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Signal Processing 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Volume Control 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Mute 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3 Automute 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.4 Individual Channel Mute 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.5 De-Emphasis Filter 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Pulse Width Modulator (PWM) 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 Clipping Indicator 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.2 Error Recovery 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.3 Individual Channel Error Recovery 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.4 PWM DC-Offset Correction 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.5 Interchannel Delay 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.6 ABD Delay 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.7 PWM/H-Bridge and Discrete H-Bridge Driver Interface 22. . . . . . . . . . . . . . . . . . . . . . .
2.5 I2C Serial Control Interface 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1 Single-Byte Write 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2 Multiple-Byte Write 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.3 Single-Byte Read 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.4 Multiple-Byte Read 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Serial Control Interface Register Definitions 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 General Status Register (0x00) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Error Status Register (0x01) 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 System Control Register 0 (0x02) 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 System Control Register 1 (0x03) 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Error Recovery Register (0x04) 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Automute Delay Register (0x05) 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
November 2003—Revised January 2004 SLES090A
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Contents
3.7 Dc-Offset Control Registers (0x06−0x0B) 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Interchannel Delay Registers (0x0C−0x11) 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 ABD Delay Register (0x12) 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 Individual Channel Mute Register (0x19) 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 System Procedures for Initialization, Changing Data Rates, and Switching Between Master
and Slave Modes 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 System Initialization 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Data Sample Rate 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Changing Between Master and Slave Modes 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Specifications 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Absolute Maximum Ratings Over Operating Temperature Ranges 39. . . . . . . . . . . . . . . . . . . . . . .
5.2 Recommended Operating Conditions 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Electrical Characteristics Over Recommended Operating Conditions 39. . . . . . . . . . . . . . . . . . . .
5.3.1 Static Digital Specifications Over Recommended Operating Conditions 39. . . . . . . . .
5.3.2 Digital Interpolation Filter and PWM Modulator Over
Recommended Operating Conditions (Fs = 48 kHz) 39. . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3 TAS5076/TAS5182 System Performance Measured at the Speaker Terminals
Over Recommended Operating Conditions (Fs = 48 kHz) 40. . . . . . . . . . . . . . . . . . . .
5.4 Switching Characteristics 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1 Command Sequence Timing 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2 Serial Audio Port 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
5.4.3 Serial Control Port—I
C Operation 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Application Information 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Serial Audio Interface Clock Master and Slave Interface Configuration 50. . . . . . . . . . . . . . . . . . .
6.1.1 Slave Configuration 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2 Master Configuration 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Mechanical Data 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix A—Volume Table 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
November 2003—Revised January 2004SLES090A
List of Illustrations
List of Illustrations
Figure Title Page
2−1 Crystal Circuit 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 External PLL Filter 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 I2S 64-Fs Format 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 I2S 48-Fs Format 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 Left-Justified 64-Fs Format 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 Left-Justified 48-Fs Format 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 Right-Justified 64-Fs Format 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 Right-Justified 48-Fs Format 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 DSP Format 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 Attenuation Curve 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 De-Emphasis Filter Characteristics 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−12 PWM Outputs and H-Bridge Driven in BTL Configuration 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−13 Typical I2C Sequence 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−14 Single-Byte Write Transfer 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−15 Multiple-Byte Write Transfer 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−16 Single-Byte Read 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−17 Multiple-Byte Read 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 RESET During System Initialization 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Extending the I2C Write Interval Following a Low-to-High Transition of the RESET Terminal 34. . . . . . .
4−3 Changing the Data Sample Rate Using the DBSPD Terminal 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 Changing the Data Sample Rate Using the I2C35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Changing the Data Sample Rate With an Unstable MCLK_IN Using the DBSPD Terminal 36. . . . . . . . .
4−6 Changing the Data Sample Rate With an Unstable MCLK_IN Using the I2C37. . . . . . . . . . . . . . . . . . . . .
4−7 Changing Between Master and Slave Clock Mode 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1 RESET Timing 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 Power-Down and Power-Up Timing—RESET Preceding PDN 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−3 Power-Down and Power-Up Timing—RESET Following PDN 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−4 Error Recovery Timing 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−5 Mute Timing 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−6 Right-Justified, I2S, Left-Justified Serial Protocol Timing 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−7 Right, Left, and I2S Serial Mode Timing Requirement 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−8 Serial Audio Ports Master Mode Timing 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−9 DSP Serial Port Timing 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−10 DSP Serial Port Expanded Timing 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−11 DSP Absolute Timing 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12 SCL and SDA Timing 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−13 Start and Stop Conditions Timing 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 Typical TAS5076 Application 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2 TAS5076 Serial Audio Port—Slave Mode Connection Diagram 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−3 TAS5076 Serial Audio Port—Master Mode Connection Diagram 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
November 2003—Revised January 2004 SLES090A
v
List of Tables
List of Tables
Table Title Page
2−1 Normal-Speed, Double-Speed, and Quad-Speed Operation 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 Master and Slave Clock Modes 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 LRCLK and MCLK_IN Rates 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 DCLK 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 Supported Word Lengths 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 Device Outputs During Reset 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 Values Set During Reset 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 Device Outputs During Power Down 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 Volume Register 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 De-Emphasis Filter Characteristics 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 Device Outputs During Error Recovery 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
C Register Map 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 I
3−2 General Status Register (Read Only) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 Error Status Register 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 System Control Register 0 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 System Control Register 1 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Error Recovery Register 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 Automute Delay Register 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 Dc-Offset Control Registers 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 Six Interchannel Delay Registers 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 ABD Delay Register 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 Individual Channel Mute Register 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
November 2003—Revised January 2004SLES090A
1 Introduction
The TAS5076 is an innovative, cost-effective, high-performance 24-bit six-channel digital pulse-width modulator (PWM) based on Equibit technology. Combined with a TI PurePath Digital audio amplifier power stage, these devices use noise-shaping and sophisticated error-correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The TAS5076 is designed to drive up to six digital power devices to provide six channels of digital audio amplification. The digital power devices can be six conventional monolithic power stages (such as the TAS5110) or six discrete differential power stages using gate drivers and MOSFETs.
The TAS5076 has six independent volume controls and mute. The device operates in AD and BD modes. This all-digital audio system contains only two analog components in the signal chain—an LC low-pass filter at each speaker terminal. Dynamic range of 105 dB for the front channels and 102 dB for the other channels is achievable on the TAS5076-TAS5182 EVM using the specified ABD and interchannel delay settings. The TAS5076 has a wide variety of serial input options including right justified (16-, 20-, or 24-bit), I or 24-bit) left justified, and DSP (16-bit) data formats. The device is fully compatible with AES standard sampling rates of 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz, including de-emphasis for
44.1-kHz and 48-kHz sample rates. The TAS5076 plus the TAS51xx power stage device combination was
designed for home theater applications such as DVD minicomponent systems, home theater in a box (HTIB), DVD receiver, A/V receiver, or TV sets.
1.1 Features
Introduction
2
S (16-, 20-,
TI PurePath Digital Audio Amplifier
High-Quality Audio
Up to105-dB Dynamic Range
<0.005% THD+N
Six-Channel Volume Control
Patented Soft Volume
Patented Soft Mute
16-, 20-, or 24-Bit Input Data
Sampling Rates: 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz
Supports Master and Slave Modes
3.3-V Power-Supply Operation
Economical 80-Pin TQFP Package
De-Emphasis: 32 kHz, 44.1 kHz, and 48 kHz
Clock Oscillator Circuit for Master Modes
Low-Jitter Internal PLL
Soft Volume and Mute Update
Measured TAS5076-TAS5182 EVM
Equibit and PurePath Digital are trademarks of Texas Instruments. Other trademarks are the property of their respective owners.
SLES090A—November 2003—Revised January 2004 TAS5076
1
Introduction
1.2 Functional Block Diagram
AVDD_PLL
AVSS_PLL
VREGA_CAP
VREGB_CAP
VREGC_CAP
DVDD_RCL
DVSS_RCL
DVDD_PWM
DVSS_PWM
MCLK_IN
XTAL_OUT
XTAL_IN
DBSPD
M_S
PLL_FLT_OUT
PLL_FLT_RET
SCLK
LRCLK
MCLKOUT
SDIN1 SDIN2
SDIN3 DM_SEL1 DM_SEL2
SDA SCL
CSO
RESET
PDN
CLIP
MUTE
ERR_RCVY
Clock,
PLL and
Serial
Data
I/F
Serial
Control
I/F
Reset,
Pwr Dwn
and
Status
Power Supply
Signal
Processing
Auto Mute
De-Emphasis
Soft Volume
Error Recovery
Soft Mute
Clip Detect
PWM
Section
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
Output Control
PWM_AP_1 PWM_AM_1 PWM_BP_1 PWM_BM_1 VALID_1 PWM_AP_2 PWM_AM_2 PWM_BP_2 PWM_BM_2 VALID_2 PWM_AP_3 PWM_AM_3 PWM_BP_3 PWM_BM_3 VALID_3 PWM_AP_4 PWM_AM_4 PWM_BP_4 PWM_BM_4 VALID_4 PWM_AP_5 PWM_AM_5 PWM_BP_5 PWM_BM_5 VALID_5 PWM_AP_6 PWM_AM_6 PWM_BP_6 PWM_BM_6 VALID_6
2
SLES090A—November 2003—Revised January 2004TAS5076
1.3 Terminal Assignments
AVDD_OSC
XTL_IN
XTL_OUT
AVSS_OSC
DVSS
PFC PACKAGE
(TOP VIEW)
PWM_AP1
PWM_AM_1
VALID_1
PWM_BM_1
PWM_BP_1
PWM_AP_2
PWM_AM_2
VALID_2
PWM_BM_2
PWM_BP_2
PWM_AP_3
PWM_AM_3
VALID_3
PWM_BM_3
Introduction
PWM_BP_3
NC NC
MCLK_IN
AVDD_PLL
PLL_FLT_OUT
PLL_FLT_RET
AVSS_PLL
NC
VREGA_CAP
DVSS1
NC
RESET
ERR_RCVRY
MUTE
PDN SDA
SCL CS0
NC NC
79 78 77 76 7580 74 72 71 7073
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
22 23
24
NCNCNC
25 26 27 28
CLIP
SDIN1
DBSPD
29
SDIN2
SDIN3
69 682167 66 65 64
30 31 32 33
SCLK
DVDD
LRCLK
MCLK_OUT
63 62 61
34 35 36 37 38 39 40
DVSS
M_S
DVSS1
DEM_SEL2
DEM_SEL1
VREGC_CAP
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
NC
DVSS1
VREGB_CAP DVDD_RCL DVSS_RCL DVDD_PWM DVSS_PWM PWM_AP_4 PWM_AM_4 VALID_4 PWM_BM_4 PWM_BP_4 PWM_AP_5 PWM_AM_5 VALID_5 PWM_BM_5 PWM_BP_5 PWM_AP_6 PWM_AM_6 VALID_6 PWM_BM_6 PWM_BP_6
NC − No internal connection
SLES090A—November 2003—Revised January 2004 TAS5076
3
Introduction
FUNCTION
DESCRIPTION
1.4 Ordering Information T AS
5076 PFC
Texas Instruments
Audio Solutions
Device Number
Package Type
AVAILABLE OPTIONS
PACKAGE
T
A
0°C to 70°C TAS5076PFC
PLASTIC 80-PIN TQFP
(PFC)
1.5 Terminal Functions
TERMINAL
NAME NO.
AVDD_OSC 80 P Analog power supply for internal oscillator cells AVDD_PLL 4 P Analog power supply for PLL AVSS_OSC 77 O Analog ground for internal oscillator cells AVSS_PLL 7 P Analog ground for PLL CLIP 25 O Digital clipping indicator, active low CS0 18 I I2C serial control chip address select input, active high DBSPD 24 I Sample rate is double speed (88.2 kHz or 96 kHz), active high DEM_SEL1 36 I De-emphasis select bit 2, 10 = 48 kHz, 11= undefined (none) DEM_SEL2 35 I De-emphasis select bit 1 (0 = none, 01 = 32 kHz, 10 = 44.1 kHz DVDD 32 P Digital power supply DVDD_PWM 57 P Digital power supply for PWM DVDD_RCL 59 P Digital power supply for reclocker DVSS 33, 76 P Digital ground for digital core and most of I/O buffers DVSS1 10, 38, 39 I/O Digital ground for digital core and most of I/O buffers DVSS_PWM 56 P Digital ground for PWM DVSS_RCL 58 P Digital ground for reclocker ERR_RCVRY 13 I Error recovery input, active low LRCLK 31 I/O Serial audio data left / right clock (sampling rate clock) (input when M_S = 0; output when
M_S 37 I Master/slave mode input signal (master = 1, slave = 0) MCLK_IN 3 I MCLK input, slave mode (or master / double-speed mode) MCLK_OUT 29 O MCLK output buffered system clock output if M_S = 1; otherwise set to 0 MUTE 14 I Mute input signal, active low (muted signal = 0, normal mode = 1) N/C 1, 2, 8, 11,
PDN 15 I Power down, active low PLL_FLT_OUT 5 O PLL external filter
I = input; O = output; I/O = input/output; P = power
19−23, 40
Not connected
M_S = 1)
4
SLES090A—November 2003—Revised January 2004TAS5076
TERMINAL
FUNCTION
DESCRIPTION
NAME NO.
PLL_FLT_RET 6 O PLL external filter (internally connected to AVSS_PLL) PWM_AM_1 74 O PWM 1 output (differential -); {positive H-bridge side} PWM_AM_2 69 O PWM 2 output (differential -); {positive H-bridge side} PWM_AM_3 64 O PWM 3 output (differential -); {positive H-bridge side} PWM_AM_4 54 O PWM 4 output (differential -); {positive H-bridge side} PWM_AM_5 49 O PWM 5 output (differential -); {positive H-bridge side} PWM_AM_6 44 O PWM 6 output (differential -); {positive H-bridge side} PWM_AP_1 75 O PWM 1 output (differential +); {positive H-bridge side} PWM_AP_2 70 O PWM 2 output (differential +); {positive H-bridge side} PWM_AP_3 65 O PWM 3 output (differential +); {positive H-bridge side} PWM_AP_4 55 O PWM 4 output (differential +); {positive H-bridge side} PWM_AP_5 50 O PWM 5 output (differential +); {positive H-bridge side} PWM_AP_6 45 O PWM 6 output (differential +); {positive H-bridge side} PWM_BM_1 72 O PWM 1 output (differential -); {negative H-bridge side} PWM_BM_2 67 O PWM 2 output (differential -); {negative H-bridge side} PWM_BM_3 62 O PWM 3 output (differential -); {negative H-bridge side} PWM_BM_4 52 O PWM 4 output (differential -); {negative H-bridge side} PWM_BM_5 47 O PWM 5 output (differential -); {negative H-bridge side} PWM_BM_6 42 O PWM 6 output (differential -); {negative H-bridge side} PWM_BP_1 71 O PWM 1 output (differential +); {negative H-bridge side} PWM_BP_2 66 O PWM 2 output (differential +); {negative H-bridge side} PWM_BP_3 61 O PWM 3 output (differential +); {negative H-bridge side} PWM_BP_4 51 O PWM 4 output (differential +); {negative H-bridge side} PWM_BP_5 46 O PWM 5 output (differential +); {negative H-bridge side} PWM_BP_6 41 O PWM 6 output (differential +); {negative H-bridge side} RESET 12 I System reset input, active low SCL 17 I I2C serial control clock input SCLK 30 I/O Serial audio data clock (shift clock) SDA 16 I/O I2C serial control data input/ output SDIN1 26 I Serial audio data 1 input SDIN2 27 I Serial audio data 2 input SDIN3 28 I Serial audio data 3 input VALID_1 73 O Output indicating validity of PWM outputs, channel 1, active high VALID_2 68 O Output indicating validity of PWM outputs, channel 2, active high VALID_3 63 O Output indicating validity of PWM outputs, channel 3, active high VALID_4 53 O Output indicating validity of PWM outputs, channel 4, active high VALID_5 48 O Output indicating validity of PWM outputs, channel 5, active high VALID_6 43 O Output indicating validity of PWM outputs, channel 6, active high VREGA_CAP 9 P Voltage regulator capacitor VREGB_CAP 60 P Voltage regulator capacitor VREGC_CAP 34 P Voltage regulator capacitor XTL_IN 79 I Crystal or TTL level clock input XTL_OUT 78 O Crystal output (not for external usage)
Introduction
I = input; O = output; I/O = input/output; P = power
SLES090A—November 2003—Revised January 2004 TAS5076
5
Introduction
6
SLES090A—November 2003—Revised January 2004TAS5076
2 Architecture Overview
The TAS5076 is composed of six functional elements:
Clock, PLL, and serial data interface (I
Reset/power-down circuitry
Serial control interface (I2C)
Signal processing unit
Pulse-width modulator (PWM)
Power supply
2.1 Clock and Serial Data Interface
The TAS5076 clock and serial data interface contain an input serial data slave and the clock master/slave interface. The serial data slave interface receives information from a digital source such as a DSP, S/PDIF receiver, analog-to-digital converter (ADC), digital audio processor (DAP), or other serial bus master. The serial data interface has three serial data inputs that can accept up to six channels of data at data sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, or 192 kHz. The serial data interfaces support left justified and right justified for 16, 20, and 24 bits. In addition, the serial data interface supports the DSP protocol for 16 bits and the I
The TAS5076 can function as a receiver or a generator for the MCLK_IN (master clock), SCLK (shift clock), and LRCLK (left/right clock) signals that control the flow of data on the three serial data interfaces. The T AS5076 i s a c l o c k m a s t e r when it generates these clocks and is a clock slave when it receives these clocks.
The TAS5076 is a synchronous design that relies upon the master clock to provide a reference clock for all of the device operations and communication via the I2C. When operating as a slave, this reference clock is MCLK_IN. When operating as a master , the reference clock is either a TTL clock input t o X TAL_IN or a crystal attached across XTAL_IN and XTAL_OUT.
2
S protocol for 24 bits.
Architecture Overview
2
S)
The clock and serial data interface has two control parameters: data sample rate and clock master or slave.
2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection
The data sample rate is selected through a terminal (DBSPD) or the serial control register 0 (0x02). The data sample rate control sets the frequencies of the SCLK and LRCLK in clock slave mode and the output frequencies of SCLK and LRCLK in clock master mode. There are three data rates: normal speed, double speed, and quad speed.
Normal-speed mode supports data rates of 32 kHz, 44.1 kHz, and 48 kHz. Normal speed is supported in the master and slave modes. Double-speed mode is used to support sampling rates of 88.2 kHz and 96 kHz. Double speed is supported in master and slave modes. Quad-speed mode is used to support sampling rates of 176.4 kHz and 192 kHz.
The PWM is placed in normal speed by setting the DBSPD terminal low or by setting the normal mode bits in the system control register 0 (0x02) through the serial control interface. The PWM is placed in double speed mode by setting the DBSPD terminal high or by setting the double speed bits in the system control register. Quad-speed mode is supported; in slave mode it is auto-detected, and in master mode it is invoked using the
2
I
C serial control interface. In slave mode, if the TAS5076 is not in double speed mode, quad-speed mode is automatically detected when MCLK_IN is 128 Fs. In master mode, the PWM is placed in quad-speed mode by setting the quad-speed bit in the system control register through the serial control interface.
If the master clock is well behaved during the frequency transition (the high or low clock periods are not less than 20 ns), then a simple speed selection is performed by setting the DBSPD terminal or the serial control register.
When the sample rate is changed, the T AS5076 temporarily suspends processing, places the PWM outputs in a hard mute (PWM P outputs low, PWM M outputs high, and all VALID signals low), resets all internal processes, and suspends all I noiselessly restarts the PWM output. The TAS5076 preserves all control register settings throughout this sequence. If desired, the sample rate change can be performed while mute is active to provide a completely silent transition. The timing of this control sequence is shown in Section 4.
2
C operations. The TAS5076 then performs a partial re-initialization and
SLES090A—November 2003—Revised January 2004 TAS5076
7
Architecture Overview
If the master clock input can encounter high clock or low clock period of less than 20 ns while the data rates are changing, then RESET
must be applied during this time. There are two recommended control procedures for this case, depending upon whether the DBSPD terminal or the serial control interface is used. These control sequences are shown in Section 4.
Table 2−1. Normal-Speed, Double-Speed, and Quad-Speed Operation
QUAD-SPEED CONTROL
REGISTER BIT
0 0 Master or slave Normal speed 0 1 Master or slave Double speed 1 0 Master or slave Quad speed 0 0 Slave Quad speed if MCLK_IN = 128Fs 1 1 Master or slave Error
DBSPD TERMINAL OR
CONTROL REGISTER BIT
2.1.2 Clock Master/Slave Mode (M_S)
Clock master and slave mode can be invoked using the M_S (master slave) terminal. This terminal specifies the default mode that is set immediately following a device RESET. The serial data
interface setting permits the clock generation mode to be changed during normal operation.
MODE SPEED SELECTION
The transition to master mode occurs following a RESET The transition to slave mode occurs following a RESET
2.1.3 Clock Master Mode
When M_S = 1 following a RESET, the TAS5076 provides the master clock, SCLK, and LRCLK to the rest of the system. In the master mode, the TAS5076 outputs the audio system clocks MCLK_OUT, SCLK, and LRCLK.
The TAS5076 device generates these clocks plus its internal clocks from the internal phase-locked loop (PLL). The reference clock for the PLL can be provided by either an external clock source (attached to XTAL_IN) or a crystal (connected across terminals XTAL_IN and XTAL_OUT). The external source attached to MCLK_IN is 256 times (128 in quad mode) the data sample rate (Fs). The SCLK frequency is 64 times the data sample rate and the SCLK frequency of 48 times the data sample rate is not supported in the master mode. The LRCLK frequency is the data sample rate.
when M_S terminal has a logic high applied.
when M_S terminal has a logic low applied.
8
SLES090A—November 2003—Revised January 2004TAS5076
2.1.3.1 Crystal Type and Circuit
In clock master mode the TAS5076 can derive the MCLKOUT, SCLK, and LRCLK from a crystal. In this case, the TAS5076 uses a parallel-mode fundamental crystal. This crystal is connected to the TAS5076 as shown in Figure 2−1.
Architecture Overview
TAS5076
rd = Drive Level Control Resistor − Crystal Vendor Specified CL = Crystal Load Capacitance (Capacitance of Circuitry Between the Two Terminals of the Crystal) CL = (C1 × C2 )/(C1 + C2 ) + CS (Where CS = Board Stray Capacitance 3 pF) Example: Vendor-Recommended CL = 18 pF, CS = 3 pF C1 = C2 = 2 × (18−3) = 30 pF
2.1.4 Clock Slave Mode
In the slave mode (M_S = 0), the master clock, LRCLK, and SCLK are inputs to the TAS5076. The master clock is supplied through the MCLK_IN terminal.
As in the master mode, the TAS5076 device develops its internal timing from the internal phase-locked loop (PLL). The reference clock for the PLL is provided by the input to the MCLK_IN terminal. This input is at a frequency of 256 times (128 in quad mode) the input data rate. The SCLK frequency is 48 or 64 times the data sample rate. The LRCLK frequency is the data sample rate. The TAS5076 does not require any specific phase relationship between SRCLK and MCLK_IN, but there must be synchronization. The TAS5076 monitors the relationship between MCLK, SCLK, and LRCLK. The TAS5076 detects if any of the three clocks is absent, if the LRCLK rate changes more than 10 MCLK cycles since the last device reset or clock error, or if the MCLK frequency is changing substantially with respect to the PLL frequency.
C
1
C
2
r
d
OSC
MACRO
XO
XI
AVSS
Figure 2−1. Crystal Circuit
When a clock error is detected, the TAS5076 performs a clock error management sequence. The clock error management sequence temporarily suspends processing, places the PWM outputs in a hard
mute (PWM_P outputs are low, PWM_M outputs are high, and all VALID signals are low), resets all internal processes, sets the volumes to mute, and suspends all I
2
C operations.
When the error condition is corrected, the TAS5076 exits the clock error sequence by performing a partial re-initialization, noiselessly restarting the PWM output, and ramping the volume up to the level specified in the volume control registers. This sequence is performed over a 60-ms interval. The TAS5076 preserves all control register settings that were set prior to the clock interruption.
If a clock error occurs while the ERR_RCVRY
terminal is asserted (low), the TAS5076 performs the error management sequence up to the unmute sequence. In this case, the volume remains at full attenuation with the PWM output at a 50% duty cycle. The volume can be restored from this latched mute state by triggering a mute/unmute sequence by asserting and releasing MUTE
either by using the terminal, the system control
register 0x01 D4, or the individual channel mute register D5−D0.
SLES090A—November 2003—Revised January 2004 TAS5076
9
Architecture Overview
Alternatively , t h e TAS 50 76 ca n be pre vented from entering the latched mute state following a clock error when the ERR_RCVRY
terminal or the error recovery I2C command (register 0x03 bit D2) is active by writing 0x7F
to the individual error recovery register (0x04) and 0x84 to the feature enable register (0x1F).
Table 2−2. Master and Slave Clock Modes
DESCRIPTION M_S DBSPD
Internal PLL, master, normal speed 1 0 8.192 2.048 32 8.192 Internal PLL, master, normal speed 1 0 11.2896 2.8224 44.1 11.2896 Internal PLL, master, normal speed 1 0 12.288 3.072 48 12.288 Internal PLL, master, double speed 1 1 22.5792 Internal PLL, master, double speed 1 1 24.576 Internal PLL, master, quad speed 1 0 22.5792 11.2896 176.4 22.5792 Internal PLL, master, quad speed 1 0 24.576 12.288 192 24.576 Internal PLL, slave, normal speed 0 0 8.192 Internal PLL, slave, normal speed 0 0 11.2896 Internal PLL, slave, normal speed 0 0 12.288 Internal PLL, slave, double speed 0 1 22.5792 5.6448 88.2 Digital GND Internal PLL, slave, double speed 0 1 24.576 Internal PLL, slave, quad speed Internal PLL, slave, quad speed
A crystal oscillator is connected to XTL_IN.
MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN_IN is provided.
§
External MCLK_IN connected to MCLK_IN_IN input
SCLK and LRCLK are outputs when M_S = 1, and inputs when M_S = 0.
#
MCLK_OUT is driven low when M_S = 0.
||
Quad-speed mode is detected automatically.
|| ||
0 0 22.5792 0 0 24.576
XTL_IN
(MHz)
k SCLK can be 48 or 64 times Fs
MCLK_IN
(MHz)
§
SCLK
(MHz)
k
§
§
§
§
§
§
§
5.6448 88.2 22.5792
6.144 96 24.576
2.0484 32 Digital GND
2.8224 44.1 Digital GND
3.072 48 Digital GND
6.144 96 Digital GND
11.2896 176 Digital GND
12.288 192 Digital GND
LRCLK
(kHz)
MCLK_OUT
(MHz)
#
Table 2−3. LRCLK and MCLK_IN Rates
NORMAL SPEED (kHz) DOUBLE SPEED (kHz) QUAD SPEED (kHz)
LRCLK 1 Fs 32 44.1 48 1 Fs 64 88.2 96 1 Fs 176.4 192
MCLK_IN 256 Fs 8,192 11,289.6 12,288 256 Fs 16,384 22,579.2 24,576 128 Fs 22,579.2 24,576
2.1.5 PLL External Filter
In the TAS5076, a low-jitter PLL produces the internal timing (when in master mode), the master clock, SCLK, and LRCLK. Connections for the PLL external filter are provided through PLL_FL T_OUT and PLL_FLT_RET as shown in Figure 2−2.
PLL_FLT_OUT
110
22 nF
TAS5076
220 nF
PLL_FLT_RET
10
Figure 2−2. PLL External Filter
SLES090A—November 2003—Revised January 2004TAS5076
2.1.6 DCLK
DCLK is the internal high-frequency clock that is produced by the PLL circuitry from MCLK. The TAS5076 uses the DCLK to control all internal operations. DCLK is 8 times the speed of MCLK in normal speed mode, 4 times MCLK in double speed, and 2 times MCLK in quad speed. With respect to the I clock cycles are used to specify interchannel delay and to detect when the MCLK frequency is drifting. Table 2−4 DCLK shows the relationship between sample rate, MCLK, and DCLK.
Table 2−4. DCLK
Architecture Overview
2
C addressable registers, DCLK
Fs
(kHz)
32 8.1920 65.5360 15.3
44.1 11.2896 90.3168 11.1 48 12.2880 98.3040 10.2 88 22.5280 90.1120 11.1 96 24.5760 98.3040 10.2
192 49.1520 98.3040 10.2
2.1.7 Serial Data Interface
The TAS5076 operates as a slave only/receive only serial data interface in all modes. The TAS5076 has three PCM serial data interfaces to accept six channels of digital data though the SDIN1, SDIN2, SDIN3 inputs. The serial audio data is in MSB-first, twos-complement format.
The serial data interfaces of the TAS5076 can be configured in right-justified, I This interface supports 32-kHz, 44.1-kHz, 48-kHz, 88-kHz, 96-kHz, 176.4-kHz, and 192-kHz data sample rates. The serial data interface format is specified using the data interface control register . The supported word lengths are shown in Table 2−5.
During normal operating conditions if the serial data interface settings change state, an error recovery sequence is initiated.
DATA MODES
Right justified, MSB first 16 0 0 0 Right justified, MSB first 20 0 0 1 Right justified, MSB first 24 0 1 0
Left justified, MSB first 24 1 1 0
DSP frame 16 1 1 1
MCLK
(MHz)
DCLK (MHz)
DCLK Period
(ns)
2
S, left-justified, or DSP modes.
Table 2−5. Supported Word Lengths
WORD
LENGTHS
I2S 16 0 1 1 I2S 20 1 0 0 I2S 24 1 0 1
MOD2 MOD1 MOD0
2.1.7.1 I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel or the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 48 or 64 times Fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5076 masks unused trailing data bit positions. Master mode only supports a 64 times Fs bit clock.
SLES090A—November 2003—Revised January 2004 TAS5076
11
Architecture Overview
2-Channel I2S (Philips Format) Stereo Input
32 Clks
32 Clks
LRCLK (Note Reversed Phase) Left Channel
SCLK
MSB LSB
24-Bit Mode
22
23
20-Bit Mode
19 18
16-Bit Mode
9 8 5 4 1 0
5 4 1 0
1 015 14
Figure 2−3. I2S 64-Fs Format
2-Channel I2S Stereo Input/Output (24-Bit Transfer Word Size)
24 Clks
LRCLK
Left Channel
Right Channel
SCLK
MSB LSB
23 22
19 18 5 4 1 0
9 8 5 4 1 0
1 015 14
24 Clks
Right Channel
SCLK
MSB LSB
24-Bit Mode
23
22
20-Bit Mode
19 18
16-Bit Mode
20 19 8 7 2 1
16 15 1 0
12
11
13
4
517
1 015 14
4 3521
Figure 2−4. I2S 48-Fs Format
2.1.7.2 Left-Justified Timing
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 48 or 64 times Fs is used to clock in the data. The first bit of data appears on the data lines at the same time that LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5076 masks unused trailing data bit positions. Master mode only supports a 64 times Fs bit clock.
SCLK
MSB LSB
23 22
0
19 18 16 15 1 0
20 19 8 7 2 1
4
517
12
11
1 015 14
13
4 3521
12
SLES090A—November 2003—Revised January 2004TAS5076
Architecture Overview
2-Channel Left-Justified Stereo Input
2-Channel Left-Justified Stereo Input/Output (24-Bit Transfer Word Size)
32 Clks
LRCLK
Left Channel
SCLK
MSB LSB
24-Bit Mode
23
22
NOTE: All data presented in 2s complement form with MSB first.
9 8 5 4 1 0
Figure 2−5. Left-Justified 64-Fs Format
24 Clks
LRCLK
Left Channel
32 Clks
LRCLK
Right Channel
MSB LSB
23 22
9 8 5 4 1 0
24 Clks
Right Channel
SCLK
MSB LSB
24-Bit Mode
22 21
19 9 8 1 0
3 242023 22 21
Figure 2−6. Left-Justified 48-Fs Format
2.1.7.3 Right-Justified Timing
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 48 or 64 times Fs is used to clock in the data. The first bit of data appears following the eighth bit-clock period (for 24-bit data) after LRCLK toggles. In RJ mode, the last bit clock before LRCLK transitions always clocks the LSB of data. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5076 masks unused leading data bit positions. Master mode only supports a 64 times Fs bit clock.
MSB LSB
19 9 8 1 0
5
3 2420235
SLES090A—November 2003—Revised January 2004 TAS5076
13
Architecture Overview
2-Channel Right-Justified (Sony Format) Stereo Input
2-Channel Right-Justified Stereo Input/Output (24-Bit Transfer Word Size)
32 Clks
LRCLK
Left Channel
SCLK
MSB LSB
24-Bit Mode
23
22
20-Bit Mode
16-Bit Mode
NOTE: All data presented in 2s complement form with MSB first.
19 18 15 14 1 0
19 18
15 14 1 0
1 015 14
Figure 2−7. Right-Justified 64-Fs Format
32 Clks
Right Channel
MSB LSB
23 22
19 18 15 14 1 0
19 18 15 14 1 0
1 015 14
24 Clks
LRCLK
Left Channel
SCLK
MSB LSB
24-Bit Mode
22 21
20-Bit Mode
16-Bit Mode
NOTE: All data presented in 2s complement form with MSB first.
19 1 0
2023
18
18 89
19 1 0
15 14 22 21
15 14
89
8915 14
1 0
Figure 2−8. Right-Justified 48-Fs Format
24 Clks
Right Channel
MSB LSB
19 1 0
2023
18
18 89
19 1 0
15 14
15 14
89
8915 14
1 0
14
SLES090A—November 2003—Revised January 2004TAS5076
2.1.7.4 DSP Mode Timing
DSP mode timing uses LRCLK to define when data is to be transmitted for both channels. A bit clock running at 64 × Fs is used to clock in the data. The first bit of the left channel data appears on the data lines following the LRCLK transition. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5076 masks unused trailing data bit positions.
SCLK
LRCLK
Architecture Overview
64 SCLKS
LSBMSB
SDIN
16 Bits
Left
Channel
Figure 2−9. DSP Format
2.2 Reset, Power Down, and Status
The reset, power-down, and status circuitry provides the necessary controls to bring the TAS5076 to the initial inactive condition, achieve low-power standby, and report system status.
2.2.1 Reset—RESET
The TAS5076 is placed in the reset mode by setting the RESET terminal low. RESET
1−6 outputs low, and places the PWM in the hard mute state. Volume is immediately set to full attenuation (there is no ramp down).
As long as the RESET bus operations are ignored. Table 2−6 shows the device output signals while RESET
is an asynchronous control signal that restores the TAS5076 to its default conditions, sets the valid
terminal is held low, the device is in the reset state. During reset, all I2C and serial data
16 Bits
Right
Channel
LSBMSB
32 Bits Unused
is active.
Upon the release of RESET
, if POWER_DWN is high, the system performs a 4-ms to 5-ms device initialization and then ramps the volume up to 0 db using a soft volume update sequence. If MCLK_IN is not active when RESET
is released high, then a 4-ms to 5-ms initialization sequence is produced once MCLK_IN becomes
active. During device initialization all controls are reset to their initial states. Table 2−7 shows the control settings that
are changed during initialization. RESET
SLES090A—November 2003—Revised January 2004 TAS5076
must be applied during power-up initialization or while changing the master slave clock states.
15
Architecture Overview
Because the RESET is an asynchronous control signal, small clicks and pops can be produced during the application (the leading edge) of this control. However, when RESET mute state back to normal operation is performed synchronously using a quiet sequence.
Table 2−6. Device Outputs During Reset
SIGNAL MODE SIGNAL STATE
Valid 1−Valid 6 All Low PWM_P outputs All Low PWM_M outputs All Low MCLK_OUT All Low SCLK Master Low SCLK Slave Signal input LRCLK Master Low LRCLK Slave Signal input SDA All Signal input CLIP All High
is released, the transition from the hard
If a completely quiet reset sequence is desired, MUTE
CONTROL SETTING
Volume 0 dB MCLK_IN frequency 256 Master/slave mode M_S terminal state Automute Enabled De-emphasis None Dc offset 0 Interchannel delay Each channel is set to default value
2.2.2 Power Down—PDN
The TAS5076 can be placed into the power-down mode by holding the PDN terminal low. When the power-down mode is entered, both the PLL and the oscillator are shut down. V olume is immediately set to full attenuation (there is no ramp down). The valid 1−6 outputs are immediately asserted low and the PWM outputs are placed in the hard mute state. PDN terminal is held low, the device is in the power-down (hard mute) state.
During power down, all I signals while PDN
To place the device in total power-down mode, both RESET and power-down modes must be enabled. Prior to bringing PDN
is active.
high, RESET must be brought low for a minimum of 50 ns.
must be applied before applying RESET.
Table 2−7. Values Set During Reset
initiates device power down without clock inputs. As long as the PDN
2
C and serial data bus operations are ignored. Table 2−8 shows the device output
Table 2−8. Device Outputs During Power Down
SIGNAL MODE SIGNAL STATE
Valid 1−Valid 6 All Low PWM_P outputs All Low PWM_M outputs All Low MCLK_OUT All Low SCLK Master Low SCLK Slave Signal input LRCLK Master Low LRCLK Slave Signal input SDA All Signal input CLIP All High
16
SLES090A—November 2003—Revised January 2004TAS5076
Because PDN is an asynchronous control signal, small clicks and pops can be produced during the application (the leading edge) of this control. However, when PDN to normal operation is performed synchronously using a quiet sequence.
If a completely quiet reset sequence is desired, MUTE
2.2.3 General Status Register
The general status register is a read-only register. This register provides an indication when a volume update is in progress or one of the channels is inactive. The device ID can be read using this register.
Volume update is in progress—Whenever a volume change is in progress due to a volume update command or mute, this status bit is high.
Device identification code—The device identification code 0 0000 is displayed. No internal errors (all valid signals are high)—When there are no internal errors in the TAS5076 and all
outputs are valid, this status bit is high. One or more valid signals are inactive—If low, one or more channels of the TAS5076 are not outputting data.
The valid signals for those channels are inactive. Inactive valid signals can be produced by one of these causes:
One or more of the clock signals are in error.
ERROR
The automute has silenced one or more channels that are receiving 0 inputs.
MUTE
Volume control has been set to full attenuation.
If this signal is high, the TAS5076 is outputting data on all channels.
recover is active (low).
has been set.
Architecture Overview
is released, the transition from the hard mute state back
must be applied before applying PDN.
2.2.4 Error Status Register
The error status register indicates historical information on control signal changes and clock errors. This register latches these indications when they occur. The indications are cleared by writing 00h to the register.
This register is intended as a diagnostic tool to be used only when the system is not operating correctly . This is because the error status bits are set when the data rate, serial data interface format, or master/slave mode is changed. As a result, this register indicates an error condition even though the system is operating normally. This register must be used only while diagnosing transient error conditions.
Any clock error or control signal terminal change that occurs since the last time the error status register was cleared is displayed. In using this register, the first step is to initialize the device and ve rify that all of the clock signals are active. Then this register must be cleared by writing 00h. After this point, the register indicates any errors or control signal changes.
This register indicates an error condition by a high for the following conditions:
Fs error
A control terminal change has occurred (M_S, DBLSPD).
LRCLK error
MCLK_IN count error
DCLK phase error with respect to MCLK_IN
MCLK_IN phase error with respect to DCLK
PWM timing error
If all bits of the register are low, no errors have occurred and no control terminals changed. There is no one-to-one correspondence of clock error indication to a system error condition. A particular
system error can be indicated by one or more error indications in this register. The system error conditions and the reported errors are as follows:
There is no correct number of MCLKs per LRCLK:
Fs error has occurred.
LRCLK error
MCLK_IN count error
SLES090A—November 2003—Revised January 2004 TAS5076
17
Architecture Overview
LRCLK is absent:
LRCLK error MCLK is the wrong frequency, changing frequency, or absent:
DCLK phase error with respect to MCLK
MCLK phase error with respect to DCLK
PWM timing error
SCLK is the wrong frequency or absent
SCLK error
2.3 Signal Processing
This section contains the signal processing functions that are contained in the TAS5076. The signal processing is performed using a high-speed 24-bit signal processing architecture. The TAS5076 has the following signal processing features:
Individual channel soft volume with a range of 24 dB to −114 dB plus mute
Soft mute
Automute
50-µs/15-µs de-emphasis filter supported in the sampling rates 32 kHz, 44.1 kHz, and 48 kHz
2.3.1 Volume Control
The gain of each output can be adjusted by a soft digital volume control for each channel. Volume adjustments are performed using a soft gain update s-curve, which is approximated using a second-order filter fit. The curve fit is performed over a transition interval between 41 ms and 65 ms.
The volume of each channel can be adjusted from mute to −114 dB to 24 dB in 0.5 dB steps. Because of the numerical representation that is used to control the volume, at very low volume levels the step size increases for gains of that are less than −96 dB. The default volume setting following power up or reset is 0 dB for all channels. The step size adjustment is linear down to approximately −90 dB, see Figure 2−10.
STEP SIZE
vs
ATTENUATION (GAIN)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
Step Size − dB
2.0
1.5
1.0
0.5
0.0
−110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 10 20 Attenuation (Gain) − dB
Figure 2−10. Attenuation Curve
18
The volume control format for each channel is expressed in 8 bits. The volume for each channel is set by writing 8 bits via the serial control interface. The MSB bit is written first as in the bit position 0 (LSB position).
SLES090A—November 2003—Revised January 2004TAS5076
The volume for each channel can be set using a single- or multiple-address write operation to the volume control register via the serial control interface. Changing the volume of all six channels requires that 6 registers be updated.
To coordinate the volume adjustment of multiple channels simultaneously, the TAS5076 performs a delayed volume update upon receiving a volume change command. Following the completion of the register volume write operations, the TAS5076 waits for 5 ms for another volume command to be given. If no volume command is issued in that period of time, the TAS5076 starts adjusting the volume of the channels that received volume settings.
While a volume update is being performed, the system status register indicates that the update is in progress. During the update, all subsequent volume control setting requests that are sent to the TAS5076 are received and stored as a single next value for a subsequent update. If more than one volume setting request is sent, only the last is retained.
2.3.2 Mute
Table 2−9. V olume Register
VOLUME REGISTER
D7 D6 D5 D4 D3 D2 D1 D0
Vol
Bit 7
Vol
Bit 6
Vol
Bit 5
Vol
Bit 4
Vol
Bit 3
Vol
Bit 2
Vol
Bit 1
Architecture Overview
Vol
Bit 0
The application of mute ramps the volume from any setting to the noiseless hard-mute state. There are two methods in which the TAS5076 can be placed into mute. The TAS5076 is placed in the noiseless mute when the MUTE
terminal is asserted low for a minimum of 3 MCLK_IN cycles. Alternatively , the mute mode can be initiated by setting the mute bit in the system control register through the serial control interface. The TAS5076 is held in mute state as long as the terminal is low or I and exit sequences to and from the hard-mute state.
If an error recovery (described in the PWM section) occurs after a mute request has been received, the device returns from error recovery with the channel volume set as specified by the mute command.
2.3.3 Automute
Automute is an automatic sequence that can be enabled or disabled via the serial control interface. The default for this control is enabled. When enabled, the PWM automutes an individual channel when a channel receives from 5 ms to 50 ms of consecutive zeros. This time interval can be selectable using the automute delay register. The default interval is 5 ms. This duration is independent of the sample rate. The automute state is exited when two consecutive samples of nonzero data are received. The TAS5076 exit from automute is performed quickly and preserves all music information.
This mode uses the valid low to provide a low-noise floor while maintaining a short start-up time. Noise free entry and exit is achieved by using the PWM quiet start and stop sequences.
2.3.4 Individual Channel Mute
Individual channel mute is invoked through the serial interface. Individual channel mute permits each channel of the TAS5076 to be individually muted and unmuted. The operation that is performed is identical to the mute operation; however, it is performed on a per-channel basis. A TAS5076 channel is held in the mute state as long as the serial interface mute setting for that channel is set.
2
C mute setting is active. This command uses quiet entry
2.3.5 De-Emphasis Filter
For audio sources that have been pre-emphasized, a precision 50-µs/15-µs de-emphasis filter is provided to support the sampling rates of 32 kHz, 44.1 kHz, and 48 kHz. See Figure 2−11 for a graph showing the de-emphasis filtering characteristics. De-emphasis is set using two bits in the system control register.
SLES090A—November 2003—Revised January 2004 TAS5076
19
Architecture Overview
Table 2−10. De-Emphasis Filter Characteristics
DEM_SEL2 (MSB) DEM_SEL1 DESCRIPTION
0 0 De-emphasis disabled 0 1 De-emphasis enabled for Fs = 48 kHz 1 0 De-emphasis enabled for Fs = 44.1 kHz 1 1 De-emphasis enabled for Fs = 32 kHz
Following the change of state of the de-emphasis bits, the PWM outputs go into the soft mute state. After 128 LRCLK periods for initialization, the PWM outputs are driven to the normal (unmuted) mode.
0
−10
Response − dB
3.18 (50 µs) 10.6 (15 µs)
Figure 2−11. De-Emphasis Filter Characteristics
2.4 Pulse-Width Modulator (PWM)
De-Emphasis
f − Frequency − kHz
The TAS5076 contains six channels of high performance digital Equibit PWM modulators that are designed to drive switching output stages (back ends) in both single-ended (SE) and H-bridge (bridge tied load) configuration. The TAS5076 device uses noise shaping and sophisticated error correction algorithms to achieve high power efficiency and high-performance digital audio reproduction.
The PWM provides six pseudodifferential outputs to drive six monolithic power stages (such as TAS5110) or six discrete differential power stages using gate drivers (such as the TAS5182) and MOSFETs in single-ended or bridged configurations. The TAS5076 also provides a high-performance differential output that can be used to drive an external analog headphone amplifier.
2.4.1 Clipping Indicator
The clipping output is designed to indicate clipping. When any of the six PWM outputs exceeds the maximum allowable amplitude, the clipping indicator is asserted. The clipping indicator is cleared every 10 ms.
2.4.2 Error Recovery
Error recovery is used to provide error management and to permit the PWM output to be reset while preserving all intervolume, interchannel delay, dc offsets, and the other internal settings. Error recovery is initiated by bringing the ERR_RCVRY in control register 1. Error recovery is a level-sensitive signal.
The device also performs an error recovery automatically:
When the speed configuration is changed to normal, double, or quad speed
Following a change in the serial data bus interface configuration
When ERR_RCVRY there are any pending speed configurations, these changes are then performed. When ERR_RCVRY brought high, a delay of 4 ms to 5 ms is performed before the system starts the output re-initialization sequence. After the initialization time, the TAS5076 begins normal operation. During error recovery, all controls and device settings that were not updated are maintained in their current configurations.
is brought low, all valid signals go low, and the PWM_P and PWM_M outputs go low. If
terminal low for a minimum 5 MCLK_IN cycles or by setting the error recovery bit
is
20
To permit error recovery to be used to provide TAS5100 error management and recovery, the delay between the start of (falling edge) error recovery and the falling edge of valid 1 though valid 6 is selectable. This delay can be selected to be either 6 µs or 47 µs.
SLES090A—November 2003—Revised January 2004TAS5076
During error recovery all serial data bus operations are ignored. At the conclusion of the sequence, the error recovery register bit is returned to the normal operation state. Table 2−11 shows the device output signal states during error recovery.
Table 2−11. Device Outputs During Error Recovery
SIGNAL MODE SIGNAL STATE
Valid 1−Valid 6 All Low PWM_P outputs All Low PWM_M outputs All Low MCLK_OUT All Low SCLK Master Low SCLK Slave Signal input LRCLK Master Low LRCLK Slave Signal input SDA All Signal input CLIP All High
The transitions are done using a quiet entrance and exit sequence to prevent pops and clicks.
2.4.3 Individual Channel Error Recovery
Individual channel error recovery is used to provide error management and to permit the PWM output to be turned off. Error recovery is initiated by setting one or more of the six error recovery bits in the error recovery register to low.
Architecture Overview
While the error recover bits are brought low , the valid signals go to the low state. When the error recovery bits are brought high, a delay of 4 ms to 5 ms occurs before the channels are returned to normal operation.
The delay between the falling edge of the error recover bit and the falling edge of valid 1 though valid 6 is selectable. This delay can be selected to be either 6 µs or 47 µs.
The TAS5076 controls the relative timing of the pseudo-differential drive control signals plus the valid signal to minimize the production of system noise during error recovery operations. The transitions to valid low and valid high are done using an almost quiet entrance and exit sequence to prevent pops and clicks.
2.4.4 PWM DC-Offset Correction
An 8-bit value can be programmed to each of the six PWM offset correction registers to correct for any offset present in the output stages. The offset correction is divided into 256 intervals with a total offset correction of ±1.56% of full scale. The default value is zero correction represented by 00h. These values can be changed at any time through the serial control interface.
2.4.5 Interchannel Delay
An 8-bit value can be programmed to each of the six PWM interchannel delay registers to add a delay per channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK. Each subsequent channel has a default value that is N DCLKs larger than the preceding channel. The default interchannel delay for the first channel and the interchannel delay between subsequent channels are mask programmable. The present values are 0 for the first channel with increments of 53 for each successive channel.
These values can be updated upon power up through the serial control interface. This delay is generated in the PWM block with the appropriate control signals generated in the CTL block.
These values can be changed at any time through the serial control interface. The optimum value for interchannel delay depends on the final system. This value can be adjusted for better
performance with regard to dynamic range and THD. It is recommended that the following TC delay values be set instead of the default value. These TC delay values in conjunction with the ABD delay value (see discussion in Section 2.4.6) deliver the best performance in the TAS5076-5182 EVM board.
SLES090A—November 2003—Revised January 2004 TAS5076
21
Architecture Overview
These values must be reprogrammed every time RESET is asserted. RESET causes default values to be loaded.
2.4.6 ABD Delay
A 5-bit value is used to delay the A PWM signals with respect to B PWM signals. The value is the same for all channels. It can be programmed from 0 to 31 DCLK clock cycles. The default ABD value is 20 DCLK clock cycles (10100). This value is mask programmable.
This value can be changed at any time through the serial control interface. The optimum value for ABD delay depends on the final system. This value can be adjusted for better
performance with regard to dynamic range and THD. It is recommended that the following ABD delay value be set instead of the default value. The ABD delay value in conjunction with the TC delay values delivers the best performance in the TAS5076−5182 EVM board.
REGISTER
0Ch 01h TC delay channel 1 0Dh 49h TC delay channel 2 0Eh 91h TC delay channel 3 0Fh 39h TC delay channel 4 10h 21h TC delay channel 5 11h 69h TC delay channel 6
REGISTER SETTING FUNCTION
12h 1Dh ABD delay
SETTING FUNCTION
This value must be reprogrammed every time RESET is asserted. RESET causes the default value to be loaded.
NOTE:
The performance of a PurePath Digital amplifier system is optimized by setting the PWM timing based upon the type of back-end device that is used and the layout. These values are set during initialization using the I
2
C serial interface.
2.4.7 PWM/H-Bridge and Discrete H-Bridge Driver Interface
The TAS5076 provides six PWM outputs, which are designed to drive switching output stages (back-ends) in both single-ended (SE) and H-bridge (bridge-tied load) configuration. The back ends can be monolithic power stages (such as the T AS5110) or six discrete differential power stages using gate drivers (such as the the TAS55182) and MOSFETs in single-ended or bridged configurations.
The TAS5110 device is optimized for bridge-tied load (BTL) configurations. These devices require a pure differential PWM signal with a third signal (VALID) to control the MUTE state. In the MUTE state, the TAS5110 OUTA and OUTB are both low.
One Channel
of TAS5076
PWM_AP
PWM_AM
VALID
PWM_BP
PWM_BM
AP AM RESET BP BM
TAS5110
OUTA
OUTB
Speaker
Figure 2−12. PWM Outputs and H-Bridge Driven in BTL Configuration
PurePath Digital is a trademark of Texas Instruments.
22
SLES090A—November 2003—Revised January 2004TAS5076
2.5 I2C Serial Control Interface
p
Architecture Overview
SDA
MCLK must be active for the TAS5076 to support I2C bus transactions. The T AS5076 has a bidirectional serial control interface that is compatible with the I
2
C (Inter IC) bus protocol and supports both 100-kbps and 400-kbps data transfer rates for single- and multiple-byte write and read operations. This is a slave-only device that does not support a multi-master bus environment or wait state insertion. The control interface is used to program the registers of the device and to read device status.
The TAS5076 supports the standard-mode I operation (400 kHz maximum). The TAS5076 performs all I
2
C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits
The I
2
C bus operation (100 kHz maximum) and the fast I2C bus
2
C operations without I2C wait cycles.
in a system. Data is transferred on the bus serially one bit at a time. The address and data are transferred in byte (8 bit) format with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 2−13. The master generates the 7-bit slave address and the read/write (R/W
) bit to open communication with another device and then waits for an acknowledge condition. The TAS5076 holds SDA low during acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An I
bit (1 byte).
2
external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus.
7 Bit Slave Address
R/
8 Bit Register Address (N)A
W
8 Bit Register Data For
A
Address (N)
8 Bit Register Data For
AA
Address (N)
C
SCL
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Start Sto
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Figure 2−13. Typical I2C Sequence
There are no limits on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is also shown in Figure 2−13.
The 7-bit address for the TAS5076 is 001101X, where X is a programmable address bit. Using the CS0 terminal on the device, the LSB address bit is programmable to permit two devices to be used in a system. These two addresses are licensed I To communicate with the TAS5076, the I
2
C addresses and do not conflict with other licensed I2C audio devices.
2
C master uses 001 1010 if CS0 = 0 and 0011011 if CS0 = 1. In addition to the 7-bit device address, an 8-bit register address is used to direct communication to the proper register location within the device interface.
Read and write operations to the TAS5076 can be done using single-byte or multiple-byte data transfers.
SLES090A—November 2003—Revised January 2004 TAS5076
23
Architecture Overview
2.5.1 Single-Byte Write
As shown in Figure 2−14, a single-byte data write transfer begins with the master device transmitting a start condition followed by the I of the data transfer. For a write data transfer, the read/write bit is 0. After receiving the correct I address and the read/write bit, the TAS5076 device responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to the TAS5076 internal memory address being accessed. After receiving the address byte, the TAS5076 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5076 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data write transfer.
Start
Condition
A6 A5 A4 A3 A2 A1 A0
I2C Device Address and
Read/Write Bit
2.5.2 Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to TAS5076 as shown in Figure 2−15. After receiving each data byte, the TAS5076 responds with an acknowledge bit.
Start
Condition
Acknowledge Acknowledge Acknowledge
2
C device address and the read/write bit. The read/write bit determines the direction
Acknowledge Acknowledge Acknowledge
R/W
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Register Address Data Byte
2
C device
Stop
Condition
Figure 2−14. Single-Byte Write Transfer
Acknowledge
A6 A5 A1 A0
I2C Device Address and
Read/Write Bit
R/W
2.5.3 Single-Byte Read
As shown in Figure 2−16, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit is 0. After receiving the TAS5076 address and the read/write bit, the TAS5076 responds with an acknowledge bit. Also, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5076 address and the read/write bit again. This time the read/write bit is a 1 indicating a read transfer. After receiving the TAS5076 and the read/write bit, the TAS5076 again responds with an acknowledge bit. Next, the TAS5076 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single-byte data read transfer.
Start
Condition
A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK
I2C Device Address and
Read/Write Bit
Acknowledge Acknowledge Acknowledge
ACK A7 A5 A1 A0 ACK D7 D6 D1 D0 ACK
A4 A3A6
Register Address Last Data Byte
First Data Byte
D7 D6 D1 D0 ACK
Other
Data Bytes
Figure 2−15. Multiple-Byte Write Transfer
2
C device address and the read/write bit. For the data read transfer, a write followed
Repeat Start Condition
R/WA1 A1
Register Address Data Byte
I2C Device Address and
Read/Write Bit
D7 D6 D1 D0 ACK
Not
Acknowledge
Condition
Stop
Condition
Stop
24
Figure 2−16. Single-Byte Read
SLES090A—November 2003—Revised January 2004TAS5076
2.5.4 Multiple-Byte Read
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the TAS5076 to the master device as shown in Figure 2−17. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte.
Architecture Overview
Start
Condition
I2C Device Address and
Read/Write Bit
Repeat Start Condition
Acknowledge Acknowledge Acknowledge
A7 A6 A5
Register Address Other
A6 A0 ACK
I2C Device Address and
Read/Write Bit
Acknowledge
R/WA6 A0 R/W ACK A4 A0 ACK D7 D0 ACK
First Data Byte
Data Bytes
Figure 2−17. Multiple-Byte Read
Not
Acknowledge
D7 D6 D1 D0 ACK
Last Data Byte
Stop
Condition
SLES090A—November 2003—Revised January 2004 TAS5076
25
Architecture Overview
26
SLES090A—November 2003—Revised January 2004TAS5076
3 Serial Control Interface Register Definitions
Table 3−1 shows the register map for the TAS5076. Default values in this section are in bold.
2
T able 3−1. I
ADDR HEX DESCRIPTION
00 General status register 01 Error status register 02 System control register 0 03 System control register 1 04 Error recovery register 05 Automute delay 06 Dc-offset control register channel 1 07 Dc-offset control register channel 2 08 Dc-offset control register channel 3 09 Dc-offset control register channel 4 0A Dc-offset control register channel 5 0B Dc-offset control register channel 6 0C Interchannel delay register channel 1 0D Interchannel delay register channel 2 0E Interchannel delay register channel 3 0F Interchannel delay register channel 4 10 Interchannel delay register channel 5 11 Interchannel delay register channel 6 12 ABD delay register 13 Volume control register channel 1 14 Volume control register channel 2 15 Volume control register channel 3 16 Volume control register channel 4 17 Volume control register channel 5 18 Volume control register channel 6 19 Individual channel mute
C Register Map
Serial Control Interface Register Definitions
The volume table is contained in Appendix A. Default values are shown in bold in the following tables.
3.1 General Status Register (0x00)
Table 3−2. General Status Register (Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 No volume update is in progress.
1 Volume update is in progress.
0 Always 0
0 0 0 0 0 Device identification code
0 Any valid signal is inactive (see status register, 0x03) (see Note 1).
1 No internal errors (all valid signals are high)
NOTE 1: This bit is reset automatically when one or more channels are active.
SLES090A—November 2003—Revised January 2004 TAS5076
27
Serial Control Interface Register Definitions
3.2 Error Status Register (0x01)
Table 3−3. Error Status Register
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
1 FS error has occurred
1 Control pin change has occurred
1 LRCLK error
1 MCLK_IN count error
1 DCLK phase error with respect to MCLK_IN
1 MCLK_IN phase error with respect to DCLK
1 PWM timing error 0 0 0 0 0 0 0 0 No errors—no control pins changed (see Note 1)
NOTE 1: Write 00h to clear error indications in error status register.
3.3 System Control Register 0 (0x02)
Table 3−4. System Control Register 0
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 Normal mode (in slave mode—quad speed detected if MCLK_IN = 128 Fs)
0 1 Double speed 1 0 Quad speed 1 1 Illegal
0 Use de-emphasis pin controls
1 Use de-emphasis I2C controls
0 0 No de-emphasis
0 1 De-emphasis for Fs = 32 kHz
1 0 De-emphasis for Fs = 44.1 kHz
1 1 De-emphasis for Fs = 48 kHz
0 0 0 16 bit, MSB first; right justified
0 0 1 20 bit, MSB first; right justified
0 1 0 24 bit, MSB first; right justified
0 1 1 16-bit I2S
1 0 0 20-bit I2S
1 0 1 24-bit I2S
1 1 0 16-bit MSB first
1 1 1 16-bit DSP frame
28
SLES090A—November 2003—Revised January 2004TAS5076
Serial Control Interface Register Definitions
3.4 System Control Register 1 (0x03)
Table 3−5. System Control Register 1
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 Reserved − Set to 0 in all cases
0 Valid remains high during automute.
1 Valid goes low during automute.
0 Valid remains high during mute.
1 Valid goes low during mute.
0 Mute
1 Normal mode
0 Set error recovery delay at 6 µs
1 Set error recovery delay at 47 µs
0 Error recovery (forces error recovery initialization sequence)
1 Normal mode
0 Automute disabled
1 Automute enabled
0 Reserved − Set to 0 in all cases
3.5 Error Recovery Register (0x04)
Table 3−6. Error Recovery Register
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
1 1 Set to 11 under default conditions and when 0x00 is written into 0x1F
0 If 0x84 is written into register 0x1F –
Enable volume ramp up after an error recovery sequence is initiated by the ERR_RCVRY
1 If 0x84 is written into register 0x1F –
Disable volume ramp up after an error recovery sequence is initiated by the ERR_RCVRY
0 If 0x84 is written into register 0x1F – Enable volume ramp up after error recovery sequence is initiated by register bits
D5 – D0 of this register
1 If 0x84 is written into register 0x1F – Enable volume ramp up after error recovery sequence is initiated by register bits
D5 – D0 of this register
0 Put channel 6 into error recovery mode
0 Put channel 5 into error recovery mode
0 Put channel 4 into error recovery mode
0 Put channel 3 into error recovery mode
0 Put channel 2 into error recovery mode
0 Put channel 1 into error recovery mode
1 1 1 1 1 1 Normal operation
terminal or the I2C error recovery command (register 0x03 bit D2)
terminal or the I2C error recovery command (register 0x03 bit D2)
SLES090A—November 2003—Revised January 2004 TAS5076
29
Serial Control Interface Register Definitions
3.6 Automute Delay Register (0x05)
Table 3−7. Automute Delay Register
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 Unused
0 0 0 0 Set automute delay at 5 ms
0 0 0 1 Set automute delay at 10 ms
0 0 1 0 Set automute delay at 15 ms
0 0 1 1 Set automute delay at 20 ms
0 1 0 0 Set automute delay at 25 ms
0 1 0 1 Set automute delay at 30 ms
0 1 1 0 Set automute delay at 35 ms
0 1 1 1 Set automute delay at 40 ms
1 0 Set automute delay at 45 ms
1 1 Set automute delay at 50 ms
3.7 Dc-Offset Control Registers (0x06−0x0B)
Channels 1, 2, 3, 4, 5, and 6 are mapped into (0x06, 0x07, 0x08, 0x09, 0x0A, and 0x0B).
Table 3−8. Dc-Offset Control Registers
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
1 0 0 0 0 0 0 0 Maximum correction for positive dc offset (–1.56% FS) 0 0 0 0 0 0 0 0 No dc-offset correction 0 1 1 1 1 1 1 1 Maximum correction for negative dc offset (1.56% FS)
3.8 Interchannel Delay Registers (0x0C−0x11)
Channels 1, 2, 3, 4, 5, and 6 are mapped into (0x0C, 0x0D, 0x0E, 0x0F, 0x10, and 0x11). The first channel delay is set at 0. Each subsequent channel has a default value that is 53 DCLKs larger than
the preceding channel.
Table 3−9. Six Interchannel Delay Registers
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 0 Minimum absolute delay, 0 DCLK cycles, default for channel 1 = 0x00 0 0 1 1 0 1 0 1 Default for channel 2 = 0x35 0 1 1 0 1 0 1 0 Default for channel 3 = 0x6A 1 0 0 1 1 1 1 1 Default for channel 4 = 0x9F 1 1 0 1 0 1 0 0 Default for channel 5 = 0xD4 0 0 0 0 1 0 0 1 Default for channel 6 = 0x09
1 1 1 1 1 1 1 1 Maximum absolute delay, 255 DCLK cycles
3.9 ABD Delay Register (0x12)
Table 3−10. ABD Delay Register
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 Unused
0 0 0 0 0 Minimum ABD delay, 0 DLCK cycles
1 0 1 0 0 Default ABD delay, 20 DLCK cycles
1 1 1 1 1 Maximum ABD delay, 31 DLCK cycles
30
SLES090A—November 2003—Revised January 2004TAS5076
Serial Control Interface Register Definitions
3.10 Individual Channel Mute Register (0x19)
Table 3−11. Individual Channel Mute Register
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
1 1 Unused
1 1 1 1 1 1 No channels are muted
0 Mute channel 1
0 Mute channel 2
0 Mute channel 3
0 Mute channel 4
0 Mute channel 5
0 Mute channel 6
SLES090A—November 2003—Revised January 2004 TAS5076
31
Serial Control Interface Register Definitions
32
SLES090A—November 2003—Revised January 2004TAS5076
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
4 System Procedures for Initialization, Changing Data Rates, and
Switching Between Master and Slave Modes
4.1 System Initialization
Reset is used during system initialization to hold the TAS5076 inactive while power (VDD), the master clock (MCLK_IN), the device control, and the data signals become stable. The recommended initialization sequence is to hold RESET signals (MUTE
, PDN, M_S, ERR_RCVRY, DBSPD, and CS0) are stable.
low for 24 MCLK_IN cycles after VDD has reached 3 V and the other control
Figure 4−1 shows the recommended sequence and timing for the RESET
terminal relative to system VDD
voltage and MCLK.
3 V
VDD
RESET
24 MCLK_IN Cycles
MCLK
Figure 4−1. RESET During System Initialization
Within the first 2 ms following the low-to-high transition of the RESET must be set in the serial data interface control register using the I
terminal, the serial data interface format
2
C serial control interface. If the data rate setting is other than the setting specified by the DBSPD terminal, then the data rate must be set using the DBSPD terminal or I
2
C interface within 2 ms following the low-to-high transition of the RESET terminal.
2
The time available to set the I extended using the ERR_RCVRY Once the I
2
C control registers are set, the ERR_RCVRY terminal can be released and the TAS5076 starts operation. Figure 4−2 shows how the ERR_RCVRY necessary to set the I
SLES090A—November 2003—Revised January 2004 TAS5076
2
C registers following the low-to-high transition of the RESET terminal.
C registers following the low-to-high transition of the RESET terminal can be
terminal. While ERR_RCVRY is low, the TAS5076 outputs are held inactive.
terminal can be used to extend the interval as long as
33
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
E
MCLK
RESET
< 2 ms
RR_RCVRY
MUTE
ERR_RCVRY and MUTE can be set at any time prior to 2 ms following the low-to-high transition of RESET
Wait a minimum of 100 µs
after the low-to-high
transition of RESET
Set serial interface format, data
rate, volume, ... via I2C
> 5 ms
Release ERR_RCVRY and then MUTE registers are programmed
when I2C
Volume ramp up 120 ms
Figure 4−2. Extending the I2C Write Interval Following a Low-to-High Transition of the RESET Terminal
The operation of the TAS5076 can be tailored as desired to meet specific operating requirements by adjusting the following:
Volume
Data sample rate
Emphasis/deemphasis settings
Individual channel mute
Automute delay register
Dc-offset control registers
If desired, the TAS5076 can be set to perform an unmute sequence following the low-to-high transition of the ERR_RCVRY
terminal or the error recovery I2C command (register 0x03 bit D2). This capability is set by
writing 0x7F to the individual error recovery register (0x04) and 0x84 to the feature enable register (0x1F).
4.2 Data Sample Rate
If the master clock is well-behaved during the frequency transition (no MCLK_IN high or low clock periods less than 20 ns), then a simple speed selection is performed by setting the DBSPD terminal or the serial control register. If it is known at least 60 ms in advance that the sample rate is going to change, mute can be used to provide a completely silent transition. The timing of this control sequence is shown in Figure 4−3 and Figure 4−4.
34
SLES090A—November 2003—Revised January 2004TAS5076
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
Clock Transition
E
MCLK
MUTE
Terminal
DBSPD
Terminal
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
Volume Ramp
Down 42 − 65 ms
Set within 2 ms
of transition
< 2 ms < 2 ms
> 5 ms
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
Volume Ramp Up 42 − 65 ms
Figure 4−3. Changing the Data Sample Rate Using the DBSPD Terminal
Clock Transition
MCLK
MUTE
Terminal
RR_RCVRY
Terminal
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
Volume Ramp
Down 42 − 65 ms
< 2 ms
Set data rate via I2C
register 0x02, D7 and D6
Hold ERR_RCVRY low
to give additional timeset registers
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
> 5 ms
Volume Ramp Up 42 − 65 ms
< 2 ms
Figure 4−4. Changing the Data Sample Rate Using the I2C
However, if the master clock input can encounter a high clock or low clock period of less than 20 ns, then RESET
must be applied during this time. There are two recommended control procedures for this case, depending upon whether the DBSPD terminal or the serial control interface is used. These control sequences are shown in Figure 4−5 and Figure 4−6.
Because this sequence employs the RESET
SLES090A—November 2003—Revised January 2004 TAS5076
terminal the internal register settings are set to the default values.
35
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
E
Clock unstable during transition.
Figure 4−5 shows the procedure to change the data rate using the DBSPD terminal and then restore the register settings. In this example, the ERR_RCVRY RESET
is released. This permits the system controller to have as much additional time as necessary to restore
terminal is used to hold off system re-initialization after
the register settings. Once the data rate is set, the ERR_RCVRY
re-initializes.
HIGH and LOW intervals < 20 ns
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
MCLK
MUTE
Terminal
Volume Ramp
Down 60 ms
RESET
Terminal
DBSPD
Terminal
and MUTE terminal signals are set high and the system
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
> 5 ms
Volume Ramp
Up 120 ms
Wait a minimum of
100 µs to set DBSPD
RR_RCVRY
Terminal
ERR_RCVRY can be set at
any time within this interval
Wait a minimum of 100 µs after the
LOW to HIGH transition of RESET
< 2 ms
Restore register
settings via I2C
Release ERR_RCVRY and then MUTE registers are programmed
when I2C
Figure 4−5. Changing the Data Sample Rate With an Unstable MCLK_IN Using the DBSPD Terminal
Because this sequence employs the RESET
terminal, the internal register settings are set to the default
values. Figure 4−6 shows the procedure to change the data rate using register 0x02 D7 and D6 and then restore the
other register settings. In this example, the ERR_RCVRY terminal is used to hold off system re-initialization after RESET restore the register settings.
Once the data rate is set, the ERR_RCVRY
is released. This permits the system controller to have as much additional time as necessary to
and MUTE terminal signals are set high and the system
re-initializes.
36
SLES090A—November 2003—Revised January 2004TAS5076
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
E
Clock unstable during transition.
HIGH and LOW intervals < 20 ns
MCLK
MUTE
Terminal
RESET
Terminal
RR_RCVRY
Terminal
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
Volume Ramp
Down 60 ms
ERR_RCVRY can be set at
any time within this interval
Wait a minimum of 100 µs after the
LOW to HIGH transition of RESET
< 2 ms
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
> 5 ms
Volume Ramp
Up 120 ms
Set data rate and
restore other
register settings
via I2C
Release ERR_RCVRY and then MUTE registers are programmed
when I2C
Figure 4−6. Changing the Data Sample Rate With an Unstable MCLK_IN Using the I2C
4.3 Changing Between Master and Slave Modes
The M_S terminal is set while the RESET terminal is active. Because this sequence employs the RESET terminal the internal register settings are set to the default values.
Figure 4−7 shows the procedure to switch between master and slave modes and then restore the register settings. In this example, the ERR_RCVRY is released. This permits the system controller to have as much additional time as necessary to restore the register settings.
Once the data rate is set, the ERR_RCVRY re-initializes.
SLES090A—November 2003—Revised January 2004 TAS5076
terminal is used to hold off system re-initialization after RESET
and MUTE terminal signals are set high and the system
37
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
E
Clock unstable during transition.
MCLK
MUTE
Terminal
RESET
Terminal
M_S
Terminal
Change from Master Mode
Volume Ramp
Down 60 ms
Wait a minimum of
100 µs to set M_S
Change to Slave Mode
> 5 ms
Volume Ramp
Up 120 ms
< 2 ms
RR_RCVRY
Terminal
Release ERR_RCVRY and
ERR_RCVRY can be set at
any time within this interval
Wait a minimum of 100 µs after the
LOW to HIGH transition of RESET
then MUTE registers are programmed
Restore register
settings via I2C
when I2C
Figure 4−7. Changing Between Master and Slave Clock Mode
38
SLES090A—November 2003—Revised January 2004TAS5076
5 Specifications
Specifications
5.1 Absolute Maximum Ratings Over Operating Temperature Ranges (Unless Otherwise Noted)
Digital supply voltage range: DVDD, DVDD_PWM, DVDD_RCL −0.3 V to 4.2 V. . . . . . . . . . . . . . . . . . . . . . . . .
Analog supply voltage range: AVDD_PLL, AVDD_OSC −0.3 V to 4.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range, V
Operating free-air temperature 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
ESD 2000 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
−0.3 V to DVDD_X + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
5.2 Recommended Operating Conditions
MIN TYP MAX UNIT
Supply voltage Digital DVDD_X, see Note 2 3 3.3 3.6 V
Supply current Digital
Power dissipation Digital Supply voltage Analog AVDD_X, see Note 4 3 3.3 3.6 V
Supply current Analog
Power dissipation Analog
NOTES: 2. DVDD_CORE, DVDD_PWM, DVDD_RCL
3. If the clocks are turned off.
4. AVDD_PLL, AVDD_OSC
Operating 83 mA Power down, see Note 3 25 µA Operating 200 mW Power down 100 µW
Operating 8 mA Power down, see Note 3 25 µA Operating 35 mW Power down, see Note 3 100 µW
5.3 Electrical Characteristics Over Recommended Operating Conditions
5.3.1 Static Digital Specifications Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
V V V V I
IH IL OH OL
lkg
High-level input voltage 2 DVDD V Low-level input voltage 0 0.8 V High-level output voltage IO = −1 mA 2.4 V Low-level output voltage IO = 4 mA 0.4 V Input leakage current −10 10 µA
5.3.2 Digital Interpolation Filter and PWM Modulator Over Recommended Operating
Conditions (Unless Otherwise Noted) (Fs = 48 kHz)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Pass band 0 20 kHz Pass-band ripple ±0.012 dB Stop band 24.1 kHz Stop-band attenuation 24.1 kHz to 152.3 kHz 50 dB Group delay 700 µs PWM modulation index (gain) 0.93%
SLES090A—November 2003—Revised January 2004 TAS5076
39
Specifications
5.3.3 TAS5076/TAS5182 System Performance Measured at the Speaker Terminals Over Recommended Operating Conditions (Unless Otherwise Noted) (Fs = 48 kHz)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SNR (EIAJ) A-weighted 100 dB
Dynamic range
Measured on TAS5076-TAS5182 EVM
PWM_1 and PWM_2 All other channels
A-weighted, −60 dB, f = 1 kHz
105 102
† †
5.4 Switching Characteristics
5.4.1 Command Sequence Timing
5.4.1.1 Reset Timing—RESET
CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
w(RESET)
t
p(VALID_LOW)
t
p(VALID_HIGH)
t
d(VOLUME)
Pulse duration, RESET active 50 ns Propagation delay 1 µs Propagation delay 4 5 ms Delay time 42 65 ms
dB
RESET
VALID 1−6
VOLUME 1−6
t
p(VALID_LOW)
t
w(RESET)
Figure 5−1. RESET Timing
t
d(VOLUME)
t
p(VALID_HIGH)
40
SLES090A—November 2003—Revised January 2004TAS5076
5.4.1.2 Power-Down Timing—PDN
5.4.1.2.1 Long Recovery
CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
w(PDN)
t
d(R PDNR)
t
p(VALID_LOW)
t
p(VALID_HIGH)
t
d(VOLUME)
RESET
Pulse duration, PDN active 50 ns Reset high to PDN rising edge 16 MCLKs ns
85 100 ms 42 65 ms
t
d(R PDNR)
PDN
t
w(PDN)
Specifications
1 µs
VALID 1−6
VOLUME 1−6
Normal Operation
t
p(VALID_HIGH)
t
p(VALID_LOW)
t
d(VOLUME)
Figure 5−2. Power-Down and Power-Up Timing—RESET Preceding PDN
Normal Operation
SLES090A—November 2003—Revised January 2004 TAS5076
41
Specifications
5.4.1.2.2 Short Recovery
CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
w(PDN)
t
d(R PDNR)
t
p(VALID_LOW)
t
p(VALID_HIGH)
t
d(VOLUME)
RESET
Pulse duration, PDN active 50 ns PDN high to reset rising edge 16 MCLKs ns
4 5 ms
42 65 ms
t
d(R PDNR)
PDN
t
w(PDN)
1 µs
VALID 1−6
VOLUME 1−6
Normal Operation
t
p(VALID_HIGH)
t
p(VALID_LOW)
t
d(VOLUME)
Figure 5−3. Power-Down and Power-Up Timing—RESET Following PDN
Normal Operation
42
SLES090A—November 2003—Revised January 2004TAS5076
5.4.1.3 Error Recovery Timing—ERR_RCVRY
Selectable for minimum or maximum
CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
w(ER)
t
p(VALID_LOW)
t
p(VALID_HIGH)
ERR_RCVRY
Pulse duration, ERR_RCVRY active 5 MCLKs ns
6 47 µs 4 5 ms
t
w(ER)
Specifications
VALID 1−6
Normal Operation
t
p(VALID_LOW)
t
p(VALID_HIGH)
Figure 5−4. Error Recovery Timing
5.4.1.4 MUTE Timing—MUTE
CONTROL SIGNAL PARAMETERS OVER RECOMMENDED OPERATING CONDITIONS (UNLESS OTHERWISE NOTED)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
w(MUTE)
t
d(VOL)
MUTE
Pulse duration, PDN active 3 MCLKs ns
42 ms
t
w(MUTE)
Normal Operation
VOLUME
VALID 1−6
SLES090A—November 2003—Revised January 2004 TAS5076
Normal Operation
t
d(VOL)
Figure 5−5. Mute Timing
t
d(VOL)
Normal Operation
43
Specifications
5.4.2 Serial Audio Port
5.4.2.1 Serial Audio Ports Slave Mode Over Recommended Operating Conditions (Unless Otherwise Noted)
PARAMETER MIN TYP MAX UNIT
f
(SCLK)
t
su(SDIN)
t
h(SDIN)
f
(LRCLK)
t
su(LRCLK)
5.4.2.2 Serial Audio Ports Master Mode, Load Conditions 50 pF Over Recommended
t
(MSD)
t
(MLRD)
Frequency, SCLK 12.288 MHz SDIN setup time before SCLK rising edge 20 ns SDIN hold time before SCLK rising edge 10 ns LRCLK frequency 32 48 192 kHz MCLK_IN duty cycle 50% SCLK duty cycle 50% LRCLK duty cycle 50% LRCLK setup time before SCLK rising edge 20 ns MCLK high and low time 20 ns
Operating Conditions (Unless Otherwise Noted)
PARAMETER MIN TYP MAX UNIT
MCLK_IN to SCLK 0 5 ns MCLK_IN to LRCLK 0 5 ns
5.4.2.3 DSP Serial Interface Mode Over Recommended Operating Conditions (Unless Otherwise Noted)
PARAMETER MIN TYP MAX UNIT
f
(SCLK)
t
d(FS)
t
w(FSHIGH
t
su(SDIN)
t
h(SDIN)
) Pulse duration, sync 1/(64×Fs) ns
SCLK
SDIN
SCLK frequency 12.288 MHz Delay time, SCLK rising to Fs ns
SDIN and LRCLK setup time before SCLK falling edge 20 ns SDIN and LRCLK hold time from SCLK falling edge 10 ns SCLK duty cycle 50%
t
h(SDIN)
t
su(SDIN)
Figure 5−6. Right-Justified, I2S, Left-Justified Serial Protocol Timing
44
SLES090A—November 2003—Revised January 2004TAS5076
SCLK
t
su(LRCLK)
LRCLK
NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns).
Figure 5−7. Right, Left, and I2S Serial Mode Timing Requirement
SCLK
LRCLK
t
(MRLD)
Specifications
MCLK
SCLK
LRCLK
SDIN
t
(MSD)
t
su(LRCLK)
Figure 5−8. Serial Audio Ports Master Mode Timing
t
h(LRCLK)
t
w(FSHIGH)
t
su(SDIN)
t
h(SDIN)
Figure 5−9. DSP Serial Port Timing
SLES090A—November 2003—Revised January 2004 TAS5076
45
Specifications
SCLK
LRCLK
SDIN
t
w(FSHIGH)
64 SCLKS
SCLK
SDIN
t
su(SDIN)
16 Bits
Left
Channel
= 20 ns
16 Bits
Right
Channel
32 Bits Unused
Figure 5−10. DSP Serial Port Expanded Timing
t
h(SDIN)
= 10 ns
Figure 5−11. DSP Absolute Timing
46
SLES090A—November 2003—Revised January 2004TAS5076
Specifications
PARAMETER
TEST CONDITIONS
UNIT
PARAMETER
TEST CONDITIONS
UNIT
5.4.3 Serial Control Port—I2C Operation
5.4.3.1 Timing Characteristics for I2C Interface Signals Over Recommended Operating Conditions (Unless Otherwise Noted)
f
SCL
t
w(H)
t
w(L)
t
r
t
f
t
su1
t
h1
t
(buf)
t
su2
t
h2
t
su3
C
L
STANDARD
MODE
MIN MAX MIN MAX
Frequency, SCL 0 100 0 400 kHz Pulse duration, SCL high 4 0.6 µs Pulse duration, SCL low 4.7 1.3 µs Rise time, SCL and SDA 1000 300 ns Fall time, SCL and SDA 300 300 ns Setup time, SDA to SCL 250 100 ns Hold time, SCL to SDA 0 0 ns Bus free time between stop and start condition 4.7 1.3 µs Setup time, SCL to start condition 4.7 0.6 µs Hold time, start condition to SCL 4 0.6 µs Setup time, SCL to stop condition 4 0.6 µs Load capacitance for each bus line 400 400 pF
FAST MODE
SCLK
SDA
SCLK
t
w(H)
t
w(L)
t
su
Figure 5−12. SCL and SDA Timing
t
h2
t
su2
t
r
t
h1
t
(buf)
t
su3
t
f
SLES090A—November 2003—Revised January 2004 TAS5076
SDA
Start Condition Stop Condition
Figure 5−13. Start and Stop Conditions Timing
47
Specifications
48
SLES090A—November 2003—Revised January 2004TAS5076
6 Application Information
Application Information
DVSS_PWM DVDD_PWM DVSS_RCL DVDD_RCL VREGC_CAP VREGB_CAP VREGA_CAP
AVSS_PLL AVDD_PLL
Power Supply
PWM
Section
TAS5182
H-Bridge
SHUTDOWN
PWAP
PWBP
PWAM
PWBM
PWM_AP_1
PWM_AM_1
PWM_BP_1
PWM_BM_1
PWM Ch.
TAS5182
PWAP
RESET
VALID_1
PWM_AP_2
H-Bridge
SHUTDOWN
PWBP
PWAM
PWBM
RESET
VALID_2
PWM_AM_2
PWM_BP_2
PWM_BM_2
PWM Ch.
Signal
Processing
TAS5182
H-Bridge
SHUTDOWN
PWAP
PWBP
PWAM
PWBM
PWM_AP_3
PWM_AM_3
PWM_BP_3
PWM_BM_3
PWM Ch.
TAS5182
PWAP
RESET
VALID_3
PWM_AP_4
Auto Mute
De-Emphasis
H-Bridge
SHUTDOWN
PWBP
PWAM
PWBM
RESET
VALID_4
PWM_AM_4
PWM_BP_4
PWM_BM_4
Output Control
PWM Ch.
Soft Mute
Clip Detect
Soft Volume
Error Recovery
TAS5182
H-Bridge
SHUTDOWN
PWAP
PWBP
PWAM
PWBM
PWM_AP_5
PWM_AM_5
PWM_BP_5
PWM_BM_5
PWM Ch.
TAS5182
RESET
VALID_5
PWM_AP_6
H-Bridge
SHUTDOWN
PWAP
PWBP
PWAM
PWBM
PWM_AM_6
PWM_BP_6
PWM Ch.
RESET
VALID_6
PWM_BM_6
I/F
Serial
Control
SCL
SDA
CSO
P1.5/IA1/TDI
P1.4/SMCLK/TCK
MSP430
Reset,
Pwr Dwn
RESET
P1.0
and
PDN
P1.1
Status
P1.2
CLIP
P1.3
MUTE
ERR_RCVY
P2.0
XTAL_IN
MCLK_IN
XTAL_OUT
CLKOUT
M_S
DSP
DA610
Clock,
PLL_FLT_1
PLL
PLL_FLT_2
and
Serial
SCLK
ACLKX
I/F
Data
LRCLK
MCLKOUT
AFSX
SDIN1
SDIN2
ALKX1
ALKX0
SDIN3
ALKX2
DBSPD
DM_SEL1
DM_SEL2
Figure 6−1. Typical TAS5076 Application
SLES090A—November 2003—Revised January 2004 TAS5076
49
Application Information
6.1 Serial Audio Interface Clock Master and Slave Interface Configuration
6.1.1 Slave Configuration
Other Digital
Audio Sources
PCM1800
ADC
Left Analog
Right Analog
DOUT
BCK
LRCK
SYSCLK
Figure 6−2. TAS5076 Serial Audio Port—Slave Mode Connection Diagram
6.1.2 Master Configuration
Other Digital
Audio Sources
DA610 DSP
(Master Mode)
ALKR0
ALKR1 ALKR2
ACLKR AFSR
CLKIN
DA610 DSP
OSCI
OSCO
ALKX0 ALKX1 ALKX2
ACLKX
AFSX
CLKOUT
12.288
MHz XTAL
GND
TAS5076
(Slave Mode)
XTALI
XTALO
SDIN1 SDIN2 SDIN3
SCLK LRCK MCLKO
TAS5076
(Master Mode)
MCLKO
NC
Left Analog
Right Analog
PCM1800
ADC
SYSCLK
DOUT
BCK
LRCK
ALKR0
ALKR1 ALKR2
ACLKR AFSR
CLKIN
ALKX0 ALKX1 ALKX2
ACLKX
AFSX
CLKOUT
12.288
MHz XTAL
GND
XTALI
XTALO
SDIN1 SDIN2 SDIN3
MCLKO
Figure 6−3. TAS5076 Serial Audio Port—Master Mode Connection Diagram
SCLK LRCK
MCLKO
50
SLES090A—November 2003—Revised January 2004TAS5076
Mechanical Data
7 Mechanical Data
PFC (S-PQFP-G80) PLASTIC QUAD FLATPACK
80
61
1,05 0,95
0,50
60
0,27 0,17
41
1
9,50 TYP
12,20
SQ
11,80 14,20
SQ
13,80
20
0,08
21
40
M
0,13 NOM
Gage Plane
0,25
0,05 MIN
0,75 0,45
0°−7°
Seating Plane
1,20 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
SLES090A—November 2003—Revised January 2004 TAS5076
0,08
4073177/B 11/96
51
Mechanical Data
52
SLES090A—November 2003—Revised January 2004TAS5076
Appendix A—Volume Table
VOLUME SETTING
249 1111 1001 24 248 1111 1000 23.5 247 1111 0111 23 246 1111 0110 22.5 245 1111 0101 22 244 1111 0100 21.5 243 1111 0011 21 242 1111 0010 20.5 241 1111 0001 20 240 1111 0000 19.5 239 1110 1111 19 238 1110 1110 18.5 237 1110 1101 18 236 1110 1100 17.5 235 11101011 170 234 1110 1010 16.5 233 1110 1001 16 232 1110 1000 15.5 231 1110 0111 15 230 1110 0110 14.5 229 1110 0101 14 228 1110 0100 13.5 227 11100011 13 226 1110 0010 12.5 225 1110 0001 12 224 1110 0000 11.5 223 1101 1111 11 222 1101 1110 10.5 221 1101 1101 10 220 1101 1100 9.5 219 1101 1011 9 218 11011010 8.5 217 11011001 8 216 11011000 7.5 215 1101 0111 7 214 1101 0110 6.5 213 11010101 6 212 11010100 5.5 211 11010011 5 210 11010010 4.5 209 11010001 4 208 11010000 3.5 207 1100 1111 3 206 1100 1110 2.5
REGISTER VOLUME
(BIN)
D7 − D0
GAIN dB
Appendix A—Volume Table
VOLUME SETTING
205 1100 1101 2 204 1100 1100 1.5 203 1100 1011 1 202 11001010 0.5 201 11001001 0 200 11001000 −0.5 199 1100 0111 −1 198 1100 0110 −1.5 197 11000101 −2 196 11000100 −2.5 195 1100 0011 −3 194 11000010 −3.5 193 11000001 −4 192 11000000 −4.5 191 1011 1111 −5 190 1011 1110 −5.5 189 1011 1101 −6 188 1011 1100 −6.5 187 1011 1011 −7 186 10111010 −7.5 185 10111001 −8 184 10111000 −8.5 183 1011 0111 −9 182 1011 0110 −9.5 181 10110101 −10 180 10110100 −10.5 179 1011 0011 −11 178 10110010 −11.5 177 10110001 −12 176 10110000 −12.5 175 1010 1111 −13 174 1010 1110 −13.5 173 1010 1101 −14 172 1010 1100 −14.5 171 1010 1011 −15 170 1010 1010 −15.5 169 1010 1001 −16 168 1010 1000 −16.5 167 1010 0111 −17 166 1010 0110 −17.5 165 1010 0101 −18 164 1010 0100 −18.5 163 1010 0011 −19 162 1010 0010 −19.5
REGISTER VOLUME
(BIN)
D7 − D0
GAIN dB
SLES090A—November 2003—Revised January 2004 TAS5076
53
Appendix A—Volume Table
VOLUME SETTING
161 1010 0001 −20 160 1010 0000 −20.5 159 1001 1111 −21 158 1001 1110 −21.5 157 1001 1101 −22 156 1001 1100 −22.5 155 1001 1011 −23 154 1001 1010 −23.5 153 1001 1001 −24 152 1001 1000 −24.5 151 1001 0111 −25 150 1001 0110 −25.5 149 1001 0101 −26 148 1001 0100 −26.5 147 1001 0011 −27 146 1001 0010 −27.5 145 1001 0001 −28 144 1001 0000 −28.5 143 1000 1111 −29 142 1000 1110 −29.5 141 1000 1101 −30 140 1000 1100 −30.5 139 1000 1011 −31 138 1000 1010 −31.5 137 1000 1001 −32 136 1000 1000 −32.5 135 1000 0111 −33 134 1000 0110 −33.5 133 1000 0101 −34 132 1000 0100 −34.5 131 1000 0011 −35 130 1000 0010 −35.5 129 1000 0001 −36 128 1000 0000 −36.5 127 0111 1111 −37 126 0111 1110 −37.5 125 01111101 −38 124 01111100 −38.5 123 01111011 −39 122 0111 1010 −39.5 121 0111 1001 −40 120 0111 1000 −40.5
119 0111 0111 −41 118 01110110 −41.5 117 0111 0101 −42
REGISTER VOLUME
(BIN)
D7 − D0
GAIN dB
VOLUME
SETTING
116 0111 0100 −42.5 115 01110011 −43 114 0111 0010 −43.5 113 0111 0001 −44 112 0111 0000 −44.5
111 0110 1111 −45 110 0110 1110 −45.5 109 0110 1101 −46 108 0110 1100 −46.5 107 0110 1011 −47 106 01101010 −47.5 105 01101001 −48 104 01101000 −48.5 103 0110 0111 −49 102 0110 0110 −49.5 101 01100101 −50 100 01100100 −50.5
99 0110 0011 −51 98 0110 0010 −51.5 97 0110 0001 −52 96 0110 0000 −52.5 95 0101 1111 −53 94 0101 1110 −53.5 93 0101 1101 −54 92 0101 1100 −54.5 91 0101 1011 −55 90 0101 1010 −55.5 89 0101 1001 −56 88 0101 1000 −56.5 87 0101 0111 −57 86 0101 0110 −57.5 85 0101 0101 −58 84 0101 0100 −58.5 83 0101 0011 −59 82 0101 0010 −59.5 81 0101 0001 −60 80 0101 0000 −60.5 79 0100 1111 −61 78 0100 1110 −61.5 77 0100 1101 −62 76 0100 1100 −62.5 75 0100 1011 −63 74 0100 1010 −63.5 73 0100 1001 −64 72 0100 1000 −64.5
REGISTER VOLUME
(BIN)
D7 − D0
GAIN dB
54
SLES090A—November 2003—Revised January 2004TAS5076
Appendix A—Volume Table
VOLUME SETTING
71 0100 0111 −65 70 0100 0110 −65.5 69 0100 0101 −66 68 0100 0100 −66.5 67 0100 0011 −67 66 0100 0010 −67.5 65 0100 0001 −68 64 0100 0000 −68.5 63 0011 1111 −69 62 0011 1110 −69.5 61 0011 1101 −70 60 0011 1100 −70.5 59 0011 1011 −71 58 0011 1010 −71.5 57 0011 1001 −72 56 0011 1000 −72.5 55 0011 0111 −73 54 0011 0110 −73.5 53 0011 0101 −74 52 0011 0100 −74.5 51 0011 0011 −75 50 0011 0010 −75.5 49 0011 0001 −76 48 0011 0000 −76.6 47 0010 1111 −77 46 0010 1110 −77.5 45 0010 1101 −78 44 0010 1100 −78.5 43 0010 1011 −79 42 0010 1010 −79.6 41 0010 1001 −80.1 40 0010 1000 −80.6 39 0010 0111 −81.1 38 0010 0110 −81.5 37 0010 0101 −82.1
REGISTER VOLUME
(BIN)
D7 − D0
GAIN dB
VOLUME SETTING
36 0010 0100 −82.6 35 0010 0011 −83 34 0010 0010 −83.5 33 0010 0001 −84 32 0010 0000 −84.6 31 0001 1111 −85.1 30 0001 1110 −85.8 29 0001 1101 −86.1 28 0001 1100 −86.8 27 0001 1011 −87.2 26 0001 1010 −87.5 25 0001 1001 −88.4 24 0001 1000 −88.8 23 0001 0111 −89.3 22 0001 0110 −89.8 21 0001 0101 −90.3 20 0001 0100 −90.9 19 0001 0011 −91.5 18 0001 0010 −92.1 17 0001 0001 −92.8 16 0001 0000 −93.6 15 0000 1111 −94.4 14 0000 1110 −95.3 13 0000 1101 −96.3 12 0000 1100 −97.5 11 0000 1011 −98.8 10 0000 1010 −100.4
9 0000 1001 −102.4 8 0000 1000 −104.9 7 0000 0111 −108.4 6 0000 0110 −114.4 5 0000 0101 MUTE 4 0000 0100 MUTE 3 0000 0011 MUTE 2 0000 0010 MUTE 1 0000 0001 MUTE 0 0000 0000 MUTE
REGISTER VOLUME
(BIN)
D7 − D0
GAIN dB
SLES090A—November 2003—Revised January 2004 TAS5076
55
Appendix A—Volume Table
56
SLES090A—November 2003—Revised January 2004TAS5076
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