TEXAS INSTRUMENTS TAS5076 Technical data
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查询TAS5076供应商
TM
Data M anua
January 2004 DAV Digital Audio/Speaker
SLES090A
IMPORTANT NOTICE
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Products Applications
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Contents
Contents
Section Page
1 Introduction 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Functional Block Diagram 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Terminal Assignments 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Ordering Information 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Terminal Functions 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Architecture Overview 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Clock and Serial Data Interface 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection 7. . . . . . . . . . . . . . . . . . .
2.1.2 Clock Master/Slave Mode (M_S) 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3 Clock Master Mode 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4 Clock Slave Mode 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5 PLL External Filter 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.6 DCLK 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.7 Serial Data Interface 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Reset, Power Down, and Status 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Reset—RESET 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Power Down—PDN 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3 General Status Register 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4 Error Status Register 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Signal Processing 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Volume Control 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Mute 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3 Automute 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.4 Individual Channel Mute 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.5 De-Emphasis Filter 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Pulse Width Modulator (PWM) 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 Clipping Indicator 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.2 Error Recovery 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.3 Individual Channel Error Recovery 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.4 PWM DC-Offset Correction 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.5 Interchannel Delay 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.6 ABD Delay 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.7 PWM/H-Bridge and Discrete H-Bridge Driver Interface 22. . . . . . . . . . . . . . . . . . . . . . .
2.5 I2C Serial Control Interface 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1 Single-Byte Write 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2 Multiple-Byte Write 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.3 Single-Byte Read 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.4 Multiple-Byte Read 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Serial Control Interface Register Definitions 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 General Status Register (0x00) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Error Status Register (0x01) 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 System Control Register 0 (0x02) 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 System Control Register 1 (0x03) 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Error Recovery Register (0x04) 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Automute Delay Register (0x05) 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
November 2003—Revised January 2004 SLES090A
iii
Contents
3.7 Dc-Offset Control Registers (0x06−0x0B) 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Interchannel Delay Registers (0x0C−0x11) 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 ABD Delay Register (0x12) 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 Individual Channel Mute Register (0x19) 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 System Procedures for Initialization, Changing Data Rates, and Switching Between Master
and Slave Modes 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 System Initialization 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Data Sample Rate 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Changing Between Master and Slave Modes 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Specifications 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Absolute Maximum Ratings Over Operating Temperature Ranges 39. . . . . . . . . . . . . . . . . . . . . . .
5.2 Recommended Operating Conditions 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Electrical Characteristics Over Recommended Operating Conditions 39. . . . . . . . . . . . . . . . . . . .
5.3.1 Static Digital Specifications Over Recommended Operating Conditions 39. . . . . . . . .
5.3.2 Digital Interpolation Filter and PWM Modulator Over
Recommended Operating Conditions (Fs = 48 kHz) 39. . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3 TAS5076/TAS5182 System Performance Measured at the Speaker Terminals
Over Recommended Operating Conditions (Fs = 48 kHz) 40. . . . . . . . . . . . . . . . . . . .
5.4 Switching Characteristics 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1 Command Sequence Timing 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2 Serial Audio Port 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
5.4.3 Serial Control Port—I
C Operation 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Application Information 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Serial Audio Interface Clock Master and Slave Interface Configuration 50. . . . . . . . . . . . . . . . . . .
6.1.1 Slave Configuration 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2 Master Configuration 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Mechanical Data 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix A—Volume Table 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
November 2003—Revised January 2004SLES090A
List of Illustrations
List of Illustrations
Figure Title Page
2−1 Crystal Circuit 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 External PLL Filter 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 I2S 64-Fs Format 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 I2S 48-Fs Format 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 Left-Justified 64-Fs Format 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 Left-Justified 48-Fs Format 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 Right-Justified 64-Fs Format 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 Right-Justified 48-Fs Format 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 DSP Format 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 Attenuation Curve 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 De-Emphasis Filter Characteristics 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−12 PWM Outputs and H-Bridge Driven in BTL Configuration 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−13 Typical I2C Sequence 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−14 Single-Byte Write Transfer 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−15 Multiple-Byte Write Transfer 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−16 Single-Byte Read 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−17 Multiple-Byte Read 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 RESET During System Initialization 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Extending the I2C Write Interval Following a Low-to-High Transition of the RESET Terminal 34. . . . . . .
4−3 Changing the Data Sample Rate Using the DBSPD Terminal 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 Changing the Data Sample Rate Using the I2C35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Changing the Data Sample Rate With an Unstable MCLK_IN Using the DBSPD Terminal 36. . . . . . . . .
4−6 Changing the Data Sample Rate With an Unstable MCLK_IN Using the I2C37. . . . . . . . . . . . . . . . . . . . .
4−7 Changing Between Master and Slave Clock Mode 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1 RESET Timing 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 Power-Down and Power-Up Timing—RESET Preceding PDN 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−3 Power-Down and Power-Up Timing—RESET Following PDN 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−4 Error Recovery Timing 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−5 Mute Timing 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−6 Right-Justified, I2S, Left-Justified Serial Protocol Timing 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−7 Right, Left, and I2S Serial Mode Timing Requirement 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−8 Serial Audio Ports Master Mode Timing 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−9 DSP Serial Port Timing 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−10 DSP Serial Port Expanded Timing 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−11 DSP Absolute Timing 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12 SCL and SDA Timing 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−13 Start and Stop Conditions Timing 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 Typical TAS5076 Application 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2 TAS5076 Serial Audio Port—Slave Mode Connection Diagram 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−3 TAS5076 Serial Audio Port—Master Mode Connection Diagram 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
November 2003—Revised January 2004 SLES090A
v
List of Tables
List of Tables
Table Title Page
2−1 Normal-Speed, Double-Speed, and Quad-Speed Operation 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 Master and Slave Clock Modes 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 LRCLK and MCLK_IN Rates 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 DCLK 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 Supported Word Lengths 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 Device Outputs During Reset 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 Values Set During Reset 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 Device Outputs During Power Down 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 Volume Register 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 De-Emphasis Filter Characteristics 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 Device Outputs During Error Recovery 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
C Register Map 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 I
3−2 General Status Register (Read Only) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 Error Status Register 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 System Control Register 0 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 System Control Register 1 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Error Recovery Register 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 Automute Delay Register 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 Dc-Offset Control Registers 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 Six Interchannel Delay Registers 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 ABD Delay Register 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 Individual Channel Mute Register 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
November 2003—Revised January 2004SLES090A
1 Introduction
The TAS5076 is an innovative, cost-effective, high-performance 24-bit six-channel digital pulse-width
modulator (PWM) based on Equibit technology. Combined with a TI PurePath Digital audio amplifier power
stage, these devices use noise-shaping and sophisticated error-correction algorithms to achieve high power
efficiency and high-performance digital audio reproduction. The TAS5076 is designed to drive up to six digital
power devices to provide six channels of digital audio amplification. The digital power devices can be six
conventional monolithic power stages (such as the TAS5110) or six discrete differential power stages using
gate drivers and MOSFETs.
The TAS5076 has six independent volume controls and mute. The device operates in AD and BD modes. This
all-digital audio system contains only two analog components in the signal chain—an LC low-pass filter at each
speaker terminal. Dynamic range of 105 dB for the front channels and 102 dB for the other channels is
achievable on the TAS5076-TAS5182 EVM using the specified ABD and interchannel delay settings. The
TAS5076 has a wide variety of serial input options including right justified (16-, 20-, or 24-bit), I
or 24-bit) left justified, and DSP (16-bit) data formats. The device is fully compatible with AES standard
sampling rates of 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz, including de-emphasis for
44.1-kHz and 48-kHz sample rates. The TAS5076 plus the TAS51xx power stage device combination was
designed for home theater applications such as DVD minicomponent systems, home theater in a box (HTIB),
DVD receiver, A/V receiver, or TV sets.
1.1 Features
Introduction
2
S (16-, 20-,
• TI PurePath Digital Audio Amplifier
• High-Quality Audio
− Up to105-dB Dynamic Range
− <0.005% THD+N
• Six-Channel Volume Control
− Patented Soft Volume
− Patented Soft Mute
• 16-, 20-, or 24-Bit Input Data
• Sampling Rates: 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz
• Supports Master and Slave Modes
• 3.3-V Power-Supply Operation
• Economical 80-Pin TQFP Package
• De-Emphasis: 32 kHz, 44.1 kHz, and 48 kHz
• Clock Oscillator Circuit for Master Modes
• Low-Jitter Internal PLL
• Soft Volume and Mute Update
†
Measured TAS5076-TAS5182 EVM
†
Equibit and PurePath Digital are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
SLES090A—November 2003—Revised January 2004 TAS5076
1
Introduction
1.2 Functional Block Diagram
AVDD_PLL
AVSS_PLL
VREGA_CAP
VREGB_CAP
VREGC_CAP
DVDD_RCL
DVSS_RCL
DVDD_PWM
DVSS_PWM
MCLK_IN
XTAL_OUT
XTAL_IN
DBSPD
M_S
PLL_FLT_OUT
PLL_FLT_RET
SCLK
LRCLK
MCLKOUT
SDIN1
SDIN2
SDIN3
DM_SEL1
DM_SEL2
SDA
SCL
CSO
RESET
PDN
CLIP
MUTE
ERR_RCVY
Clock,
PLL
and
Serial
Data
I/F
Serial
Control
I/F
Reset,
Pwr Dwn
and
Status
Power Supply
Signal
Processing
Auto Mute
De-Emphasis
Soft Volume
Error Recovery
Soft Mute
Clip Detect
PWM
Section
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
Output Control
PWM_AP_1
PWM_AM_1
PWM_BP_1
PWM_BM_1
VALID_1
PWM_AP_2
PWM_AM_2
PWM_BP_2
PWM_BM_2
VALID_2
PWM_AP_3
PWM_AM_3
PWM_BP_3
PWM_BM_3
VALID_3
PWM_AP_4
PWM_AM_4
PWM_BP_4
PWM_BM_4
VALID_4
PWM_AP_5
PWM_AM_5
PWM_BP_5
PWM_BM_5
VALID_5
PWM_AP_6
PWM_AM_6
PWM_BP_6
PWM_BM_6
VALID_6
2
SLES090A—November 2003—Revised January 2004TAS5076
1.3 Terminal Assignments
AVDD_OSC
XTL_IN
XTL_OUT
AVSS_OSC
DVSS
PFC PACKAGE
(TOP VIEW)
PWM_AP1
PWM_AM_1
VALID_1
PWM_BM_1
PWM_BP_1
PWM_AP_2
PWM_AM_2
VALID_2
PWM_BM_2
PWM_BP_2
PWM_AP_3
PWM_AM_3
VALID_3
PWM_BM_3
Introduction
PWM_BP_3
NC
NC
MCLK_IN
AVDD_PLL
PLL_FLT_OUT
PLL_FLT_RET
AVSS_PLL
NC
VREGA_CAP
DVSS1
NC
RESET
ERR_RCVRY
MUTE
PDN
SDA
SCL
CS0
NC
NC
79 78 77 76 7580 74 72 71 7073
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22 23
24
NCNCNC
25 26 27 28
CLIP
SDIN1
DBSPD
29
SDIN2
SDIN3
69 682167 66 65 64
30 31 32 33
SCLK
DVDD
LRCLK
MCLK_OUT
63 62 61
34 35 36 37 38 39 40
DVSS
M_S
DVSS1
DEM_SEL2
DEM_SEL1
VREGC_CAP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC
DVSS1
VREGB_CAP
DVDD_RCL
DVSS_RCL
DVDD_PWM
DVSS_PWM
PWM_AP_4
PWM_AM_4
VALID_4
PWM_BM_4
PWM_BP_4
PWM_AP_5
PWM_AM_5
VALID_5
PWM_BM_5
PWM_BP_5
PWM_AP_6
PWM_AM_6
VALID_6
PWM_BM_6
PWM_BP_6
NC − No internal connection
SLES090A—November 2003—Revised January 2004 TAS5076
3
Introduction
FUNCTION
†
DESCRIPTION
1.4 Ordering Information
T AS
5076 PFC
Texas Instruments
Audio Solutions
Device Number
Package Type
AVAILABLE OPTIONS
PACKAGE
T
A
0°C to 70°C TAS5076PFC
PLASTIC 80-PIN TQFP
(PFC)
1.5 Terminal Functions
TERMINAL
NAME NO.
AVDD_OSC 80 P Analog power supply for internal oscillator cells
AVDD_PLL 4 P Analog power supply for PLL
AVSS_OSC 77 O Analog ground for internal oscillator cells
AVSS_PLL 7 P Analog ground for PLL
CLIP 25 O Digital clipping indicator, active low
CS0 18 I I2C serial control chip address select input, active high
DBSPD 24 I Sample rate is double speed (88.2 kHz or 96 kHz), active high
DEM_SEL1 36 I De-emphasis select bit 2, 10 = 48 kHz, 11= undefined (none)
DEM_SEL2 35 I De-emphasis select bit 1 (0 = none, 01 = 32 kHz, 10 = 44.1 kHz
DVDD 32 P Digital power supply
DVDD_PWM 57 P Digital power supply for PWM
DVDD_RCL 59 P Digital power supply for reclocker
DVSS 33, 76 P Digital ground for digital core and most of I/O buffers
DVSS1 10, 38, 39 I/O Digital ground for digital core and most of I/O buffers
DVSS_PWM 56 P Digital ground for PWM
DVSS_RCL 58 P Digital ground for reclocker
ERR_RCVRY 13 I Error recovery input, active low
LRCLK 31 I/O Serial audio data left / right clock (sampling rate clock) (input when M_S = 0; output when
M_S 37 I Master/slave mode input signal (master = 1, slave = 0)
MCLK_IN 3 I MCLK input, slave mode (or master / double-speed mode)
MCLK_OUT 29 O MCLK output buffered system clock output if M_S = 1; otherwise set to 0
MUTE 14 I Mute input signal, active low (muted signal = 0, normal mode = 1)
N/C 1, 2, 8, 11,
PDN 15 I Power down, active low
PLL_FLT_OUT 5 O PLL external filter
†
I = input; O = output; I/O = input/output; P = power
19−23, 40
— Not connected
M_S = 1)
4
SLES090A—November 2003—Revised January 2004TAS5076
TERMINAL
FUNCTION
†
DESCRIPTION
NAME NO.
PLL_FLT_RET 6 O PLL external filter (internally connected to AVSS_PLL)
PWM_AM_1 74 O PWM 1 output (differential -); {positive H-bridge side}
PWM_AM_2 69 O PWM 2 output (differential -); {positive H-bridge side}
PWM_AM_3 64 O PWM 3 output (differential -); {positive H-bridge side}
PWM_AM_4 54 O PWM 4 output (differential -); {positive H-bridge side}
PWM_AM_5 49 O PWM 5 output (differential -); {positive H-bridge side}
PWM_AM_6 44 O PWM 6 output (differential -); {positive H-bridge side}
PWM_AP_1 75 O PWM 1 output (differential +); {positive H-bridge side}
PWM_AP_2 70 O PWM 2 output (differential +); {positive H-bridge side}
PWM_AP_3 65 O PWM 3 output (differential +); {positive H-bridge side}
PWM_AP_4 55 O PWM 4 output (differential +); {positive H-bridge side}
PWM_AP_5 50 O PWM 5 output (differential +); {positive H-bridge side}
PWM_AP_6 45 O PWM 6 output (differential +); {positive H-bridge side}
PWM_BM_1 72 O PWM 1 output (differential -); {negative H-bridge side}
PWM_BM_2 67 O PWM 2 output (differential -); {negative H-bridge side}
PWM_BM_3 62 O PWM 3 output (differential -); {negative H-bridge side}
PWM_BM_4 52 O PWM 4 output (differential -); {negative H-bridge side}
PWM_BM_5 47 O PWM 5 output (differential -); {negative H-bridge side}
PWM_BM_6 42 O PWM 6 output (differential -); {negative H-bridge side}
PWM_BP_1 71 O PWM 1 output (differential +); {negative H-bridge side}
PWM_BP_2 66 O PWM 2 output (differential +); {negative H-bridge side}
PWM_BP_3 61 O PWM 3 output (differential +); {negative H-bridge side}
PWM_BP_4 51 O PWM 4 output (differential +); {negative H-bridge side}
PWM_BP_5 46 O PWM 5 output (differential +); {negative H-bridge side}
PWM_BP_6 41 O PWM 6 output (differential +); {negative H-bridge side}
RESET 12 I System reset input, active low
SCL 17 I I2C serial control clock input
SCLK 30 I/O Serial audio data clock (shift clock)
SDA 16 I/O I2C serial control data input/ output
SDIN1 26 I Serial audio data 1 input
SDIN2 27 I Serial audio data 2 input
SDIN3 28 I Serial audio data 3 input
VALID_1 73 O Output indicating validity of PWM outputs, channel 1, active high
VALID_2 68 O Output indicating validity of PWM outputs, channel 2, active high
VALID_3 63 O Output indicating validity of PWM outputs, channel 3, active high
VALID_4 53 O Output indicating validity of PWM outputs, channel 4, active high
VALID_5 48 O Output indicating validity of PWM outputs, channel 5, active high
VALID_6 43 O Output indicating validity of PWM outputs, channel 6, active high
VREGA_CAP 9 P Voltage regulator capacitor
VREGB_CAP 60 P Voltage regulator capacitor
VREGC_CAP 34 P Voltage regulator capacitor
XTL_IN 79 I Crystal or TTL level clock input
XTL_OUT 78 O Crystal output (not for external usage)
Introduction
†
I = input; O = output; I/O = input/output; P = power
SLES090A—November 2003—Revised January 2004 TAS5076
5
Introduction
6
SLES090A—November 2003—Revised January 2004TAS5076
2 Architecture Overview
The TAS5076 is composed of six functional elements:
• Clock, PLL, and serial data interface (I
• Reset/power-down circuitry
• Serial control interface (I2C)
• Signal processing unit
• Pulse-width modulator (PWM)
• Power supply
2.1 Clock and Serial Data Interface
The TAS5076 clock and serial data interface contain an input serial data slave and the clock master/slave
interface. The serial data slave interface receives information from a digital source such as a DSP, S/PDIF
receiver, analog-to-digital converter (ADC), digital audio processor (DAP), or other serial bus master. The
serial data interface has three serial data inputs that can accept up to six channels of data at data sample rates
of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, or 192 kHz. The serial data interfaces support left
justified and right justified for 16, 20, and 24 bits. In addition, the serial data interface supports the DSP protocol
for 16 bits and the I
The TAS5076 can function as a receiver or a generator for the MCLK_IN (master clock), SCLK (shift clock),
and LRCLK (left/right clock) signals that control the flow of data on the three serial data interfaces. The
T AS5076 i s a c l o c k m a s t e r when it generates these clocks and is a clock slave when it receives these clocks.
The TAS5076 is a synchronous design that relies upon the master clock to provide a reference clock for all
of the device operations and communication via the I2C. When operating as a slave, this reference clock is
MCLK_IN. When operating as a master , the reference clock is either a TTL clock input t o X TAL_IN or a crystal
attached across XTAL_IN and XTAL_OUT.
2
S protocol for 24 bits.
Architecture Overview
2
S)
The clock and serial data interface has two control parameters: data sample rate and clock master or slave.
2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection
The data sample rate is selected through a terminal (DBSPD) or the serial control register 0 (0x02). The data
sample rate control sets the frequencies of the SCLK and LRCLK in clock slave mode and the output
frequencies of SCLK and LRCLK in clock master mode. There are three data rates: normal speed, double
speed, and quad speed.
Normal-speed mode supports data rates of 32 kHz, 44.1 kHz, and 48 kHz. Normal speed is supported in the
master and slave modes. Double-speed mode is used to support sampling rates of 88.2 kHz and 96 kHz.
Double speed is supported in master and slave modes. Quad-speed mode is used to support sampling rates
of 176.4 kHz and 192 kHz.
The PWM is placed in normal speed by setting the DBSPD terminal low or by setting the normal mode bits
in the system control register 0 (0x02) through the serial control interface. The PWM is placed in double speed
mode by setting the DBSPD terminal high or by setting the double speed bits in the system control register.
Quad-speed mode is supported; in slave mode it is auto-detected, and in master mode it is invoked using the
2
I
C serial control interface. In slave mode, if the TAS5076 is not in double speed mode, quad-speed mode
is automatically detected when MCLK_IN is 128 Fs. In master mode, the PWM is placed in quad-speed mode
by setting the quad-speed bit in the system control register through the serial control interface.
If the master clock is well behaved during the frequency transition (the high or low clock periods are not less
than 20 ns), then a simple speed selection is performed by setting the DBSPD terminal or the serial control
register.
When the sample rate is changed, the T AS5076 temporarily suspends processing, places the PWM outputs
in a hard mute (PWM P outputs low, PWM M outputs high, and all VALID signals low), resets all internal
processes, and suspends all I
noiselessly restarts the PWM output. The TAS5076 preserves all control register settings throughout this
sequence. If desired, the sample rate change can be performed while mute is active to provide a completely
silent transition. The timing of this control sequence is shown in Section 4.
2
C operations. The TAS5076 then performs a partial re-initialization and
SLES090A—November 2003—Revised January 2004 TAS5076
7
Architecture Overview
If the master clock input can encounter high clock or low clock period of less than 20 ns while the data rates
are changing, then RESET
must be applied during this time. There are two recommended control procedures
for this case, depending upon whether the DBSPD terminal or the serial control interface is used. These
control sequences are shown in Section 4.
Table 2−1. Normal-Speed, Double-Speed, and Quad-Speed Operation
QUAD-SPEED CONTROL
REGISTER BIT
0 0 Master or slave Normal speed
0 1 Master or slave Double speed
1 0 Master or slave Quad speed
0 0 Slave Quad speed if MCLK_IN = 128Fs
1 1 Master or slave Error
DBSPD TERMINAL OR
CONTROL REGISTER BIT
2.1.2 Clock Master/Slave Mode (M_S)
Clock master and slave mode can be invoked using the M_S (master slave) terminal.
This terminal specifies the default mode that is set immediately following a device RESET. The serial data
interface setting permits the clock generation mode to be changed during normal operation.
MODE SPEED SELECTION
The transition to master mode occurs following a RESET
The transition to slave mode occurs following a RESET
2.1.3 Clock Master Mode
When M_S = 1 following a RESET, the TAS5076 provides the master clock, SCLK, and LRCLK to the rest of
the system. In the master mode, the TAS5076 outputs the audio system clocks MCLK_OUT, SCLK, and
LRCLK.
The TAS5076 device generates these clocks plus its internal clocks from the internal phase-locked loop (PLL).
The reference clock for the PLL can be provided by either an external clock source (attached to XTAL_IN) or
a crystal (connected across terminals XTAL_IN and XTAL_OUT). The external source attached to MCLK_IN
is 256 times (128 in quad mode) the data sample rate (Fs). The SCLK frequency is 64 times the data sample
rate and the SCLK frequency of 48 times the data sample rate is not supported in the master mode. The LRCLK
frequency is the data sample rate.
when M_S terminal has a logic high applied.
when M_S terminal has a logic low applied.
8
SLES090A—November 2003—Revised January 2004TAS5076
2.1.3.1 Crystal Type and Circuit
In clock master mode the TAS5076 can derive the MCLKOUT, SCLK, and LRCLK from a crystal. In this case,
the TAS5076 uses a parallel-mode fundamental crystal. This crystal is connected to the TAS5076 as shown
in Figure 2−1.
Architecture Overview
TAS5076
rd = Drive Level Control Resistor − Crystal Vendor Specified
CL = Crystal Load Capacitance (Capacitance of Circuitry Between the Two Terminals of the Crystal)
CL = (C1 × C2 )/(C1 + C2 ) + CS (Where CS = Board Stray Capacitance ≈ 3 pF)
Example: Vendor-Recommended CL = 18 pF, CS = 3 pF ≥ C1 = C2 = 2 × (18−3) = 30 pF
2.1.4 Clock Slave Mode
In the slave mode (M_S = 0), the master clock, LRCLK, and SCLK are inputs to the TAS5076. The master clock
is supplied through the MCLK_IN terminal.
As in the master mode, the TAS5076 device develops its internal timing from the internal phase-locked loop
(PLL). The reference clock for the PLL is provided by the input to the MCLK_IN terminal. This input is at a
frequency of 256 times (128 in quad mode) the input data rate. The SCLK frequency is 48 or 64 times the data
sample rate. The LRCLK frequency is the data sample rate. The TAS5076 does not require any specific phase
relationship between SRCLK and MCLK_IN, but there must be synchronization. The TAS5076 monitors the
relationship between MCLK, SCLK, and LRCLK. The TAS5076 detects if any of the three clocks is absent,
if the LRCLK rate changes more than 10 MCLK cycles since the last device reset or clock error, or if the MCLK
frequency is changing substantially with respect to the PLL frequency.
C
1
C
2
r
d
OSC
MACRO
XO
XI
AVSS
Figure 2−1. Crystal Circuit
When a clock error is detected, the TAS5076 performs a clock error management sequence.
The clock error management sequence temporarily suspends processing, places the PWM outputs in a hard
mute (PWM_P outputs are low, PWM_M outputs are high, and all VALID signals are low), resets all internal
processes, sets the volumes to mute, and suspends all I
2
C operations.
When the error condition is corrected, the TAS5076 exits the clock error sequence by performing a partial
re-initialization, noiselessly restarting the PWM output, and ramping the volume up to the level specified in
the volume control registers. This sequence is performed over a 60-ms interval. The TAS5076 preserves all
control register settings that were set prior to the clock interruption.
If a clock error occurs while the ERR_RCVRY
terminal is asserted (low), the TAS5076 performs the error
management sequence up to the unmute sequence. In this case, the volume remains at full attenuation with
the PWM output at a 50% duty cycle. The volume can be restored from this latched mute state by triggering
a mute/unmute sequence by asserting and releasing MUTE
either by using the terminal, the system control
register 0x01 D4, or the individual channel mute register D5−D0.
SLES090A—November 2003—Revised January 2004 TAS5076
9
Architecture Overview
Alternatively , t h e TAS 50 76 ca n be pre vented from entering the latched mute state following a clock error when
the ERR_RCVRY
terminal or the error recovery I2C command (register 0x03 bit D2) is active by writing 0x7F
to the individual error recovery register (0x04) and 0x84 to the feature enable register (0x1F).
Table 2−2. Master and Slave Clock Modes
DESCRIPTION M_S DBSPD
Internal PLL, master, normal speed 1 0 8.192 – 2.048 32 8.192
Internal PLL, master, normal speed 1 0 11.2896 – 2.8224 44.1 11.2896
Internal PLL, master, normal speed 1 0 12.288 – 3.072 48 12.288
Internal PLL, master, double speed 1 1 – 22.5792
Internal PLL, master, double speed 1 1 – 24.576
Internal PLL, master, quad speed 1 0 – 22.5792 11.2896 176.4 22.5792
Internal PLL, master, quad speed 1 0 – 24.576 12.288 192 24.576
Internal PLL, slave, normal speed 0 0 – 8.192
Internal PLL, slave, normal speed 0 0 – 11.2896
Internal PLL, slave, normal speed 0 0 – 12.288
Internal PLL, slave, double speed 0 1 – 22.5792 5.6448 88.2 Digital GND
Internal PLL, slave, double speed 0 1 – 24.576
Internal PLL, slave, quad speed
Internal PLL, slave, quad speed
†
A crystal oscillator is connected to XTL_IN.
‡
MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN_IN is provided.
§
External MCLK_IN connected to MCLK_IN_IN input
¶
SCLK and LRCLK are outputs when M_S = 1, and inputs when M_S = 0.
#
MCLK_OUT is driven low when M_S = 0.
||
Quad-speed mode is detected automatically.
||
||
0 0 – 22.5792
0 0 – 24.576
XTL_IN
(MHz)
k SCLK can be 48 or 64 times Fs
†
MCLK_IN
‡
(MHz)
§
SCLK
(MHz)
k
§
§
§
§
§
§
§
5.6448 88.2 22.5792
6.144 96 24.576
2.0484 32 Digital GND
2.8224 44.1 Digital GND
3.072 48 Digital GND
6.144 96 Digital GND
11.2896 176 Digital GND
12.288 192 Digital GND
LRCLK
(kHz)
¶
MCLK_OUT
(MHz)
#
Table 2−3. LRCLK and MCLK_IN Rates
NORMAL SPEED (kHz) DOUBLE SPEED (kHz) QUAD SPEED (kHz)
LRCLK 1 Fs 32 44.1 48 1 Fs 64 88.2 96 1 Fs 176.4 192
MCLK_IN 256 Fs 8,192 11,289.6 12,288 256 Fs 16,384 22,579.2 24,576 128 Fs 22,579.2 24,576
2.1.5 PLL External Filter
In the TAS5076, a low-jitter PLL produces the internal timing (when in master mode), the master clock, SCLK,
and LRCLK. Connections for the PLL external filter are provided through PLL_FL T_OUT and PLL_FLT_RET
as shown in Figure 2−2.
PLL_FLT_OUT
110 Ω
22 nF
TAS5076
220 nF
PLL_FLT_RET
10
Figure 2−2. PLL External Filter
SLES090A—November 2003—Revised January 2004TAS5076
2.1.6 DCLK
DCLK is the internal high-frequency clock that is produced by the PLL circuitry from MCLK. The TAS5076 uses
the DCLK to control all internal operations. DCLK is 8 times the speed of MCLK in normal speed mode, 4 times
MCLK in double speed, and 2 times MCLK in quad speed. With respect to the I
clock cycles are used to specify interchannel delay and to detect when the MCLK frequency is drifting.
Table 2−4 DCLK shows the relationship between sample rate, MCLK, and DCLK.
Table 2−4. DCLK
Architecture Overview
2
C addressable registers, DCLK
Fs
(kHz)
32 8.1920 65.5360 15.3
44.1 11.2896 90.3168 11.1
48 12.2880 98.3040 10.2
88 22.5280 90.1120 11.1
96 24.5760 98.3040 10.2
192 49.1520 98.3040 10.2
2.1.7 Serial Data Interface
The TAS5076 operates as a slave only/receive only serial data interface in all modes. The TAS5076 has three
PCM serial data interfaces to accept six channels of digital data though the SDIN1, SDIN2, SDIN3 inputs. The
serial audio data is in MSB-first, twos-complement format.
The serial data interfaces of the TAS5076 can be configured in right-justified, I
This interface supports 32-kHz, 44.1-kHz, 48-kHz, 88-kHz, 96-kHz, 176.4-kHz, and 192-kHz data sample
rates. The serial data interface format is specified using the data interface control register . The supported word
lengths are shown in Table 2−5.
During normal operating conditions if the serial data interface settings change state, an error recovery
sequence is initiated.
DATA MODES
Right justified, MSB first 16 0 0 0
Right justified, MSB first 20 0 0 1
Right justified, MSB first 24 0 1 0
Left justified, MSB first 24 1 1 0
DSP frame 16 1 1 1
MCLK
(MHz)
DCLK
(MHz)
DCLK Period
(ns)
2
S, left-justified, or DSP modes.
Table 2−5. Supported Word Lengths
WORD
LENGTHS
I2S 16 0 1 1
I2S 20 1 0 0
I2S 24 1 0 1
MOD2 MOD1 MOD0
2.1.7.1 I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel or the right channel.
LRCLK is low for the left channel and high for the right channel. A bit clock running at 48 or 64 times Fs is used
to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first
bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS5076 masks unused trailing data bit positions. Master mode only supports a 64 times Fs bit clock.
SLES090A—November 2003—Revised January 2004 TAS5076
11
Architecture Overview
2-Channel I2S (Philips Format) Stereo Input
32 Clks
32 Clks
LRCLK (Note Reversed Phase) Left Channel
SCLK
MSB LSB
24-Bit Mode
22
23
20-Bit Mode
19 18
16-Bit Mode
9 8 5 4 1 0
5 4 1 0
1 015 14
Figure 2−3. I2S 64-Fs Format
2-Channel I2S Stereo Input/Output (24-Bit Transfer Word Size)
24 Clks
LRCLK
Left Channel
Right Channel
SCLK
MSB LSB
23 22
19 18 5 4 1 0
9 8 5 4 1 0
1 015 14
24 Clks
Right Channel
SCLK
MSB LSB
24-Bit Mode
23
22
20-Bit Mode
19 18
16-Bit Mode
20 19 8 7 2 1
16 15 1 0
12
11
13
4
517
1 015 14
4 3521
Figure 2−4. I2S 48-Fs Format
2.1.7.2 Left-Justified Timing
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and the
right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 48 or 64
times Fs is used to clock in the data. The first bit of data appears on the data lines at the same time that LRCLK
toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5076 masks
unused trailing data bit positions. Master mode only supports a 64 times Fs bit clock.
SCLK
MSB LSB
23 22
0
19 18 16 15 1 0
20 19 8 7 2 1
4
517
12
11
1 015 14
13
4 3521
12
SLES090A—November 2003—Revised January 2004TAS5076
Architecture Overview
2-Channel Left-Justified Stereo Input
2-Channel Left-Justified Stereo Input/Output (24-Bit Transfer Word Size)
32 Clks
LRCLK
Left Channel
SCLK
MSB LSB
24-Bit Mode
23
22
NOTE: All data presented in 2s complement form with MSB first.
9 8 5 4 1 0
Figure 2−5. Left-Justified 64-Fs Format
24 Clks
LRCLK
Left Channel
32 Clks
LRCLK
Right Channel
MSB LSB
23 22
9 8 5 4 1 0
24 Clks
Right Channel
SCLK
MSB LSB
24-Bit Mode
22 21
19 9 8 1 0
3 242023 22 21
Figure 2−6. Left-Justified 48-Fs Format
2.1.7.3 Right-Justified Timing
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and
the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 48
or 64 times Fs is used to clock in the data. The first bit of data appears following the eighth bit-clock period
(for 24-bit data) after LRCLK toggles. In RJ mode, the last bit clock before LRCLK transitions always clocks
the LSB of data. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5076
masks unused leading data bit positions. Master mode only supports a 64 times Fs bit clock.
MSB LSB
19 9 8 1 0
5
3 2420235
SLES090A—November 2003—Revised January 2004 TAS5076
13
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