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The TAS5076 is an innovative, cost-effective, high-performance 24-bit six-channel digital pulse-width
modulator (PWM) based on Equibit technology. Combined with a TI PurePath Digital audio amplifier power
stage, these devices use noise-shaping and sophisticated error-correction algorithms to achieve high power
efficiency and high-performance digital audio reproduction. The TAS5076 is designed to drive up to six digital
power devices to provide six channels of digital audio amplification. The digital power devices can be six
conventional monolithic power stages (such as the TAS5110) or six discrete differential power stages using
gate drivers and MOSFETs.
The TAS5076 has six independent volume controls and mute. The device operates in AD and BD modes. This
all-digital audio system contains only two analog components in the signal chain—an LC low-pass filter at each
speaker terminal. Dynamic range of 105 dB for the front channels and 102 dB for the other channels is
achievable on the TAS5076-TAS5182 EVM using the specified ABD and interchannel delay settings. The
TAS5076 has a wide variety of serial input options including right justified (16-, 20-, or 24-bit), I
or 24-bit) left justified, and DSP (16-bit) data formats. The device is fully compatible with AES standard
sampling rates of 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz, including de-emphasis for
44.1-kHz and 48-kHz sample rates. The TAS5076 plus the TAS51xx power stage device combination was
designed for home theater applications such as DVD minicomponent systems, home theater in a box (HTIB),
DVD receiver, A/V receiver, or TV sets.
SLES090A—November 2003—Revised January 2004TAS5076
3
Introduction
FUNCTION
†
DESCRIPTION
1.4Ordering Information
TAS
5076PFC
Texas Instruments
Audio Solutions
Device Number
Package Type
AVAILABLE OPTIONS
PACKAGE
T
A
0°C to 70°CTAS5076PFC
PLASTIC 80-PIN TQFP
(PFC)
1.5Terminal Functions
TERMINAL
NAMENO.
AVDD_OSC80PAnalog power supply for internal oscillator cells
AVDD_PLL4PAnalog power supply for PLL
AVSS_OSC77OAnalog ground for internal oscillator cells
AVSS_PLL7PAnalog ground for PLL
CLIP25ODigital clipping indicator, active low
CS018II2C serial control chip address select input, active high
DBSPD24ISample rate is double speed (88.2 kHz or 96 kHz), active high
DEM_SEL136IDe-emphasis select bit 2, 10 = 48 kHz, 11= undefined (none)
DEM_SEL235IDe-emphasis select bit 1 (0 = none, 01 = 32 kHz, 10 = 44.1 kHz
DVDD32PDigital power supply
DVDD_PWM57PDigital power supply for PWM
DVDD_RCL59PDigital power supply for reclocker
DVSS33, 76PDigital ground for digital core and most of I/O buffers
DVSS110, 38, 39I/ODigital ground for digital core and most of I/O buffers
DVSS_PWM56PDigital ground for PWM
DVSS_RCL58PDigital ground for reclocker
ERR_RCVRY13IError recovery input, active low
LRCLK31I/OSerial audio data left / right clock (sampling rate clock) (input when M_S = 0; output when
M_S37IMaster/slave mode input signal (master = 1, slave = 0)
MCLK_IN3IMCLK input, slave mode (or master / double-speed mode)
MCLK_OUT29OMCLK output buffered system clock output if M_S = 1; otherwise set to 0
MUTE14IMute input signal, active low (muted signal = 0, normal mode = 1)
N/C1, 2, 8, 11,
PDN15IPower down, active low
PLL_FLT_OUT5OPLL external filter
†
I = input; O = output; I/O = input/output; P = power
19−23, 40
—Not connected
M_S = 1)
4
SLES090A—November 2003—Revised January 2004TAS5076
I = input; O = output; I/O = input/output; P = power
SLES090A—November 2003—Revised January 2004TAS5076
5
Introduction
6
SLES090A—November 2003—Revised January 2004TAS5076
2Architecture Overview
The TAS5076 is composed of six functional elements:
•Clock, PLL, and serial data interface (I
•Reset/power-down circuitry
•Serial control interface (I2C)
•Signal processing unit
•Pulse-width modulator (PWM)
•Power supply
2.1Clock and Serial Data Interface
The TAS5076 clock and serial data interface contain an input serial data slave and the clock master/slave
interface. The serial data slave interface receives information from a digital source such as a DSP, S/PDIF
receiver, analog-to-digital converter (ADC), digital audio processor (DAP), or other serial bus master. The
serial data interface has three serial data inputs that can accept up to six channels of data at data sample rates
of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, or 192 kHz. The serial data interfaces support left
justified and right justified for 16, 20, and 24 bits. In addition, the serial data interface supports the DSP protocol
for 16 bits and the I
The TAS5076 can function as a receiver or a generator for the MCLK_IN (master clock), SCLK (shift clock),
and LRCLK (left/right clock) signals that control the flow of data on the three serial data interfaces. The
T AS5076 i s a c l o c k m a s t e r when it generates these clocks and is a clock slave when it receives these clocks.
The TAS5076 is a synchronous design that relies upon the master clock to provide a reference clock for all
of the device operations and communication via the I2C. When operating as a slave, this reference clock is
MCLK_IN. When operating as a master , the reference clock is either a TTL clock input t o X TAL_IN or a crystal
attached across XTAL_IN and XTAL_OUT.
2
S protocol for 24 bits.
Architecture Overview
2
S)
The clock and serial data interface has two control parameters: data sample rate and clock master or slave.
2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection
The data sample rate is selected through a terminal (DBSPD) or the serial control register 0 (0x02). The data
sample rate control sets the frequencies of the SCLK and LRCLK in clock slave mode and the output
frequencies of SCLK and LRCLK in clock master mode. There are three data rates: normal speed, double
speed, and quad speed.
Normal-speed mode supports data rates of 32 kHz, 44.1 kHz, and 48 kHz. Normal speed is supported in the
master and slave modes. Double-speed mode is used to support sampling rates of 88.2 kHz and 96 kHz.
Double speed is supported in master and slave modes. Quad-speed mode is used to support sampling rates
of 176.4 kHz and 192 kHz.
The PWM is placed in normal speed by setting the DBSPD terminal low or by setting the normal mode bits
in the system control register 0 (0x02) through the serial control interface. The PWM is placed in double speed
mode by setting the DBSPD terminal high or by setting the double speed bits in the system control register.
Quad-speed mode is supported; in slave mode it is auto-detected, and in master mode it is invoked using the
2
I
C serial control interface. In slave mode, if the TAS5076 is not in double speed mode, quad-speed mode
is automatically detected when MCLK_IN is 128 Fs. In master mode, the PWM is placed in quad-speed mode
by setting the quad-speed bit in the system control register through the serial control interface.
If the master clock is well behaved during the frequency transition (the high or low clock periods are not less
than 20 ns), then a simple speed selection is performed by setting the DBSPD terminal or the serial control
register.
When the sample rate is changed, the T AS5076 temporarily suspends processing, places the PWM outputs
in a hard mute (PWM P outputs low, PWM M outputs high, and all VALID signals low), resets all internal
processes, and suspends all I
noiselessly restarts the PWM output. The TAS5076 preserves all control register settings throughout this
sequence. If desired, the sample rate change can be performed while mute is active to provide a completely
silent transition. The timing of this control sequence is shown in Section 4.
2
C operations. The TAS5076 then performs a partial re-initialization and
SLES090A—November 2003—Revised January 2004TAS5076
7
Architecture Overview
If the master clock input can encounter high clock or low clock period of less than 20 ns while the data rates
are changing, then RESET
must be applied during this time. There are two recommended control procedures
for this case, depending upon whether the DBSPD terminal or the serial control interface is used. These
control sequences are shown in Section 4.
Table 2−1. Normal-Speed, Double-Speed, and Quad-Speed Operation
QUAD-SPEED CONTROL
REGISTER BIT
00Master or slaveNormal speed
01Master or slaveDouble speed
10Master or slaveQuad speed
00SlaveQuad speed if MCLK_IN = 128Fs
11Master or slaveError
DBSPD TERMINAL OR
CONTROL REGISTER BIT
2.1.2 Clock Master/Slave Mode (M_S)
Clock master and slave mode can be invoked using the M_S (master slave) terminal.
This terminal specifies the default mode that is set immediately following a device RESET. The serial data
interface setting permits the clock generation mode to be changed during normal operation.
MODESPEED SELECTION
The transition to master mode occurs following a RESET
The transition to slave mode occurs following a RESET
2.1.3 Clock Master Mode
When M_S = 1 following a RESET, the TAS5076 provides the master clock, SCLK, and LRCLK to the rest of
the system. In the master mode, the TAS5076 outputs the audio system clocks MCLK_OUT, SCLK, and
LRCLK.
The TAS5076 device generates these clocks plus its internal clocks from the internal phase-locked loop (PLL).
The reference clock for the PLL can be provided by either an external clock source (attached to XTAL_IN) or
a crystal (connected across terminals XTAL_IN and XTAL_OUT). The external source attached to MCLK_IN
is 256 times (128 in quad mode) the data sample rate (Fs). The SCLK frequency is 64 times the data sample
rate and the SCLK frequency of 48 times the data sample rate is not supported in the master mode. The LRCLK
frequency is the data sample rate.
when M_S terminal has a logic high applied.
when M_S terminal has a logic low applied.
8
SLES090A—November 2003—Revised January 2004TAS5076
2.1.3.1Crystal Type and Circuit
In clock master mode the TAS5076 can derive the MCLKOUT, SCLK, and LRCLK from a crystal. In this case,
the TAS5076 uses a parallel-mode fundamental crystal. This crystal is connected to the TAS5076 as shown
in Figure 2−1.
Architecture Overview
TAS5076
rd = Drive Level Control Resistor − Crystal Vendor Specified
CL = Crystal Load Capacitance (Capacitance of Circuitry Between the Two Terminals of the Crystal)
CL = (C1 × C2 )/(C1 + C2 ) + CS (Where CS = Board Stray Capacitance ≈ 3 pF)
Example: Vendor-Recommended CL = 18 pF, CS = 3 pF ≥ C1 = C2 = 2 × (18−3) = 30 pF
2.1.4 Clock Slave Mode
In the slave mode (M_S = 0), the master clock, LRCLK, and SCLK are inputs to the TAS5076. The master clock
is supplied through the MCLK_IN terminal.
As in the master mode, the TAS5076 device develops its internal timing from the internal phase-locked loop
(PLL). The reference clock for the PLL is provided by the input to the MCLK_IN terminal. This input is at a
frequency of 256 times (128 in quad mode) the input data rate. The SCLK frequency is 48 or 64 times the data
sample rate. The LRCLK frequency is the data sample rate. The TAS5076 does not require any specific phase
relationship between SRCLK and MCLK_IN, but there must be synchronization. The TAS5076 monitors the
relationship between MCLK, SCLK, and LRCLK. The TAS5076 detects if any of the three clocks is absent,
if the LRCLK rate changes more than 10 MCLK cycles since the last device reset or clock error, or if the MCLK
frequency is changing substantially with respect to the PLL frequency.
C
1
C
2
r
d
OSC
MACRO
XO
XI
AVSS
Figure 2−1. Crystal Circuit
When a clock error is detected, the TAS5076 performs a clock error management sequence.
The clock error management sequence temporarily suspends processing, places the PWM outputs in a hard
mute (PWM_P outputs are low, PWM_M outputs are high, and all VALID signals are low), resets all internal
processes, sets the volumes to mute, and suspends all I
2
C operations.
When the error condition is corrected, the TAS5076 exits the clock error sequence by performing a partial
re-initialization, noiselessly restarting the PWM output, and ramping the volume up to the level specified in
the volume control registers. This sequence is performed over a 60-ms interval. The TAS5076 preserves all
control register settings that were set prior to the clock interruption.
If a clock error occurs while the ERR_RCVRY
terminal is asserted (low), the TAS5076 performs the error
management sequence up to the unmute sequence. In this case, the volume remains at full attenuation with
the PWM output at a 50% duty cycle. The volume can be restored from this latched mute state by triggering
a mute/unmute sequence by asserting and releasing MUTE
either by using the terminal, the system control
register 0x01 D4, or the individual channel mute register D5−D0.
SLES090A—November 2003—Revised January 2004TAS5076
9
Architecture Overview
Alternatively , t h e TAS 50 76 ca n be pre vented from entering the latched mute state following a clock error when
the ERR_RCVRY
terminal or the error recovery I2C command (register 0x03 bit D2) is active by writing 0x7F
to the individual error recovery register (0x04) and 0x84 to the feature enable register (0x1F).
In the TAS5076, a low-jitter PLL produces the internal timing (when in master mode), the master clock, SCLK,
and LRCLK. Connections for the PLL external filter are provided through PLL_FL T_OUT and PLL_FLT_RET
as shown in Figure 2−2.
PLL_FLT_OUT
110 Ω
22 nF
TAS5076
220 nF
PLL_FLT_RET
10
Figure 2−2. PLL External Filter
SLES090A—November 2003—Revised January 2004TAS5076
2.1.6 DCLK
DCLK is the internal high-frequency clock that is produced by the PLL circuitry from MCLK. The TAS5076 uses
the DCLK to control all internal operations. DCLK is 8 times the speed of MCLK in normal speed mode, 4 times
MCLK in double speed, and 2 times MCLK in quad speed. With respect to the I
clock cycles are used to specify interchannel delay and to detect when the MCLK frequency is drifting.
Table 2−4 DCLK shows the relationship between sample rate, MCLK, and DCLK.
The TAS5076 operates as a slave only/receive only serial data interface in all modes. The TAS5076 has three
PCM serial data interfaces to accept six channels of digital data though the SDIN1, SDIN2, SDIN3 inputs. The
serial audio data is in MSB-first, twos-complement format.
The serial data interfaces of the TAS5076 can be configured in right-justified, I
This interface supports 32-kHz, 44.1-kHz, 48-kHz, 88-kHz, 96-kHz, 176.4-kHz, and 192-kHz data sample
rates. The serial data interface format is specified using the data interface control register . The supported word
lengths are shown in Table 2−5.
During normal operating conditions if the serial data interface settings change state, an error recovery
sequence is initiated.
DATA MODES
Right justified, MSB first16000
Right justified, MSB first20001
Right justified, MSB first24010
Left justified, MSB first24110
DSP frame16111
MCLK
(MHz)
DCLK
(MHz)
DCLK Period
(ns)
2
S, left-justified, or DSP modes.
Table 2−5. Supported Word Lengths
WORD
LENGTHS
I2S16011
I2S20100
I2S24101
MOD2MOD1MOD0
2.1.7.1I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel or the right channel.
LRCLK is low for the left channel and high for the right channel. A bit clock running at 48 or 64 times Fs is used
to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first
bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS5076 masks unused trailing data bit positions. Master mode only supports a 64 times Fs bit clock.
SLES090A—November 2003—Revised January 2004TAS5076
11
Architecture Overview
2-Channel I2S (Philips Format) Stereo Input
32 Clks
32 Clks
LRCLK (Note Reversed Phase)Left Channel
SCLK
MSBLSB
24-Bit Mode
22
23
20-Bit Mode
19 18
16-Bit Mode
985410
5410
1015 14
Figure 2−3. I2S 64-Fs Format
2-Channel I2S Stereo Input/Output (24-Bit Transfer Word Size)
24 Clks
LRCLK
Left Channel
Right Channel
SCLK
MSBLSB
23 22
19 185410
985410
1015 14
24 Clks
Right Channel
SCLK
MSBLSB
24-Bit Mode
23
22
20-Bit Mode
19 18
16-Bit Mode
20 198721
16 1510
12
11
13
4
517
1015 14
43521
Figure 2−4. I2S 48-Fs Format
2.1.7.2Left-Justified Timing
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and the
right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 48 or 64
times Fs is used to clock in the data. The first bit of data appears on the data lines at the same time that LRCLK
toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5076 masks
unused trailing data bit positions. Master mode only supports a 64 times Fs bit clock.
SCLK
MSBLSB
23 22
0
19 1816 1510
20 198721
4
517
12
11
1015 14
13
43521
12
SLES090A—November 2003—Revised January 2004TAS5076
Architecture Overview
2-Channel Left-Justified Stereo Input
2-Channel Left-Justified Stereo Input/Output (24-Bit Transfer Word Size)
32 Clks
LRCLK
Left Channel
SCLK
MSBLSB
24-Bit Mode
23
22
NOTE: All data presented in 2s complement form with MSB first.
985410
Figure 2−5. Left-Justified 64-Fs Format
24 Clks
LRCLK
Left Channel
32 Clks
LRCLK
Right Channel
MSBLSB
23 22
985410
24 Clks
Right Channel
SCLK
MSBLSB
24-Bit Mode
22 21
199810
324202322 21
Figure 2−6. Left-Justified 48-Fs Format
2.1.7.3Right-Justified Timing
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and
the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 48
or 64 times Fs is used to clock in the data. The first bit of data appears following the eighth bit-clock period
(for 24-bit data) after LRCLK toggles. In RJ mode, the last bit clock before LRCLK transitions always clocks
the LSB of data. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5076
masks unused leading data bit positions. Master mode only supports a 64 times Fs bit clock.
MSBLSB
199810
5
32420235
SLES090A—November 2003—Revised January 2004TAS5076
2-Channel Right-Justified Stereo Input/Output (24-Bit Transfer Word Size)
32 Clks
LRCLK
Left Channel
SCLK
MSBLSB
24-Bit Mode
23
22
20-Bit Mode
16-Bit Mode
NOTE: All data presented in 2s complement form with MSB first.
19 1815 1410
19 18
15 1410
1015 14
Figure 2−7. Right-Justified 64-Fs Format
32 Clks
Right Channel
MSBLSB
23 22
19 1815 1410
19 1815 1410
1015 14
24 Clks
LRCLK
Left Channel
SCLK
MSBLSB
24-Bit Mode
22 21
20-Bit Mode
16-Bit Mode
NOTE: All data presented in 2s complement form with MSB first.
1910
2023
18
1889
1910
15 1422 21
15 14
89
8915 14
10
Figure 2−8. Right-Justified 48-Fs Format
24 Clks
Right Channel
MSBLSB
1910
2023
18
1889
1910
15 14
15 14
89
8915 14
10
14
SLES090A—November 2003—Revised January 2004TAS5076
2.1.7.4DSP Mode Timing
DSP mode timing uses LRCLK to define when data is to be transmitted for both channels. A bit clock running
at 64 × Fs is used to clock in the data. The first bit of the left channel data appears on the data lines following
the LRCLK transition. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5076
masks unused trailing data bit positions.
SCLK
LRCLK
Architecture Overview
64 SCLKS
LSBMSB
SDIN
16 Bits
Left
Channel
Figure 2−9. DSP Format
2.2Reset, Power Down, and Status
The reset, power-down, and status circuitry provides the necessary controls to bring the TAS5076 to the initial
inactive condition, achieve low-power standby, and report system status.
2.2.1 Reset—RESET
The TAS5076 is placed in the reset mode by setting the RESET terminal low.
RESET
1−6 outputs low, and places the PWM in the hard mute state. Volume is immediately set to full attenuation
(there is no ramp down).
As long as the RESET
bus operations are ignored. Table 2−6 shows the device output signals while RESET
is an asynchronous control signal that restores the TAS5076 to its default conditions, sets the valid
terminal is held low, the device is in the reset state. During reset, all I2C and serial data
16 Bits
Right
Channel
LSBMSB
32 Bits Unused
is active.
Upon the release of RESET
, if POWER_DWN is high, the system performs a 4-ms to 5-ms device initialization
and then ramps the volume up to 0 db using a soft volume update sequence. If MCLK_IN is not active when
RESET
is released high, then a 4-ms to 5-ms initialization sequence is produced once MCLK_IN becomes
active.
During device initialization all controls are reset to their initial states. Table 2−7 shows the control settings that
are changed during initialization.
RESET
SLES090A—November 2003—Revised January 2004TAS5076
must be applied during power-up initialization or while changing the master slave clock states.
15
Architecture Overview
Because the RESET is an asynchronous control signal, small clicks and pops can be produced during the
application (the leading edge) of this control. However, when RESET
mute state back to normal operation is performed synchronously using a quiet sequence.
If a completely quiet reset sequence is desired, MUTE
CONTROLSETTING
Volume0 dB
MCLK_IN frequency 256
Master/slave modeM_S terminal state
AutomuteEnabled
De-emphasisNone
Dc offset0
Interchannel delayEach channel is set to default value
2.2.2 Power Down—PDN
The TAS5076 can be placed into the power-down mode by holding the PDN terminal low. When the
power-down mode is entered, both the PLL and the oscillator are shut down. V olume is immediately set to full
attenuation (there is no ramp down). The valid 1−6 outputs are immediately asserted low and the PWM outputs
are placed in the hard mute state. PDN
terminal is held low, the device is in the power-down (hard mute) state.
During power down, all I
signals while PDN
To place the device in total power-down mode, both RESET and power-down modes must be enabled. Prior
to bringing PDN
is active.
high, RESET must be brought low for a minimum of 50 ns.
must be applied before applying RESET.
Table 2−7. Values Set During Reset
initiates device power down without clock inputs. As long as the PDN
2
C and serial data bus operations are ignored. Table 2−8 shows the device output
SLES090A—November 2003—Revised January 2004TAS5076
Because PDN is an asynchronous control signal, small clicks and pops can be produced during the application
(the leading edge) of this control. However, when PDN
to normal operation is performed synchronously using a quiet sequence.
If a completely quiet reset sequence is desired, MUTE
2.2.3 General Status Register
The general status register is a read-only register. This register provides an indication when a volume update
is in progress or one of the channels is inactive. The device ID can be read using this register.
Volume update is in progress—Whenever a volume change is in progress due to a volume update
command or mute, this status bit is high.
Device identification code—The device identification code 0 0000 is displayed.
No internal errors (all valid signals are high)—When there are no internal errors in the TAS5076 and all
outputs are valid, this status bit is high.
One or more valid signals are inactive—If low, one or more channels of the TAS5076 are not outputting data.
The valid signals for those channels are inactive.
Inactive valid signals can be produced by one of these causes:
•One or more of the clock signals are in error.
•ERROR
•The automute has silenced one or more channels that are receiving 0 inputs.
•MUTE
•Volume control has been set to full attenuation.
If this signal is high, the TAS5076 is outputting data on all channels.
recover is active (low).
has been set.
Architecture Overview
is released, the transition from the hard mute state back
must be applied before applying PDN.
2.2.4 Error Status Register
The error status register indicates historical information on control signal changes and clock errors. This
register latches these indications when they occur. The indications are cleared by writing 00h to the register.
This register is intended as a diagnostic tool to be used only when the system is not operating correctly . This
is because the error status bits are set when the data rate, serial data interface format, or master/slave mode
is changed. As a result, this register indicates an error condition even though the system is operating normally.
This register must be used only while diagnosing transient error conditions.
Any clock error or control signal terminal change that occurs since the last time the error status register was
cleared is displayed. In using this register, the first step is to initialize the device and ve rify that all of the clock
signals are active. Then this register must be cleared by writing 00h. After this point, the register indicates any
errors or control signal changes.
This register indicates an error condition by a high for the following conditions:
•Fs error
•A control terminal change has occurred (M_S, DBLSPD).
•LRCLK error
•MCLK_IN count error
•DCLK phase error with respect to MCLK_IN
•MCLK_IN phase error with respect to DCLK
•PWM timing error
If all bits of the register are low, no errors have occurred and no control terminals changed.
There is no one-to-one correspondence of clock error indication to a system error condition. A particular
system error can be indicated by one or more error indications in this register. The system error conditions
and the reported errors are as follows:
There is no correct number of MCLKs per LRCLK:
•Fs error has occurred.
•LRCLK error
•MCLK_IN count error
SLES090A—November 2003—Revised January 2004TAS5076
17
Architecture Overview
LRCLK is absent:
•LRCLK error
MCLK is the wrong frequency, changing frequency, or absent:
•DCLK phase error with respect to MCLK
•MCLK phase error with respect to DCLK
•PWM timing error
SCLK is the wrong frequency or absent
•SCLK error
2.3Signal Processing
This section contains the signal processing functions that are contained in the TAS5076. The signal
processing is performed using a high-speed 24-bit signal processing architecture. The TAS5076 has the
following signal processing features:
•Individual channel soft volume with a range of 24 dB to −114 dB plus mute
•Soft mute
•Automute
•50-µs/15-µs de-emphasis filter supported in the sampling rates 32 kHz, 44.1 kHz, and 48 kHz
2.3.1 Volume Control
The gain of each output can be adjusted by a soft digital volume control for each channel. Volume adjustments
are performed using a soft gain update s-curve, which is approximated using a second-order filter fit. The curve
fit is performed over a transition interval between 41 ms and 65 ms.
The volume of each channel can be adjusted from mute to −114 dB to 24 dB in 0.5 dB steps. Because of the
numerical representation that is used to control the volume, at very low volume levels the step size increases
for gains of that are less than −96 dB. The default volume setting following power up or reset is 0 dB for all
channels. The step size adjustment is linear down to approximately −90 dB, see Figure 2−10.
STEP SIZE
vs
ATTENUATION (GAIN)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
Step Size − dB
2.0
1.5
1.0
0.5
0.0
−110 −100−90−80−70−60−50−40−30−20−1001020
Attenuation (Gain) − dB
Figure 2−10. Attenuation Curve
18
The volume control format for each channel is expressed in 8 bits. The volume for each channel is set by writing
8 bits via the serial control interface. The MSB bit is written first as in the bit position 0 (LSB position).
SLES090A—November 2003—Revised January 2004TAS5076
The volume for each channel can be set using a single- or multiple-address write operation to the volume
control register via the serial control interface. Changing the volume of all six channels requires that 6 registers
be updated.
To coordinate the volume adjustment of multiple channels simultaneously, the TAS5076 performs a delayed
volume update upon receiving a volume change command. Following the completion of the register volume
write operations, the TAS5076 waits for 5 ms for another volume command to be given. If no volume command
is issued in that period of time, the TAS5076 starts adjusting the volume of the channels that received volume
settings.
While a volume update is being performed, the system status register indicates that the update is in progress.
During the update, all subsequent volume control setting requests that are sent to the TAS5076 are received
and stored as a single next value for a subsequent update. If more than one volume setting request is sent,
only the last is retained.
2.3.2 Mute
Table 2−9. V olume Register
VOLUME REGISTER
D7D6D5D4D3D2D1D0
Vol
Bit 7
Vol
Bit 6
Vol
Bit 5
Vol
Bit 4
Vol
Bit 3
Vol
Bit 2
Vol
Bit 1
Architecture Overview
Vol
Bit 0
The application of mute ramps the volume from any setting to the noiseless hard-mute state. There are two
methods in which the TAS5076 can be placed into mute. The TAS5076 is placed in the noiseless mute when
the MUTE
terminal is asserted low for a minimum of 3 MCLK_IN cycles. Alternatively , the mute mode can be
initiated by setting the mute bit in the system control register through the serial control interface. The TAS5076
is held in mute state as long as the terminal is low or I
and exit sequences to and from the hard-mute state.
If an error recovery (described in the PWM section) occurs after a mute request has been received, the device
returns from error recovery with the channel volume set as specified by the mute command.
2.3.3 Automute
Automute is an automatic sequence that can be enabled or disabled via the serial control interface. The default
for this control is enabled. When enabled, the PWM automutes an individual channel when a channel receives
from 5 ms to 50 ms of consecutive zeros. This time interval can be selectable using the automute delay
register. The default interval is 5 ms. This duration is independent of the sample rate. The automute state is
exited when two consecutive samples of nonzero data are received. The TAS5076 exit from automute is
performed quickly and preserves all music information.
This mode uses the valid low to provide a low-noise floor while maintaining a short start-up time. Noise free
entry and exit is achieved by using the PWM quiet start and stop sequences.
2.3.4 Individual Channel Mute
Individual channel mute is invoked through the serial interface. Individual channel mute permits each channel
of the TAS5076 to be individually muted and unmuted. The operation that is performed is identical to the mute
operation; however, it is performed on a per-channel basis. A TAS5076 channel is held in the mute state as
long as the serial interface mute setting for that channel is set.
2
C mute setting is active. This command uses quiet entry
2.3.5 De-Emphasis Filter
For audio sources that have been pre-emphasized, a precision 50-µs/15-µs de-emphasis filter is provided to
support the sampling rates of 32 kHz, 44.1 kHz, and 48 kHz. See Figure 2−11 for a graph showing the
de-emphasis filtering characteristics. De-emphasis is set using two bits in the system control register.
SLES090A—November 2003—Revised January 2004TAS5076
19
Architecture Overview
Table 2−10. De-Emphasis Filter Characteristics
DEM_SEL2 (MSB)DEM_SEL1DESCRIPTION
00De-emphasis disabled
01De-emphasis enabled for Fs = 48 kHz
10De-emphasis enabled for Fs = 44.1 kHz
11De-emphasis enabled for Fs = 32 kHz
Following the change of state of the de-emphasis bits, the PWM outputs go into the soft mute state. After 128
LRCLK periods for initialization, the PWM outputs are driven to the normal (unmuted) mode.
0
−10
Response − dB
3.18 (50 µs)10.6 (15 µs)
Figure 2−11. De-Emphasis Filter Characteristics
2.4Pulse-Width Modulator (PWM)
De-Emphasis
f − Frequency − kHz
The TAS5076 contains six channels of high performance digital Equibit PWM modulators that are designed
to drive switching output stages (back ends) in both single-ended (SE) and H-bridge (bridge tied load)
configuration. The TAS5076 device uses noise shaping and sophisticated error correction algorithms to
achieve high power efficiency and high-performance digital audio reproduction.
The PWM provides six pseudodifferential outputs to drive six monolithic power stages (such as TAS5110) or
six discrete differential power stages using gate drivers (such as the TAS5182) and MOSFETs in single-ended
or bridged configurations. The TAS5076 also provides a high-performance differential output that can be used
to drive an external analog headphone amplifier.
2.4.1 Clipping Indicator
The clipping output is designed to indicate clipping. When any of the six PWM outputs exceeds the maximum
allowable amplitude, the clipping indicator is asserted. The clipping indicator is cleared every 10 ms.
2.4.2 Error Recovery
Error recovery is used to provide error management and to permit the PWM output to be reset while preserving
all intervolume, interchannel delay, dc offsets, and the other internal settings. Error recovery is initiated by
bringing the ERR_RCVRY
in control register 1. Error recovery is a level-sensitive signal.
The device also performs an error recovery automatically:
•When the speed configuration is changed to normal, double, or quad speed
•Following a change in the serial data bus interface configuration
When ERR_RCVRY
there are any pending speed configurations, these changes are then performed. When ERR_RCVRY
brought high, a delay of 4 ms to 5 ms is performed before the system starts the output re-initialization
sequence. After the initialization time, the TAS5076 begins normal operation. During error recovery, all
controls and device settings that were not updated are maintained in their current configurations.
is brought low, all valid signals go low, and the PWM_P and PWM_M outputs go low. If
terminal low for a minimum 5 MCLK_IN cycles or by setting the error recovery bit
is
20
To permit error recovery to be used to provide TAS5100 error management and recovery, the delay between
the start of (falling edge) error recovery and the falling edge of valid 1 though valid 6 is selectable. This delay
can be selected to be either 6 µs or 47 µs.
SLES090A—November 2003—Revised January 2004TAS5076
During error recovery all serial data bus operations are ignored. At the conclusion of the sequence, the error
recovery register bit is returned to the normal operation state. Table 2−11 shows the device output signal
states during error recovery.
The transitions are done using a quiet entrance and exit sequence to prevent pops and clicks.
2.4.3 Individual Channel Error Recovery
Individual channel error recovery is used to provide error management and to permit the PWM output to be
turned off. Error recovery is initiated by setting one or more of the six error recovery bits in the error recovery
register to low.
Architecture Overview
While the error recover bits are brought low , the valid signals go to the low state. When the error recovery bits
are brought high, a delay of 4 ms to 5 ms occurs before the channels are returned to normal operation.
The delay between the falling edge of the error recover bit and the falling edge of valid 1 though valid 6 is
selectable. This delay can be selected to be either 6 µs or 47 µs.
The TAS5076 controls the relative timing of the pseudo-differential drive control signals plus the valid signal
to minimize the production of system noise during error recovery operations. The transitions to valid low and
valid high are done using an almost quiet entrance and exit sequence to prevent pops and clicks.
2.4.4 PWM DC-Offset Correction
An 8-bit value can be programmed to each of the six PWM offset correction registers to correct for any offset
present in the output stages. The offset correction is divided into 256 intervals with a total offset correction of
±1.56% of full scale. The default value is zero correction represented by 00h. These values can be changed
at any time through the serial control interface.
2.4.5 Interchannel Delay
An 8-bit value can be programmed to each of the six PWM interchannel delay registers to add a delay per
channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK.
Each subsequent channel has a default value that is N DCLKs larger than the preceding channel. The default
interchannel delay for the first channel and the interchannel delay between subsequent channels are mask
programmable. The present values are 0 for the first channel with increments of 53 for each successive
channel.
These values can be updated upon power up through the serial control interface. This delay is generated in
the PWM block with the appropriate control signals generated in the CTL block.
These values can be changed at any time through the serial control interface.
The optimum value for interchannel delay depends on the final system. This value can be adjusted for better
performance with regard to dynamic range and THD. It is recommended that the following TC delay values
be set instead of the default value. These TC delay values in conjunction with the ABD delay value (see
discussion in Section 2.4.6) deliver the best performance in the TAS5076-5182 EVM board.
SLES090A—November 2003—Revised January 2004TAS5076
21
Architecture Overview
These values must be reprogrammed every time RESET is asserted. RESET causes default values to be
loaded.
2.4.6 ABD Delay
A 5-bit value is used to delay the A PWM signals with respect to B PWM signals. The value is the same for
all channels. It can be programmed from 0 to 31 DCLK clock cycles. The default ABD value is 20 DCLK clock
cycles (10100). This value is mask programmable.
This value can be changed at any time through the serial control interface.
The optimum value for ABD delay depends on the final system. This value can be adjusted for better
performance with regard to dynamic range and THD. It is recommended that the following ABD delay value
be set instead of the default value. The ABD delay value in conjunction with the TC delay values delivers the
best performance in the TAS5076−5182 EVM board.
This value must be reprogrammed every time RESET is asserted. RESET causes the default value to be
loaded.
NOTE:
The performance of a PurePath Digital amplifier system is optimized by setting the PWM
timing based upon the type of back-end device that is used and the layout. These values are
set during initialization using the I
2
C serial interface.
2.4.7 PWM/H-Bridge and Discrete H-Bridge Driver Interface
The TAS5076 provides six PWM outputs, which are designed to drive switching output stages (back-ends)
in both single-ended (SE) and H-bridge (bridge-tied load) configuration. The back ends can be monolithic
power stages (such as the T AS5110) or six discrete differential power stages using gate drivers (such as the
the TAS55182) and MOSFETs in single-ended or bridged configurations.
The TAS5110 device is optimized for bridge-tied load (BTL) configurations. These devices require a pure
differential PWM signal with a third signal (VALID) to control the MUTE state. In the MUTE state, the TAS5110
OUTA and OUTB are both low.
One Channel
of TAS5076
PWM_AP
PWM_AM
VALID
PWM_BP
PWM_BM
AP
AM
RESET
BP
BM
TAS5110
OUTA
OUTB
Speaker
Figure 2−12. PWM Outputs and H-Bridge Driven in BTL Configuration
PurePath Digital is a trademark of Texas Instruments.
22
SLES090A—November 2003—Revised January 2004TAS5076
2.5I2C Serial Control Interface
p
Architecture Overview
SDA
MCLK must be active for the TAS5076 to support I2C bus transactions. The T AS5076 has a bidirectional serial
control interface that is compatible with the I
2
C (Inter IC) bus protocol and supports both 100-kbps and
400-kbps data transfer rates for single- and multiple-byte write and read operations. This is a slave-only device
that does not support a multi-master bus environment or wait state insertion. The control interface is used to
program the registers of the device and to read device status.
The TAS5076 supports the standard-mode I
operation (400 kHz maximum). The TAS5076 performs all I
2
C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits
The I
2
C bus operation (100 kHz maximum) and the fast I2C bus
2
C operations without I2C wait cycles.
in a system. Data is transferred on the bus serially one bit at a time. The address and data are transferred in
byte (8 bit) format with the most significant bit (MSB) transferred first. In addition, each byte transferred on the
bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with
the master device driving a start condition on the bus and ends with the master device driving a stop condition
on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and
stop conditions. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop.
Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in
Figure 2−13. The master generates the 7-bit slave address and the read/write (R/W
) bit to open
communication with another device and then waits for an acknowledge condition. The TAS5076 holds SDA
low during acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits
the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W
All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An I
bit (1 byte).
2
external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus.
7 Bit Slave Address
R/
8 Bit Register Address (N)A
W
8 Bit Register Data For
A
Address (N)
8 Bit Register Data For
AA
Address (N)
C
SCL
7 6 5 4 3 2 1 07 6 5 4 3 2 1 0
StartSto
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Figure 2−13. Typical I2C Sequence
There are no limits on the number of bytes that can be transmitted between start and stop conditions. When
the last word transfers, the master generates a stop condition to release the bus. A generic data transfer
sequence is also shown in Figure 2−13.
The 7-bit address for the TAS5076 is 001101X, where X is a programmable address bit. Using the CS0
terminal on the device, the LSB address bit is programmable to permit two devices to be used in a system.
These two addresses are licensed I
To communicate with the TAS5076, the I
2
C addresses and do not conflict with other licensed I2C audio devices.
2
C master uses 001 1010 if CS0 = 0 and 0011011 if CS0 = 1. In addition
to the 7-bit device address, an 8-bit register address is used to direct communication to the proper register
location within the device interface.
Read and write operations to the TAS5076 can be done using single-byte or multiple-byte data transfers.
SLES090A—November 2003—Revised January 2004TAS5076
23
Architecture Overview
2.5.1 Single-Byte Write
As shown in Figure 2−14, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I
of the data transfer. For a write data transfer, the read/write bit is 0. After receiving the correct I
address and the read/write bit, the TAS5076 device responds with an acknowledge bit. Next, the master
transmits the address byte or bytes corresponding to the TAS5076 internal memory address being accessed.
After receiving the address byte, the TAS5076 again responds with an acknowledge bit. Next, the master
device transmits the data byte to be written to the memory address being accessed. After receiving the data
byte, the TAS5076 again responds with an acknowledge bit. Finally, the master device transmits a stop
condition to complete the single-byte data write transfer.
Start
Condition
A6 A5 A4 A3 A2 A1 A0
I2C Device Address and
Read/Write Bit
2.5.2 Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to TAS5076 as shown in Figure 2−15. After receiving each data byte,
the TAS5076 responds with an acknowledge bit.
Start
Condition
AcknowledgeAcknowledgeAcknowledge
2
C device address and the read/write bit. The read/write bit determines the direction
As shown in Figure 2−16, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I
by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory
address to be read. As a result, the read/write bit is 0. After receiving the TAS5076 address and the read/write
bit, the TAS5076 responds with an acknowledge bit. Also, after sending the internal memory address byte or
bytes, the master device transmits another start condition followed by the TAS5076 address and the read/write
bit again. This time the read/write bit is a 1 indicating a read transfer. After receiving the TAS5076 and the
read/write bit, the TAS5076 again responds with an acknowledge bit. Next, the TAS5076 transmits the data
byte from the memory address being read. After receiving the data byte, the master device transmits a not
acknowledge followed by a stop condition to complete the single-byte data read transfer.
Start
Condition
A6 A5A0 R/W ACK A7 A6 A5 A4A0 ACKA6 A5A0ACK
I2C Device Address and
Read/Write Bit
AcknowledgeAcknowledgeAcknowledge
ACK A7A5A1 A0 ACK D7 D6D1 D0 ACK
A4 A3A6
Register AddressLast Data Byte
First Data Byte
D7 D6D1 D0 ACK
Other
Data Bytes
Figure 2−15. Multiple-Byte Write Transfer
2
C device address and the read/write bit. For the data read transfer, a write followed
Repeat Start Condition
R/WA1A1
Register AddressData Byte
I2C Device Address and
Read/Write Bit
D7 D6D1 D0 ACK
Not
Acknowledge
Condition
Stop
Condition
Stop
24
Figure 2−16. Single-Byte Read
SLES090A—November 2003—Revised January 2004TAS5076
2.5.4 Multiple-Byte Read
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TAS5076 to the master device as shown in Figure 2−17. Except for the last data byte,
the master device responds with an acknowledge bit after receiving each data byte.
Architecture Overview
Start
Condition
I2C Device Address and
Read/Write Bit
Repeat Start Condition
AcknowledgeAcknowledgeAcknowledge
A7 A6 A5
Register AddressOther
A6A0ACK
I2C Device Address and
Read/Write Bit
Acknowledge
R/WA6A0 R/W ACKA4A0 ACKD7D0 ACK
First Data Byte
Data Bytes
Figure 2−17. Multiple-Byte Read
Not
Acknowledge
D7 D6D1 D0 ACK
Last Data Byte
Stop
Condition
SLES090A—November 2003—Revised January 2004TAS5076
25
Architecture Overview
26
SLES090A—November 2003—Revised January 2004TAS5076
3Serial Control Interface Register Definitions
Table 3−1 shows the register map for the TAS5076. Default values in this section are in bold.
2
T able 3−1. I
ADDR HEXDESCRIPTION
00General status register
01Error status register
02System control register 0
03System control register 1
04Error recovery register
05Automute delay
06Dc-offset control register channel 1
07Dc-offset control register channel 2
08Dc-offset control register channel 3
09Dc-offset control register channel 4
0ADc-offset control register channel 5
0BDc-offset control register channel 6
0CInterchannel delay register channel 1
0DInterchannel delay register channel 2
0EInterchannel delay register channel 3
0FInterchannel delay register channel 4
10Interchannel delay register channel 5
11Interchannel delay register channel 6
12ABD delay register
13Volume control register channel 1
14Volume control register channel 2
15Volume control register channel 3
16Volume control register channel 4
17Volume control register channel 5
18Volume control register channel 6
19Individual channel mute
C Register Map
Serial Control Interface Register Definitions
The volume table is contained in Appendix A.
Default values are shown in bold in the following tables.
3.1General Status Register (0x00)
Table 3−2. General Status Register (Read Only)
D7D6D5D4D3D2D1D0FUNCTION
0−−−−−−−No volume update is in progress.
1−−−−−−−Volume update is in progress.
−0−−−−−−Always 0
−−00000−Device identification code
−−−−−−−0Any valid signal is inactive (see status register, 0x03) (see Note 1).
−−−−−−−1No internal errors (all valid signals are high)
NOTE 1: This bit is reset automatically when one or more channels are active.
SLES090A—November 2003—Revised January 2004TAS5076
27
Serial Control Interface Register Definitions
3.2Error Status Register (0x01)
Table 3−3. Error Status Register
D7D6D5D4D3D2D1D0FUNCTION
1−−−−−−−FS error has occurred
−1−−−−−−Control pin change has occurred
−−−1−−−−LRCLK error
−−−−1−−−MCLK_IN count error
−−−−−1−−DCLK phase error with respect to MCLK_IN
−−−−−−1−MCLK_IN phase error with respect to DCLK
−−−−−−−1PWM timing error
00000000No errors—no control pins changed (see Note 1)
NOTE 1: Write 00h to clear error indications in error status register.
3.3System Control Register 0 (0x02)
Table 3−4. System Control Register 0
D7D6D5D4D3D2D1D0FUNCTION
00−−−−−−Normal mode (in slave mode—quad speed detected if MCLK_IN = 128 Fs)
11−−−−−−Set to 11 under default conditions and when 0x00 is written into 0x1F
0−−−−−−−If 0x84 is written into register 0x1F –
Enable volume ramp up after an error recovery sequence is initiated by the
ERR_RCVRY
1−−−−−−−If 0x84 is written into register 0x1F –
Disable volume ramp up after an error recovery sequence is initiated by the
ERR_RCVRY
−0−−−−−−If 0x84 is written into register 0x1F –
Enable volume ramp up after error recovery sequence is initiated by register bits
D5 – D0 of this register
−1−−−−−−If 0x84 is written into register 0x1F –
Enable volume ramp up after error recovery sequence is initiated by register bits
D5 – D0 of this register
−−0−−−−−Put channel 6 into error recovery mode
−−−0−−−−Put channel 5 into error recovery mode
−−−−0−−−Put channel 4 into error recovery mode
−−−−−0−−Put channel 3 into error recovery mode
−−−−−−0−Put channel 2 into error recovery mode
−−−−−−−0Put channel 1 into error recovery mode
−−111111Normal operation
terminal or the I2C error recovery command (register 0x03 bit D2)
terminal or the I2C error recovery command (register 0x03 bit D2)
SLES090A—November 2003—Revised January 2004TAS5076
29
Serial Control Interface Register Definitions
3.6Automute Delay Register (0x05)
Table 3−7. Automute Delay Register
D7D6D5D4D3D2D1D0FUNCTION
0000−−−−Unused
−−−−0000Set automute delay at 5 ms
−−−−0001Set automute delay at 10 ms
−−−−0010Set automute delay at 15 ms
−−−−0011Set automute delay at 20 ms
−−−−0100Set automute delay at 25 ms
−−−−0101Set automute delay at 30 ms
−−−−0110Set automute delay at 35 ms
−−−−0111Set automute delay at 40 ms
−−−−1−−0Set automute delay at 45 ms
−−−−1−−1Set automute delay at 50 ms
3.7Dc-Offset Control Registers (0x06−0x0B)
Channels 1, 2, 3, 4, 5, and 6 are mapped into (0x06, 0x07, 0x08, 0x09, 0x0A, and 0x0B).
Table 3−8. Dc-Offset Control Registers
D7D6D5D4D3D2D1D0FUNCTION
10000000Maximum correction for positive dc offset (–1.56% FS)
00000000No dc-offset correction
01111111Maximum correction for negative dc offset (1.56% FS)
3.8Interchannel Delay Registers (0x0C−0x11)
Channels 1, 2, 3, 4, 5, and 6 are mapped into (0x0C, 0x0D, 0x0E, 0x0F, 0x10, and 0x11).
The first channel delay is set at 0. Each subsequent channel has a default value that is 53 DCLKs larger than
the preceding channel.
Table 3−9. Six Interchannel Delay Registers
D7D6D5D4D3D2D1D0FUNCTION
00000000Minimum absolute delay, 0 DCLK cycles, default for channel 1 = 0x00
00110101Default for channel 2 = 0x35
01101010Default for channel 3 = 0x6A
10011111Default for channel 4 = 0x9F
11010100Default for channel 5 = 0xD4
00001001Default for channel 6 = 0x09
11111111Maximum absolute delay, 255 DCLK cycles
3.9ABD Delay Register (0x12)
Table 3−10. ABD Delay Register
D7D6D5D4D3D2D1D0FUNCTION
000−−−−−Unused
−−−00000Minimum ABD delay, 0 DLCK cycles
−−−10100Default ABD delay, 20 DLCK cycles
−−−11111Maximum ABD delay, 31 DLCK cycles
30
SLES090A—November 2003—Revised January 2004TAS5076
Serial Control Interface Register Definitions
3.10 Individual Channel Mute Register (0x19)
Table 3−11. Individual Channel Mute Register
D7D6D5D4D3D2D1D0FUNCTION
11−−−−−−Unused
−−111111No channels are muted
−−−−−−−0Mute channel 1
−−−−−−0−Mute channel 2
−−−−−0−−Mute channel 3
−−−−0−−−Mute channel 4
−−−0−−−−Mute channel 5
−−0−−−−−Mute channel 6
SLES090A—November 2003—Revised January 2004TAS5076
31
Serial Control Interface Register Definitions
32
SLES090A—November 2003—Revised January 2004TAS5076
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
4System Procedures for Initialization, Changing Data Rates, and
Switching Between Master and Slave Modes
4.1System Initialization
Reset is used during system initialization to hold the TAS5076 inactive while power (VDD), the master clock
(MCLK_IN), the device control, and the data signals become stable. The recommended initialization
sequence is to hold RESET
signals (MUTE
, PDN, M_S, ERR_RCVRY, DBSPD, and CS0) are stable.
low for 24 MCLK_IN cycles after VDD has reached 3 V and the other control
Figure 4−1 shows the recommended sequence and timing for the RESET
terminal relative to system VDD
voltage and MCLK.
3 V
VDD
RESET
24 MCLK_IN Cycles
MCLK
Figure 4−1. RESET During System Initialization
Within the first 2 ms following the low-to-high transition of the RESET
must be set in the serial data interface control register using the I
terminal, the serial data interface format
2
C serial control interface. If the data rate
setting is other than the setting specified by the DBSPD terminal, then the data rate must be set using the
DBSPD terminal or I
2
C interface within 2 ms following the low-to-high transition of the RESET terminal.
2
The time available to set the I
extended using the ERR_RCVRY
Once the I
2
C control registers are set, the ERR_RCVRY terminal can be released and the TAS5076 starts
operation. Figure 4−2 shows how the ERR_RCVRY
necessary to set the I
SLES090A—November 2003—Revised January 2004TAS5076
2
C registers following the low-to-high transition of the RESET terminal.
C registers following the low-to-high transition of the RESET terminal can be
terminal. While ERR_RCVRY is low, the TAS5076 outputs are held inactive.
terminal can be used to extend the interval as long as
33
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
E
MCLK
RESET
< 2 ms
RR_RCVRY
MUTE
ERR_RCVRY and MUTE can
be set at any time prior to 2 ms
following the low-to-high
transition of RESET
Wait a minimum of 100 µs
after the low-to-high
transition of RESET
Set serial interface format, data
rate, volume, ... via I2C
> 5 ms
Release ERR_RCVRY and
then MUTE
registers are programmed
when I2C
Volume ramp
up 120 ms
Figure 4−2. Extending the I2C Write Interval Following a Low-to-High Transition of the RESET Terminal
The operation of the TAS5076 can be tailored as desired to meet specific operating requirements by adjusting
the following:
•Volume
•Data sample rate
•Emphasis/deemphasis settings
•Individual channel mute
•Automute delay register
•Dc-offset control registers
If desired, the TAS5076 can be set to perform an unmute sequence following the low-to-high transition of the
ERR_RCVRY
terminal or the error recovery I2C command (register 0x03 bit D2). This capability is set by
writing 0x7F to the individual error recovery register (0x04) and 0x84 to the feature enable register (0x1F).
4.2Data Sample Rate
If the master clock is well-behaved during the frequency transition (no MCLK_IN high or low clock periods less
than 20 ns), then a simple speed selection is performed by setting the DBSPD terminal or the serial control
register. If it is known at least 60 ms in advance that the sample rate is going to change, mute can be used
to provide a completely silent transition. The timing of this control sequence is shown in Figure 4−3 and
Figure 4−4.
34
SLES090A—November 2003—Revised January 2004TAS5076
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
Clock Transition
E
MCLK
MUTE
Terminal
DBSPD
Terminal
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
Volume Ramp
Down 42 − 65 ms
Set within 2 ms
of transition
< 2 ms< 2 ms
> 5 ms
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
Volume Ramp
Up 42 − 65 ms
Figure 4−3. Changing the Data Sample Rate Using the DBSPD Terminal
Clock Transition
MCLK
MUTE
Terminal
RR_RCVRY
Terminal
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
Volume Ramp
Down 42 − 65 ms
< 2 ms
Set data rate via I2C
register 0x02, D7 and D6
Hold ERR_RCVRY low
to give additional timeset registers
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
> 5 ms
Volume Ramp
Up 42 − 65 ms
< 2 ms
Figure 4−4. Changing the Data Sample Rate Using the I2C
However, if the master clock input can encounter a high clock or low clock period of less than 20 ns, then
RESET
must be applied during this time. There are two recommended control procedures for this case,
depending upon whether the DBSPD terminal or the serial control interface is used. These control sequences
are shown in Figure 4−5 and Figure 4−6.
Because this sequence employs the RESET
SLES090A—November 2003—Revised January 2004TAS5076
terminal the internal register settings are set to the default values.
35
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
E
Clock unstable during transition.
Figure 4−5 shows the procedure to change the data rate using the DBSPD terminal and then restore the
register settings. In this example, the ERR_RCVRY
RESET
is released. This permits the system controller to have as much additional time as necessary to restore
terminal is used to hold off system re-initialization after
the register settings.
Once the data rate is set, the ERR_RCVRY
re-initializes.
HIGH and LOW intervals < 20 ns
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
MCLK
MUTE
Terminal
Volume Ramp
Down 60 ms
RESET
Terminal
DBSPD
Terminal
and MUTE terminal signals are set high and the system
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
> 5 ms
Volume Ramp
Up 120 ms
Wait a minimum of
100 µs to set DBSPD
RR_RCVRY
Terminal
ERR_RCVRY can be set at
any time within this interval
Wait a minimum of 100 µs after the
LOW to HIGH transition of RESET
< 2 ms
Restore register
settings via I2C
Release ERR_RCVRY and
then MUTE
registers are programmed
when I2C
Figure 4−5. Changing the Data Sample Rate With an Unstable MCLK_IN Using the DBSPD Terminal
Because this sequence employs the RESET
terminal, the internal register settings are set to the default
values.
Figure 4−6 shows the procedure to change the data rate using register 0x02 D7 and D6 and then restore the
other register settings. In this example, the ERR_RCVRY terminal is used to hold off system re-initialization
after RESET
restore the register settings.
Once the data rate is set, the ERR_RCVRY
is released. This permits the system controller to have as much additional time as necessary to
and MUTE terminal signals are set high and the system
re-initializes.
36
SLES090A—November 2003—Revised January 2004TAS5076
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
E
Clock unstable during transition.
HIGH and LOW intervals < 20 ns
MCLK
MUTE
Terminal
RESET
Terminal
RR_RCVRY
Terminal
Change from a 96-kHz data rate
MCLK_IN = 24.576 MHz
Volume Ramp
Down 60 ms
ERR_RCVRY can be set at
any time within this interval
Wait a minimum of 100 µs after the
LOW to HIGH transition of RESET
< 2 ms
Change to a 48-kHz data rate
MCLK_IN = 12.288 MHz
> 5 ms
Volume Ramp
Up 120 ms
Set data rate and
restore other
register settings
via I2C
Release ERR_RCVRY and
then MUTE
registers are programmed
when I2C
Figure 4−6. Changing the Data Sample Rate With an Unstable MCLK_IN Using the I2C
4.3Changing Between Master and Slave Modes
The M_S terminal is set while the RESET terminal is active. Because this sequence employs the RESET
terminal the internal register settings are set to the default values.
Figure 4−7 shows the procedure to switch between master and slave modes and then restore the register
settings. In this example, the ERR_RCVRY
is released. This permits the system controller to have as much additional time as necessary to restore the
register settings.
Once the data rate is set, the ERR_RCVRY
re-initializes.
SLES090A—November 2003—Revised January 2004TAS5076
terminal is used to hold off system re-initialization after RESET
and MUTE terminal signals are set high and the system
37
System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes
E
Clock unstable during transition.
MCLK
MUTE
Terminal
RESET
Terminal
M_S
Terminal
Change from Master Mode
Volume Ramp
Down 60 ms
Wait a minimum of
100 µs to set M_S
Change to Slave Mode
> 5 ms
Volume Ramp
Up 120 ms
< 2 ms
RR_RCVRY
Terminal
Release ERR_RCVRY and
ERR_RCVRY can be set at
any time within this interval
Wait a minimum of 100 µs after the
LOW to HIGH transition of RESET
then MUTE
registers are programmed
Restore register
settings via I2C
when I2C
Figure 4−7. Changing Between Master and Slave Clock Mode
38
SLES090A—November 2003—Revised January 2004TAS5076
5Specifications
Specifications
5.1Absolute Maximum Ratings Over Operating Temperature Ranges (Unless
Otherwise Noted)
Digital supply voltage range: DVDD, DVDD_PWM, DVDD_RCL −0.3 V to 4.2 V. . . . . . . . . . . . . . . . . . . . . . . . .
Analog supply voltage range: AVDD_PLL, AVDD_OSC −0.3 V to 4.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Frequency, SCLK12.288MHz
SDIN setup time before SCLK rising edge20ns
SDIN hold time before SCLK rising edge10ns
LRCLK frequency3248192kHz
MCLK_IN duty cycle50%
SCLK duty cycle50%
LRCLK duty cycle50%
LRCLK setup time before SCLK rising edge20ns
MCLK high and low time20ns
Operating Conditions (Unless Otherwise Noted)
PARAMETERMINTYPMAXUNIT
MCLK_IN to SCLK05ns
MCLK_IN to LRCLK05ns
5.4.2.3DSP Serial Interface Mode Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETERMINTYPMAXUNIT
f
(SCLK)
t
d(FS)
t
w(FSHIGH
t
su(SDIN)
t
h(SDIN)
)Pulse duration, sync1/(64×Fs)ns
SCLK
SDIN
SCLK frequency12.288MHz
Delay time, SCLK rising to Fsns
SDIN and LRCLK setup time before SCLK falling edge20ns
SDIN and LRCLK hold time from SCLK falling edge10ns
SCLK duty cycle50%
t
h(SDIN)
t
su(SDIN)
Figure 5−6. Right-Justified, I2S, Left-Justified Serial Protocol Timing
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SLES090A—November 2003—Revised January 2004TAS5076
SCLK
t
su(LRCLK)
LRCLK
NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns).
Figure 5−7. Right, Left, and I2S Serial Mode Timing Requirement
SCLK
LRCLK
t
(MRLD)
Specifications
MCLK
SCLK
LRCLK
SDIN
t
(MSD)
t
su(LRCLK)
Figure 5−8. Serial Audio Ports Master Mode Timing
t
h(LRCLK)
t
w(FSHIGH)
t
su(SDIN)
t
h(SDIN)
Figure 5−9. DSP Serial Port Timing
SLES090A—November 2003—Revised January 2004TAS5076
45
Specifications
SCLK
LRCLK
SDIN
t
w(FSHIGH)
64 SCLKS
SCLK
SDIN
t
su(SDIN)
16 Bits
Left
Channel
= 20 ns
16 Bits
Right
Channel
32 Bits Unused
Figure 5−10. DSP Serial Port Expanded Timing
t
h(SDIN)
= 10 ns
Figure 5−11. DSP Absolute Timing
46
SLES090A—November 2003—Revised January 2004TAS5076
Specifications
PARAMETER
TEST CONDITIONS
UNIT
PARAMETER
TEST CONDITIONS
UNIT
5.4.3 Serial Control Port—I2C Operation
5.4.3.1Timing Characteristics for I2C Interface Signals Over Recommended Operating
Conditions (Unless Otherwise Noted)
f
SCL
t
w(H)
t
w(L)
t
r
t
f
t
su1
t
h1
t
(buf)
t
su2
t
h2
t
su3
C
L
STANDARD
MODE
MINMAXMINMAX
Frequency, SCL01000400kHz
Pulse duration, SCL high40.6µs
Pulse duration, SCL low4.71.3µs
Rise time, SCL and SDA1000300ns
Fall time, SCL and SDA300300ns
Setup time, SDA to SCL250100ns
Hold time, SCL to SDA00ns
Bus free time between stop and start condition4.71.3µs
Setup time, SCL to start condition4.70.6µs
Hold time, start condition to SCL40.6µs
Setup time, SCL to stop condition40.6µs
Load capacitance for each bus line400400pF
FAST MODE
SCLK
SDA
SCLK
t
w(H)
t
w(L)
t
su
Figure 5−12. SCL and SDA Timing
t
h2
t
su2
t
r
t
h1
t
(buf)
t
su3
t
f
SLES090A—November 2003—Revised January 2004TAS5076
SDA
Start ConditionStop Condition
Figure 5−13. Start and Stop Conditions Timing
47
Specifications
48
SLES090A—November 2003—Revised January 2004TAS5076